TW202211396A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TW202211396A
TW202211396A TW109130061A TW109130061A TW202211396A TW 202211396 A TW202211396 A TW 202211396A TW 109130061 A TW109130061 A TW 109130061A TW 109130061 A TW109130061 A TW 109130061A TW 202211396 A TW202211396 A TW 202211396A
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Taiwan
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electronic
conductive
package
electronic package
manufacturing
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TW109130061A
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English (en)
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TWI753561B (zh
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高灃
王隆源
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矽品精密工業股份有限公司
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Priority to TW109130061A priority Critical patent/TWI753561B/zh
Priority to CN202011123218.8A priority patent/CN114203686A/zh
Priority to US17/102,841 priority patent/US11973047B2/en
Application granted granted Critical
Publication of TWI753561B publication Critical patent/TWI753561B/zh
Publication of TW202211396A publication Critical patent/TW202211396A/zh
Priority to US18/413,887 priority patent/US20240162180A1/en

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Abstract

一種電子封裝件，係將一作為集成穩壓器之電子結構堆疊於電子元件上，以利於近距離配合電子元件進行電性傳輸。

Description

電子封裝件及其製法
本發明係有關一種半導體裝置，尤指一種電子封裝件及其製法與電子結構。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。例如，集成穩壓器(IVR)嵌入高性能處理器中，以提高效率，如開關頻率、降低功耗，且可提高可靠性，甚至降低製作成本。此外，目前應用於晶片封裝領域之技術，包含有例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組，或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
圖1係為習知3D晶片堆疊之封裝結構1之剖面示意圖。如圖1所示，該封裝結構1包括一矽中介板(Through Silicon interposer，簡稱TSI)1a，其具有一矽板體10及複數形成於其中之導電矽穿孔(Through-silicon via，簡稱TSV)101，且該矽板體10之表面上形成有一電性連接該導電矽穿孔101之線路重佈結構(Redistribution layer，簡稱RDL)。具體地，該線路重佈結構係包含一介電層11及 一形成於該介電層11上之線路層12，且該線路層12電性連接該導電矽穿孔101，並形成一絕緣保護層13於該介電層11與該線路層12上，且該絕緣保護層13外露部分該線路層12，以結合複數銲錫凸塊14。
再者，可先形成另一絕緣保護層15於該矽板體10上，且該絕緣保護層15外露該些導電矽穿孔101之端面，以結合複數銲錫凸塊16於該些導電矽穿孔101之端面上，且該銲錫凸塊16電性連接該導電矽穿孔101，其中，可選擇性於該導電矽穿孔101之端面上形成供接置該銲錫凸塊16之凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)160。
又，該封裝結構1復包括一封裝基板19，供該矽中介板1a藉由該些銲錫凸塊16設於其上，使該封裝基板19電性連接該些導電矽穿孔101，且以底膠191包覆該些銲錫凸塊16。
另外，該封裝結構1復包括複數系統單晶片(System-On-Chip，簡稱SOC)型半導體晶片17，其設於該些銲錫凸塊14上，使該半導體晶片17電性連接該線路層12，且以底膠171包覆該些銲錫凸塊14，並形成封裝材18於該封裝基板19上，以令該封裝材18包覆該半導體晶片17與該矽中介板1a。
於後續應用中，該封裝結構1可形成複數銲球192於該封裝基板19之下側，以接置於一電路板1’上。
早期商品化產品中，係將一穩壓器(IVR)1b’直接安裝於該電路板上，但此方法將造成終端產品的體積無法達到輕薄短小的要求，且該穩壓器1b’與該封裝結構1之距離過遠，造成與其相關電性連接的半導體晶片17傳遞訊號之路徑過遠，導致電性功能下降，致使功耗隨之增加。
因此，業界遂將該穩壓器1b整合至與該封裝基板19之下側，以縮短該穩壓器1b與該半導體晶片17之間的傳輸距離，藉此縮減該電路板1’之表面積及體積。
惟，隨著消費市場需求，現今終端產品之功能需求越加繁多，故接置於該封裝基板19上之半導體晶片17越來越多，因而與其配合之穩壓器1b之需求量大增，致使該封裝基板19之下側並無多餘空間配置更多穩壓器1b，導致單一封裝結構1已無法符合現今終端產品相關輕薄短小、低功耗、高電性效能等需求。
再者，雖可將該穩壓器1b整合於該半導體晶片17中，但需重新設計該封裝結構1，不僅增加製作成本，且需擴增該半導體晶片17之尺寸，因而難以符合微小化之需求。
因此，如何克服上述習知技術之種種問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：電子結構，係包含有一電子主體，其具有相對之第一側與第二側，且於該電子主體之第一側上形成有導電體；電子元件，係結合該電子結構之導電體；導電柱，係設於該電子元件上，以令該電子元件電性連接該導電柱與該導電體；以及包覆層，係形成於該電子元件上，以包覆該電子結構與導電柱。
本發明復提供一種電子封裝件之製法，係包括：提供一電子主體，其具有相對之第一側與第二側；形成導電體於該電子主體之第一側上，以形成電 子結構；將該電子結構以其導電體設於一電子元件上，且該電子元件上形成有複數導電柱，以令該電子元件電性連接該導電柱與該導電體；以及形成一包覆層於該電子元件上，以包覆該電子結構與導電柱。
前述之電子封裝件及其製法中，該電子主體係具有一基部與一形成於該基部上之線路部，以令該基部定義出該第二側，而該線路部則定義出該第一側，且該基部中具有複數電性連接該線路部並外露出該第二側之導電穿孔。例如，該導電體形成於該電子主體之第二側上，且於該電子主體之第二側上形成絕緣層，使該絕緣層包覆該第二側上之導電體。
前述之電子封裝件及其製法中，該包覆層之表面係齊平該導電柱之端面。
前述之電子封裝件及其製法中，該導電柱之端面係外露出該包覆層之表面。
前述之電子封裝件及其製法中，該導電體係藉由導電凸塊電性連接該電子元件。
前述之電子封裝件及其製法中，復包括形成複數導電元件於該包覆層上，且令該複數導電元件電性連接該導電柱。
前述之電子封裝件及其製法中，復包括形成線路結構於該包覆層上，且令該線路結構電性連接該導電柱。例如，復包括形成複數導電元件於該線路結構上，且令該複數導電元件電性連接該線路結構。或者，該線路結構係為扇入型配置或扇出型配置。
由上可知，本發明之電子封裝件及其製法中，主要藉由將該電子結構堆疊於該電子元件上以近距離配合該電子元件，故相較於習知技術，本 發明無需重新設計該電子封裝件，因而能大幅節省製作成本，且無需擴增該電子元件之尺寸，以利於滿足微小化之需求，並有利於呈現高電性效能。
1:封裝結構
1’:電路板
1a:矽中介板
1b,1b’:穩壓器
10:矽板體
101:導電矽穿孔
11,260:介電層
12:線路層
13,15:絕緣保護層
14,16:銲錫凸塊
160:凸塊底下金屬層
17:半導體晶片
171,191:底膠
18:封裝材
19:封裝基板
192:銲球
2,2’,3:電子封裝件
2a:整版面晶圓體
2b,3b:電子結構
21,31:電子主體
21’:基部
21”:線路部
21a,31a:第一側
21b,31b:第二側
210:導電穿孔
211:鈍化層
212:線路層
22:導電凸塊
23:導電柱
23b:端面
24:結合層
25:包覆層
25a:第一表面
25b:第二表面
26:線路結構
261:線路重佈層
27:導電元件
270:金屬柱
28:絕緣層
280a:第一導電體
280b:第二導電體
29:電子元件
29a:作用面
29b:非作用面
290,310:電極墊
3a:堆疊組件
38:導電體
8:佈線板件
9:承載板
90:離形層
91:黏著層
L,S:切割路徑
圖1係為習知封裝結構之剖視示意圖。
圖2A至圖2G係為本發明之電子封裝件之製法之第一實施例之剖視示意圖。
圖2G’係為對應圖2G之其它實施例之剖視示意圖。
圖2H係為圖2G之後續製程之剖視示意圖。
圖3A至圖3F係為本發明之電子封裝件之製法之第二實施例之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2G係為本發明之電子封裝件2之製法之第一實施例的剖面示意圖。
如圖2A所示，提供一整版面晶圓體2a，其包含複數陣列排列之電子主體21，且該電子主體21具有相對之第一側21a與第二側21b。
於本實施例中，該電子主體21係為主動元件，如半導體晶片，其具有一矽材基部21’與一形成於該基部21’上之線路部21”，且該基部21’中具有複數外露出該基部21’之導電穿孔210，如導電矽穿孔(Through-silicon via，簡稱TSV)，以電性連接該線路部21”。例如，該線路部21”係包含至少一鈍化層211及結合該鈍化層211之線路層212，以令該線路層212電性連接該導電穿孔210。具體地，該基部21’係定義出該第二側21b，且該線路部21”係定義出該第一側21a。應可理解地，有關具有該導電穿孔210之主動元件之結構態樣繁多，並無特別限制。
如圖2B所示，進行薄化製程，如藉由研磨方式，移除該電子主體21之第二側21b(或該基部21’)之部分材質，以令該導電穿孔210外露出該第二側21b。
如圖2C所示，形成複數第一導電體280a與第二導電體280b於該電子主體21之第一側21a與第二側21b上，以令該些第一導電體280a與第二導電體280b電性連接該線路層212與導電穿孔210。
於本實施例中，各該導電穿孔210之外露兩端分別接觸該第一導電體280a與第二導電體280b。例如，該第一導電體280a與第二導電體280b係為如銅柱之金屬柱。
再者，可形成一絕緣層28於該電子主體21之第二側21b上，使該絕緣層28包覆該些第二導電體280b。例如，該第二導電體280b係未外露出該絕緣層 28，且複數該第一導電體280a係結合複數導電凸塊22。具體地，該導電凸塊22係為如銅柱、銲錫球等金屬凸塊。
又，可沿切割路徑L進行切單製程，以獲取複數電子結構2b，其作為集成穩壓器(Integrated Voltage Regulator，簡稱IVR)。
如圖2D所示，提供一設於承載板9上之電子元件29，且該電子元件29上形成有複數導電柱23，以將至少一電子結構2b設於該電子元件29上。
於本實施例中，該電子元件29係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該電子元件29係為半導體晶片，如系統單晶片(System-On-Chip，簡稱SOC)型之功能晶片，其具有相對之作用面29a與非作用面29b，且其作用面29a上具有複數電極墊290，並以其非作用面29b設於該承載板9上。
再者，該承載板9係例如為半導體材質(如矽或玻璃)之板體，其上可依需求形成有一離形層90(或黏著層)，以供該電子元件29設於該離形層90上。
又，該導電柱23係設於該電子元件29之其中一部分電極墊290上並電性連接該電極墊290，且形成該導電柱23之材質係為如銅之金屬材或銲錫材。
另外，該電子結構2b係藉由複數導電凸塊22結合至該電子元件29之另一部分電極墊290上以電性連接該電極墊290。例如，可依需求以如底膠之結合層24包覆該些導電凸塊22與第一導電體280a。
如圖2E所示，形成一包覆層25於該電子元件29之作用面29a上，以令該包覆層25包覆該電子結構2b、結合層24與該些導電柱23，其中，該包覆層25係具有相對之第一表面25a與第二表面25b，且其以第一表面25a結合該電子元件29之作用面29a。接著，藉由整平製程，使該包覆層25之第二表面25b齊平該導電 柱23之端面23b與該電子結構2b之絕緣層28(或該第二導電體280b之端面)，令該導電柱23之端面23b與該電子結構2b之絕緣層28(或該第二導電體280b之端面)外露出該包覆層25之第二表面25b。
於本實施例中，該包覆層25係為絕緣材，如環氧樹脂之封裝膠體，其可用壓合(lamination)或模壓(molding)之方式形成於該電子元件29上。
再者，該整平製程係藉由研磨方式，移除該導電柱23之部分材質、該電子結構2b之絕緣層28(或該第二導電體280b)之部分材質與該包覆層25之部分材質。
又，若未形成該結合層24，該包覆層25可包覆該些導電凸塊22與第一導電體280a。
如圖2F所示，形成一線路結構26於該包覆層25之第二表面25b上，且令該線路結構26電性連接該些導電柱23與該電子結構2b之第二導電體280b。
於本實施例中，該線路結構26係包括複數第二介電層260、及設於該複數介電層260上之複數線路重佈層(RDL)261，且最外層之介電層260可作為防銲層，以令最外層之線路重佈層261部分外露出該防銲層。或者，該線路結構26亦可僅包括單一介電層260及單一線路重佈層261。
再者，形成該線路重佈層261之材質係為銅，且形成該介電層260之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)或其它等之介電材。
又，可於最外層之線路重佈層261上形成複數如銲球之導電元件27，以令該複數導電元件27電性連接該導電柱23及/或該第二導電體280b。例如，該線路結構26係為扇入(fan-in)型配置，使該些導電元件27之佈設範圍不會超過該電子元件29之作用面29a之面積。
如圖2G所示，移除該承載板9及其上之離形層90，以外露該電子元件29，再沿如圖2F所示之切割路徑S進行切單製程，以獲取該電子封裝件2。
於本實施例中，如圖2H所示，於後續製程中可藉由該些導電元件27接置於一佈線板件8上側，如有機材板體(如具有核心層與線路部之封裝基板(substrate)或具有線路部之無核心層式(coreless)封裝基板)或無機材板體(如矽板材)，且該佈線板件8下側可接置於一如電路板之電子裝置(圖未示)上。
再者，於另一實施例中，如圖2G’所示之電子封裝件2’，可依需求省略該線路結構26之製作。例如，將該些導電元件27接置於該電子結構2b之第二導電體280b與該導電柱23上，以電性連接該第二導電體280b與該導電柱23。具體地，該導電元件27可藉由如銅柱之金屬柱270結合至該第二導電體280b與該導電柱23上。
因此，本發明之製法藉由將作為IVR之電子結構2b堆疊於該電子元件29上，以利於配合不同功能之電子元件29，故相較於習知將IVR整合於SOC中，本發明之製法無需重新設計該電子封裝件2,2’，因而能大幅節省製作成本，且無需擴增該電子元件29之尺寸，以利於滿足微小化之需求。
再者，相較於習知將IVR整合至電路板或封裝基板上，本發明之電子結構2b與該電子元件29之間的電性傳輸距離可最短化(無需經過封裝基板或電路板)，以利於降低損耗及縮小該電子封裝件2,2’之尺寸，並提升電性效能。
圖3A至圖3F係為本發明之電子封裝件3之製法之第二實施例的剖面示意圖。本實施例與第一實施例之差異在於電子結構3b之態樣，其它製程大致相同，故以下不再贅述相同處。
如圖3A所示，提供一電子結構3b，其具有複數用以結合導電凸塊22之導電體38，以作為集成穩壓器(Integrated Voltage Regulator，簡稱IVR)。
於本實施例中，該電子結構3b係為主動元件，如半導體晶片，其電子主體31係具有相對之第一側31a與第二側31b，且其第一側31a上具有複數電極墊310，以結合該導電體38，並且該電子主體31未形成有該導電穿孔210。
如圖3B所示，將該電子結構3b以導電凸塊22設於電子元件29上以形成堆疊組件3a，且該電子元件29上形成有複數導電柱23。之後，進行切單製程，以獲取複數堆疊組件3a。
於本實施例中，該電子結構3b係藉由複數導電凸塊22以覆晶方式結合至該電子元件29之部分電極墊290上以電性連接該電極墊290。例如，可依需求以如底膠之結合層24包覆該些導電凸塊22與該導電體38。
如圖3C所示，將該堆疊組件3a以其電子元件29之非作用面29b設於一承載板9上。
於本實施例中，該承載板9係例如為半導體材質(如矽或玻璃)之板體，其上可依需求依序形成有一離形層90與一黏著層91，以供該電子元件29設於該黏著層91上。
如圖3D所示，形成一包覆層25於該承載板9之黏著層91上，以令該包覆層25包覆該堆疊組件3a，其中，該包覆層25係具有相對之第一表面25a與第二表面25b，且其以第一表面25a結合該黏著層91。接著，藉由整平製程，使該包覆層25之第二表面25b齊平該導電柱23之端面23b與該電子結構3b之電子主體31之第二側31b，令該導電柱23之端面23b外露出於該包覆層25之第二表面25b。
於本實施例中，該包覆層25係為絕緣材，如環氧樹脂之封裝膠體，其可用壓合(lamination)或模壓(molding)之方式形成於該黏著層91上。
再者，該整平製程係藉由研磨方式，移除該導電柱23之部分材質與該包覆層25之部分材質(甚至該電子主體31之部分材質)。
如圖3E所示，形成一線路結構26於該包覆層25上，且該線路結構26電性連接該些導電柱23，並形成複數如銲球之導電元件27於最外層之線路重佈層261上，以令該複數導電元件27電性連接該線路重佈層261。
於本實施例中，該線路結構26係為扇出(fan-out)型配置，使該些導電元件27之佈設範圍超過該電子元件29之作用面29a之面積。
如圖3F所示，移除該承載板9及其上之離形層90與黏著層91，以外露該電子元件29之非作用面29b。之後，沿如圖3E所示之切割路徑S進行切單製程，以完成本發明之電子封裝件3，且該電子封裝件3可藉由該些導電元件27於後續製程中接置如封裝結構或其它結構(如電路板或中介板)之電子裝置(圖略)上。
因此，本發明之製法藉由將作為IVR之電子結構3b堆疊於該電子元件29上，以利於配合不同功能之電子元件29，故相較於習知將IVR整合於SOC中，本發明之製法無需重新設計該電子封裝件3，因而能大幅節省製作成本，且無需擴增該電子元件29之尺寸，以利於滿足微小化之需求。
再者，相較於習知將IVR整合至電路板或封裝基板上，本發明之電子結構3b與該電子元件29之間的電性傳輸距離可最短化(無需經過封裝基板或電路板)，以利於降低損耗及縮小該電子封裝件3之尺寸，並提升電性效能。
本發明復提供一種電子封裝件2,2’,3，係包括：一電子結構2b,3b、一電子元件29、複數導電柱23以及一包覆層25。
所述之電子結構2b,3b係包含有一電子主體21,31，其具有相對之第一側21a,31a與第二側21b,31b，且於該電子主體21,31之第一側21a,31a上形成有第一導電體280a(或導電體38)。
所述之電子元件29係結合該電子結構2b,3b之第一導電體280a(或導電體38)。
所述之導電柱23係設於該電子元件29上，以令該電子元件29電性連接該導電柱23與該第一導電體280a或導電體38。
所述之包覆層25係形成於該電子元件29上，以包覆該電子結構2b,3b與導電柱23。
於一實施例中，該電子主體21係具有一基部21’與一形成於該基部21’上之線路部21”，以令該基部21’定義出該第二側21b，而該線路部21”則定義出該第一側21a，且該基部21’中具有複數電性連接該線路部21”並外露出該第二側21b之導電穿孔210。例如，第二導電體280b復形成於該電子主體21之第二側21b上，且於該電子主體21之第二側21b上形成一絕緣層28，使該絕緣層28包覆該第二導電體280b。
於一實施例中，該包覆層25之第二表面25b係齊平該導電柱23之端面23b。
於一實施例中，該導電柱23之端面23b係外露出該包覆層25之第二表面25b。
於一實施例中，第一導電體280a(或導電體38)係藉由導電凸塊22電性連接該電子元件29。
於一實施例中，所述之電子封裝件2’復包括形成於該包覆層25上之複數導電元件27，以令該複數導電元件27電性連接該導電柱23。
於一實施例中，所述之電子封裝件2,3復包括形成於該包覆層25上之線路結構26，以令該線路結構26電性連接該導電柱23。進一步，所述之電子封裝件2,3復包括形成於該線路結構26上之複數導電元件27，以令該複數導電元件27電性連接該線路結構26。例如，該線路結構26係為扇入型配置或扇出型配置。
綜上所述，本發明之電子封裝件及其製法，係藉由將該電子結構堆疊於該電子元件上以近距離配合該電子元件，故本發明無需重新設計該電子 封裝件，因而能大幅節省製作成本，且無需擴增該電子元件之尺寸，以利於滿足微小化之需求，並有利於呈現高電性效能。
再者，藉由將作為IVR之電子結構嵌埋於該包覆層中，使該電子封裝件可適用於伺服器或基站處理器。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
2b:電子結構
21:電子主體
21’:基部
21”:線路部
210:導電穿孔
22:導電凸塊
23:導電柱
25:包覆層
25a:第一表面
25b:第二表面
26:線路結構
27:導電元件
29:電子元件

Claims (20)

  1. 一種電子封裝件，係包括：
    電子結構，係包含有一電子主體，其具有相對之第一側與第二側，且於該電子主體之第一側上形成有導電體；
    電子元件，係結合該電子結構之導電體；
    導電柱，係設於該電子元件上，以令該電子元件電性連接該導電柱與該導電體；以及
    包覆層，係形成於該電子元件上，以包覆該電子結構與導電柱。
  2. 如請求項1所述之電子封裝件，其中，該電子主體係具有一基部與一形成於該基部上之線路部，以令該基部定義出該第二側，而該線路部則定義出該第一側，且該基部中具有複數電性連接該線路部並外露出該第二側之導電穿孔。
  3. 如請求項2所述之電子封裝件，其中，該導電體形成於該電子主體之第二側上，且於該電子主體之第二側上形成有包覆該導電體之絕緣層。
  4. 如請求項1所述之電子封裝件，其中，該包覆層之表面係齊平該導電柱之端面。
  5. 如請求項1所述之電子封裝件，其中，該導電柱之端面係外露出該包覆層之表面。
  6. 如請求項1所述之電子封裝件，其中，該導電體係藉由導電凸塊電性連接該電子元件。
  7. 如請求項1所述之電子封裝件，復包括形成於該包覆層上之複數導電元件，且令該複數導電元件電性連接該導電柱。
  8. 如請求項1所述之電子封裝件，復包括形成於該包覆層上之線路結構，且令該線路結構電性連接該導電柱。
  9. 如請求項8所述之電子封裝件，復包括形成於該線路結構上之複數導電元件，且令該複數導電元件電性連接該線路結構。
  10. 如請求項8所述之電子封裝件，其中，該線路結構係為扇入型配置或扇出型配置。
  11. 一種電子封裝件之製法，係包括：
    提供一電子主體，其具有相對之第一側與第二側；
    形成導電體於該電子主體之第一側上，以形成電子結構；
    將該電子結構以其導電體設於一電子元件上，且該電子元件上形成有複數導電柱，以令該電子元件電性連接該導電柱與該導電體；以及
    形成一包覆層於該電子元件上，以包覆該電子結構與導電柱。
  12. 如請求項11所述之電子封裝件之製法，其中，該電子主體係具有一基部與一形成於該基部上之線路部，以令該基部定義出該第二側，而該線路部則定義出該第一側，且該基部中具有複數電性連接該線路部並外露出該第二側之導電穿孔。
  13. 如請求項12所述之電子封裝件之製法，其中，該導電體形成於該電子主體之第二側上，且於該電子主體之第二側上形成包覆該第二側上之導電體絕緣層，使該絕緣層包覆該第二側上之導電體。
  14. 如請求項11所述之電子封裝件之製法，其中，該包覆層之表面係齊平該導電柱之端面。
  15. 如請求項11所述之電子封裝件之製法，其中，該導電柱之端面係外露出該包覆層之表面。
  16. 如請求項11所述之電子封裝件之製法，其中，該導電體係藉由導電凸塊電性連接該電子元件。
  17. 如請求項11所述之電子封裝件之製法，復包括形成複數導電元件於該包覆層上，且令該複數導電元件電性連接該導電柱。
  18. 如請求項11所述之電子封裝件之製法，復包括形成線路結構於該包覆層上，且令該線路結構電性連接該導電柱。
  19. 如請求項18所述之電子封裝件之製法，復包括形成複數導電元件於該線路結構上，且令該複數導電元件電性連接該線路結構。
  20. 如請求項18所述之電子封裝件之製法，其中，該線路結構係為扇入型配置或扇出型配置。
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