TW202147557A - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TW202147557A
TW202147557A TW110120776A TW110120776A TW202147557A TW 202147557 A TW202147557 A TW 202147557A TW 110120776 A TW110120776 A TW 110120776A TW 110120776 A TW110120776 A TW 110120776A TW 202147557 A TW202147557 A TW 202147557A
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Taiwan
Prior art keywords
die
semiconductor package
layer
substrate
inductor
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TW110120776A
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English (en)
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TWI752884B (zh
Inventor
崢 曾
柯慶忠
詹歸娣
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聯發科技股份有限公司
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    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
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Abstract

本發明公開一種半導體封裝，包括：第一晶粒，包括上表面和與該上表面相對的下表面，其中，該第一晶粒包括複數個貫穿第一晶粒的矽通孔；第二晶粒，堆疊在該第一晶粒的該上表面上；中介層，設置在該第一晶粒的該下表面上；以及電感器，佈置在該中介層中，其中該電感器包括直接耦接到該矽通孔的端子。

Description

半導體封裝
本發明半導體技術領域，尤其涉及一種半導體封裝。
在積體電路應用中實現片上電感器仍然是滿足高品質因數（Q factor，quality factor）、小面積消耗、有限的寄生耦接、易於佈局和製造的要求的挑戰。
常規地，在倒裝晶粒封裝的製造過程中使用晶粒或晶粒的互連結構的附加金屬層來提高Q因數。 然而，額外的金屬層增加了晶粒上的面積和製造成本，並且不利地影響了製造產量。
有鑑於此，本發明提供一種具有高性能的貫穿矽通孔（through-silicon via，TSV）電感器的改進的半導體封裝，以解決上述問題。
根據本發明的第一方面，公開一種半導體封裝，包括：
第一晶粒，包括上表面和與該上表面相對的下表面，其中，該第一晶粒包括複數個貫穿第一晶粒的矽通孔；
第二晶粒，堆疊在該第一晶粒的該上表面上；
中介層，設置在該第一晶粒的該下表面上；以及
電感器，佈置在該中介層中，其中該電感器包括直接耦接到該矽通孔的端子。
本發明的半導體封裝由於包括：第一晶粒，包括上表面和與該上表面相對的下表面，其中，該第一晶粒包括複數個貫穿第一晶粒的矽通孔；第二晶粒，堆疊在該第一晶粒的該上表面上；中介層，設置在該第一晶粒的該下表面上；以及電感器，佈置在該中介層中，其中該電感器包括直接耦接到該矽通孔的端子。採用這種方式，電感器設置在晶粒的正面，直接透過連接焊盤與晶粒連接，這樣來縮短電路徑和減少面積佔用。其中晶粒與電感器之間僅有例如單層的連接焊盤，而沒有其他例如連接線等連接結構，電路徑更短，並且電感器可以位於晶粒的豎直投影區域內，從而不增加半導體封裝結構的面積大小，減少面積佔用。
以下發明提供了用於實現所提供的主題的不同特徵的許多不同的實施例或示例。下面描述組件和佈置的特定示例以簡化本發明。當然，這些僅是示例，而無意於進行限制。例如，在下面的描述中，在第二特徵之上或之上的第一特徵的形成可以包括其中第一特徵和第二特徵形成為直接接觸實施例，並且還可以包括其中在第一特徵和第二特徵之間形成附加特徵的實施例，使得第一和第二特徵可以不直接接觸。另外，本發明可以在各個示例中重複參考數字和/或字母。該重複是出於簡單和清楚的目的，並且其本身並不指示所討論的各種實施例和/或配置之間的關係。
此外，為了便於描述，本文中可以使用諸如“在...下方”、“在...之下”、“在...下”、“在...上方”、“在...之上”之類的空間相對術語，以便於描述一個元件或特徵與之的關係。如圖所示的另一元件或特徵。除了在圖中描述的方位之外，空間相對術語還意圖涵蓋設備在使用或操作中的不同方位。該裝置可以以其他方式定向（旋轉90度或以其他定向），並且在此使用的空間相對描述語可以同樣地被相應地解釋。另外，還將理解的是，當層被稱為在兩層“之間”時，它可以是兩層之間的唯一層，或者也可以存在一個或複數個中間層。
本文所使用的術語僅出於描述特定實施例的目的，並不旨在限制本發明構思。如本文所使用的，單數形式“一個”、“一種”和“該”也旨在包括複數形式，除非上下文另外明確指出。還將理解，術語“包括”和/或“包含”在本說明書中使用時，指定存在該特徵，整數，步驟，操作，元件和/或組件，但是不排除存在或添加一個或複數個其他特徵，整數，步驟，操作，元素，組件和/或其組。如本文所使用的，術語“和/或”包括一個或複數個相關聯的所列專案的任何和所有組合，並且可以縮寫為“/”。
將理解的是，當將元件或層稱為在另一元件或層“上”，“連接至”，“耦接至”或“鄰近”時，它可以直接在其他元素或層上，與其連接，耦接或相鄰，或者可以存在中間元素或層。相反，當元件稱為“直接在”另一元件或層“上”，“直接連接至”，“直接耦接至”或“緊鄰”另一元件或層時，則不存在中間元件或層。
注意：（i）在整個附圖中相同的特徵將由相同的附圖標記表示，並且不一定在它們出現的每個附圖中都進行詳細描述，並且（ii）一系列附圖可能顯示單個專案的不同方面，每個方面都與各種參考標籤相關聯，這些參考標籤可能會出現在整個序列中，或者可能只出現在序列的選定圖中。
本發明涉及包括第一晶粒和堆疊在第一晶粒上的第二晶粒的堆疊晶粒封裝。提出的電感器設計為放置在扇出中介層中的第一個晶粒的背面，以有效利用矽面積，並且可以透過TSV連接到下方晶粒的正面（front side）電路。本案將電感器設置在晶粒的正面，直接透過連接焊盤與晶粒連接，這樣來縮短電路徑和減少面積佔用。其中晶粒與電感器之間僅有例如單層的連接焊盤，而沒有其他例如連接線等連接結構，電路徑更短，並且電感器可以位於晶粒的豎直投影區域內，從而不增加半導體封裝結構的面積大小，減少面積佔用。
請參考圖1，圖1為繪示依照本發明實施例的一種堆疊式晶粒封裝（或半導體封裝）1的剖面示意圖。如圖1所示，堆疊式晶粒封裝或半導體封裝1包括第一晶粒10和堆疊在第一晶粒10上的第二晶粒20。根據一個實施例，第一晶粒10和第二晶粒20執行不同的功能並且透過以不同的製程節點技術中製造，例如，第一晶粒10可以是透過5nm製程製造的數據機晶粒，第二晶粒20可以是透過3nm製程製造的處理器晶粒，但不限於此。如在右側的圓形區域中所示，該圓形區域示出了堆疊式晶粒封裝1的一部分的放大圖，第一晶粒10具有上表面S1和與上表面S1相對的下表面S2。第二晶粒20安裝在上表面S1上。
第一晶粒10可以透過第一晶粒10的上表面S1上的導電焊盤AP和微凸塊BP電連接至第二晶粒20。微凸塊BP在第二晶粒20的接合墊（或接合焊盤）201和第一晶粒10的導電墊AP之間延伸。根據一些實施例，可以在接合墊201和導電墊AP之間進一步提供焊料層SP，但不限於此。在一些實施例中，導電墊（或導電焊盤）AP可以由鋁製成，但是不限於此。第二晶粒20和第一晶粒10之間的間隙G可以填充有密封劑或模塑料MC1，但不限於此。
第一晶粒10包括晶粒基板100。晶粒基板100可以是半導體基板，例如，矽基板。應該理解，可以使用其他類型的半導體基板。例如，在一些實施例中，晶粒基板100可以是絕緣體上矽、矽鍺或其他類型的半導體基板。電路組件102可以形成在晶粒基板100上或內部。例如，電路組件102可以包括具有閘極和源極/漏極區域的電晶體。
線後端（back-end of line，BEOL）結構BL設置在晶粒基板100上。根據一個實施例，例如，BEOL結構BL包括形成在其上的至少一個超低介電常數（超低k）層110。例如，根據一個實施例，超低k層110可以具有小於2.6的介電常數，例如小於2.55，但是不限於此。 BEOL結構BL可以進一步包括至少一個層間介電（inter-layer dielectric，ILD）層120，例如形成在超低k層110上的未摻雜的矽酸鹽玻璃（un-doped silicate glass，USG）層。 ILD層120可以具有大約3.3的介電常數，但是不限於此。可以在ILD層120中形成至少一個金屬互連層121。例如，金屬互連層121可以具有大約2.8微米的厚度。例如，金屬互連層121可以具有小於2.8微米的厚度。例如，金屬互連層121可以具有小於3.0微米的厚度。可以在ILD層120上形成導電焊盤AP。可以在ILD層120上形成諸如氮化矽層的鈍化層130。可以在鈍化層130中提供開口APO以部分地暴露導電焊盤AP。可以透過開口APO在導電焊盤AP上形成微凸塊BP。
根據一個實施例，第一晶粒10還包括複數個矽通孔（through silicon via，TSV）150。TSV 150穿過晶粒基板100和至少超低k層110。TSV 150可以電連接至ILD層120中的金屬互連層121。每個TSV 150的另一端可以連接至設置在第一晶粒10下表面S2上之扇出中介層（fan-out interposer layer）（或重分佈層（re-distribution layer））30的連接焊盤350。根據一個實施例，連接焊盤350可以進一步連接到由扇出中介層30中的金屬跡線ML形成的電感器360。例如，電感器360設置在第一晶粒10下表面S2下方的扇出插入層30的水平高度（horizontal level）。扇出中介層30的介電層310將電感器360與晶粒基板100分開。在一些實施例中，介電層310由高分子材料製成。TSV 150可以用於連接電感器360（例如透過連接焊盤350）與第二晶粒20（例如透過金屬互連層121、導電焊盤AP、微凸塊BP和接合墊201等），這樣可以使第二晶粒20與電感器360之間電連接路徑更短，提高電性能。
圖2示出了示例性電感器的俯視圖。電感器360例如包括形成第一和第二同心環的金屬跡線ML。根據一個實施例，金屬跡線ML具有等於或大於3.0微米的厚度。同心環包括電感器電路的幾何形狀。包括至少一個外部段361和至少一個內部段362的同心環由同心環間間隔363隔開。電感器360包括第一端子365和第二端子366。電感器360的第一端子365和第二端子366耦接到外部段361的第一端E1。外部段361的第二端E2透過跨接聯接器367聯接到內部段362的第二端E2。跨接聯接器367例如設置在扇出中介層30的第二平面水平面上，該第二水平面不同于形成電感器360的同心環的第一水平面上。第一端子365和第二端子366直接連接到對應的TSV 150。
如上所述，電感器360是出於說明的目的，而不應限於此。 電感器360可以包括其他合適類型的配置。 例如，電感器360可以形成在複數個金屬層上。
如圖1所示，扇出中介層（或重分佈層）30可以用於將第一晶粒10的端子在第二表面S2上從更緊密的間距散佈為更鬆散的間距。在扇出中介層30的下表面S3上，可以設置複數個焊球SB以進一步連接。第一晶粒10和第二晶粒20可以由模塑料MC1密封。第一晶粒10、模塑料MC1和扇出中介層30的上表面由模塑料MC2密封。模塑料MC2的底表面可以與第一晶粒10的下表面S2大致齊平。扇出中介層（interposer）30設置在模塑料MC2的底表面上和第一模子的下表面S2上。第一晶粒10的TSV 150的下端電連接至扇出中介層30的金屬層。優選地，電感器360直接設置在第一晶粒10的下面，以在電感器360和第一晶粒10之間形成較短的電路徑，並且將提供更好的晶片性能。應當理解，在一些實施例中，電感器360可以與第一晶粒10部分重疊，以便在第一晶粒10和電感器360之間實現較短的電路徑。電感器360可以與第一晶粒10也可以完全重疊或至少部分重疊。
請參考圖3，圖3為根據本發明另一實施例的堆疊式晶粒封裝2的剖面示意圖，其中相同的元件，區域或層以相同的數字或標號標示。同樣地，如圖3所示，堆疊式晶粒封裝或半導體封裝2包括第一晶粒10和堆疊在第一晶粒10上的第二晶粒20。第一晶粒10可以透過微凸塊BP電連接至第二晶粒20。電感器360設置在第一晶粒10下方的扇出中介層30中。電感器360的端子直接耦接到穿透第一晶粒10的對應的TSV 150。堆疊的晶粒封裝2還包括在模塑料MC2和第二晶粒20上的重分佈層50。可以在重新分佈層50上安裝諸如記憶體封裝或DRAM封裝之類的半導體封裝（或稱為上封裝或堆疊封裝）40。半導體封裝40可以透過貫通模通孔（through molding via，TMV）450電耦接至扇出中介層30。本案中使用TMV 450連接半導體封裝40和中介層30，具有更短的電連接路徑，同時半導體封裝40也可以以更短的電路徑連接到電感器40，提高電性能。
儘管已經對本發明實施例及其優點進行了詳細說明，但應當理解的是，在不脫離本發明的精神以及申請專利範圍所定義的範圍內，可以對本發明進行各種改變、替換和變更。所描述的實施例在所有方面僅用於說明的目的而並非用於限制本發明。本發明的保護範圍當視所附的申請專利範圍所界定者為准。本領域技術人員皆在不脫離本發明之精神以及範圍內做些許更動與潤飾。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1,2,40:半導體封裝 10:第一晶粒 20:第二晶粒 30:鈍化層 50:重分佈層 100:晶粒基板 102:電路組件 110:超低k層 120:ILD層 121:金屬互連層 130:鈍化層 150:TSV 201:接合墊 310:介電層 350:連接焊盤 360:電感器 G:間隙 BL:BEOL結構 SB:焊球 BP:微凸塊 MC1,MC2:模塑料 AP:導電墊 APO:開口 S1:上表面 S2:下表面 ML:金屬跡線 361:外部段 362:內部段 363:同心環間間隔 365:第一端子 366:第二端子 367:跨接聯接器 E1:第一端 E2:第二端
透過閱讀後續的詳細描述和實施例可以更全面地理解本發明，本實施例參照附圖給出，其中： 圖1是示出根據本發明的一個實施例的堆疊式晶粒封裝的示意性截面圖。 圖2示出了電感器的實施例的俯視圖。 圖3是示出根據本發明的另一實施例的堆疊式晶粒封裝的示意性截面圖。
1:半導體封裝
10:第一晶粒
20:第二晶粒
30:鈍化層
100:晶粒基板
102:電路組件
110:超低k層
120:ILD層
121:金屬互連層
130:鈍化層
150:TSV
201:接合墊
310:介電層
350:連接焊盤
360:電感器
G:間隙
BL:BEOL結構
SB:焊球
BP:微凸塊
MC1,MC2:模塑料
AP:導電墊
APO:開口
S1:上表面
S2:下表面

Claims (16)

  1. 一種半導體封裝，包括： 第一晶粒，包括上表面和與該上表面相對的下表面，其中，該第一晶粒包括貫穿第一晶粒的矽通孔； 第二晶粒，堆疊在該第一晶粒的該上表面上； 中介層，設置在該第一晶粒的該下表面上；以及 電感器，佈置在該中介層中，其中該電感器包括直接耦接到該矽通孔的端子。
  2. 如請求項1之半導體封裝，其中，該第一晶粒透過該第一晶粒的上表面上的導電焊盤和微凸塊與該第二晶粒電連接。
  3. 如請求項2之半導體封裝，其中，該微凸塊在該第二晶粒的接合焊盤與該第一晶粒的該導電焊盤之間延伸。
  4. 如請求項1之半導體封裝，其中，該第二晶粒和該第一晶粒的上表面由第一模塑料密封，該第二晶粒和該第一晶粒之間的間隙填充有該第一模塑料。
  5. 如請求項1之半導體封裝，其中，該第一晶粒包括晶粒基板，並且其中，該矽通孔穿透該晶粒基板。
  6. 如請求項5之半導體封裝，其中，該晶粒基板包括矽基板、絕緣體上矽基板或矽鍺基板。
  7. 如請求項5之半導體封裝，其中，在該晶粒基板上設置有線後端結構，並且其中，該線後端結構包括在晶粒基板上的至少一個超低介電常數層。
  8. 如請求項7之半導體封裝，其中，該線後端結構還包括在該超低介電常數層上的至少一個層間介電層。
  9. 如請求項8之半導體封裝，其中，在該層間介電層層中形成至少一個金屬互連層，並且其中，該金屬互連層的厚度小於3.0微米。
  10. 如請求項9之半導體封裝，其中，該矽通孔穿透該晶粒基板和至少該超低介電常數層，並且其中，該矽通孔電連接至該層間介電層中的該金屬互連層，該矽通孔還連接至該中介層的連接焊盤。
  11. 如請求項10之半導體封裝，其中，該連接焊盤連接至由該中介層中的金屬跡線形成的電感器，並且其中，該金屬跡線的厚度等於或大於3.0微米。
  12. 如請求項1之半導體封裝，其中，該電感器設置在該第一晶粒下方的該中介層的水平位置中。
  13. 如請求項1之半導體封裝，其中，該電感器佈置為與該第一晶粒部分重疊。
  14. 如請求項4之半導體封裝，其中，該第一晶粒、該第一模塑料以及該中介層的上表面由第二模塑料密封。
  15. 如請求項14之半導體封裝，還包括： 重分佈層，在該第二模塑料和該第二晶粒上； 半導體封裝，安裝在該重分佈層上；以及 貫通模通孔，在該第二模塑料中，其中，該半導體封裝透過該通模通孔電耦接至該中介層。
  16. 如請求項15之半導體封裝，其中，該半導體封裝包括DRAM封裝。
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