CN113782519A - 半导体封装 - Google Patents

半导体封装 Download PDF

Info

Publication number
CN113782519A
CN113782519A CN202110559835.0A CN202110559835A CN113782519A CN 113782519 A CN113782519 A CN 113782519A CN 202110559835 A CN202110559835 A CN 202110559835A CN 113782519 A CN113782519 A CN 113782519A
Authority
CN
China
Prior art keywords
die
semiconductor package
inductor
layer
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110559835.0A
Other languages
English (en)
Inventor
曾峥
柯庆忠
詹归娣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN113782519A publication Critical patent/CN113782519A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/182—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开一种半导体封装，包括：第一晶粒，包括上表面和与该上表面相对的下表面，其中，该第一晶粒包括贯穿第一晶粒的硅通孔；第二晶粒，堆叠在该第一晶粒的该上表面上；中介层，设置在该第一晶粒的该下表面上；以及电感器，布置在该中介层中，其中该电感器包括直接耦接到该硅通孔的端子。采用这种方式，电感器设置在晶粒的正面，直接通过连接焊盘与晶粒连接，这样来缩短电路径和减少面积占用。

Description

半导体封装
技术领域
本发明半导体技术领域，尤其涉及一种半导体封装。
背景技术
在集成电路应用中实现片上电感器仍然是满足高质量因子(Q factor，qualityfactor)、小面积消耗、有限的寄生耦接、易于布局和制造的要求的挑战。
常规地，在倒装晶粒封装的制造过程中使用晶粒或晶粒的互连结构的附加金属层来提高Q因子。然而，额外的金属层增加了晶粒上的面积和制造成本，并且不利地影响了制造产量。
发明内容
有鉴于此，本发明提供一种具有高性能的贯穿硅通孔(through-silicon via，TSV)电感器的改进的半导体封装，以解决上述问题。
根据本发明的第一方面，公开一种半导体封装，包括：
第一晶粒，包括上表面和与该上表面相对的下表面，其中，该第一晶粒包括多个贯穿第一晶粒的硅通孔；
第二晶粒，堆叠在该第一晶粒的该上表面上；
中介层，设置在该第一晶粒的该下表面上；以及
电感器，布置在该中介层中，其中该电感器包括直接耦接到该硅通孔的端子。
本发明的半导体封装由于包括：第一晶粒，包括上表面和与该上表面相对的下表面，其中，该第一晶粒包括多个贯穿第一晶粒的硅通孔；第二晶粒，堆叠在该第一晶粒的该上表面上；中介层，设置在该第一晶粒的该下表面上；以及电感器，布置在该中介层中，其中该电感器包括直接耦接到该硅通孔的端子。采用这种方式，电感器设置在晶粒的正面，直接通过连接焊盘与晶粒连接，这样来缩短电路径和减少面积占用。其中晶粒与电感器之间仅有例如单层的连接焊盘，而没有其他例如连接线等连接结构，电路径更短，并且电感器可以位于晶粒的竖直投影区域内，从而不增加半导体封装结构的面积大小，减少面积占用。
附图说明
图1是示出根据本发明的一个实施例的堆叠式晶粒封装的示意性截面图。
图2示出了电感器的实施例的俯视图。
图3是示出根据本发明的另一实施例的堆叠式晶粒封装的示意性截面图。
具体实施方式
以下发明提供了用于实现所提供的主题的不同特征的许多不同的实施例或示例。下面描述组件和布置的特定示例以简化本发明。当然，这些仅是示例，而无意于进行限制。例如，在下面的描述中，在第二特征之上或之上的第一特征的形成可以包括其中第一特征和第二特征形成为直接接触实施例，并且还可以包括其中在第一特征和第二特征之间形成附加特征的实施例，使得第一和第二特征可以不直接接触。另外，本发明可以在各个示例中重复参考数字和/或字母。该重复是出于简单和清楚的目的，并且其本身并不指示所讨论的各种实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在...下方”、“在...之下”、“在...下”、“在...上方”、“在...之上”之类的空间相对术语，以便于描述一个元件或特征与之的关系。如图所示的另一元件或特征。除了在图中描述的方位之外，空间相对术语还意图涵盖设备在使用或操作中的不同方位。该装置可以以其他方式定向(旋转90度或以其他定向)，并且在此使用的空间相对描述语可以同样地被相应地解释。另外，还将理解的是，当层被称为在两层“之间”时，它可以是两层之间的唯一层，或者也可以存在一个或多个中间层。
本文所使用的术语仅出于描述特定实施例的目的，并不旨在限制本发明构思。如本文所使用的，单数形式“一个”、“一种”和“该”也旨在包括复数形式，除非上下文另外明确指出。还将理解，术语“包括”和/或“包含”在本说明书中使用时，指定存在该特征，整数，步骤，操作，元件和/或组件，但是不排除存在或添加一个或多个其他特征，整数，步骤，操作，元素，组件和/或其组。如本文所使用的，术语“和/或”包括一个或多个相关联的所列项目的任何和所有组合，并且可以缩写为“/”。
将理解的是，当将元件或层称为在另一元件或层“上”，“连接至”，“耦接至”或“邻近”时，它可以直接在其他元素或层上，与其连接，耦接或相邻，或者可以存在中间元素或层。相反，当元件称为“直接在”另一元件或层“上”，“直接连接至”，“直接耦接至”或“紧邻”另一元件或层时，则不存在中间元件或层。
注意：(i)在整个附图中相同的特征将由相同的附图标记表示，并且不一定在它们出现的每个附图中都进行详细描述，并且(ii)一系列附图可能显示单个项目的不同方面，每个方面都与各种参考标签相关联，这些参考标签可能会出现在整个序列中，或者可能只出现在序列的选定图中。
本发明涉及包括第一晶粒和堆叠在第一晶粒上的第二晶粒的堆叠晶粒封装。提出的电感器设计为放置在扇出中介层中的第一个晶粒的背面，以有效利用硅面积，并且可以通过TSV连接到下方晶粒的正面(front side)电路。本案将电感器设置在晶粒的正面，直接通过连接焊盘与晶粒连接，这样来缩短电路径和减少面积占用。其中晶粒与电感器之间仅有例如单层的连接焊盘，而没有其他例如连接线等连接结构，电路径更短，并且电感器可以位于晶粒的竖直投影区域内，从而不增加半导体封装结构的面积大小，减少面积占用。
请参考图1，图1为绘示依照本发明实施例的一种堆叠式晶粒封装(或半导体封装)1的剖面示意图。如图1所示，堆叠式晶粒封装或半导体封装1包括第一晶粒10和堆叠在第一晶粒10上的第二晶粒20。根据一个实施例，第一晶粒10和第二晶粒20执行不同的功能并且通过以不同的制程节点技术中制造，例如，第一晶粒10可以是通过5nm制程制造的调制解调器晶粒，第二晶粒20可以是通过3nm制程制造的处理器晶粒，但不限于此。如在右侧的圆形区域中所示，该圆形区域示出了堆叠式晶粒封装1的一部分的放大图，第一晶粒10具有上表面S1和与上表面S1相对的下表面S2。第二晶粒20安装在上表面S1上。
第一晶粒10可以通过第一晶粒10的上表面S1上的导电焊盘AP和微凸块BP电连接至第二晶粒20。微凸块BP在第二晶粒20的接合垫(或接合焊盘)201和第一晶粒10的导电垫AP之间延伸。根据一些实施例，可以在接合垫201和导电垫AP之间进一步提供焊料层SP，但不限于此。在一些实施例中，导电垫(或导电焊盘)AP可以由铝制成，但是不限于此。第二晶粒20和第一晶粒10之间的间隙G可以填充有密封剂或模塑料MC1，但不限于此。
第一晶粒10包括晶粒基板100。晶粒基板100可以是半导体基板，例如，硅基板。应该理解，可以使用其他类型的半导体基板。例如，在一些实施例中，晶粒基板100可以是绝缘体上硅、硅锗或其他类型的半导体基板。电路组件102可以形成在晶粒基板100上或内部。例如，电路组件102可以包括具有栅极和源极/漏极区域的晶体管。
线后端(back-end of line，BEOL)结构BL设置在晶粒基板100上。根据一个实施例，例如，BEOL结构BL包括形成在其上的至少一个超低介电常数(超低k)层110。例如，根据一个实施例，超低k层110可以具有小于2.6的介电常数，例如小于2.55，但是不限于此。BEOL结构BL可以进一步包括至少一个层间介电(inter-layer dielectric，ILD)层120，例如形成在超低k层110上的未掺杂的硅酸盐玻璃(un-doped silicate glass，USG)层。ILD层120可以具有大约3.3的介电常数，但是不限于此。可以在ILD层120中形成至少一个金属互连层121。例如，金属互连层121可以具有大约2.8微米的厚度。例如，金属互连层121可以具有小于2.8微米的厚度。例如，金属互连层121可以具有小于3.0微米的厚度。可以在ILD层120上形成导电焊盘AP。可以在ILD层120上形成诸如氮化硅层的钝化层130。可以在钝化层130中提供开口APO以部分地暴露导电焊盘AP。可以通过开口APO在导电焊盘AP上形成微凸块BP。
根据一个实施例，第一晶粒10还包括多个硅通孔(through silicon via，TSV)150。TSV 150穿过晶粒基板100和至少超低k层110。TSV 150可以电连接至ILD层120中的金属互连层121。每个TSV 150的另一端可以连接至设置在第一晶粒10下表面S2上之扇出中介层(fan-out interposer layer)(或重分布层(re-distribution layer))30的连接焊盘350。根据一个实施例，连接焊盘350可以进一步连接到由扇出中介层30中的金属迹线ML形成的电感器360。例如，电感器360设置在第一晶粒10下表面S2下方的扇出插入层30的水平高度(horizontal level)。扇出中介层30的介电层310将电感器360与晶粒基板100分开。在一些实施例中，介电层310由高分子材料制成。TSV 150可以用于连接电感器360(例如通过连接焊盘350)与第二晶粒20(例如通过金属互连层121、导电焊盘AP、微凸块BP和接合垫201等)，这样可以使第二晶粒20与电感器360之间电连接路径更短，提高电性能。
图2示出了示例性电感器的俯视图。电感器360例如包括形成第一和第二同心环的金属迹线ML。根据一个实施例，金属迹线ML具有等于或大于3.0微米的厚度。同心环包括电感器电路的几何形状。包括至少一个外部段361和至少一个内部段362的同心环由同心环间间隔363隔开。电感器360包括第一和第二端子365和366。电感器360的第一端子365和第二端子366耦接到外部段361的第一端E1。外部段361的第二端E2通过跨接联接器367联接到内部段362的第二端E2。跨接耦接器367例如设置在扇出中介层30的第二平面水平面上，该第二水平面不同于形成电感器360的同心环的第一水平面上。第一端子365和第二端子366直接连接到对应的TSV 150。
如上所述，电感器360是出于说明的目的，而不应限于此。电感器360可以包括其他合适类型的配置。例如，电感器360可以形成在多个金属层上。
如图1所示，扇出中介层(或重分布层)30可以用于将第一晶粒10的端子在第二表面S2上从更紧密的间距散布为更松散的间距。在扇出中介层30的下表面S3上，可以设置多个焊球SB以进一步连接。第一晶粒10和第二晶粒20可以由模塑料MC2密封。第一晶粒10、模塑料MC1和扇出中介层30的上表面由模塑料MC2密封。模塑料MC2的底表面可以与第一晶粒10的下表面S2大致齐平。扇出中介层(interposer)30设置在模塑料MC2的底表面上和第一模子的下表面S2上。第一晶粒10的TSV 150的下端电连接至扇出中介层30的金属层。优选地，电感器360直接设置在第一晶粒10的下面，以在电感器360和第一晶粒10之间形成较短的电路径，并且将提供更好的芯片性能。应当理解，在一些实施例中，电感器360可以与第一晶粒10部分重叠，以便在第一晶粒10和电感器360之间实现较短的电路径。电感器360可以与第一晶粒10也可以完全重叠或至少部分重叠。
请参考图3，图3为根据本发明另一实施例的堆叠式晶粒封装2的剖面示意图，其中相同的元件，区域或层以相同的数字或标号标示。同样地，如图3所示，堆叠式晶粒封装或半导体封装2包括第一晶粒10和堆叠在第一晶粒10上的第二晶粒20。第一晶粒10可以通过微凸块BP电连接至第二晶粒20。电感器360设置在第一晶粒10下方的扇出中介层30中。电感器360的端子直接耦接到穿透第一晶粒10的对应的TSV 150。堆叠的晶粒封装2还包括在模塑料MC2和第二晶粒20上的重分布层50。可以在重新分布层50上安装诸如存储器封装或DRAM封装之类的半导体封装(或称为上封装或堆叠封装)40。半导体封装40可以通过贯通模通孔(through molding via，TMV)450电耦接至扇出中介层30。本案中使用TMV 450连接半导体封装40和中介层30，具有更短的电连接路径，同时半导体封装40也可以以更短的电路径连接到电感器40，提高电性能。
本领域的技术人员将容易地观察到，在保持本发明教导的同时，可以做出许多该装置和方法的修改和改变。因此，上述公开内容应被解释为仅由所附权利要求书的界限和范围所限制。

Claims (16)

1.一种半导体封装，其特征在于，包括：
第一晶粒，包括上表面和与该上表面相对的下表面，其中，该第一晶粒包括贯穿第一晶粒的硅通孔；
第二晶粒，堆叠在该第一晶粒的该上表面上；
中介层，设置在该第一晶粒的该下表面上；以及
电感器，布置在该中介层中，其中该电感器包括直接耦接到该硅通孔的端子。
2.如权利要求1所述的半导体封装，其特征在于，该第一晶粒通过该第一晶粒的上表面上的导电焊盘和微凸块与该第二晶粒电连接。
3.如权利要求2所述的半导体封装，其特征在于，该微凸块在该第二晶粒的接合焊盘与该第一晶粒的该导电焊盘之间延伸。
4.如权利要求1所述的半导体封装，其特征在于，该第二晶粒和该第一晶粒的上表面由第一模塑料密封，该第二晶粒和该第一晶粒之间的间隙填充有该第一模塑料。
5.如权利要求1所述的半导体封装，其特征在于，该第一晶粒包括晶粒基板，并且其中，该硅通孔穿透该晶粒基板。
6.如权利要求5所述的半导体封装，其特征在于，该晶粒基板包括硅基板、绝缘体上硅基板或硅锗基板。
7.如权利要求5所述的半导体封装，其特征在于，在该晶粒基板上设置有线后端结构，并且其中，该线后端结构包括在晶粒基板上的至少一个超低介电常数层。
8.如权利要求7所述的半导体封装，其特征在于，该线后端结构还包括在该超低介电常数层上的至少一个层间介电层。
9.如权利要求8所述的半导体封装，其特征在于，在该层间介电层层中形成至少一个金属互连层，并且其中，该金属互连层的厚度小于3.0微米。
10.如权利要求9所述的半导体封装，其特征在于，该硅通孔穿透该晶粒基板和至少该超低介电常数层，并且其中，该硅通孔电连接至该层间介电层中的该金属互连层，该硅通孔还连接至该中介层的连接焊盘。
11.如权利要求10所述的半导体封装，其特征在于，该连接焊盘连接至由该中介层中的金属迹线形成的电感器，并且其中，该金属迹线的厚度等于或大于3.0微米。
12.如权利要求1所述的半导体封装，其特征在于，该电感器设置在该第一晶粒下方的该中介层的水平位置中。
13.如权利要求1所述的半导体封装，其特征在于，该电感器布置为与该第一晶粒部分重叠。
14.如权利要求4所述的半导体封装，其特征在于，该第一晶粒、该第一模塑料以及该中介层的上表面由第二模塑料密封。
15.如权利要求14所述的半导体封装，其特征在于，还包括：
重分布层，在该第二模塑料和该第二晶粒上；
半导体封装，安装在该重分布层上；以及
贯通模通孔，在该第二模塑料中，其中，该半导体封装通过该通模通孔电耦接至该中介层。
16.如权利要求15所述的半导体封装，其特征在于，该半导体封装包括DRAM封装。
CN202110559835.0A 2020-06-09 2021-05-21 半导体封装 Pending CN113782519A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202063036526P 2020-06-09 2020-06-09
US63/036,526 2020-06-09
US17/319,078 2021-05-12
US17/319,078 US11715754B2 (en) 2020-06-09 2021-05-12 Semiconductor package with TSV inductor

Publications (1)

Publication Number Publication Date
CN113782519A true CN113782519A (zh) 2021-12-10

Family

ID=76059642

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110559835.0A Pending CN113782519A (zh) 2020-06-09 2021-05-21 半导体封装

Country Status (4)

Country Link
US (2) US11715754B2 (zh)
EP (1) EP3923323A3 (zh)
CN (1) CN113782519A (zh)
TW (1) TWI752884B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024144917A1 (en) * 2022-12-26 2024-07-04 Western Digital Technologies, Inc. Tsv semiconductor device including inductive compensation loops

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11715754B2 (en) * 2020-06-09 2023-08-01 Mediatek Inc. Semiconductor package with TSV inductor
CN117810209A (zh) * 2022-09-22 2024-04-02 长鑫存储技术有限公司 半导体封装结构

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140134804A1 (en) * 2012-11-15 2014-05-15 Michael G. Kelly Method And System For A Semiconductor For Device Package With A Die-To-Packaging Substrate First Bond
US20140264716A1 (en) * 2013-03-15 2014-09-18 Advanced Semiconductor Engineering, Inc. Semiconductor wafer, semiconductor process and semiconductor package
US20140264733A1 (en) * 2013-03-14 2014-09-18 GLOBALFOUNDERS Singapore Pte. Ltd. Device with integrated passive component
US20150115405A1 (en) * 2013-10-31 2015-04-30 Qualcomm Incorporated Wireless interconnects in an interposer
US20160049385A1 (en) * 2014-08-15 2016-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and methods of manufacture thereof
US9330823B1 (en) * 2011-12-19 2016-05-03 Xilinx, Inc. Integrated circuit structure with inductor in silicon interposer
US20190131273A1 (en) * 2017-10-27 2019-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-chip wafer level packages and methods of forming the same

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8168529B2 (en) * 2009-01-26 2012-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. Forming seal ring in an integrated circuit die
US8357564B2 (en) * 2010-05-17 2013-01-22 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die
US9059026B2 (en) 2010-06-01 2015-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. 3-D inductor and transformer
US8384227B2 (en) * 2010-11-16 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die
US8823133B2 (en) * 2011-03-29 2014-09-02 Xilinx, Inc. Interposer having an inductor
US20130015871A1 (en) * 2011-07-11 2013-01-17 Cascade Microtech, Inc. Systems, devices, and methods for two-sided testing of electronic devices
US9406738B2 (en) * 2011-07-20 2016-08-02 Xilinx, Inc. Inductive structure formed using through silicon vias
KR20130037609A (ko) * 2011-10-06 2013-04-16 한국전자통신연구원 하부 인덕터를 포함하는 실리콘 인터포저
US9391010B2 (en) * 2012-04-02 2016-07-12 Taiwan Semiconductor Manufacturing Co., Ltd. Power line filter for multidimensional integrated circuits
US10236209B2 (en) * 2014-12-24 2019-03-19 Intel Corporation Passive components in vias in a stacked integrated circuit package
KR20160080965A (ko) * 2014-12-30 2016-07-08 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9627365B1 (en) * 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
WO2018125213A1 (en) * 2016-12-30 2018-07-05 Intel Corporation Recessed semiconductor die in a die stack to accommodate a component
KR102663810B1 (ko) 2016-12-30 2024-05-07 삼성전자주식회사 전자 소자 패키지
WO2019066985A1 (en) * 2017-09-30 2019-04-04 Intel Corporation MINIMUM REDUCTION IN INSERTION LOSS VARIATION IN SILICON CONNECTION HOLES (TSV)
US10504784B2 (en) 2017-10-25 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Inductor structure for integrated circuit
CN109712943B (zh) 2017-10-26 2020-11-20 联发科技股份有限公司 半导体封装组件
US11715754B2 (en) * 2020-06-09 2023-08-01 Mediatek Inc. Semiconductor package with TSV inductor

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9330823B1 (en) * 2011-12-19 2016-05-03 Xilinx, Inc. Integrated circuit structure with inductor in silicon interposer
US20140134804A1 (en) * 2012-11-15 2014-05-15 Michael G. Kelly Method And System For A Semiconductor For Device Package With A Die-To-Packaging Substrate First Bond
US20140264733A1 (en) * 2013-03-14 2014-09-18 GLOBALFOUNDERS Singapore Pte. Ltd. Device with integrated passive component
US20140264716A1 (en) * 2013-03-15 2014-09-18 Advanced Semiconductor Engineering, Inc. Semiconductor wafer, semiconductor process and semiconductor package
US20150115405A1 (en) * 2013-10-31 2015-04-30 Qualcomm Incorporated Wireless interconnects in an interposer
US20160049385A1 (en) * 2014-08-15 2016-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and methods of manufacture thereof
US20190131273A1 (en) * 2017-10-27 2019-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-chip wafer level packages and methods of forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024144917A1 (en) * 2022-12-26 2024-07-04 Western Digital Technologies, Inc. Tsv semiconductor device including inductive compensation loops

Also Published As

Publication number Publication date
US20240079444A1 (en) 2024-03-07
EP3923323A3 (en) 2022-01-12
US11715754B2 (en) 2023-08-01
US20210384291A1 (en) 2021-12-09
EP3923323A2 (en) 2021-12-15
TWI752884B (zh) 2022-01-11
TW202147557A (zh) 2021-12-16

Similar Documents

Publication Publication Date Title
US11935802B2 (en) Integrated circuit package and method of forming same
US10971371B2 (en) Multi-chip structure and method of forming same
US11532594B2 (en) Integrated fan-out package and the methods of manufacturing
US11282784B2 (en) Semiconductor package and manufacturing method of the same
US11532598B2 (en) Package structure with protective structure and method of fabricating the same
CN113782519A (zh) 半导体封装
US11862605B2 (en) Integrated circuit package and method of forming same
TW202117866A (zh) 半導體封裝
TW202105663A (zh) 積體電路封裝
US12062608B2 (en) Semiconductor packages
US11362069B2 (en) Three-dimensional stacking structure and manufacturing method thereof
TW202230540A (zh) 封裝結構及其製造方法
US9929081B2 (en) Interposer fabricating process
US20240321794A1 (en) Semiconductor chip having a through electrode and semiconductor package including the semiconductor chip
US20230082412A1 (en) Semiconductor package
CN114050145A (zh) 半导体封装结构及其制造方法
US20240055378A1 (en) Semiconductor chip and semiconductor package including the same
US20240332176A1 (en) Semiconductor Packages and Methods of Forming the Same
US20230069511A1 (en) Semiconductor package
US20230253303A1 (en) Semiconductor Package and Method of Manufacture
US20240145418A1 (en) Semiconductor package
US20240120315A1 (en) Semiconductor devices and methods of manufacturing thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination