TW202145569A - 半導體元件 - Google Patents

半導體元件 Download PDF

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TW202145569A
TW202145569A TW110119031A TW110119031A TW202145569A TW 202145569 A TW202145569 A TW 202145569A TW 110119031 A TW110119031 A TW 110119031A TW 110119031 A TW110119031 A TW 110119031A TW 202145569 A TW202145569 A TW 202145569A
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Taiwan
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layer
fin
semiconductor
gate
structures
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TW110119031A
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English (en)
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楊建勳
建倫 楊
張克正
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台灣積體電路製造股份有限公司
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Publication of TW202145569A publication Critical patent/TW202145569A/zh

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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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Abstract

本揭露描述一種半導體元件，其包括第一鰭片結構、隔離結構接觸第一鰭片結構的頂面、基底層接觸隔離結構、磊晶層接觸隔離結構和基底層、以及第二鰭片結構於第一鰭片結構之上並接觸磊晶層。

Description

半導體元件
本發明實施例是關於半導體結構及其形成方法，特別是關於堆疊的半導體元件。
隨著半導體技術的演進，增加了具有較高儲存容量、更快處理系統、較高性能、以及較低成本的需求。為了符合這些需求，半導體業界持續縮小半導體元件的尺寸，如金屬氧化物半導體場效電晶體（metal oxide semiconductor field effect transistor, MOSFET），包括平面金屬氧化物半導體場效電晶體和鰭式場效電晶體（fin field effect transistor, finFET）。這樣的縮小增加了半導體製造過程的複雜度。
一種半導體元件，包括：第一鰭片結構；隔離結構，接觸第一鰭片結構的頂面；基底層，接觸隔離結構；磊晶層，接觸隔離結構和基底層；以及第二鰭片結構，於第一鰭片結構之上並接觸磊晶層。
一種半導體元件，包括：第一鰭片結構；第一隔離結構，於第一鰭片結構的頂面上；基底層，於第一隔離結構上；第一磊晶層，於第一隔離結構和基底層上；第二隔離結構，於第一磊晶層上；第二磊晶層，於第二隔離結構上；以及第二鰭片結構，於第一鰭片結構上並接觸第二磊晶層。
一種半導體元件的形成方法，包括：形成第一鰭片結構；形成基底層於第一鰭片結構上；形成隔離結構於基底層和第一鰭片結構之間；形成磊晶層接觸隔離結構和基底層；以及形成第二鰭片結構於第一鰭片結構上並接觸磊晶層。
以下揭露提供了許多不同的實施例或範例，用於實施所提供事務的不同部件。組件和配置的具體範例描述如下，以簡化本揭露實施例。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例來說，敘述中提及第一部件形成於第二部件之上，可包括形成第一和第二部件直接接觸的實施例，也可包括額外的部件形成於第一和第二部件之間，使得第一和第二部件不直接接觸的實施例。如於此所使用，在第二部件上形成第一部件表示第一部件的形成是直接接觸第二部件。此外，本揭露可在各種範例中重複參考符號及∕或字母。這樣的重複本身並非主導所討論各種實施例及∕或配置之間的關係。
再者，此處可使用空間上相關的用語，例如「在…下方」、「下方的」、「低於」、「高於」、「上方的」、和類似用語，以便描述一元件或部件和其他元件或部件之間的關係，如在圖式中所示。空間上相關的用語企圖涵蓋這些元件除了在圖式中描繪的方位以外的不同方位。當裝置被轉至其他方位（旋轉90°或其他方位），則在此所使用的空間相對描述可同樣依旋轉後的方位來解讀。
應注意的是，在說明書所參考的「實施例」、「一實施例」、「範例實施例」、「例示的」等，表示所述實施例可包括特定的特徵、結構、或特性，但每個實施例可非必要地包括其特定的特徵、結構、或特性。此外，這些用語並不必要參照至相同的實施例。再者，當描述特定的特徵、結構、或特性連結至一實施例時，在本發明所屬技術領域中具有通常知識者的知識範圍內可將其特徵、結構、或特性連結至另外的實施例，無論是否有明確的描述。
應能理解，本文的措辭或術語是出於描述的目的而非用以限制，因此說明書的術語或措辭將由本發明所屬技術領域中具有通常知識者根據本文的教示進行解釋。
此處所使用的用語「標稱上的（nominal）」，表示在產品或製程的設計階段期間所設定之組件或製程步驟的特徵或參數之期望值或目標值，以及高於及/或低於此期望值之數值範圍。此數值範圍一般是由製造過程或容許差度的所造成的微小變化。
如本文所使用的，用詞「蝕刻選擇比」指的是在相同蝕刻條件下兩個不同材料的蝕刻速率比例。
如本文所使用的，用詞「基底」描述一種材料，其後續材料層將疊加於其上。可圖案化基底本身。在基底頂部增加的材料可被圖案化或維持不被圖案化。再者，基底可為半導體材料的廣範系列，如矽、鍺、砷化鎵、磷化銦等。替代地，基底可由非導電材料形成，如玻璃和藍寶石晶圓。
如本文所使用的，用詞「高介電常數（high-k）」指的是高介電常數值。在半導體裝置結構與製程領域中，高介電常數指的是介電常數大於SiO2 的介電常數（例如，大於約3.9）。
如本文所使用的，用詞「低介電常數（low-k）」指的是低介電常數值。在半導體裝置結構與製程領域中，低介電常數指的是介電常數小於SiO2 的介電常數（例如，小於約3.9）。
如本文所使用的，用詞「P型」定義的是以如硼的P型摻質所摻雜的結構、膜層、及∕或區域。
如本文所使用的，用詞「N型」定義的是以如磷的N型摻質所摻雜的結構、膜層、及∕或區域。
如本文所使用的，用詞「垂直的」表示標稱上沿著垂直於基底表面的方向。
如本文所使用的，用詞「交叉」表示多個結構沿其方向在一個點交叉。
如本文所使用的，用詞「約」和「大抵」可表示給定量的數值可基於目標半導體裝置相關的特定技術節點而改變。在一些實施例中，基於特定的技術節點，「約」和「大抵」的用語可表示給定量的數值的差異介於目標值的5%以內（例如目標值的±1%、±2%、±3%、±4%、±5%）。
於此所揭露的鰭片結構的實施例可藉由任何合適的方法圖案化。舉例來說，可使用一或多個光微影製程（包括雙重圖案化或多重圖案化製程）圖案化鰭片結構。雙重圖案化或多重圖案化製程結合了光微影和自對準製程，比使用單一或直接光微影製程所得的節距更小的圖案。舉例來說，在基底上形成犧牲層，並使用光微影製程對其進行圖案化。使用自對準製程在圖案化後的犧牲層旁邊形成間隔物。之後，移除犧牲層，然後可使用剩餘的間隔物作為遮罩以圖案化鰭片結構。
隨著半導體技術的演進，已導入多重閘極元件，藉由增加閘極通道耦合、減少改善關閉狀態電流、以及減少短通道效應（short-channel effect, SCE）而改善閘極控制。已導入多重閘極元件的其中一個為全繞式閘極鰭式場效電晶體（gate-all-around fin field effect transistor, GAA finFET）。全繞式閘極鰭式場效電晶體在堆疊奈米片∕奈米線配置中提供通道。全繞式閘極鰭式場效電晶體係由閘極結構延伸圍繞通道並在通道的兩側或四側上提供通道的閘極控制以衍生出其名稱。全繞式閘極鰭式場效電晶體與金屬氧化物半導體場效電晶體的製造過程相容，其允許結構縮小，而維持閘極控制並緩解短通道效應。
全繞式閘極鰭式場效電晶體可為平面全繞式閘極鰭式場效電晶體，其具有在同一個平面中的N型和P型全繞式閘極鰭式場效電晶體，並由同一個堆疊的奈米片∕奈米線製造。隨著半導體元件較低功率消耗、高性能、以及小面積（統稱為功率、性能、面積（power performance area, PPA））的需求的增加，平面全繞式閘極鰭式場效電晶體有其挑戰性。舉例來說，N型和P型平面全繞式閘極鰭式場效電晶體具有相同的奈米片∕奈米線尺寸和堆疊奈米片∕奈米線之間的間距，因而對於N型和P型功函數填充物具有相同間距。N型和P型全繞式閘極鰭式場效電晶體可能需要不同間距以在N型和P型功函數填充物中提供彈性。此外，N型和P型平面全繞式閘極鰭式場效電晶體具有相同介電常數（也被稱為k值）的內間隔物材料。N型和P型全繞式閘極鰭式場效電晶體針對不同元件性能需求可能需要不同的內間隔物材料。此外，在平面全繞式閘極鰭式場效電晶體的蝕刻製程期間，奈米片∕奈米線混合的臨界電壓（threshold voltage）的邊界可能會偏移。奈米片∕奈米線混合的臨界電壓的邊界偏移可降低平面全繞式閘極鰭式場效電晶體的元件性能。再者，平面全繞式閘極鰭式場效電晶體具有相同的奈米片∕奈米線尺寸和堆疊奈米片∕奈米線之間的間距，但多重臨界電壓需要不同厚度的功函數金屬。因此，透過功函數金屬奈米片∕奈米線圖案化在平面全繞式閘極鰭式場效電晶體中包含多重臨界電壓可能具有挑戰性。
根據本揭露的各種實施例提供堆疊半導體元件的形成方法。根據一些實施例，堆疊半導體元件可包括在沿著一個方向的底部鰭片結構的頂部上垂直堆疊沿著相同方向的頂部鰭片結構（被稱為垂直堆疊）。在一些實施例中，垂直堆疊的頂部和底部鰭片結構可各自獨立地控制其奈米片∕奈米線的尺寸和間距。在一些實施例中，可在沿著第二方向旋轉的底部鰭片結構的頂部上堆疊沿著第一方向旋轉的頂部鰭片結構，其中第一方向和第二方向相對於彼此旋轉約90°。這於此也被稱為「交叉堆疊」。在一些實施例中，交叉堆疊半導體元件可針對頂部和底部鰭片結構提供緊湊的金屬互連位置和路由，因此改善PPA的表現。在一些實施例中，交叉堆疊的半導體元件可包括頂部閘極結構，相對於底部閘極結構旋轉一些角度，例如約90°（被稱為旋轉閘極）。在一些實施例中，具有旋轉閘極的交叉堆疊半導體元件可提供更加緊湊的金屬互連路由和位置以減少寄生電阻和電容，因而改善PPA的表現。在一些實施例中，隔離層可隔離頂部鰭片結構和底部鰭片結構。在一些實施例中，在頂部鰭片結構和底部鰭片結構之間的額外隔離層可改善隔離。
第1A圖是根據一些實施例，繪示垂直堆疊半導體元件100的等距示意圖，其具有在全繞式閘極鰭式場效電晶體102A上垂直堆疊的全繞式閘極鰭式場效電晶體102B。第1B圖是根據一些實施例，繪示垂直堆疊半導體元件100沿著線段B-B的部分剖面示意圖。在一些實施例中，第1A和1B圖繪示部分積體電路（integrated circuit, IC）佈局，其中鰭片結構之間的間距（例如鰭片節距）、鰭片結構的尺寸、以及閘極結構的尺寸可與第1A和1B圖所示相似或不同。此外，在第1A和1B圖中的半導體元件100的等距和剖面示意圖以及後續圖式為例示性目的。第1A和1B圖和後續圖式可能未反映實際結構、部件、或膜層的實際幾何。
參照第1A和1B圖，垂直堆疊半導體元件100可包括全繞式閘極鰭式場效電晶體102A和102B、源極∕汲極互連件103和105連接至全繞式閘極鰭式場效電晶體102A和102B、閘極結構112、以及閘極互連件111連接至閘極結構112。全繞式閘極鰭式場效電晶體102A和102B可進一步包括鰭片結構104A和104B、閘極結構112A和112B、內間隔物結構116A和116B、隔離結構120、摻雜層126、以及半導體層128。
在一些實施例中，全繞式閘極鰭式場效電晶體102A和102B可皆為P型鰭式場效電晶體（p-type fin field effect transistor, PFET）、皆為N型鰭式場效電晶體（n-type fin field effect transistor, NFET）、或是每個導電類型都有的鰭式場效電晶體。在一些實施例中，全繞式閘極鰭式場效電晶體102A可為P型（也被稱為P型鰭式場效電晶體102A），而全繞式閘極鰭式場效電晶體102B可為N型（也被稱為N型鰭式場效電晶體102B）。儘管第1A和1B圖繪示兩種全繞式閘極鰭式場效電晶體，垂直堆疊半導體元件100可具有任何數量的全繞式閘極鰭式場效電晶體。另外，儘管第1A和1B圖繪示一個閘極結構112，垂直堆疊半導體元件100可具有額外的閘極結構，其與閘極結構112類似並與閘極結構112平行。此外，半導體元件100可透過使用其他結構組件被納入積體電路中，其結構組件如接觸件、導孔、導線、介電層、鈍化層等，為了簡單起見未繪示。全繞式閘極鰭式場效電晶體102A和102B具有相同標號部件的討論可適用於彼此，除非另外提及。
如第1A圖所示，可在基底106上形成全繞式閘極鰭式場效電晶體102A。基底106可為半導體材料，如矽。在一些實施例中，基底106可包括結晶矽基底（例如晶圓）。在一些實施例中，基底106可包括：（1）元素半導體，如鍺（Ge）；（2）化合物半導體，包括碳化矽（SiC）、砷化矽（SiAs）、砷化鎵（GaAs）、磷化鎵（GaP）、磷化銦（InP）、砷化銦（InAs）、銻化銦（InSb）、及∕或III-V族半導體材料；（3）合金半導體，包括矽鍺（SiGe）、碳化矽鍺（SiGeC）、鍺錫（GeSn）、鍺錫化矽（SiGeSn）、砷磷化鎵（GaAsP）、磷化鎵銦（GaInP）、砷化鎵銦（GaInAs）、砷磷化鎵銦（GaInAsP）、砷化鋁銦（AlInAs）、及∕或砷化鋁鎵（AlGaAs）；（4）絕緣層上矽（silicon-on-insulator, SOI）結構；（5）絕緣層上矽鍺結構；（6）絕緣層上鍺結構；或（7）其組合。再者，可摻雜基底106，取決於設計需求（例如P型基底或N型基底）。在一些實施例中，可以P型摻質（例如硼、銦、鋁、或鎵）或N型摻質（例如磷或砷）摻雜基底106。
如第1A和1B圖所示，可在磊晶層130、半導體層128、以及摻雜層126上形成全繞式閘極鰭式場效電晶體102B。在一些實施例中，半導體層128和摻雜層126可作為全繞式閘極鰭式場效電晶體102B的基底層127。摻雜層126可設置在全繞式閘極鰭式場效電晶體102A上，且包括與基底106類似或不同的半導體材料。在一些實施例中，摻雜層126可包括矽。在一些實施例中，摻雜層126的半導體材料可在磊晶成長製程期間使用（1）P型摻質（如硼、銦、或鎵）；及∕或（2）N型摻質（如磷或砷）以原位（in-situ）摻雜。針對P型原位摻雜，可使用如二硼烷（diborane, B2 H6 ）、三氟化硼（boron trifluoride, BF3 ）、或其他P型摻雜前驅物（precursor）。針對N型原位摻雜，可使用如膦（phosphine, PH3 ）、胂（arsine, AsH3 ）、或其他N型摻雜前驅物。摻雜層126可沿著Z軸具有約5nm至10nm範圍的垂直尺寸126t（例如厚度）。在一些實施例中，可以與基底106不同的導電類型摻雜摻雜層126，如基底106為N型而摻雜層126為P型。在一些實施例中，摻雜層126可作為全繞式閘極鰭式場效電晶體102B的佈植井。摻雜層126的其他尺寸、材料、以及摻雜類型皆於本揭露的範圍和精神之內。
可在摻雜層126上設置半導體層128，其包括與摻雜層126類似或不同的半導體材料。在一些實施例中，半導體層128可包括矽。半導體層128的半導體材料可為未摻雜或可使用類似摻雜層126的磊晶成長製程原位摻雜。半導體層128可沿著Z軸具有約12nm至20nm範圍的厚度128t。在一些實施例中，半導體層128可助於後續磊晶層130和鰭片結構104B的成長。
可在半導體層128和隔離結構120上設置磊晶層130。在一些實施例中，可磊晶成長磊晶層130，類似於半導體層128。在一些實施例中，磊晶層130可包括矽，而沒有任何實質量的鍺。在一些實施例中，可在半導體層128上磊晶成長磊晶層130，並與隔離結構120在磊晶鰭片區110A上的部分合併。在一些實施例中，磊晶層130可沿著Z軸具有約10nm至20nm範圍的厚度130t。
半導體元件100可更包括鰭片結構104A和104B沿著X軸延伸，且分別穿過全繞式閘極鰭式場效電晶體102A和102B。在一些實施例中，鰭片結構104A和104B可各包括堆疊鰭片部108A和108B以及磊晶鰭片區110A和110B。每個堆疊鰭片部108A和108B可包括半導體層122A和122B的堆疊，其可為奈米片或奈米線的形式。每個半導體層122A和122B可分別形成在全繞式閘極鰭式場效電晶體102A和102B的閘極結構112A和112B下方的通道區。
在一些實施例中，半導體層122A和122B可包括類似或不同於基底106的半導體材料。在一些實施例中，每個半導體層122A和122B可包括矽鍺（SiGe），其鍺在約5原子百分比至50原子百分比的範圍，而任何剩餘的原子百分比為矽，或可包括矽而未有任何實質量的鍺。半導體層122A和122B的半導體材料可為未摻雜或可使用類似摻雜層126的磊晶成長製程原位摻雜。半導體層122A和122B可個別沿著Z軸具有約5nm至12nm範圍的厚度122At和122Bt。半導體層122A和122B也可個別沿著Z軸在彼此之間具有約6nm至16nm範圍的間距122As和122Bs。半導體層122A和122B的其他尺寸和材料皆於本揭露的範圍和精神之內。儘管在第1A和1B圖中的每個全繞式閘極鰭式場效電晶體102A和102B繪示三個半導體層122A和122B，全繞式閘極鰭式場效電晶體102A和102B可各具有任何數量的半導體層122A和122B。
參照第1A和1B圖，可分別設置磊晶鰭片區110A和110B鄰近堆疊鰭片部108A和108B。在一些實施例中，磊晶鰭片區110A和110B可具有任何幾何形狀，如多邊形、橢圓形、或圓形。磊晶鰭片區110A和110B可包括磊晶成長的半導體材料。在一些實施例中，磊晶成長的半導體材料與基底106的材料相同。在一些實施例中，磊晶成長的半導體材料包括與基底106的材料不同。在一些實施例中，磊晶鰭片區110A和110B的磊晶成長的半導體材料可彼此相同或不同。磊晶成長的半導體材料可包括：（1）半導體材料，如鍺或矽；（2）化合物半導體材料，如砷化鎵或砷化鋁鎵；或（3）半導體合金，如矽鍺或砷磷化鎵。
在一些實施例中，磊晶鰭片區110A可為P型鰭式場效電晶體102A的P型（也被稱為P型磊晶鰭片區110A），而磊晶鰭片區110B可為N型鰭式場效電晶體102B的N型（也被稱為N型磊晶鰭片區110B）。在一些實施例中，P型磊晶鰭片區110A可包括矽鍺，且可在磊晶成長製程期間使用P型摻質（如硼、銦、或鎵）原位摻雜。在一些實施例中，P型磊晶鰭片區110A可具有多重次區，其可包括矽鍺，並可基於例如摻雜濃度、磊晶成長製程條件、及∕或鍺對矽的相對濃度彼此不同。
在一些實施例中，N型磊晶鰭片區110B可包括矽，且可在磊晶成長製程期間使用N型摻質（如磷或砷）原位摻雜。在一些實施例中，N型磊晶鰭片區110B可具有多重次區，其可基於例如摻雜濃度、及∕或磊晶成長製程條件彼此不同。
參照第1A和1B圖，堆疊的鰭片結構104A和104B可個別為全繞式閘極鰭式場效電晶體102A和102B的電流承載結構。可在個別堆疊的鰭片結構104A和104B於閘極結構112A和112B下方的部分中形成全繞式閘極鰭式場效電晶體102A和102B的通道區。磊晶鰭片區110A和110B可作為個別全繞式閘極鰭式場效電晶體102A和102B的源極∕汲極（source/drain, S/D）區。
根據一些實施例，可在鰭片結構104A的頂部上堆疊鰭片結構104B，並藉由隔離結構120隔離，如第1A和1B圖所示。在一些實施例中，堆疊的鰭片結構104A和104B可分別提供半導體層122A和122B的尺寸和間距的獨立控制。在一些實施例中，可控制半導體層122A和122B的寬度和厚度以取得功率消耗和性能之間的平衡。舉例來說，半導體層122A可沿著Y軸增加寬度（未繪示）和厚度122At以改善全繞式閘極鰭式場效電晶體102A的性能。半導體層122B可沿著Y軸減少寬度（未繪示）和厚度122Bt以減少全繞式閘極鰭式場效電晶體102B的功率和面積消耗。在一些實施例中，可控制半導體層之間的厚度和間距以平衡導電面積和寄生電容。在另一個範例中，半導體層122A可增加厚度122At和間距122As以增加全繞式閘極鰭式場效電晶體102A的導電面積。半導體層122B可減少厚度122Bt和間距122Bs以減少全繞式閘極鰭式場效電晶體102B的寄生電容。此外，針對不同導電類型的功函數金屬填充物，半導體層122B可具有與半導體層122A不同的間距。
參照第1A和1B圖，可在鰭片結構104A和104B之間設置隔離結構120。根據一些實施例，隔離結構120可隔離全繞式閘極鰭式場效電晶體102A和102B。根據一些實施例，隔離結構120可包括絕緣材料，如氧化矽、氮化矽、低介電常數材料、其他合適的絕緣材料、或其組合。在一些實施例中，隔離結構120可包括在堆疊鰭片部108A上的第一部分和在磊晶鰭片區110A上的第二部分。在一些實施例中，隔離結構120可沿著Z軸具有約5nm至10nm範圍的垂直尺寸（例如厚度）120t。
參照第1A和1B圖，閘極結構112A和112B可為多膜層結構，且可包繞堆疊鰭片部108A和108B。在一些實施例中，可分別藉由閘極結構112A和112B的其中一個或閘極結構112A和112B的其中一個的一或多的膜層包繞堆疊鰭片部108A和108B的半導體層122A和122B中的每一個，其閘極結構112A和112B可被稱為「全繞式閘極結構」或「水平全繞式閘極結構」，而全繞式閘極鰭式場效電晶體102A和102B可被稱為「全繞式閘極場效電晶體」或「全繞式閘極鰭式場效電晶體」。
在一些實施例中，閘極結構112A和112B可包括閘極電極的單一膜層或膜層堆疊，其分別包繞半導體層122A和122B。在一些實施例中，P型鰭式場效電晶體102A可針對閘極結構112A的閘極電極包括P型功函數材料。在一些實施例中，N型鰭式場效電晶體102B可針對閘極結構112B的閘極電極包括N型功函數材料。在一些實施例中，閘極結構112A和112B的閘極電極可包括例如鋁（Al）、銅（Cu）、鎢（W）、鈦（Ti）、鉭（Ta）、氮化鈦（TiN）、氮化鉭（TaN）、矽化鎳（NiSi）、矽化鈷（CoSi）、銀（Ag）、碳化鉭（TaC）、矽氮化鉭（TaSiN）、碳氮化鉭（TaCN）、鈦鋁（TiAl）、氮化鈦鋁（TiAlN）、氮化鎢（WN）、金屬合金、或其組合。
參照第1A和1B圖，根據一些實施例，可在磊晶鰭片區110A和110B與部分閘極結構112A和112B之間設置內間隔物結構116A和116B。內間隔物結構116A和116B可包括介電材料，如氧碳化矽（SiOC）、碳氮化矽（SiCN）、氧碳氮化矽（SiOCN）、氮化矽（SiN）、氧化矽（SiOx ）、氧氮化矽（SiOy N）、或其組合。在一些實施例中，內間隔物結構116A和116B可包括單一膜層或多重膜層的絕緣材料。在一些實施例中，內間隔物結構116A和116B可將閘極結構112A和112B與磊晶鰭片區110A和110B隔離。在一些實施例中，內間隔物結構116A和116B可沿著X軸具有約3nm至7nm範圍的厚度116At和116Bt。
參照第1A和1B圖，閘極互連件111可連接至閘極電源供應線，而源極∕汲極互連件103和105可連接至源極∕汲極電源供應線。在一些實施例中，閘極互連件111可連接至全繞式閘極鰭式場效電晶體102A和102B之上的閘極電源供應線，且提供至全繞式閘極鰭式場效電晶體102A和102B的閘極控制。在一些實施例中，源極∕汲極互連件103和105可連接至埋入基底106內的源極∕汲極電源供應線。埋入式電源供應線可減少標準單元路由和記憶單元路由。舉例來說，全繞式閘極鰭式場效電晶體102A的汲極端可連接至埋入式汲極電壓電源供應線，而全繞式閘極鰭式場效電晶體102B的源極端可連接至埋入式源極電壓電源供應線。
在一些實施例中，半導體元件100可更包括淺溝槽隔離（shallow trench isolation, STI）區、閘極介電層、層間介電（interlayer dielectric, ILD）層、蝕刻停止層（etch stop layer, ESL）、源極∕汲極和閘極接觸結構、以及其他合適的膜層和結構（為了簡單起見未繪示）。
第2A圖是根據一些實施例，繪示具有垂直閘極的交叉堆疊半導體元件200A的等距示意圖。如第2A圖所示，全繞式閘極鰭式場效電晶體202B的鰭片結構的延伸方向不同於全繞式閘極鰭式場效電晶體202A的鰭片結構，其可被稱為交叉堆疊半導體元件200A。在一些實施例中，全繞式閘極鰭式場效電晶體202B的鰭片結構的方向可由全繞式閘極鰭式場效電晶體202A的鰭片結構的方向旋轉約90°。舉例來說，如第2A圖所示，全繞式閘極鰭式場效電晶體202B的鰭片結構可沿著X軸延伸，而全繞式閘極鰭式場效電晶體202A的鰭片結構可沿著Y軸延伸。根據一些實施例，相較於垂直堆疊半導體元件100，交叉堆疊半導體元件200A除了獨立控制鰭片結構的尺寸和間距，可更提供在微影中更多的簡易、更緊湊的金屬互連件以減少寄生電阻和電容、更有彈性的位置和路由、以及改善的位置定律。
第2B圖是根據一些實施例，繪示具有旋轉閘極的交叉堆疊半導體元件200B的等距示意圖。如第2B圖所示，全繞式閘極鰭式場效電晶體202D的鰭片結構和閘極結構可分別與全繞式閘極鰭式場效電晶體202C的鰭片結構和閘極結構沿著不同的方向延伸。在一些實施例中，全繞式閘極鰭式場效電晶體202D的鰭片結構的方向可由全繞式閘極鰭式場效電晶體202C的鰭片結構的方向旋轉約90°，而全繞式閘極鰭式場效電晶體202D的閘極結構212D的方向可由全繞式閘極鰭式場效電晶體202C的閘極結構212C的方向旋轉約90°。舉例來說，如第2B圖所示，全繞式閘極鰭式場效電晶體202C的鰭片結構可沿著X軸延伸，而閘極結構212C可沿著Y軸延伸。全繞式閘極鰭式場效電晶體202D的鰭片結構可沿著Y軸延伸，而閘極結構212D可沿著X軸延伸。在一些實施例中，相較於交叉堆疊半導體元件200A，具有旋轉閘極的交叉堆疊半導體元件200B可藉由提供更短的路由路徑提供更緊湊的金屬互連件以減少寄生電阻和電容，因而改善PPA的表現。在一些實施例中，相較於其他平面全繞式閘極鰭式場效電晶體，具有旋轉閘極的交叉堆疊半導體元件可減少元件面積約30%至50%。在一些實施例中，相較於其他平面全繞式閘極鰭式場效電晶體，交叉堆疊半導體元件200B可減少元件面積約30%至50%。
第3圖是根據一些實施例，用以製造堆疊半導體元件（如半導體元件100、200A、以及200B）的方法300的流程圖。可在方法300的各種操作之間進行額外的製造步驟，其可為了簡化和描述上的便利起見而省略。可同時地進行一些操作，或在與第3圖所示的不同順序下進行。可在方法300之前、之間、及∕或之後提供額外製程，且這些額外製程可於此簡略的描述。為了例示性目的，第3圖中所示的操作將參考第4～23圖所示製造垂直堆疊半導體元件100的製造過程範例來描述。第4～23圖是根據一些實施例，沿著垂直堆疊半導體元件100的線段B-B在製造過程的各種階段的部分剖面示意圖。儘管第4～23圖繪示垂直堆疊半導體元件100的製造過程，方法300可適用於交叉堆疊半導體元件200A和200B、以及其他堆疊半導體元件。在第4～23圖中的部件與第1A和1B圖的部件以相同標號標示，其於上所述。
參照第3圖，方法300開始於操作310，形成第一鰭片結構的製程。舉例來說，如第4圖所示，可在基底106上形成鰭片結構104A*。鰭片結構104A*可包括半導體層412A和122A在交錯的配置下堆疊。半導體層412A和122A的每一個可在其下方層上磊晶成長，且可包括彼此不同的半導體材料。在一些實施例中，半導體層412A和122A可包括與基底106類似或不同的半導體材料。在一些實施例中，半導體層412A和122A可包括彼此不同的氧化速率及∕或蝕刻選擇比的半導體材料。在一些實施例中，半導體層412A可包括矽鍺，其鍺在約20原子百分比至40原子百分比的範圍，任何剩餘原子百分比為矽。在一些實施例中，半導體層122A可包括矽，而未有任何實質量的鍺。
半導體層412A及∕或122A可為未摻雜，或可在磊晶成長製程期間使用（1）P型摻質（如硼、銦、或鎵）；及∕或（2）N型摻質（如磷或砷）原位摻雜。針對P型原位摻雜，可使用如二硼烷、三氟化硼、及∕或其他P型摻雜前驅物。針對N型原位摻雜，可使用如膦、胂、及∕或其他N型摻雜前驅物。半導體層412A和122A可沿著Z軸具有個別的厚度412At和122At，其分別在約5nm至12nm和約6nm至10nm的範圍。厚度412At和122At可彼此相等或不同。儘管在第4圖中繪示鰭片結構104A*的三對半導體層412A和122A，垂直堆疊半導體元件100可具有任何數量的半導體層412A和122A。
參照第3圖，在操作320中，在第一鰭片結構上形成基底層。如第4圖所示，可在鰭片結構104A*的頂部上形成另一個半導體層420、摻雜層126、以及另一對半導體層128和430。針對後續磊晶層和第二鰭片結構的成長，摻雜層126和半導體層128可被稱為的基底層127。摻雜層126、以及半導體層420、128、以及430也可在其下方膜層上磊晶成長，且可包括彼此不同的半導體材料。在一些實施例中，摻雜層126和半導體層420、128、以及430可為未摻雜，或可類似半導體層412A和122A原位摻雜。
在一些實施例中，半導體層420可包括矽鍺，其鍺在約10原子百分比至20原子百分比的範圍，任何剩餘原子百分比為矽。在一些實施例中，摻雜層126可包括矽，而未有任何實質量的鍺，且以不同於基底106的導電類型摻雜。舉例來說，基底106可以N型摻質摻雜，而摻雜層126可以P型摻質摻雜。在一些實施例中，半導體層420和摻雜層126可沿著Z軸分別具有厚度420t和厚度126t。
在一些實施例中，半導體層128和430可分別與半導體層122A和412A相同。在一些實施例中，半導體層430可作為蓋層以保護半導體層128。在一些實施例中，可使用半導體層128以磊晶成長額外的半導體層。在一些實施例中，半導體層430可包括矽鍺，其鍺在約20原子百分比至40原子百分比的範圍，任何剩餘原子百分比為矽。在一些實施例中，半導體層128可包括矽，而未有任何實質量的鍺。在一些實施例中，半導體層128可沿著Z軸具有約12nm至20nm範圍的厚度128t。在一些實施例中，半導體層430可沿著Z軸具有約10nm至16nm範圍的厚度430t。
參照第3圖，在操作330中，在第一鰭片結構和基底層之間形成隔離結構。舉例來說，第5～14圖繪示在鰭片結構104A和摻雜層126之間型成隔離結構120。形成隔離結構120可包括：（1）半導體層122A、412A、128、420、以及430、以及摻雜層126的垂直蝕刻；（2）半導體層412A和420的橫向蝕刻；（3）形成內間隔物結構116A；以及（4）填充隔離結構120。
參照第5圖，可垂直地蝕刻半導體層122A、412A、128、420、以及430、以及摻雜層126以形成開口532。在一些實施例中，可在後續製程中於開口532中形成源極∕汲極區。在一些實施例中，開口532可沿著X軸方向具有約12nm至20nm範圍的水平尺寸532w（例如寬度）。在一些實施例中，半導體層122A、412A、128、420、以及430、以及摻雜層126的垂直蝕刻可包括偏壓蝕刻製程（biased etching process）。可在約1mTorr至1000mTorr的氣壓下、在約50W至1000W的功率下、在約20V至500V的偏壓下、在約40°C至60°C的溫度下、且使用溴化氫（HBr）及∕或氯氣（Cl2 ）作為蝕刻氣體進行偏壓蝕刻製程。在一些實施例中，偏壓蝕刻製程可具有方向性，且半導體層122A、412A、128、420、以及430、以及摻雜層126可實質上不具有橫向蝕刻。
半導體層122A、412A、128、420、以及430、以及摻雜層126的垂直蝕刻之後，可接著進行半導體層412A、420、以及430的橫向蝕刻，如第6圖所示。可藉由乾蝕刻製程、濕蝕刻製程、或其組合進行橫向蝕刻。蝕刻製程可包括複數個循環的蝕刻和驅淨（purging）製程，如約3至20循環的蝕刻和驅淨製程。每個循環的蝕刻製程可包括使用具有氫氟酸（HF）和氟基氣體的氣體混合物。在氣體混合物中氫氟酸對氟基氣體的氣體比例可在約4至30的範圍。每個循環中的驅淨製程可包括使用具有氫氟酸和氮氣（N2 ）的氣體混合物。在驅淨製程中的氫氟酸可移除副產物及∕或為了後續循環清潔被蝕刻部分的表面。在每個循環中，驅淨製程可比蝕刻製程更長。
在一些實施例中，半導體層412A*和430*的蝕刻速率可高於半導體層420*的蝕刻速率。在一些實施例中，在半導體層412A*和430*中較高的鍺濃度可導致比半導體層420*更高的蝕刻速率。在一些實施例中，在半導體層412A*和430*中的鍺濃度可比在半導體層420*中的鍺濃度高至少10原子百分比。在一些實施例中，可橫向地蝕刻半導體層412A*，且形成橫向凹槽412r，其沿著X軸具有約8nm至10nm範圍的水平尺寸412d（例如深度）。在一些實施例中，可橫向地蝕刻半導體層420*，且形成橫向凹槽420r，其沿著X軸具有約2nm至3nm範圍的水平尺寸420d（例如深度）。
半導體層412A、420、以及430的橫向蝕刻之後，可接著形成內間隔物結構116A，如第7和8圖所示。形成內間隔物結構116A可更包括：（1）沉積內間隔物層；以及（2）橫向蝕刻沉積後的內間隔物層。
參照第7圖，可在第6圖的結構上沉積內間隔物層116A*。在一些實施例中，沉積製程可包括多重循環的沉積和蝕刻製程。在每個循環中，蝕刻製程可接續沉積製程，藉由移除在橫向凹槽420r和橫向凹槽412r內形成的縫隙以避免在內間隔物層116A*內形成空洞。內間隔物層116A*可包括單一膜層或堆疊的介電層，其藉由原子層沉積（atomic layer deposition, ALD）、流動性化學氣相沉積（flowable chemical vapor deposition, FCVD）、或其他合適方法沉積。內間隔物層116A*可包括介電材料，如氧碳化矽、碳氮化矽、氧碳氮化矽、氮化矽、氧化矽、氧氮化矽、或其組合。在一些實施例中，在沉積製程之後，在橫向凹槽412r中的內間隔物層116A*可沿著X軸具有約10nm至15nm範圍的水平尺寸412rt（例如厚度）。在一些實施例中，在沉積製程之後，在橫向凹槽420r中的內間隔物層116A*可沿著X軸具有約3nm至5nm範圍的水平尺寸420rt（例如厚度）。
沉積內間隔物層116A*之後，可接著進行橫向蝕刻以形成在橫向凹槽412r內的內間隔物結構116A，如第8圖所示。在一些實施例中，橫向蝕刻內間隔物層116A*可包括使用氫氟酸和三氟化氮（NF3 ）的氣體混合物的乾蝕刻製程。在橫向蝕刻之後，可由半導體層122A和128、以及摻雜層126移除內間隔物層116A*。橫向凹槽420r可實質上不具有內間隔物層，而橫向凹槽412r可具有內間隔物結構116A，其具有約5nm至7nm範圍的厚度116At。在橫向凹槽412r中的內間隔物結構116A可保護半導體層412A*不在形成隔離結構120的後續製程中被蝕刻。
形成內間隔物結構116A之後，可接著填充隔離結構120，如第9～14圖中所示。隔離結構120的填充可更包括：（1）移除半導體層420*以形成開口；（2）以隔離層填入開口；（3）蝕刻一部分的隔離層；（4）形成源極∕汲極磊晶鰭片區；以及（5）在源極∕汲極磊晶鰭片區上形成另一個隔離層。
參照第9圖，可移除半導體層420*以形成開口920。在一些實施例中，可藉由乾蝕刻製程、濕蝕刻製程、或其組合進行半導體層420*的移除。蝕刻製程可包括多重循環的蝕刻和驅淨製程，如約3至20循環的蝕刻和驅淨製程。每個循環的蝕刻製程可包括使用具有氫氟酸和氟基氣體的氣體混合物。氫氟酸對氟基氣體的氣體比例可在約4至30的範圍。每個循環中的驅淨製程可包括使用具有氫氟酸和氮氣的氣體混合物。在驅淨製程中的氫氟酸可移除副產物及∕或為了後續循環清潔被蝕刻部分的表面。在移除半導體層420*期間，半導體層412*可被內間隔物結構116A保護。在移除半導體層420*之後，可在半導體層122A和摻雜層126之間形成開口920。
移除半導體層420*之後，可接著以隔離層1020填入開口920，如第10圖所示。在一些實施例中，可在第9圖的結構上沉積隔離層1020。在一些實施例中，可藉由原子層沉積、化學氣相沉積（chemical vapor deposition, CVD）、或其他合適沉積方法沉積隔離層1020以避免在半導體層122A和摻雜層126之間的隔離層1020中形成縫隙。在一些實施例中，在沉積製程之後，開口920可被隔離層1020填充。在一些實施例中，隔離層1020可包括絕緣材料，如氧化矽、氮化矽、低介電常數材料、其他合適的絕緣材料、或其組合。隔離層1020的其他沉積方法和絕緣材料皆於本揭露的範圍和精神之內。
以隔離層1020填充開口920之後，可接著蝕刻部分的隔離層1020，如第11圖所示。在一些實施例中，蝕刻製程可包括使用氫氟酸和氨（ammonia, NH3 ）的氣體混合物的乾蝕刻製程。氫氟酸對氨的氣體比例可在約1至20的範圍。在一些實施例中，可從半導體層122A、128、以及430*、摻雜層126、以及內間隔物結構116A蝕去隔離層1020。在一些實施例中，在蝕刻製程之後，可在半導體層122A和摻雜層126之間形成隔離層1020*。
蝕刻部分的隔離層1020之後，可接著形成磊晶鰭片區110A，如第12圖所示。在一些實施例中，形成磊晶鰭片區110A可包括成長磊晶鰭片區和蝕刻磊晶鰭片區。在一些實施例中，可在半導體層122A和128、以及摻雜層126的露出表面上成長磊晶鰭片區。在一些實施例中，可蝕刻成長在露出表面上的磊晶鰭片區以形成磊晶鰭片區110A。在一些實施例中，蝕刻製程可包括乾蝕刻及∕或其他方向性蝕刻方法。在一些實施例中，可蝕刻磊晶鰭片區至低於摻雜層126。在一些實施例中，在蝕刻製程之後，沿著Z軸在磊晶鰭片區110A的頂面和摻雜層126的底部之間的垂直尺寸1020d（例如距離）可在約3nm至5nm的範圍。在一些實施例中，垂直尺寸1020d可將全繞式閘極鰭式場效電晶體102A的磊晶鰭片區110A與全繞式閘極鰭式場效電晶體102B的摻雜層126和半導體層128隔離開。
形成磊晶鰭片區110A之後，可接著在磊晶鰭片區110A上形成另一個隔離層，如第13和14圖所示。參照第13圖，可在第12圖的結構上沉積隔離層1320。在一些實施例中，可藉由原子層沉積、化學氣相沉積、或其他合適方法沉積隔離層1320。在一些實施例中，隔離層1320可包括與隔離層1020*相同的隔離材料。在一些實施例中，可研磨隔離層1320和半導體層430*，且研磨製程可停止於半導體層128，如第14圖所示。在一些實施例中，研磨製程可包括化學機械研磨（chemical mechanical polishing, CMP）製程。在一些實施例中，在先前製程期間，半導體層430*可被損傷，因而將其研磨掉，使得可在半導體層128上磊晶成長後續的半導體層。在一些實施例中，也可在形成奈米片∕奈米線形狀的半導體層的後續製程中移除半導體層430*。在一些實施例中，在研磨製程之後，可形成隔離結構120。在一些實施例中，隔離結構120可包括在摻雜層126和堆疊鰭片部108A之間的第一部分。在一些實施例中，隔離結構120可包括在磊晶鰭片區110A上的第二部分。
形成隔離結構120之後，可接著形成金屬閘極，如第15和16圖所示。在一些實施例中，形成金屬閘極可包括形成奈米片∕奈米線形狀的半導體層122A和填充金屬閘極。參照第15圖，可移除半導體層412A*，且在半導體層122A之間形成開口1512。在一些實施例中，可藉由使用具有氫氟酸和氟基氣體的氣體混合物的蝕刻製程移除半導體層412A*。在一些實施例中，在氣體混合物中氫氟酸對氟基氣體的氣體比例可在約60至100的範圍。
形成奈米片∕奈米線形狀的半導體層122A之後，可接著進行金屬閘極填充，如第16圖所示。在金屬閘極填充之前，可在半導體層122A上形成閘極介電層。在一些實施例中，閘極介電層可包繞奈米片∕奈米線形狀的半導體層122A，且可包括介面層（interfacial layer, IL）和高介電常數介電層。參照第16圖，可在開口1512中填入金屬閘極以形成閘極結構112A。在一些實施例中，閘極結構112A也可包繞奈米片∕奈米線形狀的半導體層122A，且可包括N型或P型功函數金屬。
參照第3圖，在操作340中，形成磊晶層接觸基底層和隔離結構。舉例來說，如第17圖所示，可形成磊晶層130接觸基底層127和隔離結構120。基底層127可包括半導體層128和摻雜層126。在一些實施例中，可磊晶成長磊晶層130，類似於半導體層122A。在一些實施例中，磊晶層130可包括矽，而未有任何實質量的鍺。在一些實施例中，可在半導體層128上磊晶成長磊晶層130，其與隔離結構120在磊晶鰭片區110A上的部分合併。在一些實施例中，磊晶層130可沿著Z軸具有約10nm至20nm範圍的厚度130t。
參照第3圖，在操作350中，形成第二鰭片結構於第一鰭片結構上並接觸磊晶層。舉例來說，如第17圖所示，可形成鰭片結構104B*接觸磊晶層130。在一些實施例中，隔離結構120可將鰭片結構104B*與鰭片結構104A隔離開。在一些實施例中，鰭片結構104B*的半導體層122B*可沿著Z軸具有厚度122Bt和間距122Bs，其分別與鰭片結構104A的半導體層122A的厚度122At和間距122As不同。
堆疊鰭片結構104A和104B*可針對每個半導體層的尺寸和間距提供獨立控制。在一些實施例中，可控制半導體層的寬度和厚度以提供功率消耗和性能之間的平衡。舉例來說，半導體層122A可增加沿著Y軸的寬度（未繪示）和厚度122At以改善全繞式閘極鰭式場效電晶體102A的性能。半導體層122B*可減少沿著Y軸的寬度（未繪示）和厚度122Bt以減少全繞式閘極鰭式場效電晶體102B的功率和面積消耗。在一些實施例中，可控制半導體層之間的厚度和間距以平衡導電面積和寄生電容。在另一個範例中，半導體層122A可增加厚度122At和間距122As以增加全繞式閘極鰭式場效電晶體102A的導電面積。半導體層122B*可減少厚度122Bt和間距122Bs以減少全繞式閘極鰭式場效電晶體102B的寄生電容。此外，針對不同導電類型的功函數金屬填充物，半導體層122B*可具有與半導體層122A不同的間距。
在一些實施例中，可在鰭片結構104A上垂直堆疊鰭片結構104B*，其可沿著與鰭片結構104A相同的方向延伸，如第17圖所示。在一些實施例中，可在鰭片結構104A上交叉堆疊鰭片結構104B*，其可沿著與鰭片結構104A不同的方向延伸。舉例來說，鰭片結構104B*可沿著Y軸延伸，而鰭片結構104A可沿著X軸延伸。根據一些實施例，相較於垂直堆疊鰭片結構104B*和104A，交叉堆疊鰭片結構104B*和104A除了獨立控制半導體層的尺寸和間距，可更提供在微影中更多的簡易、更緊湊的金屬互連件，其允許更有彈性的位置和路由以改善位置定律和互連路由。
形成第二鰭片結構之後，可接著進行半導體層橫向蝕刻、內間隔物結構沉積和蝕刻、磊晶鰭片區沉積和蝕刻、形成奈米片∕奈米線形狀的半導體層、以及形成金屬閘極。第1B圖繪示在形成第二鰭片結構的金屬閘極之後的剖面示意圖。在一些實施例中，全繞式閘極鰭式場效電晶體102B的半導體層的橫向蝕刻、內間隔物結構的沉積和蝕刻、磊晶鰭片區的沉積和蝕刻、奈米片∕奈米線形狀的半導體層的形成、以及金屬閘極的形成可與形成全繞式閘極鰭式場效電晶體102A的製程相似。藉由堆疊的全繞式閘極鰭式場效電晶體102A和102B，全繞式閘極鰭式場效電晶體102B可具有閘極結構112B和半導體層122B的獨立控制。在一些實施例中，全繞式閘極鰭式場效電晶體102B的閘極結構的延伸方向可不同於全繞式閘極鰭式場效電晶體102A的閘極結構的延伸方向。舉例來說，如第2B圖所示，閘極結構212D可沿著X軸延伸，而閘極結構212C可沿著Y軸延伸。根據一些實施例，具有旋轉閘極的交叉堆疊半導體元件可提供進一步緊湊的金屬互連件，具有更短的路由路徑以減少寄生電阻和電容，因而改善PPA的表現。在一些實施例中，相較於其他平面全繞式閘極鰭式場效電晶體，具有旋轉閘極的交叉堆疊半導體元件可減少元件面積約30%至50%。
參照第18～23圖，可在全繞式閘極鰭式場效電晶體102A和102B之間形成額外隔離結構。如第18圖所示，在形成金屬閘極之後，可在第16圖的結構上成長磊晶層1830。在一些實施例中，磊晶層1830可包括類似於半導體層128的半導體材料，且沿著Z軸具有約10nm至30nm範圍的厚度1830t。在一些實施例中，針對後續的半導體層成長，磊晶層1830可覆蓋半導體層128和隔離結構120。可在磊晶層1830上形成犧牲鰭片結構1837，其包括半導體層1838和1840在交錯的配置下堆疊。在一些實施例中，可形成犧牲鰭片結構1837類似第17圖中所示的鰭片結構104B*。在一些實施例中，半導體層1838可包括矽鍺，其鍺在約20原子百分比至40原子百分比的範圍，任何剩餘原子百分比為矽。在一些實施例中，半導體層1840可包括矽，而未有任何實質量的鍺。在一些實施例中，可垂直地蝕刻半導體層1838和1840，如第18圖所示。在一些實施例中，半導體層1838可沿著Z軸具有約20nm至25nm範圍的厚度1838t。在一些實施例中，半導體層1840可沿著Z軸具有約3nm至7nm範圍的厚度1840t。
形成犧牲鰭片結構1837之後，可接著移除半導體層1838，如第19圖所示。可藉由類似於形成奈米片∕奈米線形狀的半導體層（繪示於第15圖中）的蝕刻製程進行半導體層1838的移除。
移除半導體層1838之後，可接著形成隔離結構2020，如第20和21圖所示。形成隔離結構2020可包括沉積隔離層2020*和隔離層2020*的化學機械研磨。參照第20圖，可沉積隔離層2020*，類似於隔離層1320（繪示於第13圖中）。參照第21圖，可藉由與隔離結構120類似的化學機械研磨製程形成隔離結構2020。根據一些實施例，隔離結構120和2020可改善頂部全繞式閘極鰭式場效電晶體和底部全繞式閘極鰭式場效電晶體之間的隔離。
形成隔離結構2020之後，可接著進行另一個磊晶層成長和鰭片結構104B*的形成，如第22和23圖所示。參照第22圖，可在第21圖的結構上成長磊晶層2242。在一些實施例中，磊晶層2242可包括類似於半導體層1840的半導體材料，且可沿著Z軸具有約10nm至30nm範圍的厚度2242t。在一些實施例中，針對後續的半導體層成長，磊晶層2242可覆蓋半導體層1840和隔離結構2020。在一些實施例中，磊晶層2242可改善頂部全繞式閘極鰭式場效電晶體和底部全繞式閘極鰭式場效電晶體之間的隔離。參照第23圖，可在磊晶層2242上成長鰭片結構104B*。可在鰭片結構104B*上進行後續製程以形成全繞式閘極鰭式場效電晶體102B。
根據本揭露的各種實施例提供堆疊半導體元件的形成方法，如垂直堆疊半導體元件100和交叉堆疊半導體元件200A和200B。根據一些實施例，垂直堆疊半導體元件100可包括在沿著X軸的底部鰭片結構104A的頂部上垂直堆疊沿著另一個X軸的頂部鰭片結構104B。在一些實施例中，垂直堆疊的鰭片結構104A和104B可各自獨立地控制其奈米片∕奈米線尺寸和間距。在一些實施例中，可在沿著一方向的底部鰭片結構的頂部上堆疊沿著另一個方向的頂部鰭片結構，其另一個方向旋轉一些角度，如約90°。在一些實施例中，交叉堆疊半導體元件200A和200B可針對頂部和底部鰭片結構提供緊湊金屬互連件位置和路由，因此改善PPA的表現。在一些實施例中，交叉堆疊的半導體元件200B可包括頂部閘極結構，相對於底部閘極結構旋轉一些角度，例如約90°。在一些實施例中，具有旋轉閘極的交叉堆疊的半導體元件200B可提供更加緊湊的金屬互連路由和位置以減少寄生電阻和電容，因而改善PPA的表現。在一些實施例中，隔離結構120可隔離鰭片結構104B和鰭片結構104A。在一些實施例中，額外隔離結構2020可改善鰭片結構104B和鰭片結構104A之間的隔離。在一些實施例中，相較於其他平面全繞式閘極鰭式場效電晶體，交叉堆疊半導體元件200B可減少元件面積約30%至50%。
在一些實施例中，一種半導體元件，包括：第一鰭片結構；接觸第一鰭片結構的頂面的隔離結構；接觸隔離結構的基底層；接觸隔離結構和基底層的磊晶層；以及於第一鰭片結構之上並接觸磊晶層的第二鰭片結構。
在一些實施例中，半導體元件更包括圍繞第一鰭片結構和第二鰭片結構的閘極結構。在一些實施例中，半導體元件更包括圍繞第一鰭片結構的第一閘極結構，具有第一閘極長度；以及圍繞第二鰭片結構的第二閘極結構，具有第二閘極長度，第二閘極長度不同於第一閘極長度。在一些實施例中，第一鰭片結構係沿著第一方向，而第二鰭片結構係沿著第二方向，第二方向與第一方向平行。在一些實施例中，第一鰭片結構係沿著第一方向，而第二鰭片結構係沿著第二方向，第二方向與第一方向垂直。在一些實施例中，第一鰭片結構包括第一半導體層堆疊，而第二鰭片結構包括第二半導體層堆疊。在一些實施例中，第一半導體層堆疊的每個膜層具有第一厚度，而第二半導體層堆疊的每個膜層具有第二厚度，第二厚度不同於第一厚度。在一些實施例中，第一半導體層堆疊的每個膜層具有第一寬度，而第二半導體層堆疊的每個膜層具有第二寬度，第二寬度不同於第一寬度。在一些實施例中，第一半導體層堆疊於每個半導體層之間具有第一間距，而第二半導體層堆疊於每個半導體層之間具有第二間距，第二間距不同於第一間距。在一些實施例中，隔離結構包括氧化矽。
在一些實施例中，一種半導體元件，包括：第一鰭片結構；於第一鰭片結構的頂面上的第一隔離結構；於第一隔離結構上的基底層；於第一隔離結構和基底層上的第一磊晶層；於第一磊晶層上的第二隔離結構；於第二隔離結構上的第二磊晶層；以及於第一鰭片結構上並接觸第二磊晶層的第二鰭片結構。
在一些實施例中，第一鰭片結構係沿著第一方向，而第二鰭片結構係沿著第二方向，第二方向與第一方向垂直。在一些實施例中，半導體元件更包括圍繞第一鰭片結構的第一閘極結構，具有第一閘極長度；以及圍繞第二鰭片結構的第二閘極結構，具有第二閘極長度，第二閘極長度不同於第一閘極長度。在一些實施例中，第一鰭片結構包括第一半導體層堆疊，而第二鰭片結構包括第二半導體層堆疊。在一些實施例中，第一半導體層堆疊的每個膜層具有第一厚度，而第二半導體層堆疊的每個膜層具有第二厚度，第二厚度不同於第一厚度。在一些實施例中，第一半導體層堆疊的每個膜層具有第一寬度，而第二半導體層堆疊的每個膜層具有第二寬度，第二寬度不同於第一寬度。在一些實施例中，第一半導體層堆疊於每個半導體層之間具有第一間距，而第二半導體層堆疊於每個半導體層之間具有第二間距，第二間距不同於第一間距。
在一些實施例中，一種半導體元件的形成方法，包括：形成第一鰭片結構；於第一鰭片結構上形成基底層；於基底層和第一鰭片結構之間形成隔離結構；形成磊晶層接觸隔離結構和基底層；以及形成第二鰭片結構於第一鰭片結構上並接觸磊晶層。
在一些實施例中，形成隔離結構包括：移除基底層和第一鰭片結構之間的半導體層以形成開口；以及以絕緣材料層填入開口。在一些實施例中，半導體元件的形成方法更包括：形成另一隔離結構於基底層上；以及形成另一磊晶層於另一隔離結構和第二鰭片結構之間。
應理解的是，實施方式的段落，而非發明摘要的段落，企圖用於解讀發明申請專利範圍。發明摘要的段落可闡述本揭露的一或多個實施例，但並非發明人所思及的所有可能實施例，因而並非意圖以任何方式限制後附的請求項。
以上概述數個實施例之特徵，以使所屬技術領域中具有通常知識者可以更加理解本揭露實施例的觀點。所屬技術領域中具有通常知識者應理解，可輕易地以本揭露實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及∕或優勢。所屬技術領域中具有通常知識者也應理解，此類等效的結構並無悖離本揭露的精神與範圍，且可在不違背本揭露之精神和範圍下，做各式各樣的改變、取代和替換。
100:（垂直堆疊）半導體元件 102A:全繞式閘極（P型）鰭式場效電晶體 102B:全繞式閘極（N型）鰭式場效電晶體 103:源極∕汲極互連件 104A:鰭片結構 104A*:鰭片結構 104B:鰭片結構 104B*:鰭片結構 105:源極∕汲極互連件 106:基底 108A:堆疊鰭片部 108B:堆疊鰭片部 110A:（P型）磊晶鰭片區 110B:（N型）磊晶鰭片區 112:閘極結構 112A:閘極結構 112B:閘極結構 113:閘極互連件 116A:內間隔物結構 116A*:內間隔物層 116At:厚度 116B:內間隔物結構 116Bt:厚度 120:隔離結構 120t:垂直尺寸 122A:半導體層 122As:間距 122At:厚度 122B:半導體層 122B*:半導體層 122Bs:間距 122Bt:厚度 126:摻雜層 126t:垂直尺寸 127:基底層 128:半導體層 128t:厚度 130:磊晶層 130t:厚度 200A:交叉堆疊半導體元件 200B:交叉堆疊半導體元件 202A:全繞式閘極鰭式場效電晶體 202B:全繞式閘極鰭式場效電晶體 202C:全繞式閘極鰭式場效電晶體 202D:全繞式閘極鰭式場效電晶體 212C:閘極結構 212D:閘極結構 300:方法 310:操作 320:操作 330:操作 340:操作 350:操作 412A:半導體層 412A*:半導體層 412At:厚度 412d:水平尺寸 412r:橫向凹槽 412rt:水平尺寸 420:半導體層 420*:半導體層 420d:水平尺寸 420r:橫向凹槽 420rt:水平尺寸 420t:厚度 430:半導體層 430*:半導體層 430t:厚度 532:開口 532w:水平尺寸 920:開口 1020:隔離層 1020*:隔離層 1020d:垂直尺寸 1320:隔離層 1512:開口 1830:磊晶層 1830t:厚度 1837:犧牲鰭片結構 1838:半導體層 1838t:厚度 1840:半導體層 1840t:厚度 2020:隔離結構 2020*:隔離層 2242:磊晶層 2242t:厚度 B-B:線段
以下將配合所附圖式詳述本揭露實施例的面向。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製。事實上，可任意地放大或縮小各種部件的尺寸，以清楚地表現出本揭露實施例的特徵。 第1A和1B圖是根據一些實施例，分別繪示垂直堆疊半導體元件的等距（isometric）示意圖和部分剖面示意圖。 第2A和2B圖是根據一些實施例，分別繪示具有垂直閘極的交叉堆疊半導體元件和具有旋轉閘極的交叉堆疊半導體元件的等距示意圖。 第3圖是根據一些實施例，用以製造堆疊半導體元件的方法流程圖。 第4～17圖是根據一些實施例，繪示垂直堆疊半導體元件在製造過程的各種階段的部分剖面示意圖。 第18～23圖是根據一些實施例，繪示具有額外隔離結構的垂直堆疊半導體元件在製造過程的各種階段的部分剖面示意圖。
無
104A:鰭片結構
104B:鰭片結構
106:基底
108A:堆疊鰭片部
108B:堆疊鰭片部
110A:(P型)磊晶鰭片區
110B:(N型)磊晶鰭片區
112A:閘極結構
112B:閘極結構
116A:內間隔物結構
116At:厚度
116B:內間隔物結構
116Bt:厚度
120:隔離結構
120t:垂直尺寸
122A:半導體層
122As:間距
122At:厚度
122B:半導體層
122Bs:間距
122Bt:厚度
126:摻雜層
126t:垂直尺寸
127:基底層
128:半導體層
128t:厚度
130:磊晶層
130t:厚度

Claims (1)

  1. 一種半導體元件，包括： 一第一鰭片結構； 一隔離結構，接觸該第一鰭片結構的頂面； 一基底層，接觸該隔離結構； 一磊晶層，接觸該隔離結構和該基底層；以及 一第二鰭片結構，於該第一鰭片結構之上並接觸該磊晶層。
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Family Cites Families (19)

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US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
CN105993064B (zh) * 2013-12-27 2019-12-03 英特尔公司 用于环绕栅极架构的选择性蚀刻
US9406804B2 (en) 2014-04-11 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with contact-all-around
US9443769B2 (en) 2014-04-21 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap-around contact
US9831183B2 (en) 2014-08-07 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure and method of forming
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US9548366B1 (en) 2016-04-04 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Self aligned contact scheme
US11411095B2 (en) * 2017-11-30 2022-08-09 Intel Corporation Epitaxial source or drain structures for advanced integrated circuit structure fabrication
WO2019135766A1 (en) * 2018-01-08 2019-07-11 Intel Corporation Stacked transistor architecture having diverse fin geometry
US11164791B2 (en) * 2019-02-25 2021-11-02 International Business Machines Corporation Contact formation for stacked vertical transport field-effect transistors
US10964603B2 (en) * 2019-04-15 2021-03-30 International Business Machines Corporation Hybrid gate stack integration for stacked vertical transport field-effect transistors
US11069679B2 (en) * 2019-04-26 2021-07-20 International Business Machines Corporation Reducing gate resistance in stacked vertical transport field effect transistors
US11355397B2 (en) * 2019-05-13 2022-06-07 Board Of Regents, The University Of Texas System Catalyst influenced chemical etching for fabricating three-dimensional SRAM architectures
US11164799B2 (en) * 2019-06-26 2021-11-02 International Business Machines Corporation Stacked vertical transport field effect transistor contact formation
US11502199B2 (en) 2020-05-28 2022-11-15 Taiwan Semiconductor Manufacturing Co, Ltd. Independent control of stacked semiconductor device
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