TW202117708A - 具有複數個經堆疊晶粒之積體電路裝置 - Google Patents
具有複數個經堆疊晶粒之積體電路裝置 Download PDFInfo
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- TW202117708A TW202117708A TW109119680A TW109119680A TW202117708A TW 202117708 A TW202117708 A TW 202117708A TW 109119680 A TW109119680 A TW 109119680A TW 109119680 A TW109119680 A TW 109119680A TW 202117708 A TW202117708 A TW 202117708A
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Abstract
一種具有複數個經堆疊晶粒之積體電路裝置被描述。所述積體電路裝置包含:複數個經堆疊晶粒的第一晶粒,其具有裝配以接收輸入訊號之輸入/輸出元件,第一晶粒包含裝配以將輸入訊號提供到複數個經堆疊晶粒的各個晶粒之訊號驅動電路,及用來產生用於複數個經堆疊晶粒的複數個晶片選擇訊號之晶片選擇電路;及,複數個經堆疊晶粒的第二晶粒,其耦接到第一晶粒,第二晶粒具有裝配以接收輸入訊號之功能方塊;其中第二晶粒響應於複數個晶片選擇訊號中對應於第二晶粒之晶片選擇訊號而接收輸入訊號。一種實施具有複數個經堆疊晶粒之積體電路裝置的方法亦被描述。
Description
本發明概括關於積體電路裝置,且尤指一種具有複數個經堆疊晶粒之積體電路裝置及一種實施具有複數個經堆疊晶粒之積體電路裝置的方法。
積體電路裝置之實施方式持續來努力改變以縮小尺寸、降低功率、且提高積體電路裝置的性能。不同型式的積體電路裝置可包括多個晶粒,通常亦稱作為晶片。具有多個晶粒之積體電路裝置經常稱作為3D積體電路裝置。具有多個晶粒之一些積體電路裝置可包括中介層,且經常稱作為實施堆疊矽互連技術(SSIT, Stacked Silicon Interconnect Technology)之裝置。舉例來說,多個晶粒可被個別放置在中介層的表面上而不是堆疊在彼此上。微凸塊與貫穿矽通孔(TSV, through-silicon via)可被用以將晶粒各者連接到中介層。然而,微凸塊的尺寸可能引起在晶粒之間的連接為受限。較近世代的3D IC裝置可不包括矽中介層,其中在晶粒之間的連接由可使用混合凸塊與貫穿矽通孔來實施之直接連接所提供。混合凸塊的尺寸概括為小於微凸塊,致能在晶粒之間的更多連接。
儘管在經堆疊積體電路裝置中的晶粒堆疊提高積體電路裝置的邏輯容量,亦減小晶粒邊緣寬度與具有可由積體電路裝置其本身的接點所接取之晶粒的接觸墊的晶粒表面積。由於晶粒表面積之如此縮減,可從在經堆疊積體電路裝置上的接點所接取之在晶粒頂部上的較少個墊為可利用以供測試與對於積體電路裝置的晶粒之其他接取。因為在頂部晶粒上之減少數目個可利用墊,因此在頂部晶粒上之電源供應墊與接地墊的數目相較於習用的單片積體電路裝置或具有個別放置在中介層表面上的多個晶粒之積體電路裝置可能必須被降低。在頂部晶粒上之輸入/輸出(IO, input/output)接點(經常稱作為IO墊)的可利用性亦可影響經堆疊IC裝置的一些必要功能,諸如測試功能。
是以,需要一種用於實施具有經堆疊晶粒的積體電路裝置之電路與方法來克服和經堆疊晶粒有關聯的問題,諸如:和在經堆疊晶粒的頂部晶粒上之減小數目個IC接點有關聯的問題。
一種具有複數個經堆疊晶粒之積體電路裝置被描述。所述積體電路裝置包含:複數個經堆疊晶粒的第一晶粒,其具有裝配以接收輸入訊號之輸入/輸出元件,第一晶粒包含裝配以將輸入訊號提供到複數個經堆疊晶粒的各個晶粒之訊號驅動電路,及用來產生用於複數個經堆疊晶粒的複數個晶片選擇訊號之晶片選擇電路;及,複數個經堆疊晶粒的第二晶粒,其耦接到第一晶粒,第二晶粒具有裝配以接收輸入訊號之功能方塊;其中第二晶粒響應於複數個晶片選擇訊號中對應於第二晶粒之晶片選擇訊號而接收輸入訊號。
一種實施具有複數個經堆疊晶粒之積體電路裝置的方法亦被描述。所述方法包含:裝配複數個經堆疊晶粒的第一晶粒以在輸入/輸出元件處接收輸入訊號;裝配第一晶粒的訊號驅動電路以將輸入訊號提供到複數個經堆疊晶粒的各個晶粒;裝配晶片選擇電路以供產生用於複數個經堆疊晶粒的複數個晶片選擇訊號;將複數個經堆疊晶粒的第二晶粒耦接到第一晶粒,第二晶粒具有裝配以接收輸入訊號之功能方塊;且響應於複數個晶片選擇訊號中對應於第二晶粒之晶片選擇訊號而在第二晶粒處接收輸入訊號。
用於實施具有經堆疊晶粒之積體電路裝置的電路與方法包括在一個晶粒的IO接點與經堆疊晶粒的一個或多個其他晶粒上的功能方塊之間的控制電路。在複數個經堆疊晶粒的一個晶粒上的控制電路致能針對任何目的而接取到複數個經堆疊晶粒的其他晶粒,包括程式設計目的、測試目的、或操作目的。舉例來說,在第一晶粒上的晶片選擇電路可被使用以致能來自訊號驅動電路的訊號被路由到複數個經堆疊晶粒的其他晶粒之一者的電路,諸如:功能方塊。即,藉由使用晶片選擇電路,共用訊號驅動電路可被使用以取決於其他晶粒之何者為由晶片選擇電路所選擇而將訊號傳輸到其他晶粒之各者。根據一些實施方式,所述電路與方法可用可程式邏輯裝置(PLD, programmable logic device)來使用,其中資料可被路由到有關於功能方塊的組態記憶體陣列,經常稱作為組態隨機存取記憶體(CRAM, configuration random access memory)。所述電路與方法亦可被使用以改善在3D堆疊晶粒技術中的測試能力。藉由使用在晶粒上的控制電路以接取在經堆疊晶粒配置中的其他晶粒之電路元件,在晶粒頂部上之少量的IO墊可被分配給在經堆疊晶粒之各者中的測試電路,諸如CRAM或功能方塊。
儘管本說明書包括界定其視為具新穎性之本發明一個或多個實施方式的特徵之申請專利範圍,相信的是,所述電路與方法將從連同圖式之說明的考量而較佳瞭解。儘管種種電路與方法被記載,要瞭解的是,所述電路與方法僅為示範本發明配置,其可用種種形式來實施。因此,在此說明書內所記載的特定結構與功能細節並非解讀為限制性,而僅作為用於申請專利範圍的基礎且作為代表性的基礎以供教示熟習此技術人士用種種方式將本發明配置運用在實質上任何適當詳細結構中。再者,本文使用的術語與片語並無意為限制性,而是提供所述電路與方法之可瞭解的描述。
首先翻到圖1,一種示範的經堆疊積體電路裝置100之方塊圖被顯示。更特別而言,作為舉例而在此顯示為經封裝基板之基板102被裝配以容納由互連元件所電氣連接的複數個晶粒,如將在圖2所更詳細描述。封裝基板包含焊球103,其可用於附接到例如電路板,且可使用以將訊號提供到經附接到封裝基板的晶粒或接收來自晶粒的訊號。替代而言,基板可包含經定位在封裝基板上的中介層、或用於容納積體電路裝置的晶粒之任何其他元件。如在圖1所示,經堆疊的第一晶粒包含第一基板106,其具有包含致能將訊號路由到封裝基板之互連元件的對應的互連層108。互連元件可包含例如焊錫凸塊、混合互連技術、或用於將訊號路由往返晶粒的任何其他導電元件。第二基板110具有包含致能路由訊號之互連元件的對應的互連層112。第三基板116具有包含亦致能路由訊號之互連元件的對應的互連層118。第四基板120具有包含亦致能路由訊號之互連元件的對應的互連層122。第五基板124具有包含亦致能路由訊號之互連元件的對應的互連層126。封裝蓋128可被包括以覆蓋基板124或囊封複數個晶粒。如所顯示的基板與互連層配對(106與108、110與112、116與118、120與122、以及124與126)形成5個晶粒,且被裝配以路由在晶粒之間的訊號,如將參考圖2而更詳細描述於下文。互連層108可由焊錫凸塊130 (例如:C4凸塊)所連接到封裝基板的對應的接觸墊132以致能和焊錫球103之連通。
應瞭解的是,圖1之配置是意圖作為舉例來顯示經堆疊晶粒之概括配置,其中晶粒的特定配置具有正面對正面的晶粒(亦習稱為主動對主動(AoA, Active-on-Active)晶粒)與正面對背面的晶粒之不同組態,其中,正面代表金屬層側的後段製程(BEOL, back end-of-line)且背面代表基板。互連元件可包括晶粒的TSV或BEOL金屬層,視晶粒的組態而定。針對於正面對背面的接合,在晶粒之間的互連被實施在基板中(例如:使用TSV)。根據一個實例,互連層112可包含經耦接到基板110 (即:背面)的通孔之金屬層(即:正面),其中互連層112與基板110共同作成一個晶粒層。從一個晶粒到另一個晶粒或在基板封裝與晶粒之間的互連可包括金屬層(例如:混合凸塊)或TSV,視晶粒的方位而定。儘管示範的經堆疊積體電路裝置100是作為舉例所顯示,應瞭解的是,晶粒之其他配置可被實施,包括多個晶粒堆疊。
現在翻到圖2,一種示範的經堆疊積體電路裝置200的一部分之橫截面圖被顯示,其可為圖1之積體電路裝置的一部分之橫截面。經堆疊積體電路裝置200包含複數個晶粒,作為舉例在此顯示為晶粒1到晶粒5。各個晶粒可概括包含相同型式的元件,諸如以矽所形成的主動元件、金屬線跡與通孔,其用相同參考標號來標示在各個晶粒中。舉例來說,各個晶粒可包含基板202,其具有主動元件204,作為舉例在此顯示為包含在井區域209之中的源極206與汲極208、及閘極區域210之電晶體。
晶粒之基板的主動元件經由互連元件被連接到彼此以及其他晶粒的元件,互連元件可包含由非導電層所分開的金屬層之金屬線跡以及通過非導電層來連接部分的金屬層之通孔。更特定而言,如所顯示,在種種層中的互連元件212可藉由通孔214來耦接在一起。經常稱作為貫穿矽通孔(TSV)之延伸通過基板的通孔216從基板背面上的接觸元件218而延伸,接觸元件218可被耦接到接觸元件220,致使能連接到延伸通過絕緣層224之接觸墊222以提供外部連接。接觸墊222可對應於互連層108的接觸墊以致能連接到在接觸墊132上的焊錫凸塊130,其中基板102的互連元件致能連接到焊球103以供傳輸來自IC裝置的訊號或在IC裝置處接收訊號。其他接觸元件亦可被實施以提供在晶粒之間的電氣連接。舉例來說,第一晶粒的第一接觸元件226可被電氣耦接到第二晶粒的第二接觸元件228,其中第一接觸元件226與第二接觸元件228可為混合接觸元件230的部分者。圖2之實例被提供以顯示其中圖3與4的電路(如更詳述於下文)可被實施在其中之裝置的實例。
圖2之電路是作為舉例所顯示,且可包括任何數目個晶粒,其可以任何方位來實施。儘管晶粒之正面對正面配置被顯示在晶粒1與晶粒2之間且正面對背面配置被顯示在其他晶粒之連接,應瞭解的是,晶粒之其他方位可經實施。一些或所有的晶粒可為相同型式的裝置,諸如:可程式邏輯裝置(PLD),或可具有在不同晶粒中的特定功能,諸如:記憶體或邏輯元件。
現在翻到圖3,一種具有經堆疊積體電路晶粒之積體電路裝置的一部分300之方塊圖被顯示。積體電路裝置可如圖1與2所示而實施,其中在積體電路裝置之不同晶粒中的元件配置作為舉例而顯示以致能可由在積體電路裝置上的IO接點所接取之諸如驅動電路的電路之使用。藉由使用共同電路,諸如在複數個經堆疊晶粒的第一晶粒上之驅動電路以驅動複數個經堆疊晶粒的其他晶粒各者,第一晶粒上的相同IO接點可被用以接取其他晶粒各者的電路,諸如:功能方塊。即,要接取在複數個經堆疊晶粒的一個晶粒上之電路所必要的相同IO(或多個)接點可被用以接取複數個經堆疊晶粒的其他晶粒各者之電路。
具體參考圖3之晶粒的元件,作為舉例而言,圖3之積體電路裝置的部分包含5個經堆疊晶粒,包括第一晶粒302 (亦習稱為頂部晶粒且其可對應於例如圖2的晶粒1)、第二晶粒304、第三晶粒306、第四晶粒308、與第五晶粒310。頂部晶粒的IO電路312可包含對於積體電路外部為可接取的接觸元件。IO電路312被耦接到控制電路313,其中IO電路312作為舉例在此顯示為將可作為在IO電路312的接觸元件處的接收輸入(INPUT)訊號之訊號提供到控制電路313。舉例來說,IO電路312可被耦接到例如圖2之接觸元件222。應瞭解的是,IO電路可實施為專用輸入電路、專用輸出電路、或可作用以接收輸入訊號或產生輸出訊號,視控制電路的操作或用以接收來自訊號驅動電路的訊號之功能方塊或其他電路的功能性而定。功能方塊的實例是參考圖8與9而更詳細描述於下文。
控制電路313可包含訊號驅動電路314與晶片選擇電路316。即,控制電路藉由使用由晶片選擇電路316所產生的晶片選擇訊號以致能訊號轉移到複數個晶粒之另一者的電路,其中晶片選擇訊號可操作為致能訊號以致能在所選擇晶片上的電路來接收來自訊號驅動電路314的訊號。尤其,訊號驅動電路314經由訊號線路318來將訊號提供到晶粒304到310的各者。雖然單一的訊號線路318被顯示,應瞭解的是,訊號線路318可為諸如用於傳輸不同訊號(例如:位址、資料與控制訊號)的訊號匯流排之多線路的訊號線路,或多個訊號線路可由訊號驅動電路所驅動。訊號線路318在訊號輸入322處被提供到暫存器320。
晶片選擇電路316在晶片選擇訊號線路323上產生晶片選擇訊號,其中來自晶片選擇訊號線路323之第一訊號線路的訊號被路由到暫存器320的致能輸入324。根據圖3之實施方式,選擇訊號線路323包含4條線路,其中四個晶粒304到310的各者被耦接到晶片選擇訊號線路的對應者。根據其他實施方式,在提供到晶粒各者之單一線路上的訊號可被解碼已確定資料是否為意圖用於所述晶粒。晶片選擇電路316可接收其響應於致能選擇訊號(a與b)而通過到某個晶粒之致能(ENABLE)訊號,如將參考圖4所更詳細描述。晶片選擇訊號可為用以致能暫存器320之任何型式的訊號,諸如例如時脈訊號。由訊號驅動電路314所驅動的訊號可為儲存在記憶體中的資料、在組態記憶體中用於PLD的電路的組態資料、控制訊號、或用於測試積體電路裝置的種種電路之測試訊號,如將更詳細描述於下文。暫存器320的輸出325被提供到功能方塊328的輸入326,其中所述功能方塊的輸出被產生在輸出329處。
由訊號驅動電路314所產生的訊號亦經由訊號線路318被提供到其他晶粒306到310的功能方塊。更特別而言,晶粒306包含經調適以在訊號輸入332處來接收在訊號線路318上的資料訊號、且在致能輸入334處來接收在複數個訊號線路323之第二訊號線路上的致能訊號之暫存器330。產生在暫存器330的輸出335處之資料被提供到功能方塊338的輸入336,其中功能方塊的輸出被產生在輸出339處。同理,晶粒308包含經調適以在訊號輸入342處來接收在訊號線路318上的資料訊號、且在致能輸入344處來接收在複數個訊號線路323之第三訊號線路上的致能訊號之暫存器340。產生在暫存器340的輸出345處之資料被提供到功能方塊348的輸入346,其中功能方塊的輸出被產生在輸出349處。再者,晶粒310包含經調適以在訊號輸入352處來接收在訊號線路318上的資料訊號、且在致能輸入354處來接收在複數個訊號線路323之第四訊號線路上的致能訊號之暫存器350。產生在暫存器350處的輸出355之資料被提供到功能方塊358的輸入356,其中功能方塊的輸出被產生在輸出359處。由功能方塊所產生的資料可經由訊號線路363被路由到具有訊號接收器362之控制電路360,訊號線路363被耦接到訊號接收器的輸入364。控制訊號可在IO電路366處產生輸出(OUTPUT)訊號。
如在圖3所示,提供在訊號線路318上的訊號被提供到多個晶粒,諸如:經由參考例如圖2之如上所述的混合接合或TSV,其中在訊號線路318上的訊號可基於由晶片選擇電路316所產生的晶片選擇訊號而由特定晶粒所接收。因此,可理解的是,諸如IO電路312的接合墊之僅有單一接觸元件為必要以將訊號路由到晶粒304到310的功能方塊328、338、348與358。即,共同IO接點與共同訊號驅動電路可被使用以基於在第一晶粒中所產生的晶片選擇訊號而選擇性將訊號路由到在不同經堆疊晶粒中的功能方塊。
是以,在複數個經堆疊晶粒之一個晶粒上的控制電路313可為任何目的而被使用以致能接取到複數個經堆疊晶粒之其他晶粒,包括程式設計目的、測試目的、或操作目的。根據一些實施方式,電路與方法可用PLD來使用,如將參考圖8與9而更詳細描述於下文,其中資料可被路由到關於功能方塊之組態記憶體陣列,諸如:CRAM,如將參考圖5而更詳細描述於下文。電路與方法亦可被使用以改善在3D堆疊晶粒技術中的測試能力。藉由使用在晶粒上的控制電路以供接取在經堆疊晶粒配置中之其他晶粒的電路元件,在晶粒頂部上之少量測試墊足以測試在經堆疊晶粒各者中的CRAM或功能方塊。應指出的是,具有控制電路之晶粒302亦可包括功能方塊,其中訊號可藉由控制電路被路由到功能方塊以致能晶粒302的功能方塊之測試或功能操作。再者,儘管用於裝配、測試與其他操作之輸入與輸出訊號經由IO電路(例如:312與366)所提供,應瞭解的是,路由到晶粒304到310的任一者或從其所接收之訊號可被儲存或產生在晶粒302中。儘管單一功能方塊被顯示在晶粒304到310的各者中且經由用於將資料提供到晶粒302之IO電路或用於路由來自晶粒302的訊號之IO電路所接取,應瞭解的是,諸多功能方塊與IO電路可被實施在如上所述晶粒中且如同參考以下的圖8與9所述而互連。上述電路可實施為將測試訊號或其他訊號提供到一群功能方塊之一種包裝(wrapper)電路(其可稱作為包裝件)的部分者。
現在翻到圖4,可實施在經堆疊積體電路裝置的晶粒中之晶片選擇電路400的方塊圖被顯示。如在圖4所示,諸如例如耦接到晶片選擇電路316的致能訊號,致能(ENABLE)訊號可使用致能選擇訊號a、、b、與來產生,其中致能訊號基於致能選擇訊號的值而被提供到晶粒的一者。更特定而言,致能選擇訊號a被提供到反相器402的輸入,其中被產生在反相器402的輸出處。同理,致能選擇訊號b被提供到反相器404的輸入,其中被產生在反相器404的輸出處。致能選擇訊號a與b (且因此與)被選擇以將致能訊號路由到晶粒2到晶粒5之一者。即,致能選擇訊號a被提供到電晶體406的閘極以將致能訊號路由到晶粒2,且提供到電晶體408的閘極以將致能訊號路由到晶粒3。致能選擇訊號被提供到電晶體410的閘極以將致能訊號路由到晶粒4,且提供到電晶體412的閘極以將致能訊號路由到晶粒5。致能選擇訊號b被提供到電晶體414的閘極以將致能訊號路由到晶粒2,且提供到電晶體416的閘極以將致能訊號路由到晶粒4。致能選擇訊號被提供到電晶體418的閘極以將致能訊號路由到晶粒3,且提供到電晶體420的閘極以將致能訊號路由到晶粒5。如在圖4所示,a與b的四個組合可選擇4個晶粒任一者以致能將資料訊號路由到那些晶粒。儘管晶片選擇電路400作為舉例而顯示,應瞭解的是,其他類似電路可被實施以將致能訊號提供到晶粒之一者或多者。
現在翻到圖5,一種具有經堆疊積體電路晶粒之積體電路裝置的一部分500之另一個方塊圖被顯示。根據圖5之配置,不同的IO電路被使用於積體電路裝置的不同部分。圖5之積體電路配置包含5個晶粒,包括可參考圖1與2之如上所述而實施之晶粒502到510,其中在晶粒之間的連接可使用例如混合接合或TSV而實施。IO電路512被裝配以在接觸元件(諸如晶粒502的接觸墊)處來接收對於積體電路裝置的輸入訊號,其中所接收的輸入訊號被提供到控制電路513。控制電路513被調適以控制訊號驅動電路514與晶片選擇電路515來選擇性將訊號提供到不同晶粒中的種種電路區塊。舉例來說,由訊號驅動電路所驅動的訊號可為經儲存在記憶體中的資料、用於儲存或接收資料的位址、儲存在組態記憶體中用於PLD之電路的組態資料、控制訊號、或用於測試積體電路裝置之種種電路的測試訊號,如將在下文所更詳細描述。
訊號驅動電路514被裝配以將訊號驅動到晶粒504到510的電路,而晶片選擇電路515被裝配以選擇晶粒,其基於來自晶片選擇訊號線路516的訊號而接收來自訊號驅動電路514的訊號。根據圖5之實施方式,在訊號輸出518所產生的第一輸出訊號被提供在第一訊號線路519處且在訊號輸出520所產生的第二輸出訊號被提供在訊號線路521處,其中第一訊號線路519與訊號線路521被路由到晶粒504到510的各者。圖5之實施方式的晶粒各者包含記憶體與功能方塊二者,其中記憶體可包含用於功能方塊的組態資料,如將在下文所更詳細描述。
晶粒各者包括經調適以接收用於記憶體524 (作為舉例在此顯示為CRAM陣列)的資料之暫存器522、及用於接收用於位元線緩衝器528的資料之另一個暫存器526,位元線緩衝器528被耦接到記憶體524與暫存器529,其可例如為亦接收和晶粒有關聯的晶片選擇訊號之移位暫存器。更特定而言,來自訊號線路521的訊號(其可例如為位址訊號)被耦接到輸入530,而來自複數個晶片選擇訊號線路516之第一晶片選擇訊號線路的晶片選擇訊號被耦接到致能輸入532。應瞭解的是,晶片選擇訊號可為任何型式的致能訊號以供致能暫存器522,且可包含時脈訊號以供接收經提供到輸入530的資料。暫存器522可包含用於提供和待儲存在記憶體524中的資料有關聯的位址之移位暫存器。產生在暫存器522的輸出534處之資料被提供到記憶體524的輸入536。記憶體524經由介面538而和位元線緩衝器528相連通。介面538致能將資料從記憶體524讀取到位元線緩衝器528的資料或將資料從位元線緩衝器寫入到記憶體524。晶粒502還包含控制電路544之接收器電路542。接收器電路542被裝配以經由耦接到接收器電路542的輸入546之訊號線路545來接收所選擇晶粒的位元線緩衝器之緩衝器529的輸出。
訊號線路519被耦接到輸入551且複數個晶片選擇訊號線路516之第一晶片選擇訊號線路被耦接到暫存器526的致能輸入522,其中輸出547被耦接到位元線緩衝器528的輸入549。提供到位元線緩衝器528的資料可被寫入到記憶體524,或從記憶體524所讀取且提供到位元線緩衝器的資料可被產生在位元線緩衝器528的輸出559處且提供到暫存器529。晶粒502亦包含IO電路548,其致能基於藉由暫存器529所提供到接收器電路542的訊號而產生輸出,諸如在測試期間。即,控制電路可將由接收器電路542所接收的訊號提供到IO電路548。根據另一個實施方式,位元線緩衝器528的輸出可被保持在三態值,其將消除對於在位元線緩衝器528的輸出處之暫存器529的需要。
圖5之電路配置亦可包括功能方塊,其中控制電路550被耦接到IO電路557且亦包含驅動器553與耦接到複數個晶片選擇線路555之晶片選擇電路554。晶粒各者包括暫存器556與功能方塊558,其中在驅動器553之輸出560處所產生的訊號被耦接到暫存器556之輸入562。暫存器556被裝配以接收用於功能方塊的訊號且在輸入564處接收來自複數個晶片選擇線路555的第一晶片選擇線路之晶片選擇訊號。暫存器556的輸出556被耦接到功能方塊558的輸入568。功能方塊的輸出570可由訊號線路572而被提供到控制電路550之接收器電路575的輸入574。功能方塊的輸出可被保持在三態值,使得所選擇晶粒之功能方塊的輸出被提供在訊號線路572之上。替代而言,暫存器可被實施在輸出570處,諸如在位元線緩衝器528的輸出處之暫存器529。
在功能方塊被設計之後,通常需要設計可利於測試此功能方塊之電路,例如:掃描鏈電路。圖3與5之控制電路被實施以加強測試能力且降低電路需求,藉由實施單一電路以利於複數個經堆疊晶粒的各個晶粒之電路測試。控制電路作用為在IO電路與經測試之晶粒的電路(諸如:功能方塊)之間的介面。舉例來說,測試型樣與控制訊號可從IO電路被載入到諸如控制電路513或550之控制電路。這些型樣與訊號被接著使用以測試在另一個晶粒上的功能方塊。在測試後,測試結果可被載入回到另一個控制電路且提供到IO電路以由積體電路裝置來輸出。根據一些實施方式,控制電路可儲存輸入資料與控制資料以供測試功能方塊。舉例來說,要測試數學處理器,input_A = 00001,input_B = 00010,control = 00 => input_A + input_B;若control = 01 => input_Ainput_B。
應指出的是,種種方塊的輸入與輸出被顯示為將訊號路由到由晶片選擇訊號所選擇的特定晶粒之應用,諸如功能方塊的種種方塊可具有其他輸出,且經顯示之種種方塊的輸出可被提供到積體電路裝置的其他部分。對於晶粒的電路元件之種種連接被提供以作為說明允許從第一晶粒(例如:晶粒502)到另一個晶粒(例如:晶粒504到510的一者)的資料路由之實施方式,作為將訊號路由到晶粒各者的電路,且尤指由晶片選擇訊號所選擇的晶粒。根據一些實施方式,資料可從所選擇晶粒而在第一晶粒處被接收,諸如例如在測試操作期間。
儘管圖5之電路配置顯示控制電路之使用以將訊號路由到記憶體與功能方塊,應瞭解的是,將訊號路由到複數個經堆疊晶粒中的晶粒之所述電路與方法可使用任何型式的電路方塊來實施,諸如:以下在圖8與9所述之任何型式的電路方塊。再者,在晶粒各者中的類似電路方塊(即:具有關聯位元線緩衝器與功能方塊的CRAM陣列)之使用是作為舉例所顯示。應瞭解的是,所述晶粒的任一者不必具有相同電路,且不同晶粒可包括類似電路或可包括不同電路。舉例來說,所述晶粒中的一者可主要包括記憶體元件,而其他晶粒中的二者可主要包括和PLD有關聯的功能方塊。
現在翻到圖6,可實施在經堆疊積體電路裝置的晶粒中之用於在積體電路裝置的晶粒之間傳輸訊號的一種訊號驅動電路600之方塊圖被顯示。訊號驅動電路600可被實施為圖3之訊號驅動電路314或圖5之訊號驅動電路514與553。訊號驅動電路600包含裝配以在位址輸入60處3接收位址之第一移位暫存器602。第一移位暫存器602的輸出可被提供到位址解碼器604。字組線控制電路606被裝配以接收經解碼的位址,且將輸出提供到字組線驅動器608。由字組線驅動器所產生的位址被產生作為訊號驅動電路600的輸出。舉例來說,所述位址可被提供到暫存器522的輸入530。此位址可被用以選擇在特定晶粒中的框位址。訊號驅動電路600還可包含裝配以在位元線資料輸入611處接收資料之移位暫存器610。移位暫存器610的輸出被提供到位元線解碼器612。代表經解碼的值之輸出被提供到位元線控制電路614,其產生由訊號驅動電路600所輸出的資料。此資料可被應用到在所選擇框位址的CRAM格之資料線。控制訊號是響應於提供到輸入618的輸入控制位元而亦為由移位暫存器616所產生。這些控制位元被使用以控制所選擇的CRAM格之操作,諸如:讀取與寫入操作。
如在圖7所示,可使用可實施在經堆疊積體電路裝置的晶粒中之一種訊號驅動電路的移位暫存器所傳輸的示範資料之示意圖被顯示。根據一個實施方式,位址可包含複數個欄位,包括:次要位址、主要位址、與堆疊層。根據圖7之實例的移位暫存器,頂列是“標籤”且底列是移位暫存器,其中各個小區塊(“0”、“1”、…)儲存一個位元(位元0、位元1、位元2…)。圖7之移位暫存器可專用以儲存用於在分割為多個扇區之各個晶片上的CRAM陣列之CRAM位址。各個扇區可含有某個密度的CRAM格。“堆疊層”(位元0到位元2)可被用以儲存“晶片位址”(例如:晶片2、晶片3、晶片4、晶片5),“主要位址”(位元3到位元7)可被用以儲存扇區位址,且“次要位址”(位元8到位元(n-1))可被用以儲存字組線位址(WL0、WL1、WL2…)。這些位址位元可被解碼以選擇和所選擇晶片之記憶體陣列有關聯的一個晶片、一個扇區與一個字組線。
現在翻到圖8,可實施用於在經堆疊積體電路裝置中傳輸訊號的電路與方法之一種可程式邏輯裝置的方塊圖被顯示。儘管具有可程式資源的裝置可以任何型式的積體電路裝置來實施,諸如具有可程式資源的特定應用積體電路(ASIC, application specific integrated circuit),其他裝置包含專用的可程式邏輯裝置(PLD)。一個型式的PLD是複雜可程式邏輯裝置(CPLD, Complex Programmable Logic Device)。CPLD包括由互連開關矩陣所連接在一起且連接到輸入/輸出(I/O, input/output)資源之二個或多個“功能方塊”。CPLD的各個功能方塊包括類似於在可程式邏輯陣列(PLA, Programmable Logic Array)或可程式陣列邏輯(PAL, Programmable Array Logic)裝置中所使用的二階AND/OR結構。另一個型式的PLD是具有種種功能方塊的場可程式閘陣列(FPGA, field programmable gate array)。在典型FPGA中,一個陣列的可裝配邏輯方塊(CLB, configurable logic block)被耦接到可程式輸入/輸出方塊(IOB, input/output block)。CLB與IOB由階層式可程式路由資源所互連。這些CLB、IOB、與可程式路由資源包含藉由將典型來自晶片外的記憶體之組態位元流載入到FPGA的組態記憶單元所客製化的功能方塊。針對於這些型式的可程式邏輯裝置二者,裝置的功能性由組態位元流的組態資料位元(或在部分重新組態期間所傳送的組態資料位元)所控制,組態資料位元為此目的而提供到裝置。組態資料位元可被儲存在依電性記憶體(例如:靜態記憶單元,如在FPGA與一些CPLD之中)、在非依電性記憶體(例如:快閃記憶體,如在一些CPLD之中)、或在任何其他型式的記憶單元之中。
圖8之裝置包含具有實施為可程式單元片(tile)的大量不同功能方塊之一種FPGA架構800,包括:多十億位元收發器(MGT, multi-gigabit transceiver) 801、CLB 802、隨機存取記憶體方塊(BRAM, random access memory block) 803、輸入/輸出方塊(IOB) 804、組態與時脈邏輯(CONFIG/CLOCKS) 805、數位訊號處理方塊(DSP) 806、專用輸入/輸出方塊(IO) 807 (例如:組態埠與時脈埠)、以及其他可程式邏輯808,諸如數位時脈管理器、類比至數位轉換器、系統監測邏輯等。一些FPGA還包括專用處理器方塊(PROC) 810,舉例來說,其可被使用以實施軟體應用程式。
在一些FPGA中,各個可程式單元片包括具有往返在各個相鄰單元片中的對應互連元件的標準化連接之可程式互連元件(INT) 811。因此,可程式互連元件共同實施用於所例示FPGA的可程式互連結構。可程式互連元件811還包括往返在相同單元片內的可程式邏輯元件之連接,如包括在圖8的頂部處之實例所顯示。
舉例來說,CLB 802可包括可經程式設計以實施使用者邏輯之可裝配邏輯元件(CLE, configurable logic element) 812加上單一可程式互連元件811。除了一個或多個可程式互連元件,BRAM 803還可包括BRAM邏輯元件(BRL, BRAM logic element) 813。BRAM包括與組態邏輯方塊的分散式RAM分開之專用記憶體。典型而言,在單元片中所包括之互連元件的數目取決於單元片的高度。在所描繪實施方式中,BRAM單元片具有如同五個CLB的相同高度,但其他數目亦可使用。除了適當數目個可程式互連元件,DSP單元片806亦可包括DSP邏輯元件(DSPL, DSP logic element) 814。除了可程式互連元件811的一個實例,IOB 804亦可包括例如輸入/輸出邏輯元件(IOL, input/output logic element) 815的二個實例。所述電路與方法可使用IOL 815來實施。裝置之連接位置由組態位元流的組態資料位元所控制,組態資料位元為此目的而提供到裝置。可程式互連響應於組態位元流的位元而致能連接被,其包含被使用以將種種訊號耦接到經實施在可程式邏輯中的電路、或諸如BRAM或處理器的其他電路之互連線路。
在描繪的實施方式中,接近晶粒中央的柱狀區域被使用於組態、時脈、與其他控制邏輯。從此柱狀者所延伸的組態/時脈分佈區域809被使用以將時脈與組態訊號分佈跨於FPGA的寬度。利用在圖8所示的架構之一些FPGA包括將構成大部分的FPGA之規則柱狀結構擾亂的附加邏輯方塊。附加邏輯方塊可為可程式方塊及/或專用邏輯。舉例來說,在圖8所示之處理器方塊PROC 810跨越數行的CLB與BRAM。
注意的是,圖8意圖說明僅為一種示範的FPGA架構。在柱狀者中之邏輯方塊的數目、柱狀者的相對寬度、柱狀者的數目與順序、在柱狀者中所包括之邏輯方塊的型式、邏輯方塊的相對尺寸、以及在圖8的頂部處所包括之互連/邏輯實施僅為示範。舉例來說,在實際FPGA中,超過一個相鄰柱狀者的CLB被典型包括而無論CLB出現在何處,以利於使用者邏輯之有效率實施。儘管圖8之實施方式有關於具有可程式資源的積體電路,應瞭解的是,上文所陳述電路與方法可用具有可程式資源與硬體方塊的組合之任何型式的裝置來實施。
現在翻到圖9,圖8之可程式邏輯裝置的可裝配邏輯元件之方塊圖被顯示。尤其,圖9以簡化形式來說明圖8之組態邏輯方塊802的可裝配邏輯元件,其為可程式邏輯的實例。在圖9之實施方式中,片段(slice) M 901包括四個查找表(LUTM, lookup table) 901A到901D,各者由六個LUT資料輸入端子A1到A6、B1到B6、C1到C6、與D1到D6所驅動且各者提供二個LUT輸出訊號O5與O6。來自LUT 901A到901D的O6輸出端子分別驅動片段輸出端子A到D。LUT資料輸入訊號經由輸入多工器而由FPGA互連結構所供應,其可由可程式互連元件911所實施,且LUT輸出訊號亦被供應到互連結構。片段M還包括:驅動輸出端子AMUX到DMUX之輸出選擇多工器911A到911D;用以驅動記憶體元件902A到902D的資料輸入端子之多工器912A到912D;組合多工器916、918、與919;彈跳多工器電路922到923;由反相器905與多工器906 (其一起提供在輸入時脈路徑上的選用反相)所代表的電路;以及具有多工器914A到914D、915A到915D、920到921與互斥OR閘913A到913D之進位邏輯。所有這些元件被耦接在一起,如圖9所示。其中選擇輸入並未針對於在圖9所示的多工器而顯示,選擇輸入由組態記憶單元所控制。即,儲存在組態記憶單元中之組態位元流的組態位元被耦接到多工器的選擇輸入以選擇對於多工器的正確輸入。眾所周知的這些組態記憶單元為了清楚目的而從圖9所省略,同樣從在本文的其他選擇圖式所省略。
在描繪的實施方式中,各個記憶體元件902A到902D可經程式設計作用為同步或非同步的正反器或鎖存器。在同步與非同步功能性之間的選擇藉由程式設計同步/非同步(Sync/Async)選擇電路903而針對在一個片段中的所有四個記憶體元件所進行。當記憶體元件被程式設計使得設定/重設(S/R, set/reset)輸入訊號提供設定功能時,REV輸入端子提供重設功能。當記憶體元件被程式設計使得S/R輸入訊號提供重設功能時,REV輸入端子提供設定功能。記憶體元件902A到902D藉由時脈訊號CK所計時,舉例來說,時脈訊號CK可由總體時脈網路或由互連結構所提供。上述可程式記憶體元件在FPGA設計技術為眾所周知。各個記憶體元件902A到902D將暫存的輸出訊號AQ到DQ提供到互連結構。因為各個LUT 901A到901D提供二個輸出訊號:O5與O6,所以LUT可被裝配以作用為具有五個共享輸入訊號(IN1到IN5)之二個5輸入LUT,或作為具有輸入訊號IN1到IN6之一個6輸入LUT。
在圖9之實施方式中,各個LUT 901A到901D可以數種模式之任一者來作用。當在查找表模式中,各個LUT具有由FPGA互連結構經由輸入多工器所供應之六個資料輸入訊號IN1到IN6。64個資料值之一者基於訊號IN1到IN6的值而可程式設計地從組態記憶單元所選擇。當在RAM模式中,各個LUT作用為單一64位元RAM或具有共享定址之二個32位元RAM。RAM寫入資料經由輸入端子DI1 (經由用於LUT 901A到901C的多工器917A到917C)被供應到64位元RAM,或經由輸入端子DI1與DI2被供應到二個32位元RAM。在LUT RAM中的RAM寫入操作由來自多工器906的時脈訊號CK且由來自多工器907的寫入致能訊號WEN所控制,多工器907可選擇性通過時脈致能訊號CE或寫入致能訊號WE。在移位暫存器模式中,各個LUT作用為二個16位元移位暫存器,或具有二個16位元移位暫存器經串聯耦接以作成單一32位元移位暫存器。移入訊號經由輸入端子DI1與DI2之一者或二者所提供。16位元與32位元的移出訊號可透過LUT輸出端子所提供,且32位元的移出訊號亦可更直接經由LUT輸出端子MC31所提供。,經由輸出選擇多工器911D與CLE輸出端子LUT 901A之32位元的移出訊號MC31亦可提供到通用互連結構以供移位暫存器鏈接。是以,以上陳述的電路與方法可被實施在諸如圖8與9的裝置之裝置、或任何其他適合的裝置。
圖10是顯示一種實施在經堆疊積體電路裝置中的複數個晶粒之方法的流程圖。在方塊1002處,諸如例如圖3或5的經堆疊晶粒之複數個經堆疊晶粒的第一晶粒被裝配以在輸入/輸出元件處來接收輸入訊號。具有複數個經堆疊晶粒且裝配以接收輸入訊號之積體電路可如同參考例如圖1與2之上述、或使用形成具有經堆疊晶粒的積體電路裝置之其他方法所形成。在方塊1004處,諸如訊號驅動電路314或514之第一晶粒的訊號驅動電路被裝配以將輸入訊號提供到複數個經堆疊晶粒的各個晶粒。在方塊1006處,晶片選擇電路被裝配以供產生用於複數個經堆疊晶粒之複數個晶片選擇訊號。在方塊1008處,複數個經堆疊晶粒的第二晶粒被耦接到第一晶粒,其中第二晶粒具有裝配以接收輸入訊號之諸如功能方塊328的功能方塊。在方塊1010處,輸入訊號響應於複數個晶片選擇訊號中對應於第二晶粒之晶片選擇訊號而被接收在第二晶粒處。
上述方法還可包含裝配第一晶粒的接收器以接收功能方塊的輸出訊號,以及耦接第一晶粒的第二輸入/輸出元件以接收輸出訊號。再者,上述方法可包含裝配第二晶粒的暫存器以在資料輸入處接收來自訊號驅動電路的輸入訊號且在致能輸入處接收來自晶片選擇電路的晶片選擇訊號。和功能方塊相關聯的資料亦可儲存在第二晶粒的記憶體中。上述方法可更包含裝配第二晶粒的第一暫存器以在資料輸入處接收來自訊號驅動電路的輸入訊號且在致能輸入處接收來自晶片選擇電路的晶片選擇訊號,且將第一暫存器的輸出耦接到記憶體的輸入。第二暫存器亦可被裝配以在資料輸入處接收來自訊號驅動電路的位址訊號且在致能輸入處接收來自晶片選擇電路的晶片選擇訊號,且第二晶粒的位元線緩衝器亦可被裝配以在資料輸入處接收位址訊號且在致能輸入處接收來自晶片選擇電路的晶片選擇訊號。根據一些實施方式,另外的晶粒可經堆疊,諸如藉由將複數個經堆疊晶粒的第三晶粒耦接到經堆疊的第二晶粒,其中第三晶粒包含暫存器,其裝配以在資料輸入處接收來自訊號驅動電路的輸入訊號且在致能輸入處接收來自晶片選擇電路的晶片選擇訊號。
圖10之方法可使用如所描述之圖1到9的電路、或使用一些其他適合電路來實施。儘管所述方法的特定元件被描述,應瞭解的是,所述方法的另外元件、或關於所述元件的另外細節可根據圖1到9的記載內容來實施。
因此可理解的是,用於實施一種堆疊積體電路裝置的新穎電路及方法已經描述。熟習此技術人士所將理解的是,諸多的替代例與等效例將視為存在而納入已記載的本發明。是以,本發明不受限於前述實施方式,而僅由以下申請專利範圍所限定。
100:積體電路裝置
102:基板
103:焊球
106:第一基板
108、112、118、122、126:互連層
110:第二基板
116:第三基板
120:第四基板
124:第五基板
128:封裝蓋
130:焊錫凸塊
132:接觸墊
200:示範的經堆疊積體電路裝置
202:基板
204:主動元件
206:源極
208:汲極
209:井區域
210:閘極區域
212:互連元件
214、216:通孔
218、220:接觸元件
222:接觸墊
224:絕緣層
226:第一接觸元件
228:第二接觸元件
230:混合接觸元件
300:部分
302:第一晶粒
304:第二晶粒
306:第三晶粒
308:第四晶粒
310:第五晶粒
312:IO電路
313:控制電路
314:訊號驅動電路
316:晶片選擇電路
318:訊號線路
320、330、340、350:暫存器
322、332、342、352:訊號輸入
323:晶片選擇訊號線路
324、334、344、354:致能輸入
325、329、335、339、345、349、355、359:輸出
326、336、346、356、364:輸入
328、338、348、358:功能方塊
360:控制電路
362:訊號接收器
363:訊號線路
366:IO電路
400:晶片選擇電路
402、404:反相器
406、408、410、412、414、416、418、420:電晶體
500:部分
502、504:晶粒
512:IO電路
513:控制電路
514:訊號驅動電路
515:晶片選擇電路
516:晶片選擇訊號線路
518、520:訊號輸出
519:第一訊號線路
521:訊號線路
522、526、529、556:暫存器
524:記憶體
528:位元線緩衝器
530、536、546、549、551、562、564、568、574:輸入
532:致能輸入
534、547、559、560、566、570:輸出
538:介面
542、575:接收器電路
544:控制電路
545、572:訊號線路
548:IO電路
550:控制電路
552:致能輸入
553:驅動器
554:晶片選擇電路
555:晶片選擇線路
557:IO電路
558:功能方塊
575:接收器電路
600:訊號驅動電路
602:第一移位暫存器
603:位址輸入
604:位址解碼器
606:字組線控制電路
608:字組線驅動器
610:移位暫存器
611:位元線資料輸入
612:位元線解碼器
614:位元線控制電路
616:移位暫存器
618:輸入
800:FPGA架構
802:可裝配邏輯方塊(CLB)
803:隨機存取記憶體方塊BRAM
804:輸入/輸出方塊(IOB)
805:組態與時脈邏輯
806:DSP單元片
807:專用輸入/輸出方塊(IO)
808:其他可程式邏輯
809:組態/時脈分佈區域
810:處理器方塊(PROC)
811:可程式互連元件
815:輸入/輸出邏輯元件(IOL)
901:片段
901A到901D:查找表
902A到902D:記憶體元件
903:同步/非同步選擇電路
905:反相器
906、907:多工器
911:可程式互連元件
911A到911D:輸出選擇多工器
912A到912D:多工器
913A到913D:互斥OR閘
914A到914D:多工器
916、918:組合多工器
917A到917D:多工器
922、923:彈跳多工器電路
1002、1004、1006、1008、1010:方塊
[圖1]是一種示範的經堆疊積體電路裝置之方塊圖;
[圖2]是一種示範的經堆疊積體電路裝置之橫截面圖,諸如圖1之積體電路裝置;
[圖3]是具有經堆疊積體電路晶粒之一種積體電路裝置的一部分之方塊圖;
[圖4]是可實施在經堆疊積體電路裝置的晶粒中的一種晶片選擇電路之方塊圖;
[圖5]是具有經堆疊積體電路晶粒之一種積體電路裝置的一部分之另一個方塊圖;
[圖6]是可實施在經堆疊積體電路裝置的晶粒中之用於在積體電路裝置的晶粒之間傳輸訊號的一種訊號驅動電路之方塊圖;
[圖7]是可使用可實施在經堆疊積體電路裝置的晶粒中之一種訊號驅動電路的移位暫存器所傳輸的示範資料之示意圖;
[圖8]是可實施用於在積體電路裝置中傳輸訊號的電路與方法的一種可程式邏輯裝置之方塊圖;
[圖9]是圖8之可程式邏輯裝置的可裝配邏輯元件之方塊圖;且
[圖10]是顯示一種實施在經堆疊積體電路裝置中的複數個晶粒的方法之流程圖。
100:積體電路裝置
102:基板
103:焊球
106:第一基板
108、112、118、122、126:互連層
110:第二基板
116:第三基板
120:第四基板
124:第五基板
128:封裝蓋
130:焊錫凸塊
132:接觸墊
Claims (20)
- 一種具有複數個經堆疊晶粒之積體電路裝置,所述積體電路裝置包含: 所述複數個經堆疊晶粒的第一晶粒,其具有裝配以接收輸入訊號之輸入/輸出元件,所述第一晶粒包含裝配以將所述輸入訊號提供到所述複數個經堆疊晶粒的各個晶粒之訊號驅動電路,及用來產生用於所述複數個經堆疊晶粒的複數個晶片選擇訊號之晶片選擇電路;及 所述複數個經堆疊晶粒的第二晶粒,其耦接到所述第一晶粒,所述第二晶粒具有裝配以接收所述輸入訊號之功能方塊; 其中所述第二晶粒響應於所述複數個晶片選擇訊號中對應於所述第二晶粒之晶片選擇訊號而接收所述輸入訊號。
- 如請求項1之積體電路裝置,其中所述第一晶粒包含接收器,其裝配以接收所述功能方塊的輸出訊號。
- 如請求項2之積體電路裝置,其中所述第一晶粒包含第二輸入/輸出元件,其耦接以接收所述輸出訊號。
- 如請求項1之積體電路裝置,其中所述第二晶粒包含暫存器,其裝配以在資料輸入處接收來自所述訊號驅動電路的所述輸入訊號,且在致能輸入處接收來自所述晶片選擇電路的所述晶片選擇訊號。
- 如請求項1之積體電路裝置,其中所述功能方塊包含記憶體元件。
- 如請求項1之積體電路裝置,其中所述第二晶粒更包含記憶體,其裝配以儲存和所述功能方塊有關聯的資料。
- 如請求項6之積體電路裝置,其中所述第二晶粒更包含第一暫存器,其裝配以在資料輸入處接收來自所述訊號驅動電路的所述輸入訊號,且在致能輸入處接收來自所述晶片選擇電路的所述晶片選擇訊號,且所述第一暫存器的輸出被耦接到所述記憶體的輸入。
- 如請求項7之積體電路裝置,其中所述第二晶粒更包含第二暫存器,其裝配以在資料輸入處接收來自所述訊號驅動電路的資料訊號,且在致能輸入處接收來自所述晶片選擇電路的所述晶片選擇訊號。
- 如請求項8之積體電路裝置,其中所述第二晶粒更包含位元線緩衝器,其裝配以經由所述第二暫存器而在資料輸入處接收所述資料訊號。
- 如請求項1之積體電路裝置,其更包含所述複數個經堆疊晶粒的第三晶粒,其耦接到經堆疊的所述第二晶粒,其中所述第三晶粒包含暫存器,其裝配以在資料輸入處接收來自所述訊號驅動電路的所述輸入訊號,且在致能輸入處接收來自所述晶片選擇電路的所述晶片選擇訊號。
- 一種實施具有複數個經堆疊晶粒之積體電路裝置的方法,所述方法包含: 裝配所述複數個經堆疊晶粒的第一晶粒以在輸入/輸出元件處接收輸入訊號; 裝配所述第一晶粒的訊號驅動電路以將所述輸入訊號提供到所述複數個經堆疊晶粒的各個晶粒; 裝配晶片選擇電路以供產生用於所述複數個經堆疊晶粒的複數個晶片選擇訊號; 將所述複數個經堆疊晶粒的第二晶粒耦接到所述第一晶粒,所述第二晶粒具有裝配以接收所述輸入訊號之功能方塊;且 響應於所述複數個晶片選擇訊號中對應於所述第二晶粒之晶片選擇訊號而在所述第二晶粒處接收所述輸入訊號。
- 如請求項11之方法,其更包含裝配所述第一晶粒之接收器以接收所述功能方塊的輸出訊號。
- 如請求項12之方法,其更包含耦接所述第一晶粒之第二輸入/輸出元件以接收所述輸出訊號。
- 如請求項11之方法,其更包含裝配所述第二晶粒之暫存器以在資料輸入處接收來自所述訊號驅動電路的所述輸入訊號,且在致能輸入處接收來自所述晶片選擇電路的所述晶片選擇訊號。
- 如請求項11之方法,其中所述功能方塊包含記憶體元件。
- 如請求項11之方法,其更包含將和所述功能方塊有關聯的資料儲存在所述第二晶粒之記憶體中。
- 如請求項16之方法,其更包含裝配所述第二晶粒之第一暫存器以在資料輸入處接收來自所述訊號驅動電路的所述輸入訊號,且在致能輸入處接收來自所述晶片選擇電路的所述晶片選擇訊號,且將所述第一暫存器的輸出耦接到所述記憶體的輸入。
- 如請求項17之方法,其更包含裝配所述第二晶粒之第二暫存器以在資料輸入接收處來自所述訊號驅動電路的資料訊號,且在致能輸入處接收來自所述晶片選擇電路的所述晶片選擇訊號。
- 如請求項18之方法,其更包含裝配所述第二晶粒之位元線緩衝器以經由所述第二暫存器而在資料輸入處接收所述資料訊號。
- 如請求項11之方法,其更包含將所述複數個經堆疊晶粒的第三晶粒耦接到經堆疊的所述第二晶粒,其中所述第三晶粒包含暫存器,其裝配以在資料輸入處接收來自所述訊號驅動電路的所述輸入訊號,且在致能輸入處接收來自所述晶片選擇電路的所述晶片選擇訊號。
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US16/511,796 US10797037B1 (en) | 2019-07-15 | 2019-07-15 | Integrated circuit device having a plurality of stacked dies |
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JP (1) | JP2022541160A (zh) |
KR (1) | KR20220036955A (zh) |
CN (1) | CN114128147A (zh) |
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US12019527B2 (en) | 2018-12-21 | 2024-06-25 | Graphcore Limited | Processor repair |
KR20210079543A (ko) * | 2019-12-20 | 2021-06-30 | 삼성전자주식회사 | 고대역폭 메모리 및 이를 포함하는 시스템 |
US11869874B2 (en) * | 2020-12-14 | 2024-01-09 | Advanced Micro Devices, Inc. | Stacked die circuit routing system and method |
KR20220151442A (ko) * | 2021-05-06 | 2022-11-15 | 삼성전자주식회사 | 반도체 패키지 |
CN113793632B (zh) * | 2021-09-02 | 2024-05-28 | 西安紫光国芯半导体有限公司 | 非易失可编程芯片 |
CN113793844B (zh) * | 2021-09-02 | 2024-05-31 | 西安紫光国芯半导体有限公司 | 一种三维集成芯片 |
CN113722268B (zh) * | 2021-09-02 | 2024-07-19 | 西安紫光国芯半导体有限公司 | 一种存算一体的堆叠芯片 |
CN113793849A (zh) * | 2021-09-02 | 2021-12-14 | 西安紫光国芯半导体有限公司 | 集成芯片及其制备方法 |
CN113745197B (zh) * | 2021-09-03 | 2024-08-30 | 西安紫光国芯半导体股份有限公司 | 一种三维异质集成的可编程阵列芯片结构和电子器件 |
US12055586B1 (en) * | 2023-02-24 | 2024-08-06 | Cadence Design Systems, Inc. | 3D stacked die testing structure |
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US9853053B2 (en) * | 2012-09-10 | 2017-12-26 | 3B Technologies, Inc. | Three dimension integrated circuits employing thin film transistors |
US9153292B2 (en) | 2013-03-07 | 2015-10-06 | Xilinx, Inc. | Integrated circuit devices having memory and methods of implementing memory in an integrated circuit device |
US8946884B2 (en) | 2013-03-08 | 2015-02-03 | Xilinx, Inc. | Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product |
US9106229B1 (en) * | 2013-03-14 | 2015-08-11 | Altera Corporation | Programmable interposer circuitry |
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US9935733B1 (en) | 2016-09-20 | 2018-04-03 | Xilinx, Inc. | Method of and circuit for enabling a communication channel |
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