TW202110297A - Substrate structure and manufacturing method thereof - Google Patents

Substrate structure and manufacturing method thereof Download PDF

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TW202110297A
TW202110297A TW108130141A TW108130141A TW202110297A TW 202110297 A TW202110297 A TW 202110297A TW 108130141 A TW108130141 A TW 108130141A TW 108130141 A TW108130141 A TW 108130141A TW 202110297 A TW202110297 A TW 202110297A
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vias
micro
conductive
circuit layer
glass substrate
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TW108130141A
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TWI705745B (en
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簡俊賢
林柏丞
葉文亮
陳建州
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欣興電子股份有限公司
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Priority to TW108130141A priority Critical patent/TWI705745B/en
Priority to CN201910957797.7A priority patent/CN112420653B/en
Priority to US16/673,967 priority patent/US11201123B2/en
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Publication of TWI705745B publication Critical patent/TWI705745B/en
Publication of TW202110297A publication Critical patent/TW202110297A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout

Abstract

A substrate structure includes a glass substrate, a first circuit layer, a second circuit layer, and at least one conductive region. The glass substrate has a first surface and a second surface opposing the first surface. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The conductive region includes a plurality of conductive micro vias. The conductive micro vias penetrate through the glass substrate. The conductive micro vias are electrically connected to the first circuit layer and the second circuit layer, and the conductive micro vias have a via size of 2 μm to 10 μm.

Description

基板結構及其製作方法Substrate structure and manufacturing method thereof

本發明是有關於一種基板結構及其製作方法,且特別是有關於一種具有導電微通孔的基板結構及其製作方法。The invention relates to a substrate structure and a manufacturing method thereof, and more particularly to a substrate structure with conductive micro-vias and a manufacturing method thereof.

由於玻璃基板具有高度平坦的表面,因此適合極細線路的重佈層(redistribution layer,RDL)的製作。然而,玻璃基板中的玻璃通孔(TGV)卻有以下的製程困難:(1) TGV製作成本昂貴,需要經過雷射與蝕刻兩道製程,並使用危害性高的特用化學品。(2) 極細線路常常需要搭配有較高深寬比(aspect ratio, AR)的TGV,但高深寬比的玻璃基板在表面金屬圖形化製程中,為了確保銅金屬在TGV內的導通品質符合基板的需求所採取的措施(例如粗化及表面極性改質),反而不利於極細線路在玻璃基板表面的製作。Since the glass substrate has a highly flat surface, it is suitable for the production of a redistribution layer (RDL) of extremely thin circuits. However, the through-glass via (TGV) in the glass substrate has the following process difficulties: (1) TGV is expensive to manufacture, requires two processes of laser and etching, and uses highly hazardous special chemicals. (2) Very fine lines often need to be matched with a TGV with a higher aspect ratio (AR). However, in the surface metal patterning process of a glass substrate with a high aspect ratio, in order to ensure that the conduction quality of the copper metal in the TGV conforms to the substrate The required measures (such as roughening and surface polarity modification) are not conducive to the production of very fine lines on the surface of the glass substrate.

本發明提供一種基板結構及其製作方法,利用多個導電微通孔來取代習知的導電通孔,具有可縮短習知的玻璃通孔製程、增加產能、降低生產成本、增進基板的機械特性、利於後續極細線路重佈層的製作的優點。The present invention provides a substrate structure and a manufacturing method thereof, using a plurality of conductive micro-vias to replace conventional conductive vias, which can shorten the conventional glass vias manufacturing process, increase productivity, reduce production costs, and improve the mechanical properties of the substrate , Facilitate the advantages of the subsequent production of ultra-fine line re-laying layer.

本發明的基板結構,包括玻璃基板、第一線路層、第二線路層以及至少一導電區。玻璃基板具有第一表面以及相對於第一表面的第二表面。第一線路層配置於第一表面。第二線路層配置於第二表面。導電區包括多個導電微通孔。導電微通孔貫穿玻璃基板。導電微通孔電性連接第一線路層與第二線路層,且導電微通孔的孔徑為2μm至10μm。The substrate structure of the present invention includes a glass substrate, a first circuit layer, a second circuit layer and at least one conductive area. The glass substrate has a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The second circuit layer is configured on the second surface. The conductive area includes a plurality of conductive micro-vias. The conductive micro-via penetrates the glass substrate. The conductive micro-via electrically connects the first circuit layer and the second circuit layer, and the diameter of the conductive micro-via is 2 μm to 10 μm.

在本發明的一實施例中,上述的導電微通孔的總表面積與導電區的表面積的比率為10%至80%。In an embodiment of the present invention, the ratio of the total surface area of the aforementioned conductive micro-vias to the surface area of the conductive region is 10% to 80%.

在本發明的一實施例中,上述的各導電微通孔之間的最小間距等於導電微通孔的孔徑。In an embodiment of the present invention, the minimum distance between the aforementioned conductive micro-vias is equal to the diameter of the conductive micro-vias.

在本發明的一實施例中,上述的導電微通孔的深寬比大於100。In an embodiment of the present invention, the aspect ratio of the aforementioned conductive micro-via is greater than 100.

在本發明的一實施例中,上述的導電區的直徑為45μm至100μm。In an embodiment of the present invention, the diameter of the aforementioned conductive region is 45 μm to 100 μm.

在本發明的一實施例中,上述的玻璃基板的厚度為0.3mm至1.1mm。In an embodiment of the present invention, the thickness of the aforementioned glass substrate is 0.3 mm to 1.1 mm.

本發明的基板結構的製作方法包括以下步驟。提供玻璃基板。玻璃基板具有第一表面以及相對於第一表面的第二表面。形成至少一導電區。導電區包括多個導電微通孔。導電微通孔貫穿玻璃基板,且導電微通孔的孔徑為2μm至10μm。形成第一線路層於第一表面。形成第二線路層於第二表面。導電微通孔電性連接第一線路層與第二線路層。The manufacturing method of the substrate structure of the present invention includes the following steps. Provide glass substrate. The glass substrate has a first surface and a second surface opposite to the first surface. At least one conductive area is formed. The conductive area includes a plurality of conductive micro-vias. The conductive micro-via penetrates the glass substrate, and the diameter of the conductive micro-via is 2 μm to 10 μm. A first circuit layer is formed on the first surface. A second circuit layer is formed on the second surface. The conductive micro-via electrically connects the first circuit layer and the second circuit layer.

在本發明的一實施例中,上述形成多個導電微通孔於至少一導電區內的步驟包括以下步驟。形成多個微通孔於導電區內。微通孔貫穿玻璃基板,且微通孔的孔徑為2μm至10μm。填入導電材料於微通孔內。In an embodiment of the present invention, the step of forming a plurality of conductive micro-vias in at least one conductive area includes the following steps. A plurality of micro-vias are formed in the conductive area. The micro-via penetrates the glass substrate, and the aperture of the micro-via is 2 μm to 10 μm. Fill the conductive material in the micro-via.

在本發明的一實施例中,上述形成微通孔的方法為雷射鑽孔,且不需要蝕刻製程。In an embodiment of the present invention, the above-mentioned method for forming micro-vias is laser drilling, and does not require an etching process.

在本發明的一實施例中,上述的各微通孔之間的最小間距等於微通孔的孔徑。In an embodiment of the present invention, the minimum distance between the above-mentioned micro-vias is equal to the diameter of the micro-vias.

在本發明的一實施例中,上述的微通孔的深寬比大於100。In an embodiment of the present invention, the aspect ratio of the above-mentioned micro vias is greater than 100.

基於上述,在本發明提供的基板結構及其製作方法中,可利用多個導電微通孔來取代習知的導電通孔。其中,由於導電微通孔的孔徑(2μm至10μm)遠小於導電通孔的孔徑,且可利用雷射鑽孔的方式直接形成微通孔而不需要額外的蝕刻製程,因此,可縮短習知的玻璃通孔製程、增加產能、降低生產成本、增進基板的機械特性、利於後續極細線路重佈層的製作的優點。Based on the above, in the substrate structure and the manufacturing method thereof provided by the present invention, a plurality of conductive micro-vias can be used to replace the conventional conductive vias. Among them, since the aperture of the conductive micro-via (2μm to 10μm) is much smaller than that of the conductive via, and the laser drilling method can be used to directly form the micro-via without the need for an additional etching process, therefore, the conventional method can be shortened. The advantages of the glass through-hole manufacturing process, increase production capacity, reduce production costs, improve the mechanical properties of the substrate, and facilitate the production of the subsequent ultra-fine circuit redistribution layer.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

[實施例1][Example 1]

圖1A至圖1C繪示為本發明的實施例1的一種基板結構的製作方法的剖面示意圖。圖2繪示為圖1A的俯視示意圖。1A to 1C are schematic cross-sectional views of a method for manufacturing a substrate structure according to Embodiment 1 of the present invention. Fig. 2 is a schematic top view of Fig. 1A.

請同時參照圖1A與圖2,先提供一玻璃基板110。玻璃基板110具有第一表面111以及相對於第一表面111的第二表面112。玻璃基板110的厚度例如是0.3mm至1.1mm。接著,例如是以雷射鑽孔的方法,在玻璃基板110的導電區預定位置120、120a形成多個微通孔130、130a。微通孔130、130a貫穿玻璃基板110,且連通玻璃基板110的第一表面111與第二表面112。其中,微通孔130、130a的孔徑例如是2μm至10μm。微通孔130、130a的深寬比例如是大於100。舉例來說,當玻璃基板110的厚度為0.3mm時,可搭配的最大的微通孔130、130a的孔徑為3μm;而當玻璃基板110的厚度為1.1mm時,可搭配的最大的微通孔130、130a的孔徑為10μm。1A and 2 at the same time, a glass substrate 110 is provided first. The glass substrate 110 has a first surface 111 and a second surface 112 opposite to the first surface 111. The thickness of the glass substrate 110 is, for example, 0.3 mm to 1.1 mm. Next, for example, a laser drilling method is used to form a plurality of micro-vias 130, 130a at predetermined positions 120, 120a of the conductive area of the glass substrate 110. The micro through holes 130 and 130a penetrate the glass substrate 110 and communicate with the first surface 111 and the second surface 112 of the glass substrate 110. Wherein, the pore diameter of the micro through holes 130 and 130a is, for example, 2 μm to 10 μm. The aspect ratio of the micro vias 130 and 130a is, for example, greater than 100. For example, when the thickness of the glass substrate 110 is 0.3mm, the diameter of the largest microvia 130, 130a that can be matched is 3μm; and when the thickness of the glass substrate 110 is 1.1mm, the largest microvia that can be matched The pore diameter of the holes 130 and 130a is 10 μm.

具體來說,導電區預定位置120、120a於第一表面111(或第二表面112)的形狀例如是圓形或橢圓型,但不以此為限。導電區預定位置120、120a於第一表面111(或第二表面112)的直徑例如是45μm至100μm。此外,導電區預定位置120、120a中的微通孔130、130a例如是以陣列排列的方式排列於導電區預定位置120、120a。因此,各微通孔130、130a之間的間距相等,但不以此為限。也就是說,在其他實施例中,各微通孔130、130a之間的間距也可以不同,只要使間距都大於等於微通孔130、130a的孔徑,進而能穩定微通孔130、130a的結構即可。更進一步來說,在一些實施例中,各微通孔130(或130a)之間的最小間距可等於微通孔130(或130a)的孔徑。也就是說,其中一個微通孔130(或130a)的孔緣至相鄰的微通孔130(或130a)的孔緣之間的最小距離可等於微通孔130(或130a)的孔徑。舉例來說,當導電區預定位置120中的多個微通孔130的孔徑為5μm時,其中一個微通孔130的孔緣至相鄰的微通孔130的孔緣之間的最小距離為5μm。Specifically, the shape of the predetermined positions 120 and 120a of the conductive area on the first surface 111 (or the second surface 112) is, for example, a circle or an ellipse, but it is not limited thereto. The diameter of the predetermined positions 120 and 120a of the conductive area on the first surface 111 (or the second surface 112) is, for example, 45 μm to 100 μm. In addition, the micro-vias 130 and 130a in the predetermined positions 120 and 120a of the conductive area are arranged in the predetermined positions 120 and 120a of the conductive area, for example, in an array arrangement. Therefore, the spacing between the micro-vias 130 and 130a is equal, but not limited to this. That is to say, in other embodiments, the spacing between the micro-vias 130, 130a can also be different, as long as the spacing is greater than or equal to the aperture of the micro-vias 130, 130a, which can stabilize the micro-vias 130, 130a. The structure is fine. Furthermore, in some embodiments, the minimum distance between the micro-vias 130 (or 130a) may be equal to the diameter of the micro-vias 130 (or 130a). That is, the minimum distance from the edge of one micro-via 130 (or 130a) to the edge of the adjacent micro-via 130 (or 130a) may be equal to the diameter of the micro-via 130 (or 130a). For example, when the aperture of the plurality of micro-vias 130 in the predetermined position 120 of the conductive region is 5 μm, the minimum distance from the edge of one micro-via 130 to the edge of the adjacent micro-via 130 is 5μm.

接著,請參照圖1B,將導電材料填入於微通孔130、130a內,以形成導電微通孔131、131a以及導電區121、121a。可通過例如是化鍍(chemical plating)的鍍覆製程來形成導電材料。所述導電材料可為金屬或金屬合金,例如銅、鈦、鎢、鋁等或其組合。因此,在本實施例中,多個導電微通孔131、131a設置於導電區121、121a內,導電微通孔131、131a貫穿玻璃基板110,且導電微通孔131、131a的孔徑為2μm至10μm。Next, referring to FIG. 1B, a conductive material is filled in the micro-vias 130, 130a to form conductive micro-vias 131, 131a and conductive regions 121, 121a. The conductive material can be formed by a plating process such as chemical plating. The conductive material may be a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, etc., or a combination thereof. Therefore, in this embodiment, a plurality of conductive micro-vias 131, 131a are provided in the conductive regions 121, 121a, the conductive micro-vias 131, 131a penetrate the glass substrate 110, and the conductive micro-vias 131, 131a have a diameter of 2 μm. To 10μm.

具體來說,導電區121、121a於第一表面111(或第二表面112)的直徑例如是45μm至100μm。各導電微通孔131(或131a)之間的最小間距等於導電微通孔131(或131a)的孔徑。因此,其中一個導電微通孔131(或131a)的孔緣至相鄰的導電微通孔131(或131a)的孔緣之間的最小距離等於2μm至10μm。此外,每個導電區121(或121a)內的所有導電微通孔131(或131a)的總表面積與導電區121(或121a)於第一表面111或第二表面112的表面積的比率為10%至80%,以具備較好之導電性。Specifically, the diameter of the conductive regions 121 and 121a on the first surface 111 (or the second surface 112) is, for example, 45 μm to 100 μm. The minimum distance between the conductive micro-vias 131 (or 131a) is equal to the diameter of the conductive micro-vias 131 (or 131a). Therefore, the minimum distance from the edge of one conductive micro-via 131 (or 131a) to the edge of the adjacent conductive micro-via 131 (or 131a) is equal to 2 μm to 10 μm. In addition, the ratio of the total surface area of all the conductive micro-vias 131 (or 131a) in each conductive region 121 (or 121a) to the surface area of the conductive region 121 (or 121a) on the first surface 111 or the second surface 112 is 10 % To 80%, in order to have better conductivity.

然後,請參照圖1C,例如是以電鍍的方式,在玻璃基板110的第一表面111形成第一線路層140,並在玻璃基板110的第二表面112形成第二線路層150。其中,導電微通孔131、131a電性連接第一線路層140與第二線路層150。在本實施例中,第一線路層140直接接觸玻璃基板110,且第二線路層150直接接觸玻璃基板110。在一些實施例中,第一線路層140包括多個接墊141、142,第二線路層150包括多個接墊151、152,其中,接墊141對應於接墊151設置,且接墊141透過導電微通孔131電性連接至接墊151。接墊142對應於接墊152設置,且接墊142透過導電微通孔131a電性連接至接墊152。此時,已製造完成實施例1的基板結構100。Then, referring to FIG. 1C, for example, a first circuit layer 140 is formed on the first surface 111 of the glass substrate 110, and a second circuit layer 150 is formed on the second surface 112 of the glass substrate 110 by electroplating, for example. Wherein, the conductive micro vias 131 and 131a are electrically connected to the first circuit layer 140 and the second circuit layer 150. In this embodiment, the first circuit layer 140 directly contacts the glass substrate 110, and the second circuit layer 150 directly contacts the glass substrate 110. In some embodiments, the first circuit layer 140 includes a plurality of pads 141, 142, and the second circuit layer 150 includes a plurality of pads 151, 152, wherein the pad 141 is arranged corresponding to the pad 151, and the pad 141 It is electrically connected to the pad 151 through the conductive micro-via 131. The pad 142 is disposed corresponding to the pad 152, and the pad 142 is electrically connected to the pad 152 through the conductive micro-via 131a. At this time, the substrate structure 100 of Example 1 has been manufactured.

簡言之,本實施例的基板結構100包括玻璃基板110、第一線路層140、第二線路層150以及至少一導電區121、121a。玻璃基板110具有第一表面111以及相對於第一表面111的第二表面112。第一線路層140配置於第一表面111。第二線路層150配置於第二表面112。導電區121、121a包括多個導電微通孔131、131a。導電微通孔131、131a貫穿玻璃基板110,且電性連接第一線路層140與第二線路層150。導電微通孔131、131a的孔徑為2μm至10μm。此外,由於微通孔130(或130a)的孔徑小,可利用雷射鑽孔的方式直接形成且不需要額外的蝕刻製程,因此,可縮短玻璃通孔製程,進而增加產能、降低生產成本、增進基板的機械特性且可利於後續極細線路重佈層的製作。In short, the substrate structure 100 of this embodiment includes a glass substrate 110, a first circuit layer 140, a second circuit layer 150, and at least one conductive region 121, 121a. The glass substrate 110 has a first surface 111 and a second surface 112 opposite to the first surface 111. The first circuit layer 140 is disposed on the first surface 111. The second circuit layer 150 is disposed on the second surface 112. The conductive regions 121, 121a include a plurality of conductive micro-vias 131, 131a. The conductive micro vias 131 and 131 a penetrate the glass substrate 110 and electrically connect the first circuit layer 140 and the second circuit layer 150. The pore diameters of the conductive micro-vias 131 and 131a are 2 μm to 10 μm. In addition, because the aperture of the micro via 130 (or 130a) is small, it can be directly formed by laser drilling and does not require an additional etching process. Therefore, the glass via process can be shortened, thereby increasing productivity, reducing production costs, Improve the mechanical properties of the substrate and facilitate the production of the subsequent ultra-fine circuit redistribution layer.

[比較例1][Comparative Example 1]

圖3A至圖3C繪示為比較例1的基板結構的製作方法的剖面示意圖。圖4繪示為圖3B的俯視示意圖。3A to 3C are schematic cross-sectional diagrams of the manufacturing method of the substrate structure of Comparative Example 1. FIG. Fig. 4 is a schematic top view of Fig. 3B.

請參照圖3A至圖3B,其為習知製造玻璃通孔(through-glass via,TGV)的步驟。首先,以雷射的方式對玻璃基板210中的玻璃通孔預定位置220、220a進行改質,接著,再利用蝕刻製程去除玻璃通孔預定位置220、220a中的玻璃基板210,以形成玻璃通孔230、230a。其中,蝕刻製程例如是使用氫氟酸或其他適合的玻璃蝕刻液來去除改質後的玻璃。此處,玻璃通孔預定位置220、220a於玻璃基板210的表面的直徑等於玻璃通孔230、230a的孔徑,且例如是45μm至100μm。Please refer to FIG. 3A to FIG. 3B, which are the steps of manufacturing a through-glass via (TGV) in the prior art. First, the predetermined positions 220, 220a of the through-glass holes in the glass substrate 210 are modified by laser, and then the glass substrate 210 in the predetermined positions 220, 220a of the through-glass holes is removed by an etching process to form the through-glass holes. Holes 230, 230a. Among them, the etching process uses, for example, hydrofluoric acid or other suitable glass etching solutions to remove the modified glass. Here, the diameters of the predetermined positions 220 and 220a of the through-glass holes on the surface of the glass substrate 210 are equal to the diameters of the through-glass holes 230 and 230a, and are, for example, 45 μm to 100 μm.

接著,請參照圖3C,例如是以電鍍的方式,在玻璃基板210的兩側的表面分別形成第一線路層240及第二線路層250,以及在玻璃通孔230、230a的孔壁形成導電層,以形成導電通孔231、231a。導電通孔231、231a的孔徑為45μm至100μm。此時,已製造完成比較例1的基板結構200。Next, referring to FIG. 3C, for example, by electroplating, a first circuit layer 240 and a second circuit layer 250 are formed on the surfaces of both sides of the glass substrate 210, and conductive holes are formed on the walls of the glass vias 230 and 230a. Layer to form conductive vias 231, 231a. The hole diameter of the conductive vias 231 and 231a is 45 μm to 100 μm. At this time, the substrate structure 200 of Comparative Example 1 has been manufactured.

[實施例1及比較例1的比較][Comparison of Example 1 and Comparative Example 1]

請同時參照圖1A至圖1C、圖2、圖3A至圖3C以及圖4,首先,可得知實施例1的導電區121、121a與比較例1的玻璃通孔230、230a的大小相同。例如:實施例1的導電區預定位置120、120a於第一表面111(或第二表面112)的直徑與比較例1的玻璃通孔230、230a的孔徑皆為45μm至100μm。實施例1的玻璃基板110兩側分別有第一線路層140及第二線路層150,而比較例1的玻璃基板210兩側也分別有第一線路層240及第二線路層250。Please refer to FIGS. 1A to 1C, FIGS. 2, 3A to 3C, and FIG. 4 at the same time. First, it can be known that the conductive regions 121 and 121a of Example 1 have the same size as the through glass holes 230 and 230a of Comparative Example 1. For example, the diameters of the predetermined positions 120 and 120a of the conductive regions on the first surface 111 (or the second surface 112) of Example 1 and the apertures of the glass through holes 230 and 230a of Comparative Example 1 are both 45 μm to 100 μm. The glass substrate 110 of Example 1 has a first circuit layer 140 and a second circuit layer 150 on both sides, and the glass substrate 210 of Comparative Example 1 also has a first circuit layer 240 and a second circuit layer 250 on both sides.

然而,實施例1與比較例1的主要差異在於:相較於比較例1以單個導電通孔231(或導電通孔231a)來電性連接第一線路層240與第二線路層250,實施例1則是在與比較例1的導電通孔231(或導電通孔231a)相同大小的導電區121(或導電區121a)中,設置多個導電微通孔131(或導電微通孔131a)來取代比較例1的單個導電通孔231(或導電通孔231a),並用以電性連接第一線路層140與第二線路層150。也就是說,在單位面積內,實施例1以多個導電微通孔131(或導電微通孔131a)來取代比較例1的單個導電通孔231(或導電通孔231a)來電性連接第一線路層140與第二線路層150。其中,實施例1的導電微通孔131、131a的孔徑為2μm至10μm,但比較例1的導電通孔231、231a的孔徑為45μm至100μm。However, the main difference between Example 1 and Comparative Example 1 is that compared with Comparative Example 1, a single conductive via 231 (or conductive via 231a) is used to electrically connect the first circuit layer 240 and the second circuit layer 250. 1 is to provide a plurality of conductive micro-vias 131 (or conductive micro-vias 131a) in the conductive region 121 (or conductive region 121a) of the same size as the conductive via 231 (or conductive via 231a) of Comparative Example 1. It replaces the single conductive via 231 (or conductive via 231a) of Comparative Example 1, and is used to electrically connect the first circuit layer 140 and the second circuit layer 150. That is to say, in a unit area, Example 1 uses a plurality of conductive micro-vias 131 (or conductive micro-vias 131a) to replace the single conductive via 231 (or conductive vias 231a) of Comparative Example 1 to electrically connect the A circuit layer 140 and a second circuit layer 150. Among them, the conductive micro vias 131 and 131a of Example 1 have a diameter of 2 μm to 10 μm, but the conductive vias 231 and 231a of Comparative Example 1 have a diameter of 45 μm to 100 μm.

此外,由於實施例1的導電微通孔131、131a的孔徑遠小於比較例1的導電通孔231、231a的孔徑,因此,相較於比較例1須利用雷射改質及蝕刻製程來形成玻璃通孔230、230a,實施例1只須利用雷射鑽孔的方式而不需要額外的蝕刻製程,即可直接製作出多個微通孔130、130a。換言之,當欲形成的玻璃通孔的孔徑大於10μm時,實務上習知技術會利用雷射改質及蝕刻製程來形成。進一步而言,由於實施例1藉由多個微通孔130、130a來取代單個玻璃通孔230、230a的方式,進而使得實施例1具有可縮短玻璃通孔製程、增加產能以及降低生產成本的優點。In addition, since the apertures of the conductive micro-vias 131, 131a of Example 1 are much smaller than the apertures of the conductive vias 231, 231a of Comparative Example 1, they must be formed by laser modification and etching processes compared to Comparative Example 1. The glass vias 230, 230a, in the first embodiment, only a laser drilling method is used without an additional etching process, and a plurality of micro vias 130, 130a can be directly produced. In other words, when the aperture of the glass through hole to be formed is greater than 10 μm, in practice, the conventional technology will use the laser modification and etching process to form it. Furthermore, since Embodiment 1 replaces a single glass via 230, 230a with a plurality of micro vias 130, 130a, the embodiment 1 has the advantages of shortening the glass via process, increasing productivity, and reducing production costs. advantage.

接著,相較於比較例1形成導電通孔231、231a的方式,實施例1可利用化學濕製程,例如化鍍的方式,對微通孔130、130a進行金屬化製程來形成導電微通孔131、131a。此外,化學濕製程也不會受到微通孔130、130a的高深寬比的限制,且可確保金屬在微通孔130、130a內皆已導通。另外,實施例1的微通孔130、130a也不會影響後續極細線路重佈層(RDL)在玻璃基板110的表面的製作,可大幅降低電鍍製程難度。Next, compared to the method of forming the conductive vias 231, 231a in Comparative Example 1, in Example 1, a chemical wet process, such as electroless plating, can be used to perform a metallization process on the micro vias 130, 130a to form conductive micro vias. 131, 131a. In addition, the chemical wet process is not limited by the high aspect ratio of the micro vias 130, 130a, and it can ensure that the metal is conducted in the micro vias 130, 130a. In addition, the micro-vias 130 and 130a of Embodiment 1 will not affect the subsequent fabrication of the ultra-fine line redistribution layer (RDL) on the surface of the glass substrate 110, which can greatly reduce the difficulty of the electroplating process.

值得說明的是,由於本實施例的基板結構應用了導電微通孔形成於玻璃基板上,使玻璃基板具有較好的機械特性,更進而使得本實施例的基板結構具有較佳的平整度且適於極細線路重佈層(RDL)的製作,甚至還可應用於5G天線設計的一部分。It is worth noting that because the substrate structure of this embodiment uses conductive micro-vias formed on the glass substrate, the glass substrate has better mechanical properties, and furthermore, the substrate structure of this embodiment has better flatness and It is suitable for the production of ultra-fine line redistribution layer (RDL), and can even be used as part of the 5G antenna design.

綜上所述,在本發明提供的基板結構及其製作方法中,可利用多個導電微通孔來取代習知的導電通孔。其中,由於導電微通孔的孔徑(2μm至10μm)遠小於導電通孔的孔徑,且可利用雷射鑽孔的方式直接形成微通孔而不需要額外的蝕刻製程,因此,可縮短習知的玻璃通孔製程、增加產能、降低生產成本、增進基板的機械特性、利於後續極細線路重佈層的製作的優點。In summary, in the substrate structure and manufacturing method provided by the present invention, a plurality of conductive micro-vias can be used to replace the conventional conductive vias. Among them, since the aperture of the conductive micro-via (2μm to 10μm) is much smaller than that of the conductive via, and the laser drilling method can be used to directly form the micro-via without the need for an additional etching process, therefore, the conventional method can be shortened. The advantages of the glass through-hole manufacturing process, increase production capacity, reduce production costs, improve the mechanical properties of the substrate, and facilitate the production of the subsequent ultra-fine circuit redistribution layer.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100、200:基板結構 110、210:玻璃基板 111:第一表面 112:第二表面 120、120a:導電區預定位置 121、121a:導電區 130、130a:微通孔 131、131a:導電微通孔 140、240:第一線路層 141、142:接墊 150、250:第二線路層 151、152:接墊 220、220a:玻璃通孔預定位置 230、230a:玻璃通孔 231、231a:導電通孔100, 200: substrate structure 110, 210: glass substrate 111: first surface 112: second surface 120, 120a: predetermined position of conductive area 121, 121a: conductive area 130, 130a: micro-via 131, 131a: Conductive micro vias 140, 240: first circuit layer 141, 142: pads 150, 250: second circuit layer 151, 152: pads 220, 220a: predetermined position of glass through hole 230, 230a: glass through hole 231, 231a: conductive vias

圖1A至圖1C繪示為本發明的實施例1的一種基板結構的製作方法的剖面示意圖。 圖2繪示為圖1A的俯視示意圖。 圖3A至圖3C繪示為比較例1的基板結構的製作方法的剖面示意圖。 圖4繪示為圖3B的俯視示意圖。1A to 1C are schematic cross-sectional views of a method for manufacturing a substrate structure according to Embodiment 1 of the present invention. Fig. 2 is a schematic top view of Fig. 1A. 3A to 3C are schematic cross-sectional diagrams of the manufacturing method of the substrate structure of Comparative Example 1. FIG. Fig. 4 is a schematic top view of Fig. 3B.

100:基板結構 100: substrate structure

110:玻璃基板 110: glass substrate

111:第一表面 111: first surface

112:第二表面 112: second surface

131、131a:導電微通孔 131, 131a: Conductive micro vias

140:第一線路層 140: first circuit layer

141、142:接墊 141, 142: pads

150:第二線路層 150: second circuit layer

151、152:接墊 151, 152: pads

Claims (11)

一種基板結構,包括: 一玻璃基板,具有一第一表面以及相對於該第一表面的一第二表面; 一第一線路層,配置於該第一表面; 一第二線路層,配置於該第二表面;以及 至少一導電區,包括多個導電微通孔,其中該些導電微通孔貫穿該玻璃基板,該些導電微通孔電性連接該第一線路層與該第二線路層,且該些導電微通孔的孔徑為2μm至10μm。A substrate structure, including: A glass substrate having a first surface and a second surface opposite to the first surface; A first circuit layer disposed on the first surface; A second circuit layer disposed on the second surface; and At least one conductive area includes a plurality of conductive micro-vias, wherein the conductive micro-vias penetrate through the glass substrate, the conductive micro-vias are electrically connected to the first circuit layer and the second circuit layer, and the conductive micro-vias The pore diameter of the micro-via is 2 μm to 10 μm. 如申請專利範圍第1項所述的基板結構,其中該些導電微通孔的總表面積與該導電區的表面積的比率為10%至80%。In the substrate structure described in the first item of the scope of the patent application, the ratio of the total surface area of the conductive micro-vias to the surface area of the conductive region is 10% to 80%. 如申請專利範圍第1項所述的基板結構,其中各該導電微通孔之間的最小間距等於該些導電微通孔的孔徑。According to the substrate structure described in item 1 of the scope of patent application, the smallest distance between the conductive micro-vias is equal to the diameter of the conductive micro-vias. 如申請專利範圍第1項所述的基板結構,其中該些導電微通孔的深寬比大於100。In the substrate structure described in item 1 of the scope of the patent application, the aspect ratio of the conductive micro-vias is greater than 100. 如申請專利範圍第1項所述的基板結構,其中該導電區的直徑為45μm至100μm。In the substrate structure described in the first item of the scope of patent application, the diameter of the conductive region is 45 μm to 100 μm. 如申請專利範圍第1項所述的基板結構,其中該玻璃基板的厚度為0.3mm至1.1mm。According to the substrate structure described in item 1 of the scope of patent application, the thickness of the glass substrate is 0.3 mm to 1.1 mm. 一種基板結構的製作方法,包括: 提供一玻璃基板,具有一第一表面以及相對於該第一表面的一第二表面; 形成至少一導電區,包括多個導電微通孔,其中該些導電微通孔貫穿該玻璃基板,且該些導電微通孔的孔徑為2μm至10μm; 形成一第一線路層於該第一表面;以及 形成一第二線路層於該第二表面,其中該些導電微通孔電性連接該第一線路層與該第二線路層。A method for manufacturing a substrate structure includes: Providing a glass substrate having a first surface and a second surface opposite to the first surface; Forming at least one conductive area, including a plurality of conductive micro-vias, wherein the conductive micro-vias penetrate the glass substrate, and the conductive micro-vias have a diameter of 2 μm to 10 μm; Forming a first circuit layer on the first surface; and A second circuit layer is formed on the second surface, wherein the conductive micro-vias are electrically connected to the first circuit layer and the second circuit layer. 如申請專利範圍第7項所述的基板結構的製作方法,其中形成多個導電微通孔於至少一導電區內的步驟包括: 形成多個微通孔於該導電區內,其中該些微通孔貫穿該玻璃基板,且該些微通孔的孔徑為2μm至10μm;以及 填入導電材料於該些微通孔內。According to the manufacturing method of the substrate structure described in item 7 of the scope of patent application, the step of forming a plurality of conductive micro-vias in at least one conductive area includes: Forming a plurality of micro-vias in the conductive area, wherein the micro-vias penetrate the glass substrate, and the apertures of the micro-vias are 2 μm to 10 μm; and Fill the conductive material in the micro through holes. 如申請專利範圍第8項所述的基板結構的製作方法,其中形成該些微通孔的方法為雷射鑽孔,且不需要蝕刻製程。According to the manufacturing method of the substrate structure described in item 8 of the scope of the patent application, the method for forming the micro-vias is laser drilling and does not require an etching process. 如申請專利範圍第7項所述的基板結構的製作方法,其中各該微通孔之間的最小間距等於該些微通孔的孔徑。According to the manufacturing method of the substrate structure described in item 7 of the scope of patent application, the minimum distance between the micro-vias is equal to the aperture of the micro-vias. 如申請專利範圍第7項所述的基板結構的製作方法,其中該些微通孔的深寬比大於100。According to the manufacturing method of the substrate structure described in item 7 of the scope of patent application, the aspect ratio of the micro vias is greater than 100.
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