JP2012033879A - Component built-in substrate and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that the shape of a conductive via may be distorted significantly due to resin flow when a component is built in and thereby electrically stable via connection is not obtained, and a copper foil to be connected with the conductive via must satisfy the requirements of soldering.SOLUTION: A component built-in substrate 101 has a multilayer substrate 115 where a first insulation layer 102 and a second insulation layer 105 are laminated, a circuit component 112 mounted on a wiring pattern 111 on the inner layer side of the first insulation layer 102 which is the outermost layer of the multilayer substrate 115, and a housing section 114 which houses the circuit component 112. The space between the circuit component 112 and the multilayer substrate 115 is filled with a hardened matter of a second hardening resin 106, and a via 109 is formed of a conductive paste 110. The via 109 is constituted of a first metal region principally comprising an intermetallic compound and covering the periphery of surface contact area of Cu particles so as to straddle that area, and a second metal region principally comprising Bi.

Description

  The present invention relates to a component-embedded substrate that incorporates passive components, active components, and the like, and a method of manufacturing the same.

  2. Description of the Related Art In recent years, electronic devices have become more sophisticated, and devices represented by modules have been downsized. For example, an application that is strongly required to keep the substrate thickness below a certain thickness and to be miniaturized even though the number of layers required for the module substrate is as large as 6 or more, as represented by a camera module There are several. Therefore, a component built-in board has been proposed.

  A conventional electronic component built-in substrate will be described with reference to FIG. FIG. 14 is a cross-sectional view of a conventional electronic component built-in substrate.

  In FIG. 14, a conventional component-embedded substrate 1 includes an inner via 2, a wiring pattern 3, a built-in interlayer connection via 4, an electrical insulating layer 5, a composite layer 6, a circuit component 7, a component built-in layer 8, and the like.

  As prior art document information of this technology, for example, Patent Document 1 is known.

Japanese Patent No. 3547423

  In the conventional component-embedded substrate shown in Patent Document 1 or the like, an electrical insulating material (referred to as a composite material in the present specification) made of a mixture containing an inorganic filler and a curable resin whose elastic modulus is regulated to a predetermined value is used. As a result, conductive via connection can be made against the resin flow accompanying the built-in component, and the wiring pattern routing design was easy.

  On the other hand, since composite materials do not have glass cloth or other reinforcing materials, there are many handling problems, especially when working with large workpieces, chipping is likely to occur when handling composite sheets, etc. It was difficult to realize. In addition, there are many restrictions on the thickness of the sheet made of the composite material, and it has been possible to produce a component-embedded substrate using the composite sheet only within a limited thickness specification.

  To deal with these issues, it has been attempted to replace the composite sheet with a prepreg material with glass reinforcement, etc. to achieve compatibility between the component integration process and conductive via connection. There is a case where the shape of the conductive via is greatly distorted due to the resin flow, and an electrically stable via connection cannot be obtained.

  Further, the copper foil connected to the conductive via has a new problem that it must satisfy the requirement for solder mounting.

  Therefore, the present invention solves the above-mentioned conventional problems, and at the same time, realizes interlayer via connection using a stable conductive via paste in all layers while using a substrate for a wiring board such as FR4. We propose a component-embedded board that can stably embed components at a work size. Furthermore, the present invention proposes a component-embedded substrate that can achieve all of stable via connection that resists resin flow when the component is embedded, ensuring adhesion between the copper foil and the resin base material, and stable solder wettability.

  The component-embedded substrate of the present invention and the manufacturing method thereof can provide a component-embedded substrate that is excellent in size, thickness, cost, and mass productivity for the first time, and modules and packages using the substrate. The board can be replaced with an existing general-purpose module or package board.

  In order to achieve the above object, the component-embedded substrate of the present invention includes a first insulating layer having a first glass fiber, a first curable resin, and a wiring pattern, a second glass fiber, and a second curing. A multilayer substrate portion formed by laminating a second insulating layer having a conductive resin and a via portion, and mounted on the wiring pattern on the inner layer side of the first insulating layer of the outermost layer of the multilayer substrate portion A component-embedded substrate having a circuit component and a housing portion that is provided in the multilayer substrate portion and accommodates the circuit component, wherein the multilayer substrate portion is cured with the first insulating layer and uncured The second insulating layer is alternately laminated, cured and integrated, and the second insulating layer is interposed between the circuit component housed in the housing portion and the multilayer substrate portion. The cured product of the second curable resin of the layer is filled, and the via portion is the second A through hole formed in the edge layer, and component-embedded substrate, comprising the electrically connected conductive paste to the wiring pattern of the filled in the through hole of the first insulating layer.

  Furthermore, in order to ensure a stable via connection by a copper foil to be soldered and a conductive via paste, the conductive paste includes a metal portion including at least Cu, Sn, and Bi, and a resin portion, A region composed of Cu particles, a first metal region covering the periphery so as to straddle the surface contact portion of the Cu particles with an intermetallic compound as a main component, and a second metal region mainly composed of Bi. Then, the surface of the copper foil to be solder-mounted is roughened by a micro-etching method so that the shape of the bump shape is 2 μm or less, thereby stabilizing via connection that resists resin flow, copper foil and resin base It is possible to achieve both secure adhesion to the material and stable solder wettability.

  With the above configuration, a structure that can achieve compatibility between the component incorporation process and the conductive via connection, that is, a configuration using a wiring board base material such as FR4, but an interlayer via connection using a stable conductive via paste is achieved. At the same time as realizing it on all layers, it is possible to realize a process that can stably incorporate components with a large workpiece size. As a result, it is possible to provide an electronic component built-in substrate that is small, thin, cost-effective, and mass-productive, as well as modules and packages using the same, and the component built-in substrate replaces the existing module or package substrate as a general-purpose device. It becomes possible.

(A) (B) is sectional drawing of the electronic component built-in board by the 8 layer structure by Embodiment 1 of this invention both (C) and (d) are a schematic view of a connection portion and a cross-sectional SEM photograph of the conductive paste shown in FIGS. FIGS. 4A to 4F are cross-sectional views illustrating a state in which vias made of conductive paste are formed in the first insulating layer and wiring patterns are formed on both surfaces thereof. (A)-(G) are sectional drawings explaining an example of the manufacturing method of the 1st insulating layer which mounts circuit components together. (A)-(F) are sectional drawings which show an example of the manufacturing method of a 2nd insulating layer. (A) and (B) are cross-sectional views illustrating a state in which a cured first insulating layer, an uncured second insulating layer, and the like are stacked, integrated, and cured. (A) (B) is sectional drawing explaining a mode that an uncured 2nd curable resin oozes out. (A) and (B) are a cross-sectional view of the component-embedded substrate of the present invention and a cross-sectional SEM photograph, respectively (A) (B) is sectional drawing which shows the structure which implement | achieves further thinning of a component built-in board | substrate together (C), (d) and (e) are cross-sectional views of an electronic component built-in substrate each having a five-layer structure, and an enlarged view of the portion (F) and (g) are cross-sectional views of the substrate with built-in electronic components when both are plated. (A) (B) is sectional drawing which shows the structure of the comparative example 1 and the comparative example 2, respectively (A)-(C) is sectional drawing which shows the structure of Example 1, Example 2, and Example 3 together Sectional view of a conventional electronic component built-in substrate

(Embodiment 1)
Embodiment 1 of an electronic component built-in substrate and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.

  1A and 1B are a cross-sectional view of an electronic component built-in substrate having an eight-layer structure according to Embodiment 1 of the present invention, and an enlarged cross-sectional view, respectively. In addition, between FIG. 1 (A) and (B), for description, a part is changed and a part is abbreviate | omitted.

  1A and 1B, 101 is a component-embedded substrate, 102 is a first insulating layer, 103 is a first curable resin, 104 is a first glass fiber, and the first insulating layer 102 is The first glass fiber 104 and the first curable resin 103 impregnated therein are used. Reference numeral 105 denotes a second insulating layer, 106 denotes a second curable resin, 107 denotes a second glass fiber, and the second insulating layer 105 includes the second glass fiber 107 and the second impregnated therein. Curable resin 106. Reference numeral 108 denotes a through hole, 109 denotes a via, and 110 denotes a conductive paste. In FIG. 1, since these overlap at the same place, they are partially overlapped. The through-hole 108 formed in the second insulating layer 105 is filled with a conductive paste 110 to form a via 109. Reference numeral 111 denotes a wiring pattern which is formed on the first insulating layer 102, and the second insulating layer is formed between the plurality of wiring patterns 111 which are interlayer-insulated via the first insulating layer 102. The layers are electrically connected to each other by a conductive paste 110 filled in through-holes 108 formed in 105.

  Reference numeral 112 denotes a circuit component, 113 denotes a mounting material, 114 denotes a housing portion, and 115 denotes a multilayer substrate portion. The circuit component 112 is mounted on a wiring pattern 111 on the inner layer side of the first insulating layer 102 which is at least one of the outermost layers of the component-embedded substrate 101 with a mounting material 113 such as solder. The multilayer substrate 115 includes a first insulating layer 102 having a first glass fiber 104, a first curable resin 103, and a wiring pattern 111, a second glass fiber 107, and a second curable resin 106. And a second insulating layer 105 having vias 109 are stacked. In addition, it is desirable that the multilayer substrate portion 115 be formed by alternately laminating the cured first insulating layer 102 and the uncured second insulating layer 105, which are alternately stacked.

  The multilayer substrate 115 is formed with a housing 114 that is slightly larger than the circuit component 112. Then, a cured product of the second curable resin 106 impregnated in the second insulating layer 105 is filled between the circuit component 112 accommodated in the accommodating portion 114 and the multilayer substrate portion 115.

  This will be described in more detail. As shown in FIG. 1, the component-embedded substrate 101 according to the first embodiment includes a wiring material 111, a passive component such as a chip capacitor and a chip resistor, and a circuit component 112 such as a wafer level CSP as a mounting material 113 (for example, Sn-Ag). -Cu-based solder material or the like) and electrically or mechanically connected, and embedded or embedded in the accommodating portion 114. A wiring pattern 111 is also formed and arranged in the first and second insulating layers 102 and 105.

  Further, the wiring pattern 111 constituting a land electrode portion (not shown) on which the mounting material 113 is printed and applied and on which the circuit component 112 is mounted has a second portion while ensuring the wettability of the mounting material 113. The insulating layer 105 (note that the second insulating layer is not shown, but is roughened to ensure adhesion with an uncured, ie, curable prepreg insulating layer). . Even more preferably, the portion of the wiring pattern 111 that becomes the land is surrounded by a ring-shaped solder resist (not shown). The ring shape is one of solder resist pattern shapes, and refers to a pattern shape surrounding a mounting material made of solder or the like in a ring shape.

Note that it is desirable to roughen at least one surface of the copper foil constituting the wiring pattern 111 and the like. For example, according to the study by the inventors, the roughened state of the surface of the copper foil constituting the wiring pattern 111 is microetching in which the rugged shape of the uneven structure of the roughened portion is 2 μm or less (corresponding to an Rz value of about 2 μm). By adopting the structure, it is preferable to form a Cu ₆ Sn ₅ intermetallic compound layer having a uniform thickness, for example, about 2.5 μm thickness, at the interface between the second insulating layer 105 and the mounting material 113 such as solder. It has been confirmed that a good solder wettability and a stable adhesive strength, for example, a value of 0.5 KN or more (not a peeling but a mounted component destruction mode) can be obtained.

  Furthermore, the roughening treatment can secure a sufficient value of 1 KN level for the adhesion strength with the resin to be sealed (for example, the second curable resin 106 impregnated in the second insulating layer 105). I have confirmed that.

  In addition, the circuit component 112 is connected only to the wiring pattern 111 formed on the mounting surface, and does not have an electrical contact with the wiring pattern 111 formed on other layers and is built in. The second insulating layer 105 (and also the second curable resin) is interposed between the circuit component 112 and the wiring pattern 111 formed on the first insulating layer 102 formed immediately above the circuit component 112. By providing 106), the adhesion strength between these members is increased, the mechanical strength as a component-embedded substrate is increased, and the effect of suppressing the generation of voids can be obtained.

  The wiring pattern 111 is made of a material having electrical conductivity, for example, a copper (Cu) foil or a conductive resin composition. In the present invention, the Cu foil is formed by patterning into a desired shape. As the insulating material used for the first and second insulating layers 102 and 105, the first and second glass fibers 104 and 107 and the thermosetting epoxy that becomes the first and second curable resins 103 and 106 are used. Glass epoxy prepreg impregnated with resin, BT resin prepreg impregnated with thermosetting bismaleimide / triazine resin on glass woven fabric, aramid prepreg impregnated with thermosetting epoxy resin on aramid nonwoven fabric, etc. However, various materials can be used as long as the woven fabric or the nonwoven fabric is impregnated with a curable resin.

  Further, in the cross-sectional view of FIG. 1, the multilayer substrate portion 115 is formed by alternately laminating the cured first insulating layer 102 and the uncured (or prepreg) second insulating layer 105. Although cured and integrated, the second glass fiber 107 near the opening (that is, the accommodating portion 114 in FIG. 1) formed in the uncured (or prepreg) second insulating layer 105. A part of the opening is cut at an opening part (not shown) to become the accommodating part 114, and the opening is opened so that a part thereof melts (or the pitch is widened or a part of the cut piece). The portion is filled and diffused in the second curable resin (uncured state).

  As described above, the second curable resin 106 in which a part of the second glass fiber 107 constituting the second insulating layer 105 is positively filled and cured in the accommodating portion 114 (or an opening portion described later). The effect which raises toughness is acquired by providing in.

  More specifically, the structure of the present invention is excellent in filling property of the second curable resin 106 into the accommodating portion 114 for storing the circuit component 112, and is preferable for realizing airtight resin filling without voids. It is.

  As described above, the component-embedded substrate 101 shown in FIG. 1 includes the first insulating layer 102 having the first glass fiber 104, the first curable resin 103, and the wiring pattern 111, and the second glass fiber 107. , A second insulating layer 105 having a second curable resin 106 and a via 109, and an inner layer of the outermost first insulating layer 102 of the multilayer substrate 115. A component-embedded substrate 101 having a circuit component 112 mounted on the wiring pattern 111 on the side, and a housing portion 114 that is provided in the multilayer substrate portion 115 and accommodates the circuit component 112, and the multilayer substrate portion 115 is cured. The first insulating layer 102 and the uncured second insulating layer 105 are alternately laminated, cured and integrated, and the circuit component 112 accommodated in the accommodating portion 114 and the multilayer substrate portion 115 In between, the cured product of the second curable resin 106 of the second insulating layer 105 is filled, and the via 109 has a through hole 108 formed in the second insulating layer 105 and the through hole 108. The conductive paste 110 is filled and electrically connected to the wiring pattern 111 of the first insulating layer 102.

  FIGS. 2C and 2D are a schematic view and a cross-sectional SEM photograph of a connection portion using the conductive paste 110 of FIGS. 1A and 1B, respectively. 17 is a Cu particle, 18 is a first metal region mainly composed of an intermetallic compound, 19 is a second metal region, and Bi is the main component. Reference numeral 20 denotes a surface contact portion in which the Cu particles 17 are deformed and brought into surface contact with each other (indicated by a dotted line in the figure).

  As shown in FIG. 1 (B), the conductive paste 110 is made of Cu and Cu as shown in FIG. It includes a metal part including at least Sn and Bi and a resin part, and the metal part includes a region composed of Cu particles, and the periphery of the region so as to straddle the surface contact portion 20 of the Cu particles with an intermetallic compound as a main component. The first metal region is covered and the second metal region is mainly composed of Bi.

  Furthermore, since all of the vias 109 can be further compressed by the copper foil wiring pattern 111 from both sides at the time of hot pressing, a region made of a continuous body of Cu particles can be formed.

  In addition, the surface of the copper foil to be solder-mounted is rough via a fine micro-etching method so that the shape of the ridge shape is 2 μm or less, thereby stabilizing via connection that resists resin flow, copper foil and resin base It is possible to achieve both secure adhesion to the material and stable solder wettability. FIG. 2C shows an enlarged view of the connection interface. In order to ensure solder wettability, the shape of the lump shape is roughened to 2 μm or less by a fine microetching method.

  As shown in FIGS. 2C and 2D, the via 109 has a through-hole 108 formed in the second insulating layer 105, and the surface of the first insulating layer 102 filled in the through-hole 108 has a bump shape. Metal portions including at least Cu, Sn, and Bi electrically connected to the wiring pattern 111 roughened to a size of 2 μm or less (that is, Cu particles 17, first metal regions 18, second metal regions 19, and the like) Including a portion including or a resin portion (that is, a resin portion in the conductive paste 110).

  Further, the metal portion (that is, the portion including or including the Cu particles 17, the first metal region 18, and the second metal region 19) in the via 109 is a region including the Cu particles 17, Cu and Sn. As a main component of the intermetallic compound consisting of the above, the Cu particles are provided with a protrusion 118 shown in FIG. The conductive paste 110 is formed from a first metal region covering the first metal region and a second metal region containing Bi as a main component.

  The metal portion includes Cu particles 17, a first metal region 18 mainly composed of at least one metal selected from the group consisting of tin, a tin-copper alloy, and a tin-copper intermetallic compound, and Bi as a main component. And a second metal region 19. At least a part of the Cu particles 17 forms a lump of bonded body (not provided with a reference numeral or the like) via the surface contact portion 20 formed by pressurizing each other and deforming each other to make surface contact. Yes. This combined body functions as a low-resistance conduction path that electrically connects the wirings.

  The average particle diameter of the Cu particles 17 is preferably 0.1 to 20 μm, more preferably 1 to 10 μm. When the average particle diameter of the Cu particles 17 is too small, the contact resistance tends to increase in the via-hole conductor, so that the conduction resistance tends to increase. Also, particles with such a particle size tend to be expensive. On the other hand, when the average particle diameter of the Cu particles 17 is too large, it tends to be difficult to increase the filling rate when trying to form a via-hole conductor having a small diameter such as 100 to 150 μmφ.

  The purity of the Cu particles 17 is preferably 90% by mass or more, and more preferably 99% by mass or more. The Cu particles 17 become softer as the copper purity is higher. Therefore, since it becomes easy to be crushed in the pressurization process mentioned later, when a plurality of Cu particles 17 contact each other, Cu particles 17 are easily deformed, thereby increasing a contact area between Cu particles 17. Moreover, when purity is high, it is preferable also from the point which the resistance value of the Cu particle | grain 17 becomes lower.

  The average particle diameter of the Cu particles 17 and the surface contact portion 20 where the Cu particles 17 are in surface contact with each other are polished with a cross section of the via 109 after filling the formed multilayer wiring board with a resin (if necessary) It is confirmed and measured by observing a sample prepared using a fine processing means such as FOCUSED ION BEAM using a scanning electron microscope (SEM).

  A large number of Cu particles 17 are brought into contact with each other to form a combined body (not provided with a symbol or the like), thereby forming a low-resistance conductive path.

  In addition, in the via 109, a large number of Cu particles 17 are not arranged in an orderly manner but randomly contacted as shown in FIG. Preferably not formed). The reliability of the electrical connection can be increased by forming such a network by the combined body. Moreover, it is preferable that the position where many Cu particles 17 are in surface contact is also random. By bringing the Cu particles 17 into surface contact with each other at random positions, it is possible to disperse the stress generated inside the via 109 when receiving heat and the external force applied from the outside by deformation thereof.

  The volume ratio of the Cu particles 17 contained in the via 109 is preferably 30 to 90% by volume, and more preferably 40 to 70% by volume. When the volume ratio of the Cu particles 17 is too low, there is a tendency that the reliability of electrical connection as a conduction path of a bonded body formed by a large number of Cu particles 17 being in surface contact with each other decreases. If too large, the resistance value tends to fluctuate in the reliability test.

  As shown in FIG. 2C, at least a part of the first metal region 18 mainly composed of at least one metal selected from the group consisting of tin, a tin-copper alloy, and a tin-copper intermetallic compound is formed. It is formed so as to contact the surface of the Cu particles 17. Moreover, it is preferable that at least a part of the first metal region 18 covers the surface contact portion 20 that is a portion where the Cu particles 17 are in surface contact with each other. By forming the first metal region 18 so as to straddle the surface contact portion 20 in this way, the contact state of the surface contact portion 20 is further reinforced.

The first metal region 18 contains at least one metal selected from the group consisting of tin, a tin-copper alloy, and a tin-copper intermetallic compound as a main component. Specifically, for example, a metal containing Sn alone, Cu ₆ Sn ₅ , Cu ₃ Sn or the like is included as a main component. Moreover, as a remaining component, you may contain other metal elements, such as Bi and Cu, in the range which does not impair the effect of this invention, specifically, 10 mass% or less, for example.

  Further, in the metal portion (that is, the portion including the Cu particles 17, the first metal region 18, and the second metal region 19, or a portion made of these), as shown in FIG. The second metal region 19 is preferably present so as not to contact the Cu particles 17 but to contact the first metal region 18. When the second metal region 19 is present in the via 109 so as not to contact the Cu particles 17, the second metal region 19 does not lower the conductivity of the first metal region 18.

  The second metal region 19 contains Bi as a main component. Further, the second metal region 19 includes, as a remaining component, an alloy of Bi and Sn or an intermetallic compound in a range that does not impair the effects of the present invention, specifically, for example, in a range of 20% by mass or less. But you can.

  In addition, since the 1st metal area | region 18 and the 2nd metal area | region 19 have mutually contact | connected, both usually contain both Bi and Sn. In this case, the first metal region 18 has a higher Sn concentration than the second metal region 19, and the second metal region 19 has a higher Bi concentration than the first metal region 18. Moreover, it is preferable that the interface between the first metal region 18 and the second metal region 19 is unclear rather than clear. When the interface is unclear, it is possible to suppress stress concentration on the interface even under heating conditions such as a thermal shock test.

  On the other hand, the resin portion (not denoted by reference numerals) constituting the via 109 is made of a cured product of a curable resin. The curable resin is not particularly limited, and specifically, for example, a cured product of an epoxy resin is particularly preferable from the viewpoint of excellent heat resistance and a low coefficient of linear expansion.

  The volume ratio of the resin portion in the via 109 is preferably 0.1 to 50% by volume, and more preferably 0.5 to 40% by volume. When the volume ratio of the resin portion is too high, the resistance value tends to be high, and when it is too low, the preparation of the conductive paste tends to be difficult during production.

  Next, an example of a method for forming a via-hole conductor will be described.

  For example, FIG. 3 ((C) to (D), FIG. 5 (F) to FIG. 6 (A), FIG. 9 (A) to (B), or FIG. 10 (c) to (d) described later. As shown in the drawing, the conductive paste 110 provided with the protrusions 118 is pressurized and compressed, and heated while maintaining the pressurized and compressed state to form the vias 109. The pressure compression increases the density. The Cu particles 17 are in contact with each other, and initially in pressure compression, the Cu particles 17 are in point contact with each other, and then are crushed as the pressure increases, and are deformed and brought into surface contact with each other to form a surface contact portion 20. In this way, when a large number of Cu particles 17 are in surface contact with each other, a combined body for electrically connecting the upper layer wiring and the lower layer wiring in a low resistance state is formed.

  Furthermore, it heats, maintaining this pressurization compression state. By doing so, the entire surface of the Cu particles 17 is not covered with Sn—Bi solder particles, and the first and second metal regions are straddled across the surface contact portions 20 in which the Cu particles 17 are in direct surface contact with each other. 18, 19 are formed.

  That is, a large number of Cu particles 17 are pressed and compressed so as to come into contact with each other via the surface contact portions 20 that are in surface contact with each other, and in this state, Sn—Bi solder particles in the conductive paste are melted. Thus, the surface of the Cu particles 17 can be wetted with molten Sn—Bi solder. As a result, the first metal region 18 can be formed so as to straddle the surface contact portion 20 in which the Cu particles 17 are deformed and brought into surface contact with each other.

  As described above, after forming the surface contact portion 20 in which the Cu particles 17 are deformed and brought into surface contact with each other, the Sn—Bi solder particles in the conductive paste 110 are heated to the melting point or higher to be melted. As a result, the first metal region 18 and the second metal region 19 in contact with the first metal region 18 are formed.

  Examples of solder particles added to the conductive paste 110 include Sn—Pb solder, Sn—In solder, and Sn—Bi solder as solder materials that melt at a relatively low temperature. Of these materials, In is expensive and Pb is considered to have a high environmental load.

  On the other hand, the melting point of the Sn—Bi solder is 140 ° C. or lower, which is lower than a general solder reflow temperature when electronic components are surface-mounted. Therefore, when only Sn-Bi solder is used as the via hole conductor of the circuit board as a single unit, the via resistance may change due to remelting of the solder of the via hole conductor during solder reflow. On the other hand, when the via paste of this embodiment is used, Sn of the Sn—Bi solder particles reacts with the surface of the Cu particles to reduce the Sn concentration from the Sn—Bi solder particles. Through the cooling process, Bi precipitates and a Bi phase is generated. Then, by precipitating and presenting the Bi phase in this way, the solder of the via-hole conductor is not easily remelted even when subjected to solder reflow. As a result, the resistance value hardly changes even after the solder reflow.

(Embodiment 2)
Next, an example of a method for manufacturing the component-embedded substrate 101 described in the first embodiment will be described with reference to FIGS.

  The component-embedded substrate 101 includes a mounting wiring board provided on at least one outermost layer (the component mounting surface may be on the inner layer side, the outer layer or the surface layer side), and an inner layer wiring (or re-use). It can be manufactured by using a relay wiring board that constitutes (wiring) and an inter-substrate connecting layer that connects these layers (via vias).

  FIGS. 3A to 3F are cross-sectional views for explaining how the via 109 made of the conductive paste 110 and the wiring pattern 111 are formed on both surfaces of the first insulating layer 102.

  In FIG. 3, a method of manufacturing a relay wiring board constituting the component built-in board 101 will be described. In FIG. 3, 121 is a relay wiring board.

  In FIG. 3A, the first insulating layer 102 is obtained by impregnating a first glass fiber 104 (not shown) with an uncured first curable resin 103 (not shown). Corresponds to the prepreg 116 (that is, the uncured state).

  As shown in FIG. 3B, protective films 117 are provided on both surfaces of the uncured first insulating layer 102, and the through holes 108 are formed. Thereafter, the conductive paste 110 is filled into the through hole 108. Thereafter, the protective film 117 is peeled off, and a protruding portion 118 made of the conductive paste 110 is formed as shown in FIG.

  FIG. 3D is a cross-sectional view illustrating a state in which the copper foil 119 is attached to both surfaces of the sample illustrated in FIG. 3C and the second curable resin 106 is cured. In FIG. 3D, the copper foils 119 fixed on both surfaces of the first insulating layer 102 are electrically connected to each other by the conductive paste 110 filled in the through holes 108.

  FIG. 3E is a cross section showing a state in which the copper foil 119 fixed on both surfaces of the sample shown in FIG. 3D is formed into a wiring pattern 111 through exposure, development, and etching steps (details are omitted). FIG.

  FIG. 3F is a cross-sectional view illustrating a state in which the first opening 120 is provided in a predetermined portion of the sample in FIG. The thus produced relay wiring board 121 is laminated and integrated with another sheet member in FIG.

  The first opening 120 and other openings (not shown) are stacked in the thickness direction to form a receiving part 114 (not shown) for receiving the circuit component 112. become.

  As shown in FIG. 3, the wiring pattern 111 formed in the first insulating layer 102 is formed as shown in FIG. 3E in order to fill the built-in circuit component 112 shown in FIG. 1 without damage. After that, voids are formed (FIG. 3F). It is desirable that the first opening 120 serving as a gap can be formed with a drill in consideration of productivity. However, when the built-in components are concentrated, that is, when a group of circuit components 112 are mounted narrowly adjacent to each other, it is preferable to cut them out together, in which case they are cut out in a lump with a mold like a Thomson blade. It doesn't matter.

  3A to 3F, the first glass fiber 104 provided in the first insulating layer 102, the second curable resin 106, and the like are not illustrated.

  Next, the first insulating layer 102 which is one or more outermost layers of the component-embedded substrate 101 (and will be mounted with the circuit component 112) will be described with reference to FIG.

  4A to 4G are cross-sectional views illustrating an example of a method for manufacturing the first insulating layer 102 on which the circuit component 112 is mounted, and 122 is a mounting substrate.

  4A to 4D are steps similar to those in FIGS. 3A to 3D, and the details are omitted.

  4E to 4G are cross-sectional views illustrating a state in which the circuit component 112 is mounted on one surface of the first insulating layer 102 via a mounting material 113 such as solder.

  In this way, a mounting substrate 122 as shown in FIG. 4G is formed. The circuit component 112 mounted on the surface of the mounting substrate 122 is the inner layer side, and is housed in the housing portion 114 described above, whereby the component-embedded substrate 101 is obtained.

  5A to 5F are cross-sectional views illustrating an example of a method for manufacturing the second insulating layer 105.

  In FIG. 5, reference numeral 126 denotes an inter-substrate connection layer.

  FIG. 5A is a cross-sectional view of the second insulating layer 105 in an uncured state (or a prepreg state), and the second curable resin 106 and the second glass fiber 107 are not illustrated.

  As shown in FIG. 5B, a second opening 123 is formed in the second insulating layer 105 in an uncured state (or a prepreg state). Note that the second opening 123 is formed by laser, punching, drilling, or the like, similar to the formation of the first opening 120 described above.

  FIG. 5C is a cross-sectional view illustrating a state in which protective films 117 are provided on both surfaces of the second insulating layer 105 where the second opening 123 is formed.

  FIG. 5D is a cross-sectional view illustrating a state in which the through hole 108 is provided in the uncured second insulating layer 105 in a state where the protective film 117 is provided.

  FIG. 5E is a cross-sectional view showing a state where the conductive paste 110 is filled into the through hole 108 formed in the protective film 117 through the squeegee 124.

  FIG. 5F is a cross-sectional view illustrating a state where the protective film 117 is peeled from the sample in FIG. 5E, and is an example of the inter-substrate connection layer 126.

  Next, a state in which the cured first insulating layer 102, the uncured second insulating layer 105, and the like prepared in FIGS. 3 to 5 are stacked will be described with reference to FIG.

  FIGS. 6A and 6B are cross-sectional views illustrating a state in which a cured first insulating layer 102, an uncured second insulating layer 105, and the like are stacked, integrated, and cured. The arrow 125 in FIG. 6 shows the direction which pressurizes, heats, crimps | bonds, and integrates these sheet-like members. In addition, when pressurizing, heating, and integrating, a heating and pressurizing apparatus using a commercially available vacuum can be used.

  In FIG. 6A, a circuit component 112 is provided on a wiring pattern 111 on the inner layer side of the cured first insulating layer 102 which is one or more outermost layers via a mounting material 113 such as solder. Has been implemented. The cured first insulating layer 102 provided with the first opening 120 and the uncured second insulating layer 105 provided with the second opening 123 are aligned with each other. Thus, they are alternately stacked, integrated and cured to form the multilayer substrate portion 115.

  In addition, the first opening 120 and the second opening 123 are stacked in the thickness direction to form the accommodating portion 114.

  In addition, when the layers are stacked and pressed, the second curing in the uncured state is performed by the uncured second insulating layer 105 inserted between the plurality of cured first insulating layers 102. The conductive resin 106 oozes out, fills the gap between the circuit component 112 accommodated in the accommodating portion 114 and the multilayer substrate portion 115 while suppressing the generation of voids and the like, and finally cures.

  FIG. 6B shows an example of a cross section of the component-embedded substrate 101 obtained in this way.

  As shown in FIG. 6A, an accommodation portion 114 including a first opening 120 and a second opening 123 is formed in advance at a predetermined position, and the inter-substrate connection layer 126 filled with the conductive paste 110 is formed. Etc., and by laminating a plurality of sheet-like substrates, etc., in which these openings are formed in advance at a predetermined position, an interlayer connection via structure using the conductive paste 110 can be realized. If it is compressed in the direction, a stronger via connection can be realized.

  Further, a land for connecting the conductive via 109 shown in the cross-sectional view of the batch lamination shown in FIG. 6A (the land corresponds to a portion of the wiring pattern 111 that is electrically connected to the conductive paste 110). However, by adopting an electrode structure that protrudes from the periphery instead of a solid surface, it is possible to positively generate a compressive stress on the conductive paste 110 at the time of hot pressing, and realize a stable via connection. This effect is remarkably obtained when the conductive paste 110 mainly composed of copper powder whose connection is ensured mainly by compression is used for the via 109.

  Next, referring to FIG. 7, when the cured first insulating layer 102 and the uncured second insulating layer 105 are stacked, pressurized, and integrated, the uncured second insulating layer 105, the uncured second curable resin 106 oozes out, and the end surface (that is, the first opening 120) of the first insulating layer 102 stacked on the top and bottom, or the circuit accommodated in the accommodating portion 114. The manner of wetting and filling the gap with the part 112 will be described.

  FIGS. 7A and 7B are cross-sectional views illustrating how the uncured second curable resin 106 oozes out. Arrows 125 in FIGS. 7A and 7B indicate directions in which the cured first insulating layer 102 and the uncured second insulating layer 105 are stacked and pressed.

  In FIG. 7A, the wiring pattern 111 protrudes from one or more surfaces of the cured first insulating layer 102, and the conductive paste 110 protrudes from both surfaces of the second insulating layer 105. , Each formed. By doing so, the effect of increasing the adhesion between the conductive paste 110 and the wiring pattern 111 and reducing the electrical resistance of the via 109 (not shown) can be obtained.

  FIG. 7B shows that the second insulating layer 105 includes the conductive paste 110 protruding from the uncured second insulating layer 105 and the wiring pattern 111 protruding from the cured first insulating layer 102. A state in which the uncured second curable resin 106 oozes out is shown. As shown in FIG. 7B, the uncured second curable resin 106 that oozes out from the second opening 123 formed in the uncured second insulating layer 105 is the first insulating material. The gap between the first opening 120 of the layer 102 and the circuit component 112 is filled and cured, and these are integrated.

  This will be described in more detail. As shown in FIG. 7A, a conductive paste 110 filled in a through hole 108 of a prepreg 116 (not assigned a number) to be the second insulating layer 105 is provided on the first insulating layer 102. The wiring pattern 111 is pressed and pressure-bonded.

  Further, by this pressurization and pressure bonding, the second curable resin 106 constituting the prepreg 116 (the numeral 116 is not shown because it is shown as the second insulating layer 105) is transferred from the prepreg 116 to the circuit. It flows out to the component 112 side and fills the gap between the circuit component 112.

  When the second curable resin 106 contained in the prepreg 116 flows to the circuit component 112 side, the three-dimensional shape of the conductive paste 110 filled in the through hole 108 of the prepreg 116 is not affected. However, this is because the periphery of the conductive paste 110 is surrounded by the second glass fibers 107 constituting the prepreg 116.

  7A and 7B, the via 109 made of the conductive paste 110 is deformed to the circuit component 112 side even when the pressing pressure at the time of stacking is increased. It does not flow or move.

  7A and 7B, the via resistance of the via 109 formed from the conductive paste 110 can be lowered by increasing the pressure.

  6 (A) and 6 (B), since the pressurized pressure is not directly applied to the built-in circuit component 112, it does not affect the reliability of the circuit component itself or its mounting portion. .

  Note that the conductive paste 110 can be subjected to pressure lamination as shown in FIGS. 7A and 7B in a state where the conductive paste 110 has been hardened in advance, but the conductive paste 110 has been hardened. Then, during this pressure compression, it is difficult for pressure to be generated in the prepreg 116 portion, and the uncured second curable resin 106 or the like that fills the gap with the circuit component 112 is not sufficiently oozed out. This is because the pressure applied to the prepreg 116 is reduced by the amount that the conductive paste 110 supports the pressure during pressurization. Further, in the case of the cured conductive paste 110, the via resistance is not easily lowered even by pressure compression.

  On the other hand, when the uncured conductive paste 110 is used, a sufficient compression pressure is applied to the prepreg 116 because the conductive paste 110 is compressed (or densified) in the thickness direction during pressure compression. That would be the case. Further, in the case of the uncured conductive paste 110, the via resistance is likely to decrease due to pressure compression.

  Further, as shown in FIGS. 7A and 7B, a cross section of the second glass fiber 107 on the circuit component 112 side from the second opening 123 is changed to the first glass fiber of the first opening 120. The second curable resin 106 that exudes from the second insulating layer 105 can be efficiently discharged from the cross section of the circuit 104, or as a kind of priming water or a guide on the surface of the circuit component 112. The circuit component 112 can be completely filled with the second curable resin 106 so that voids can be eliminated.

  Furthermore, an effect of increasing the toughness can be obtained by charging or mixing a part of the second glass fiber 107 constituting the second insulating layer 105 into the housing portion 114 so as to melt. .

  As shown in FIG. 1 and FIG. 6, the wiring pattern 111 formed on the outermost layer of the component-embedded substrate 101 is subjected to etching after undergoing a batch lamination process such as hot pressing using a solid copper foil 119. Then, patterning may be performed (not shown). By using a solid copper foil 119, pattern deviation can be suppressed as compared with a structure in which substrates on which wiring patterns 111 are formed on both sides are collectively laminated. This is because the deviation of the wiring patterns 111 on the front and back sides can be suppressed to the necessary minimum, for example, within ± 20 μm by simultaneously performing alignment patterning using the same marker. In the case of multilayering, electrical connection is made using the conductive paste 110 in any interlayer connection.

  The via 109 is considered based on a connection method in which the conductive paste 110 is filled. However, the via 109 may be of any conformal via connection type in which plating connection is performed after drilling with a laser only for the outermost interlayer connection.

  Further, the mounting material 113 for connecting the built-in circuit component 112 may be connected by a plating connection method using the via hole drilled by the laser. By adopting the plating connection, it is possible to drastically avoid re-melting of the mounting material 113 at the time of solder reflow which is basically secondary mounting, and a further highly stable connection can be obtained. When the built-in circuit component 112 is a chip LCR component, the external electrode is preferably a Cu electrode.

  When appealing for a multi-layer structure and a small and thin structure, the housing portion 114 around the built-in circuit component 112 is made as small as possible, and the via 109 serving as an interlayer connection with the built-in circuit component 114 It is necessary to reduce the distance to the minimum necessary.

  In that case, as shown in the present invention, a wiring pattern made of copper foil 119 is formed in the first opening 120 formed by partially removing the cured first insulating layer 102 together with the first glass fiber 104. It is desirable that the wiring 111 is a receding wire rather than the first opening 120. Practically, it is desirable to recede 50 microns or more. This is because a short circuit can be avoided by using a receding wiring in consideration of processing variations in forming the opening. Here, the receding wiring means that a wiring pattern is provided outside (or in a direction away from) the opening facing the circuit component 112.

  6A and the like, even when the external electrode (not shown) of the circuit component 112 and the first opening 120 are in contact with each other due to the positional variation during the stacking process. A short circuit with the wiring pattern 111 made of the copper foil 119 formed on the surface of the first insulating layer 102 can be avoided.

  The built-in circuit component 112 is a chip-type electronic component having a desired characteristic such as a passive component chip capacitor or a chip resistor formed in advance and having a connection electrode on its outer surface. Relatively few wafer level packages are also included. The mounting material 113 is a material in which at least two kinds of metal elements are blended and can be electrically and mechanically connected together with an alloy connection between the metals, for example, tin (Sn) -silver (Ag), Tin (Sn) -silver (Ag) -copper (Cu), tin (Sn) -zinc (Zn), gold (Au) -zinc (Zn), tin (Sn) -antimony (Sb), etc. The material is usable. Furthermore, any material can be used as long as it is a mounting material capable of mounting the circuit component 112 without being limited to these materials. In addition, when the component-embedded substrate 101 of the present invention is secondarily mounted on the motherboard wiring substrate with solder, the melting point of the alloy in the mounting material 113 shifts to the high temperature side after joining, This prevents re-melting of the mounting material 113 during secondary mounting.

  However, any of the mounting materials 113 requires a material that can secure a certain degree of wetting and spreading with respect to the wiring pattern 111 and can obtain adhesion strength.

  Thus, the case where the mounting material 113 is devised will be described in more detail with reference to FIG.

  For example, as shown in FIGS. 4A to 4E, a multilayer board on which circuit components 112 built in the board are mounted is prepared. Here, an uncured first insulating layer 102 (for example, using a commercially available prepreg) filled with the conductive paste 110 is laminated with a copper foil 119 as shown in FIG. To form a multilayer board shown in FIG.

  In order to mount a built-in component, for example, a circuit component 112 such as a passive component on the wiring pattern 111, the mounting material 113 is printed and formed as shown in FIG. In this manner, the circuit component 112 incorporated is mounted and connected by mounting and reflow heating.

  In addition, since it cannot connect unless the mounting material 113 stops on the wiring pattern 111 which becomes a land electrode (not shown) including the reflow heat history at the time of secondary mounting, it is more preferably a ring-shaped resist shape. It is preferable to be surrounded. It is important that the mounting material 113 is a material that does not contain lead (Pb), which is an environmental pollutant.

  Furthermore, it is important that the structure maintain the shape of the mounting material typified by solder in the reflow performed at the time of secondary mounting.

  When the built-in component is an active component such as a wafer level CSP, it is preferable that a low-profile solder ball (BGA) is formed in advance on the wafer level CSP if the component height is allowed. .

(Embodiment 3)
Next, as a third embodiment, a component-embedded substrate 101 of the present invention will be further described using a sample produced by the inventors.

  8A and 8B are a cross-sectional view and a cross-sectional SEM photograph of the component-embedded substrate of the present invention, respectively.

  8A and 8B, the relay wiring substrate 121 made of the first insulating layer 102 and the inter-substrate connection layer 126 made of the second insulating layer 105 are alternately laminated, and the first layer is further formed on the outermost layer. 6 is a cross-sectional view of an all-layer 6-layer board in which a mounting substrate 122 made of the insulating layer 102 is provided and laminated, and a sample cross-sectional photograph of a prototype actually produced.

  8A, a part of the second glass fiber 107 near the second opening (not shown) provided in the prepreg 116 (not shown) made of the second insulating layer 105 is shown. The second opening is filled with the opening so that a part thereof is melted (or the pitch is widened or a part of the cut piece is cut) at the second opening, and the uncured second hardening is performed. The diffusing resin 106 diffuses into the housing portion 114 together with the curing of the second curable resin 106.

  By adopting this structure, the filling property of the second curable resin 106 from the second insulating layer 105 into the housing portion 114 is improved, which is preferable for realizing airtight resin filling without voids. .

  Further, as shown in the cross-sectional photograph by SEM in FIG. 8B, the second component built-in board 101 (not assigned a number) that the inventors have actually made a prototype has a second part in the accommodating portion 114 of the circuit component 112. Generation | occurrence | production of the void etc. which show unfilling of the curable resin 106 was not observed.

  The first glass fiber 104 is a first opening 120 (not shown) of the first insulating layer 102 and substantially the same portion as the first curable resin 103 (for example, in the case of drilling or cutting). Thus, the effect of increasing the adhesion with the second insulating layer 105 can be obtained by cutting into a rough surface.

  Further, when the first opening 120 is formed by a laser or the like, the first glass fiber 104 is in a state in which the tip portion is a substantially spherical mass from the cut portion of the first curable resin 103. Thus, a part of the resin can be protruded, and the adhesion with the second curable resin 106 can be increased.

  These samples were not swollen or peeled off even in a reflow test at 260 ° C. after absorbing moisture at 85 ° C., 60% RH, and 176 hr, as defined by JEDEC, and no problems occurred at each interface part. It was found that the built-in substrate 101 with high reliability was obtained.

(Embodiment 4)
Next, as a fourth embodiment, a case where the total thickness of the component-embedded substrate 101 is reduced will be described.

  FIGS. 9A and 9B are cross-sectional views illustrating how the total thickness of the built-in substrate 101 is reduced. 9A and 9B, the first and second glass fibers 104 and 107 provided in the first and second insulating layers 102 and 105 are not shown.

  FIG. 9 (A) showing the batch lamination process is basically combined with the same components as in FIG. 6 (A) described above, but the two outermost layers formed at positions facing the built-in components. In the wiring pattern 111 of the mounting substrate 122 made of a substrate, the wiring pattern 111 of the inner layer side wiring pattern 111 that overlaps the circuit component 112 is selectively deleted.

  As described above, it is desirable not to form the wiring pattern 111 in a region (or an area portion) overlapping with the built-in circuit component 112 of the wiring pattern 111. When the built-in circuit component 112 is a chip LCR component, the mounting terminal 127 (sometimes referred to as an external electrode, a terminal electrode, or an end surface electrode) is not only on the mounting side but also on the opposite side (for example, on the top and bottom and side surfaces). 3 planes, or a total of 5 planes on the top, bottom, left and right sides). If a sufficient insulation distance cannot be obtained in the thickness direction, there is a concern of causing a short circuit. Such a problem can be solved by adopting the structure (B).

  FIGS. 9A and 9B are cross-sectional views showing a structure for realizing further thinning of the component-embedded substrate 101.

  By adopting the structure of the component built-in substrate 101 of the present invention, the distance between the circuit component 112 and the wiring pattern 111 is designed to be 50 μm or less and in some cases 25 μm or less in order to reduce the total thickness of the built-in substrate 101 as much as possible. Is possible.

  Further, the height of the circuit component 112 always varies, and if a space of about 25 μm is secured, the wiring pattern 111 may be shorted between the electrodes due to the height variation if the wiring pattern 111 is located immediately above the built-in circuit component 112. There is sex. Therefore, conventionally, it is necessary to secure an unnecessarily large space in order to avoid a short circuit between electrodes, and the total thickness of the conventional component-embedded substrate is large.

  9A and 9B, the wiring pattern 111 is not formed in the region where the built-in circuit component 112 is disposed, thereby reducing the thickness space to 30 μm or less. Even if it is reduced to the minimum, it is possible to absorb the variation in the height and thickness of the circuit component 112, and no unnecessary pressure is applied to the built-in circuit component 112, and the circuit component 112 is not cracked. Moreover, the short circuit between electrodes can be avoided.

  In the fourth embodiment, an example of an eight-layer substrate is shown. However, it is not fixed to the eight-layer substrate, and an even-numbered multi-layered 10, 12 or six-layer structure is provided if necessary. Is possible. However, even at that time, the wiring layers are formed simultaneously on both sides by using the two-layer wiring board containing the circuit component 112 as a central material.

  The insulating material used for the first insulating layer 102 and the second insulating layer 105 used for the component-embedded substrate 101 is a glass epoxy prepreg in which a glass woven fabric is impregnated with a thermosetting epoxy resin, and a glass woven fabric having a thermosetting property. BT resin prepreg impregnated with bismaleimide / triazine resin, aramid prepreg impregnated with thermosetting epoxy resin on aramid nonwoven fabric, etc. can be used, but woven fabric or nonwoven fabric is impregnated with curable resin. Various materials can be used as long as they have different structures. In addition to the prepreg material obtained by impregnating a curable resin into a woven or non-woven fabric, it is also possible to use a mixture of an inorganic filler such as silicon dioxide or alumina and a curable resin.

  The composition of the thermosetting resin 106 occupying the second insulating layer 105 from the via 109 to the circuit component 112 in the via 109 of the inter-substrate connection layer 126 filled with the conductive paste 110 that constitutes a layer to be embedded in the component. The ratio can be made smaller than the composition ratio of the thermosetting resin 106 in other peripheral portions.

  Further, as described above, since only the uncured second curable resin 106 that is compressed and oozed out from the uncured second insulating layer 105 is covered with the peripheral portion of the circuit component 112 by the hot press, The resin component that fills the portion 114 has a three-dimensional isotropic physical property such as a thermal expansion coefficient, and reduces the stress mode that causes cracks and the like during the heat cycle for the built-in circuit component 112 Is obtained. On the other hand, if the circuit component 112 is built directly in a conventional prepreg with a glass cloth or the like, the thermal expansion coefficient in the XY direction and the thermal expansion coefficient in the Z-axis direction are significantly different. There is a concern that cracks and the like are likely to occur inside.

  Thus, by incorporating the circuit component 112 with the uncured second curable resin 106 that is provided with the second opening 123 and oozes out from the uncured second insulating layer 105, the circuit board is incorporated. The via 109 can be formed not only in the layer but also in the relay wiring board 121 as an intermediate board body to the very vicinity of the circuit component 112 (for example, 400 from the end of the circuit component 112 in which the center position of the via 109 is incorporated). It can be formed within a micron (300 micron or less depending on the application), and it is possible to reduce the size and increase the density.

  As described above, with the configuration of the component-embedded substrate 101 of the present invention, the inner shape of the accommodating portion 114 and the outer shape of the built-in circuit component 112 can be made closer, the clearance is 400 μm, and further Can be reduced to less than 300 μm, so that the module or package can be further downsized.

  In order to prevent warping of the substrate after lamination, it is very important to consider the linear expansion coefficient of each material, and the second glass fiber 107 can be used for adjusting such thermal expansion. .

  A solder resist may be formed on the surface of the mounting substrate 122 as necessary.

  Next, roughening of the surface of the copper foil 119 will be described.

  As a roughening method, it is preferable to roughen the surface of copper or a copper alloy by a microetching method in which process management is relatively easy in order to achieve both roughening and solder wettability. In the case of a roughened foil called a mat surface by roughening by a normal etching method, solder wettability is inappropriate even if Rz is reduced to the 1 μm level, and the necessity for microetching becomes clear. This is because the normal roughened shape of the electrolytically roughened copper foil 119 has an anchor effect because it has a convex shape with a bump, but this shape is inappropriate from the viewpoint of wettability. It became clear in the process of the present invention. On the other hand, when a roughened shape that is hollowed out by microetching is formed from a smooth copper foil 119 shape, an anchor effect with a resin component is obtained, but solder wettability is rather improved.

  In addition, when using a solder material as the conductive paste 110, when the solder material contains a compound composed of Sn and a metal having a melting point higher than Sn, that is, a high-temperature solder having a high melting point during reflow. When used, there is a tendency that the leveling effect at the time of melting the solder at the time of primary mounting tends to be insufficient, and there is a problem that the height variation of the built-in chip parts becomes large. However, it is preferable in a wide range of solder materials that the leveling property can be improved and the variation in the height of the built-in chip parts can be suppressed by mounting using a finely roughened roughened copper electrode with microetching excellent in solder wettability. As a result, it is possible to provide a device having a strong connection reliability with almost no solder deformation in an application assumed by a stricter secondary solder reflow process (high temperature reflow).

(Embodiment 5)
Hereinafter, as the fifth embodiment of the present invention, the effects of the present invention will be described using [Table 1] with reference to the above-described embodiments and comparative examples. Unless otherwise described, the same structures as those in the first embodiment and the like are given the same reference numerals and description thereof is omitted.

  [Table 1] shows the base material content of the component built-in substrate 101 composed of 6 layers, the via connectivity in various laminated structures including the content of the conductive paste 110, the solder reflow reliability at the time of moisture absorption, and the reliability test The board appearance (existence of swelling), mechanical strength reliability design issues, and process issues are summarized.

  12A and 12B are cross-sectional views showing the structures of Comparative Examples 1 and 2, respectively. Reference numeral 128 denotes a composite sheet.

  FIGS. 13A to 13C are cross-sectional views showing the structures of the first to third embodiments. In FIG. 13, 129 is a cured conductive paste containing a CuSn intermetallic compound.

  A comparative example 1 shown in FIG. 12A has a structure shown in Patent Document 1, and a circuit component 112 is built in with a connection using a composite sheet 128 by a via 109 using a conductive paste 110. Yes. The structure of Comparative Example 1 has a feature that when the built-in circuit component 112 is small, such as 0603 size, it can be built without leaving a gap, but the via is close to the circuit component 112 as shown in FIG. In particular, the via connection shape is likely to be deformed and may be distorted.

  In the structure of the comparative example 1 shown in FIG. 12A, rewiring or the like cannot be performed for the layer thickness in which the circuit component 112 is built, so that the wiring capacity is inferior when the same thickness is considered. Alternatively, the substrate thickness may increase. Alternatively, the substrate on which the circuit component 112 is mounted needs to be multilayered. Furthermore, when the composite sheet 128 was used, it was difficult to increase the size of the work to be handled, so a built-in prototype was performed with a work size of 150 mm □.

  In Comparative Example 2 shown in FIG. 12B, considering that the substrate process is performed with a large work size, the conductive paste is formed in the via 109 (not shown because it corresponds to the conductive paste 110 in the drawing). A case where the circuit component 112 is built by laminating a prepreg filled with 110 in an all-layer stack structure is shown. It was confirmed that the conductive via 109 connecting the layers is greatly distorted due to the resin flow into the gap formed for the incorporation of the circuit component 112. Further, in Comparative Example 2, it is necessary to secure a large via diameter of 200 .mu.m.phi. In order to connect via pastes with landless (meaning those without lands), and in this comparative example sample, the initial via Although the connection was confirmed, it was confirmed that the connection resistance greatly fluctuated in a reflow test or the like.

  Example 1 shown in FIG. 13A (an example of introduction of alternate layers) is an example of the structure of the present invention, and the cross section of the second glass fiber 107 of the second opening 123 and the first opening 120. The case where the cross section of the first glass fiber 104 is made substantially coincident and the surfaces are made substantially the same surface will be described. As a result, no problem occurred in the basic drop test (1.5 m drop test 1500G) of the sample of Example 1. On the other hand, in the more severe drop test (3000G, 3m drop test, etc.), it is considered that the mechanical strength of the circuit component housing part and the resin filling part cannot be maintained, but when such higher reliability is required. Can be configured as shown in the second and third embodiments.

  That is, when strict mechanical reliability is required, the configuration of the first embodiment is obtained by adopting the configuration of the second embodiment (a part of the glass fiber is inserted into the housing portion as an example of the shape of the housing portion). In addition to this, it is possible to further improve the toughness of the accommodating portion 114 by the glass fiber.

  Also from the viewpoint of resin filling property, in the case of Example 1, in principle, it is possible to fill without bubbles if it is a form in which 0603 size chip parts, 1005 size chip parts are incorporated individually, or 2 to 3 pieces are incorporated. . On the other hand, when a plurality of chip parts built in the wafer level CSP and the periphery thereof are mounted in close proximity and a large accommodating portion must be filled with resin, the majority can be filled with resin without bubbles, but a very small number An example of bubbles was confirmed. In the case of such a special built-in circuit component layout, the configuration shown in the second embodiment contributes effectively from the viewpoint of resin filling. Resin filling is 100%.

  Further, when more severe moisture absorption reflow reliability is required, in addition to the configuration of Example 1, Example 3 (Ag-coated Cu powder-based conductive paste containing CuSn intermetallic compound is introduced into vias) can be used. Connection reliability with a low rate of change in via resistance can be ensured.

  In this way, by changing the configuration as in the second and third embodiments according to the reliability level, it is possible to provide a component-embedded substrate that supports a more severe reliability level.

  In Example 2 (an example of the housing shape modification) shown in FIG. 13B, the second glass fiber 107 in the second opening 123 (not shown) has a cross section for comparison with Example 1. The prototype was manufactured so as to be positioned closer to the circuit component 112 than the cross section of the first glass fiber 104 of the first opening 120.

  In the moisture absorption reflow reliability (JEDEC Level. 2) related to the built-in circuit component 112 as in Example 1 shown in FIG. 13 (A), there is no swelling of the substrate and generation of voids, and there is no crack in the circuit component in the drop test. It has been confirmed that it satisfies the standards such as not occurring.

  However, with regard to the via 109 in the vicinity of the partially built-in circuit component 112, the via connection resistance is increased by about 20% during moisture absorption reflow.

  In Example 3 shown in FIG. 13C, an Ag-coated Cu paste containing a CuSn intermetallic compound was used for the conductive paste 110 constituting the via 109. From Example 2 shown in FIG. 13 (B), by using the Ag-coated Cu conductive paste cured product 129 containing a CuSn intermetallic compound, the change in conductive via resistance during moisture absorption reflow is suppressed to within 10%. I understand that.

  As described above, it is useful to use a conductive paste containing a CuSn intermetallic compound as the conductive paste 110 that fills the through holes 108 and plays a role of connecting the substrates. That is, the reliability can be further improved by using a conductive filler made of metal particles mainly composed of Sn—Bi alloy. This is because the conductive paste 110 for via connection filled in the through hole 108 of the second insulating layer 105 in the uncured state (or prepreg state) is resistant to the resin flow generated as the circuit component 112 is built. This is because it is necessary to be via-connected to the copper foil 119 and the like, and strong interface adhesion is required. By using the conductive paste 110 made of metal particles mainly composed of Sn—Bi alloy, the copper foil is used. This is because a stable connection can be obtained by generating metal diffusion with 119 and forming an alloy reaction layer.

  As described above, by using the present invention, the wiring layer region containing the circuit component 112 is laminated with the cured insulating layer formed with the wiring layer and the prepreg filled with the uncured conductive paste 110. By using the structure, it is possible to avoid via distortion when incorporating a component, rewiring capability as a relay substrate, and multilayering within a limited thickness range.

  With such a structure of the present invention, in a conventional component-embedded substrate, by using a cured insulating layer in which a wiring layer is formed, a housing portion that houses circuit components, that is, a circuit component housed in a hole, and a circuit component The supply source for filling the resin with respect to the gap between the first insulating layer 102 and the first insulating layer 102 and the second insulating layer 105 is limited, and a problem that voids may occur can be solved.

  In the present invention, the housing part 114 of the circuit component 112 includes a first opening 120 formed by removing a part of the hardened first insulating layer 102 together with the first glass fiber 104, and an uncured part. And a second opening 123 formed by removing a part of the second insulating layer 105 together with the second glass fiber 107, and the second opening 123 exposed in the first opening 120. This is because the cut surface of one glass fiber 104 is covered with the second curable resin 106.

  Note that the width or area of the second opening 123 is smaller than the width or area of the first opening 120, or the cross section of the second glass fiber 107 of the second opening 123 is the same as that of the first opening 120. By positioning the first glass fiber 104 on the circuit component 112 side from the cross section of the first glass fiber 104, the second curable resin 106 oozed out of the second insulating layer 105 can be efficiently circulated. Then, the area around the built-in circuit component 112 is completely filled with resin, and the effect of eliminating the generation of voids is exhibited. Furthermore, an effect of increasing toughness can be obtained by providing a part of the second glass fiber 107 in the second cured resin 106 covering the circuit component 112. As a result, in the present invention, the generation of voids can be effectively suppressed in the above.

  Furthermore, the via connection reliability of the component built-in layer can be further improved by mounting circuit components with lead-free solder partially containing CuSn intermetallic compound as required.

  Although the market demands a multilayered structure and a small and thin structure for the component-embedded substrate, the component-embedded substrate 101 according to the present invention responds to such market needs with the cured first In the first opening 120 formed by removing a part of the insulating layer 102 together with the first glass fiber 104, the wiring pattern 111 is a wiring that recedes by 50 μm or more from the opening, thereby incorporating the wiring pattern 111. A short circuit between the electrode portion of the circuit component 112 and the wiring pattern 111 formed in the first insulating layer 102 can be avoided due to position variations during the process.

  In addition, as a market need, a multilayered structure and a thinned structure are required. In response to such a market need, the component-embedded substrate 101 of the present invention includes 102 parts of the first insulating layer including the circuit component 112 to be housed. In the wiring pattern 111 formed in this manner, the wiring pattern 111 is not actively provided in a region facing the circuit component 112, thereby realizing a multilayered structure and a thinned structure.

  As described above, the component-embedded substrate 101 of the present invention has a variation in the height of the circuit component 112 (and also in the place where the tallest circuit component is mounted and incorporated), and the wiring pattern 111 immediately above the circuit component 112. Even in the case where the interface with the insulating layer having contact is brought into contact, the electrical short phenomenon can be avoided, so that excellent high reliability is realized.

(Embodiment 6)
Embodiment 6 of an electronic component built-in substrate and a method for manufacturing the same according to the present invention will be described below with reference to FIGS. 10 (c) to 10 (e).

  FIGS. 9A and 9B are cross-sectional views showing a structure for realizing further thinning of the component-embedded substrate. FIGS. 10C, 10D, and 10E are respectively 5 FIGS. 9A and 9B are cross-sectional views of an electronic component built-in substrate having a layer structure and an enlarged view thereof. FIGS. 9A and 10B are different structures and functions and effects. Is described.

  10C, 10D, and 10E are a cross-sectional view of an electronic component built-in substrate having a five-layer structure according to Embodiment 6 of the present invention, and an enlarged cross-sectional view, respectively. A) It is description regarding the electronic component built-in board | substrate different from what was demonstrated by (B).

  The connection method between the built-in component and the board wiring pattern is roughly divided into a solder connection and a plating connection, and the orientation is not suitable depending on the configuration of the terminal electrode of the component.

  Ordinary chip LCR components have a two-terminal structure and many are mounted. For this reason, solder connection in which mounting connection reliability is ensured by the self-alignment effect is preferable. On the other hand, in the case of parts having multiple terminals, especially when the terminals are arranged in the area as in the wafer level CSP, a rewiring structure in which the wiring via is drawn out directly by the plating via and fan-out is possible is preferable.

  In the present embodiment, a preferred structure and manufacturing process of a substrate incorporating both types of components (chip C and wafer level CSP) will be described.

  In this embodiment, as shown in FIG. 10C, the chip C112 is mounted on the two-layer substrate 122 by face-down solder mounting, and the wafer level CSP 130 is mounted by face-up die bonding.

  As a manufacturing method of this structure, only the interlayer vias between the layer 2 and the layer 3 are electrically connected with a conductive via paste previously filled and press-cured. The interlayer vias between layer 3 and layer 4 are connected by a heat press in batch lamination as shown in FIG. 9 (A), but this part is a resin at the time of component incorporation as described in the first embodiment. In order to achieve both via connection against flow and via connection with a roughened copper foil satisfying solder wettability, it is necessary to adopt a configuration as shown in FIGS.

  On the other hand, for the wafer level CSP 130 mounted with face-up die bonding, laser via processing is performed after accurately aligning the area-shaped external terminal electrodes, and desmear, electroless Cu plating, and electrolytic Cu plating are performed. A conformal via (or filled plating via) 131 is formed. Thereafter, Cu patterning is performed by a photolithographic method to form a fan-out rewiring layer 132.

  When the wafer level CSP 130 has a large number of external terminals and the terminal pitch is narrowly adjacent, it is preferable to use the semi-additive method as a method for forming the rewiring layer.

  In the present embodiment, the bare semiconductor described with reference to the wafer level CSP may be embedded and plated vias may be connected.

  FIG. 10 (d) shows a case where the lead-out surface of the built-in chip C112 and the rewiring lead-out surface of the wafer level CSP 130 are formed on both sides and the opposite side, respectively. As shown in FIG. 4, both parts may be drawn on the same surface side.

  FIGS. 11 (f) and 11 (g) are cross-sectional views of the electronic component built-in substrate when both are connected by plating. In the case of FIG. 11 (f), it is preferable that both parts are drawn out by the plating via 131 in the process. In the case of FIG. 11G, the structure is suitable when the solder reflow conditions and the like performed in the secondary mounting are severe conditions at high temperatures.

  The component-embedded substrate and the manufacturing method thereof according to the present invention are suitable for miniaturization and low profile, low cost, and excellent mass productivity.

17 Cu particles 18 First metal region 19 Second metal region 20 Surface contact portion 101 Component-embedded substrate 102 First insulating layer 103 First curable resin 104 First glass fiber 105 Second insulating layer 106 Second Curable resin 107 Second glass fiber 108 Through hole 109 Via 110 Conductive paste 111 Wiring pattern 112 Circuit component 113 Mounting material 114 Housing portion 115 Multilayer substrate portion 116 Prepreg 117 Protective film 118 Protruding portion 119 Copper foil 120 First opening Part 121 Relay wiring board 122 Mounting board 123 Second opening 124 Squeegee 125 Arrow 126 Inter-substrate connection layer 127 Mounting terminal 128 Composite sheet 129 Cured conductive paste containing CuSn intermetallic compound 131 Plating via 132 Fan-out rewiring layer

Claims (9)

A first insulating layer having a first glass fiber, a first curable resin, and a wiring pattern;
A multilayer substrate part formed by laminating a second insulating layer having a second glass fiber, a second curable resin, and a via;
A circuit component mounted using solder on the wiring pattern on the inner layer side of the first insulating layer of the outermost layer of the multilayer substrate portion;
A receiving portion provided in the multilayer substrate portion for receiving the circuit component;
A component-embedded substrate having
The multilayer substrate portion is formed by alternately laminating and curing the cured first insulating layer and the uncured second insulating layer,
Between the circuit component accommodated in the accommodating portion and the multilayer substrate portion, a cured product of the second curable resin of the second insulating layer is filled,
The via is electrically connected to a through hole formed in the second insulating layer and the wiring pattern filled in the through hole and the surface of the first insulating layer is roughened to have a lump shape size of 2 μm or less. A metal portion including at least Cu, Sn, and Bi, and a resin portion, wherein the metal portion includes a region made of Cu particles, and the surface contact portion between the Cu particles having an intermetallic compound as a main component. A component-embedded substrate comprising a first metal region covering the periphery of the first metal region and a conductive paste composed of a second metal region mainly composed of Bi. The housing part includes a first opening formed by removing a part of the cured first insulating layer together with the first glass fiber, and a part of the uncured second insulating layer. The second openings formed by being penetrated and removed together with the second glass fibers are alternately laminated,
The cut surface of the first glass fiber exposed in the first opening is covered with the second curable resin,
The width or area of the second opening is smaller than the width or area of the first opening, or the cross-section of the second glass fiber of the second opening is the same as that of the first opening. 2. The component-embedded substrate according to claim 1, wherein the component-embedded substrate is located closer to the circuit component than a cross section of the first glass fiber. 2. The component built-in board according to claim 1, wherein a part of the second glass fiber constituting the second insulating layer surrounding the housing portion is contained in the housing portion. The component built-in substrate according to claim 1, wherein the second glass fiber is provided between the via portion formed in the second insulating layer and the accommodating portion. The conductive paste filled in the second insulating layer includes a metal part including at least Cu, Sn, and Bi and a resin part, and the metal part includes a region composed of Cu particles, an intermetallic compound as a main component. Cu wiring composed of a first metal region covering the surface contact portion of the Cu particles so as to straddle the surface contact portion, and a second metal region mainly composed of Bi, and is interlayer-connected by this conductive paste The component-embedded substrate according to claim 1, wherein the pattern surface has a knob shape size of 2 μm or less. In the first opening portion in which a part of the cured first insulating layer is penetrated and removed together with the first glass fiber, the copper foil pattern is a wiring design that recedes from the opening portion. The component-embedded substrate according to claim 1. A first insulating layer having a first glass fiber, a first curable resin, and a wiring pattern;
A multilayer substrate part formed by laminating a second insulating layer having a second glass fiber, a second curable resin, and a via;
A circuit component mounted by using the wiring pattern and plating connection outside the first insulating layer of the outermost layer of the multilayer substrate portion;
A receiving portion provided in the multilayer substrate portion for receiving the circuit component;
A component-embedded substrate having
The multilayer substrate portion is formed by alternately laminating and curing the cured first insulating layer and the uncured second insulating layer,
Between the circuit component accommodated in the accommodating portion and the multilayer substrate portion, a cured product of the second curable resin of the second insulating layer is filled,
The via includes at least Cu, Sn, and Bi electrically connected to a through hole formed in the second insulating layer and the wiring pattern of the first insulating layer filled in the through hole. Including a metal part and a resin part, the metal part is a region made of Cu particles, a first metal region covering the periphery so as to straddle the surface contact portion of the Cu particles with an intermetallic compound as a main component, A component-embedded board comprising a conductive paste composed of a second metal region containing Bi as a main component. A first insulating layer step of preparing a plurality of cured first insulating layers having a first glass fiber, a cured first curable resin, and a wiring pattern;
A first housing portion forming step for forming a first housing portion for housing the circuit component in the first insulating layer, a second glass fiber, and an uncured second curable resin. A second insulating layer step of preparing a plurality of insulating layers of 2;
A second housing portion forming step of forming a second housing portion in the uncured second insulating layer;
A through hole forming step of forming a through hole in the uncured second insulating layer;
A filling step of filling the through hole of the uncured second insulating layer with a conductive paste;
A step of roughening the surface of the copper foil so that the size of the ridge shape is 2 μm or less by a fine micro-etching method for the wiring pattern on the inner layer side of the first insulating layer which is at least one of the outermost layers, and the copper foil A mounting process for mounting circuit components on top,
The first insulating layer in which the first accommodating portion is formed and the uncured second insulating layer in which the second accommodating portion is formed are alternately stacked, and one or more of them A lamination step of laminating the first insulating layer obtained in the mounting step on the outermost layer to form a multilayer substrate portion;
While pressing and heating the multilayer substrate part,
Electrically connecting the conductive paste filled in the through hole and the wiring pattern of the first insulating layer;
Furthermore, the uncured second curability contained in the uncured second insulating layer between the circuit component housed in the first and second housing portions and the multilayer substrate. An integrated process of filling the resin;
A method of manufacturing a component-embedded substrate having at least The conductive paste includes a metal part including at least Cu, Sn, and Bi, and a resin part. The metal part is a region made of Cu particles, and the surface contact part between the Cu particles having a constituent intermetallic compound as a main component. The method for manufacturing a component-embedded board according to claim 8, comprising: a first metal region that covers the periphery of the first metal region and a second metal region that contains Bi as a main component.