JP2008270324A - Electronic part built-in substrate and electronic device using same, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic part built-in substrate wherein interlayer connection can be simplified with high reliability. <P>SOLUTION: The electronic part built-in substrate includes an electronic part 105 that is mounted to a first wiring layer 101 and the upper surface of the first wiring layer 101, a second wiring layer 104 that is electrically connected with the first wiring layer 101 on the first wiring layer 101 via a bump 110, and an adhesive layer 108 that is arranged between the first wiring layer 101 and the second wiring layer 104 and is penetrated by the bump 110. The adhesive layer 108 is made of a fiber material and an insulating resin contained in the fiber material, and the fiber material has a first void 103 larger than the electronic part 105, wherein the electronic part 105 is arranged in this void 103. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electronic component built-in substrate in which an electronic component is embedded in a multilayer substrate, an electronic device using the same, and a manufacturing method thereof.

  As electronic devices become smaller and lighter, demands for higher density printed wiring boards and smaller mounted components have become stricter. In the printed wiring board, the density is increased in the direction parallel to the surface of the wiring board by reducing the wiring rules. Furthermore, by adopting a build-up method, wiring is laminated, and via holes are formed between arbitrary layers, so that it is possible to increase the density in a direction perpendicular to the surface of the wiring board.

  On the other hand, as a semiconductor package, a surface mount device (SMD; Surface Mount Device) such as SOP (Small Outline Package) or QFP (Quad Flat Package) having a multi-pin lead on the outer periphery of the conventional package is used. There were many. In recent years, in order to further reduce the size of a semiconductor package, a chip size package (CSP) has been achieved by flip chip mounting in which an active surface of a semiconductor element faces a substrate. According to flip-chip mounting, a semiconductor element is directly mounted on a substrate via electrode terminals called bumps without using leads as bare chips. According to the flip chip mounting described above, the area where the bare chip semiconductor can be mounted is the surface of the substrate, and the mounting density is limited by the substrate size. Therefore, it is difficult to further improve the mounting density. Therefore, means for reducing the size of an electronic device by mounting a semiconductor element inside a substrate to increase the mounting density has been proposed.

  Hereinafter, a conventional electronic component built-in substrate will be described with reference to FIG. FIG. 18 is a cross-sectional view of a conventional electronic component built-in substrate.

  In FIG. 18, a conventional electronic component built-in substrate has a first insulating layer 201 made of a base material and a second insulating layer 202 made of an insulating resin layer provided on the first insulating layer 201. An electronic component 203 made of a bare chip IC is mounted on the first conductive pattern 206 on the upper surface of the insulating layer 201 and embedded in the second insulating layer 202. The connection between the first conductive pattern 206 and the electronic component 203 is made through bumps 204 formed on the electronic component 203. A second conductive pattern 208 is formed on the other upper surface of the first insulating layer 201. A third conductive pattern 210 having a predetermined pattern is formed on the second insulating layer 202, and a via hole 215 is formed in the second insulating layer 202 above the second conductive pattern 208. A conductive layer 216 is formed in the via hole 215.

As prior art document information of this technology, for example, Patent Document 1 is known.
JP 2001-77536 A

  In such a conventional substrate with built-in electronic components, the second conductive pattern 208 and the third conductive pattern 210 are electrically connected by the via hole 215 that penetrates the second insulating layer 202. Since the electronic component 203 is built in, the thickness is large, so that the via hole 215 is also a deep hole. Therefore, it is very difficult to form the conductive layer 216 by plating in the via hole 215 which is a deep hole, and there is a problem that the mass productivity is poor.

  The present invention solves such a problem, and an object of the present invention is to provide an electronic component-embedded substrate that is simple and has high connection reliability, an electronic device using the same, and a manufacturing method thereof.

  In order to achieve the above object, the present invention provides a first wiring layer, an electronic component mounted on the upper surface of the first wiring layer, and the first wiring layer via a bump on the first wiring layer. A second wiring layer electrically connected; and an adhesive layer disposed between the first wiring layer and the second wiring layer and penetrated by the bump, the adhesive layer comprising a fiber material and It is made of an insulating resin included in the fiber material, and the fiber material has a first gap larger than the size of the electronic component, and the electronic component-embedded substrate in which the electronic component is arranged in the first gap. By using a simple and inexpensive bump connection, the connection reliability between the first wiring layer and the second wiring layer can be improved. Moreover, it can prevent that an electronic component receives the stress from a fiber material at the time of manufacture because the fiber material has a 1st space | gap larger than the size of an electronic component. As a result, an electronic component built-in substrate with high connection reliability between the first wiring layer and the electronic component can be realized.

  According to a second aspect of the present invention, the adhesive layer has a third wiring layer as an inner layer of the adhesive layer, and the first wiring layer and the third wiring layer are electrically connected via bumps. 2. The electronic component built-in substrate according to claim 1, wherein the second wiring layer and the third wiring layer are electrically connected via bumps, and can be connected using minute bumps. In addition, since wiring can be routed in a layer containing electronic components, the degree of freedom in design is improved.

  According to a third aspect of the present invention, in the electronic component built-in according to the first or second aspect, the second wiring layer has a through hole penetrating between the upper surface of the second wiring layer and the first gap. Even if the gas filled in the first gap expands when the first wiring layer, the adhesive layer, and the second wiring layer are thermocompression-bonded by providing a through hole, the expanded gas is provided. Can be released to the outside of the electronic component built-in substrate, and the yield at the time of manufacturing the electronic component built-in substrate is improved.

  According to a fourth aspect of the present invention, there is provided the second electronic component which is mounted on the upper surface of the first wiring layer or the lower surface of the second wiring layer and disposed in the first gap. The electronic component built-in substrate according to any one of 3 is provided, and the electronic component built-in substrate having a further reduced size and high density can be provided.

  According to a fifth aspect of the present invention, in the electronic component according to any one of the first to fourth aspects, the first gap between the fiber material and the electronic component is filled with the insulating resin. This is a built-in substrate, and has an effect that the connection reliability of electronic components can be increased by filling with an insulating resin.

  The invention according to claim 6 is the electronic component built-in substrate according to any one of claims 1 to 4, wherein the first gap between the fiber material and the electronic component is filled with gas. Thus, the electronic component can be built in the substrate without applying much load.

  The invention according to claim 7 is the electronic component built-in substrate according to any one of claims 1 to 4, wherein the bump comprises a metal bump using a metal wire and / or a plating bump by metal plating. Thus, the bumps can be formed by a simple method, and stable reliability can be realized for the electrical connection between the first wiring layer and the second wiring layer.

  The invention according to claim 8 is an electronic apparatus in which the electronic component built-in substrate according to any one of claims 1 to 7 and a display device connected to the electronic component built-in substrate are mounted. By using an electronic component built-in substrate that can be reduced in size and height, the electronic device can be reduced in size.

  The invention according to claim 9 includes a step of mounting an electronic component on the first wiring layer, a step of forming bumps on the first wiring layer and / or the second wiring layer, a fiber material, and the fiber material. A step of preparing an adhesive layer made of an insulating resin included in the substrate and provided with a first gap larger than the mounting area of the electronic component and a second gap larger than the formation area of the bump, and a desired on the first wiring layer The step of superimposing the adhesive layer and the second wiring layer at the positions so that the bumps are inside the first wiring layer and the second wiring layer, the first wiring layer, the adhesive layer, and the Manufacturing of an electronic component built-in substrate comprising a step of pressing and integrating the second wiring layer while heating and electrically connecting the first wiring layer and the second wiring layer via the bumps The method of connecting And by using an adhesive layer, an effect that it is possible to manufacture an electronic component-embedded board only in the heating and pressing step.

  The invention according to claim 10 is the method for manufacturing the electronic component built-in substrate according to claim 9, wherein the second wiring layer has a through-hole penetrating between the upper surface of the second wiring layer and the first gap. Even if the gas filled in the first gap expands when the first wiring layer, the adhesive layer, and the second wiring layer are heat-bonded by providing the through hole, the expanded gas is It can escape to the outside of the electronic component built-in substrate, and has an effect of improving the yield in manufacturing the electronic component built-in substrate.

  The invention according to claim 11 comprises the second electronic component mounted on the upper surface of the first wiring layer or the lower surface of the second wiring layer and disposed in the first gap. 10. The manufacturing method of the electronic component built-in substrate according to 10, which has an effect that it is possible to provide an electronic component built-in substrate that is further reduced in size and density.

  The invention according to claim 12 is any one of claims 9 to 11, wherein the insulating resin is filled in the first gap and the second gap between the fiber material and the electronic component. The method for manufacturing a substrate with built-in electronic components described in 1) has the effect that the connection reliability of electronic components and bumps can be increased by filling with an insulating resin.

  The invention according to claim 13 is the electronic component-embedded substrate according to any one of claims 9 to 11, wherein the first gap between the fiber material and the electronic component is filled with gas. This method is a manufacturing method, and has an effect that an electronic component can be built in a substrate without applying much load.

  The invention according to claim 14 is the manufacturing of the electronic component built-in substrate according to any one of claims 9 to 11, wherein the bump comprises a metal bump using a metal wire and / or a plating bump by metal plating. It is a method, and it is possible to form bumps by a simple method and to have an effect of realizing stable reliability with respect to the electrical connection between the first wiring layer and the second wiring layer. .

  The invention according to claim 15 is the manufacturing of the electronic component built-in substrate according to any one of claims 9 to 11, wherein the bump is formed by forming a metal bump using a metal wire on a plating bump formed by metal plating. In this method, the soft metal bumps are pressed against the hard metal plating film in the pressure-contact between the bumps. Therefore, it is possible to realize stable reliability with respect to the electrical connection between the first wiring layer and the second wiring layer.

  According to a sixteenth aspect of the present invention, in the electronic component according to any one of the ninth to fifteenth aspects, the first gap and the second gap formed in the adhesive layer are one integrated gap. This is a method for manufacturing a built-in substrate, and has an effect that an unnecessary load on electronic components and bumps can be prevented at a time while being a simple gap.

  The invention according to claim 17 is the method of manufacturing an electronic component built-in substrate according to any one of claims 9 to 15, wherein an anisotropic conductive film is disposed in an inner layer of the adhesive layer. The electrical connection can be further stabilized in the connection using the bump.

  According to an eighteenth aspect of the present invention, there is provided a step of mounting an electronic component on the first wiring layer and a first wiring layer having a space larger than a mounting area of the first wiring layer and / or the electronic component. A step of forming a bump, a step of forming a second bump on the second wiring layer and / or the third wiring layer, and mounting of the electronic component comprising a fiber material and an insulating resin included in the fiber material Preparing a first adhesive layer and a second adhesive layer having a first gap larger than an area and a second gap larger than a formation area of the first bump or the second bump, and the first after mounting the electronic component The first bump, the third wiring layer, the second adhesive layer, and the second wiring layer are placed at desired positions on one wiring layer, and the first bump is formed on the first wiring layer and the third wiring layer. The second bump is on the inner side and the third wiring layer Heating the first wiring layer, the first adhesive layer, the third wiring layer, the second adhesive layer, and the second wiring layer in order so as to be inside the second wiring layer; And a step of electrically connecting the first wiring layer, the third wiring layer, and the second wiring layer through the first bump and the second bump, and integrating the first wiring layer, the third wiring layer, and the second wiring layer. This is a method for manufacturing a component-embedded substrate, and wiring can be routed in a layer containing electronic components, and micro bumps can be used. By using the bump and the adhesive layer as the interlayer connection material, the electronic component built-in substrate can be manufactured only by the heating / pressurizing process.

  The invention according to claim 19 is the method for manufacturing the electronic component built-in substrate according to claim 18, wherein the second wiring layer has a through-hole penetrating between an upper surface of the second wiring layer and the first gap. Even if the gas filled in the first gap expands when the first wiring layer, the adhesive layer, and the second wiring layer are heat-bonded by providing the through hole, the expanded gas is It can escape to the outside of the electronic component built-in substrate, has an effect of improving the yield at the time of manufacturing the electronic component built-in substrate and stabilizing the reliability.

  The invention according to claim 20 comprises the second electronic component mounted on the upper surface of the first wiring layer or the lower surface of the second wiring layer and disposed in the first gap. 19. The manufacturing method of the electronic component built-in substrate according to 19, which has an effect that it is possible to provide an electronic component built-in substrate that achieves further miniaturization and high density.

  21. The invention according to claim 21, wherein the insulating resin is filled in the first gap, the second gap and the space between the fiber material and the electronic component. The electronic component built-in substrate manufacturing method according to any one of the above has an effect that the connection reliability of the electronic component and the bump can be improved by filling the insulating resin.

  The invention according to claim 22 is the electronic component according to any one of claims 18 to 20, wherein the first gap and the space between the fiber material and the electronic component are filled with gas. This is a method for manufacturing a built-in substrate, and has an effect that an electronic component can be built in the substrate without imposing much load.

  According to a twenty-third aspect of the present invention, the first bump and the second bump comprise a metal bump using a metal wire and / or a plating bump by metal plating. The bumper can be formed by a simple method, and stable electrical connection between the first wiring layer and the second wiring layer is realized. It has the effect of being able to.

  According to a twenty-fourth aspect of the invention, in the first bump and the second bump, a metal bump using a metal wire is formed on a plating bump by metal plating. This is a manufacturing method of a substrate with built-in electronic parts, and the metal bumps are crushed and stressed by the pressure during heating and pressurizing because the soft metal bumps are pressed against the hard metal plating film in the pressure contact between the bumps. Therefore, it is possible to realize stable reliability with respect to the electrical connection between the first wiring layer and the second wiring layer.

  According to a twenty-fifth aspect of the present invention, the first gap and the second gap formed in the first adhesive layer and the second adhesive layer are a single gap, respectively. The manufacturing method of the electronic component built-in substrate according to any one of the above has an effect that an unnecessary load on the electronic component and the bump can be prevented at a time while being a simple gap.

  With the above configuration, the connection reliability between the first wiring layer and the second wiring layer can be improved by using a simple and inexpensive bump connection. Moreover, it can prevent that an electronic component receives the stress from a fiber material at the time of manufacture because the fiber material has a 1st space | gap larger than the size of an electronic component. As a result, an electronic component built-in substrate with high connection reliability between the first wiring layer and the electronic component can be realized.

(Embodiment 1)
DESCRIPTION OF EMBODIMENTS Embodiments of an electronic component built-in substrate, an electronic apparatus using the same, and a manufacturing method thereof according to the present invention will be described below with reference to the drawings. 1 and 2 are sectional views of the electronic component built-in substrate according to the first embodiment of the present invention, and FIG. 9 is a manufacturing process sectional view of the electronic component built-in substrate according to the first embodiment of the present invention.

  As shown in FIG. 1A, the electronic component built-in substrate 100 according to the first embodiment includes a first wiring layer 101, a second wiring layer 104 and an electronic component 105 provided on the first wiring layer 101. Is provided. A first conductive pattern 102 and a second conductive pattern 106 are provided on the upper surface of the first wiring layer 101. The first wiring layer 101 is a multilayer wiring board whose insulating layer is made of a thermosetting resin. As the thermosetting resin, for example, epoxy resin, phenol resin, cyanate resin, or BT resin (bismaleimide / triazine resin) can be used. Epoxy resins are particularly preferred because of their high heat resistance. The first conductive pattern 102 and the second conductive pattern 106 are made of a material having electrical conductivity, for example, a Cu foil or a conductive resin composition. In the present invention, Cu foil is used as the first conductive pattern 102 and the second conductive pattern 106. The inner via 113 included in the first wiring layer 101 is made of, for example, a thermosetting conductive material such as a metal material by Cu plating or a conductive resin composition in which metal particles and a thermosetting resin are mixed. Become. Au, Ag, Cu, or the like can be used as the metal particles in the conductive material. Au, Ag, or Cu is preferable because of its high conductivity, and Cu is particularly preferable because of its high conductivity, low migration, and low cost. Moreover, as a thermosetting resin, an epoxy resin, a phenol resin, and cyanate resin can be used, for example. Epoxy resins are particularly preferred because of their high heat resistance.

  An Au plating film is formed on the first conductive pattern 102 on the upper surface of the first wiring layer 101. For example, the Au plating film is formed by performing Ni plating by an electroless plating method on a base metal, and forming an Au plating film by an electroless plating method on the Ni plating. Note that the Au plating film forming method is not limited to the method described above, and can be realized by various methods. However, in order to stabilize the electrical continuity when the electronic component 105 is mounted later, the Au plating film forming method is the most important. It is important that an Au plating film is formed on the surface layer.

  An electronic component 105 is mounted on the first conductive pattern 102 on which the Au plating film is formed. As the electronic component 105, a passive component composed of a semiconductor component or a chip component such as an LCR can be used. The semiconductor component is, for example, a semiconductor bare chip IC on which bumps 110 are formed, and is connected to the first conductive pattern 102 by a flip chip mounting method. As a material of the bump 110, a bump that can be formed by a simple method such as an Au stud bump by Au wire, an Au or solder bump by plating, an Ag bump by conductive paste, or the like can be used. Note that the bumps 110 may be formed by various methods without being limited to the method described above. As for the flip-chip mounting method of the semiconductor bare chip IC, an Au-Au direct connection method that does not use an auxiliary material at the time of mounting or a solder connection method using solder bumps can be used. Any flip-chip mounting method can be used as long as the mounting method is down. Further, as the mounting auxiliary material 111, a pressure contact method using Au bumps using ACF or NCF, or a method of filling an underfill between the semiconductor bare chip IC and the first wiring layer 101 after flip-chip mounting can be used. FIG. 1A shows a structure using the mounting auxiliary material 111. Note that the present invention is not limited to the above method, and any method can be used as long as it is a flip-chip mounting method in which the semiconductor bare chip IC is mounted face-down using the mounting auxiliary material 111. In addition, when a chip component is used as the electronic component 105, solder or a conductive adhesive can be used as the mounting material. As the solder, materials such as Sn—Ag, Sn—Ag—Cu, Sn—Zn, and Au—Zn can be used. However, the material is not limited to these materials and can be used to mount the electronic component 105. Any material can be used. However, it is important that the material does not contain Pb, which is an environmental pollutant. As the conductive adhesive, a material obtained by mixing metal particles such as Au, Ag, or Cu and a thermosetting resin such as an epoxy resin, a phenol resin, or a cyanate resin can be used. Among them, a combination of Ag and an epoxy resin is particularly preferable because it has high conductivity and high heat resistance.

  On the first wiring layer 101, a second wiring layer 104 is laminated via an adhesive layer 108 so as to confine the electronic component 105 inside. As the adhesive layer 108, a glass epoxy prepreg in which a glass woven fabric is impregnated with a thermosetting epoxy resin, a BT resin prepreg in which a glass woven fabric is impregnated with a thermosetting bismaleimide / triazine resin, and an aramid nonwoven fabric are thermally cured. It is possible to use an aramid prepreg impregnated with a curable epoxy resin, but various materials can be used as long as the structure is a woven fabric or nonwoven fabric impregnated with a thermosetting resin. .

  The second wiring layer 104 is a wiring substrate having a third conductive pattern 115 and a fourth conductive pattern 116 on the front and back surfaces, and an insulating layer made of a thermosetting resin. Similar to the first wiring layer 101, as the thermosetting resin, for example, epoxy resin, phenol resin, cyanate resin, or BT resin can be used. Epoxy resins are particularly preferred because of their high heat resistance. The third conductive pattern 115 and the fourth conductive pattern 116 are made of a material having electrical conductivity, for example, a Cu foil or a conductive resin composition. In the present invention, Cu foil is used. In the present invention, the second wiring layer 104 has a two-layer structure, but is not limited to a two-layer structure, and a multilayer wiring board may be used. In addition, as a method for performing interlayer connection in the second wiring layer 104, a general printed wiring board connection method such as an inner via structure or a through-hole structure can be used. Note that the material selection of the first wiring layer 101, the adhesive layer 108, and the second wiring layer 104 can be arbitrarily performed, but the difference in linear expansion coefficient is not increased when the materials are made of the same kind of material. It is particularly preferable in that it works effectively for preventing warpage and maintains high reliability.

  Electrical connection between the first wiring layer 101 and the second wiring layer 104 is made by a bump 118 formed between the second conductive pattern 106 and the third conductive pattern 115. The second conductive pattern 106 and the third conductive pattern 115 are formed with an Au plating film on the surface for good connection with the bump 118. A method of roughening the pattern surface may be used instead of the Au plating film. The bump 118 is made of a metal bump or a metal plating film such as an Au stud bump made of Au wire, a Cu stud bump made of Cu wire, or an Al stud bump made of Al wire. Au stud bumps are particularly preferable because they are soft and have high connection stability.

  A first gap 103 that is a space larger than the size of the electronic component 105 is formed in the adhesive layer 108 made of the fiber material so that the fiber material does not contact the electronic component 105. When the electronic component 105 is built in the space surrounded by the first wiring layer 101, the adhesive layer 108, and the second wiring layer 104 due to the presence of the first gap 103 larger than the size of the electronic component 105, Unnecessary stress applied to the portion can be avoided, and the connection reliability of the electronic component 105 can be stabilized. The first gap 103 may have a structure in which only a gas is present as shown in FIG. 1A, but as shown in FIG. A structure in which the curable resin 107 is filled may be employed. As an advantage of the structure in which the thermosetting resin 107 is filled in the first gap 103, it is possible to adopt a structure in which the thermosetting resin 107 applies a uniform pressure to the entire surface of the electronic component 105. The connection reliability can be further stabilized.

  Further, as shown in FIG. 2A, the second wiring layer 104 can have a structure having a through hole 117. By forming the through hole 117, it is possible to avoid the stress applied to the first wiring layer 101 and the second wiring layer 104 due to the expansion and contraction of the gas inside the first gap 103 due to various temperature conditions. The effectiveness of the through-hole 117 formed in the second wiring layer 104 can be increased if it is at least one, but the effectiveness can be further improved by forming a plurality of through-holes 117. . 1B, as shown in FIG. 2B, the thermosetting resin 107 is filled in the first gap 103 even in the structure in which the through hole 117 is formed in the second wiring layer 104. It is good also as a structure to do.

  With the above configuration, by using the bump 118 as the interlayer connection material, it becomes possible to realize an electronic component built-in substrate using a simple and inexpensive method, and the presence of the first gap 103 allows the electronic component built-in substrate to be realized. Since it is possible to avoid stress from the fiber material with respect to the electronic component 105 disposed inside, an electronic component-embedded substrate with high connection reliability can be realized.

  Next, an embodiment of a method for manufacturing an electronic component built-in substrate according to the present invention will be described with reference to the drawings.

  FIG. 9 is a manufacturing process sectional view of the electronic circuit device according to the first embodiment of the present invention.

  As shown in FIG. 9A, the first conductive pattern of the multilayer wiring board including the first conductive pattern 102 disposed on the upper surface of the first wiring layer 101, the second conductive pattern 106, and the inner via 113. An Au plating film is formed on 102. Thereafter, as shown in FIG. 9B, the electronic component 105 made of a semiconductor bare chip IC in which bumps 110 are formed on the electrodes is flip-chip mounted on the first conductive pattern 102.

  Next, as shown in FIG. 9C, bumps 118 are formed on the third conductive pattern 115 side of the second wiring layer 104 having the third conductive pattern 115 and the fourth conductive pattern 116 on the front and back surfaces. . The bump 118 includes an Au stud bump made of Au wire, a Cu stud bump made of Cu wire, an Al stud bump made of Al wire, an Au plated film in which an Au plated film is formed on an electroless Ni plated film, and Cu formed by Cu plating. A metal plating film such as a plating film can be used. Au stud bumps are particularly preferable because they are soft and have high connection stability. When Au stud bumps are used for the bumps 118, an Au plating film is formed on the surface of the third conductive pattern 115 in order to easily form the bumps 118. Then, the surface of the second conductive pattern 106 connected to the bump 118 is not formed by previously forming an Au plating film on the surface in order to make a good connection with the second bump 118 or by forming an Au plating film. Alternatively, a method of roughening the pattern surface by etching or the like may be used. Although FIG. 9C shows a structure in which the bump 118 is formed on the second wiring layer 104, the bump 118 may be formed on the second conductive pattern 106 side on the first wiring layer 101. good.

  Next, as shown in FIG. 9D, an adhesive layer 108 having a structure in which a woven fabric or a nonwoven fabric is impregnated with a thermosetting resin is overlapped with the first wiring layer 101 and the second wiring layer 104 later. At this time, a first gap 103 that is a space larger than the electronic component 105 and a second gap 135 that is substantially equal to or larger than the bump 118 are formed at positions corresponding to the electronic component 105 and the bump 118.

  Next, as shown in FIG. 9E, the adhesive layer 108 in which the first gap 103 and the second gap 135 are formed on the first wiring layer 101 after the electronic component 105 is mounted, and the second wiring layer 104 are bumped. The layers 118 are sequentially overlapped so that 118 is positioned between the first wiring layer 101 and the second wiring layer 104. Note that the first wiring layer 101, the adhesive layer 108, and the second wiring layer 104 are preferably made of the same composition material in order to prevent warping and deformation of the laminated substrate, but when different materials are used. It is important to select a material having a small difference in thermal expansion coefficient.

  Further, the adhesive layer 108 is formed thicker than the height from the first wiring layer 101 after the electronic component 105 is mounted so that the electronic component 5 is not pressurized when the second wiring layer 104 contacts the electronic component 105. There is a need.

  On the other hand, it is difficult to avoid a high cost because it is a custom-made product to make the adhesive layer 108 thick in order to avoid contact with the electronic component 105, and it is difficult to mass-produce it. It is unsuitable. Therefore, a desired thickness is secured for the adhesive layer 108 by using a plurality of prepregs having a general thickness (for example, 100 μm) that are normally used for manufacturing a wiring board.

  The adhesive layer 108 is a mixed sheet of woven or non-woven fabric and an uncured thermosetting resin. The adhesive layer 108 is a thermosetting resin softened from the adhesive layer 108 by applying pressure while heating. Flows out and is always thinner than the initial thickness after heating and pressurization. For this reason, if the thickness reduction is designed in advance, it is possible to prevent the second wiring layer 104 from coming into contact with the electronic component 105 even after lamination.

  Finally, as shown in FIG. 9 (f), the bumps 118 are formed by pressurizing each of the superimposed constituent materials with a press machine (not shown) at a pressure of 2 MPa while heating at 200 ° C., for example. Is sandwiched between the second conductive pattern 106 and the third conductive pattern 115. At this time, the bump 118 exists between the first wiring layer 101 and the second wiring layer 104 while being crushed to a height substantially equal to the thickness of the adhesive layer 108. In this manner, the first bumps 132 are crushed and come into contact with the second conductive pattern 106 and the third conductive pattern 115, so that the bump 118, sufficient between the second conductive pattern 106 and the third conductive pattern 115 are sufficient. Therefore, a stable contact area can be secured and stable electrical conduction can be performed.

  In addition, the figure which filled the 1st space | gap 103 with the thermosetting resin 107 by controlling the amount of thermosetting resins contained in the contact bonding layer 108, using the same method as the manufacturing method shown in FIG. It is possible to produce the structure shown in 1 (b).

  Further, if the second wiring layer 104 in which the through holes 117 are formed in advance is used instead of the second wiring layer 104 shown in FIG. 9, the electronic component built-in substrate shown in FIGS. 2A and 2B is manufactured. can do.

  Hereinafter, the characteristics of the electronic component built-in substrate and the manufacturing method thereof shown in the first embodiment will be described.

  In the electronic component built-in substrate and the method for manufacturing the same according to the present invention, the electrical connection of the electronic component built-in layer can be realized only by the heating and pressurizing process by pressing by using the bump and the adhesive layer. . Further, a first gap having a size larger than that of the electronic component is formed in the adhesive layer so as not to apply a load to the electronic component, and the bump formed in either the first wiring layer or the second wiring layer is securely disposed on the other side. In order to contact the substrate, a second gap is formed at a position corresponding to the bump of the adhesive layer. In addition, the bump can be formed with a high-precision bump while being inexpensive by using a metal bump using a metal wire or a plating bump made of a metal plating film. With the above configuration, an electronic component built-in substrate with high interlayer connection reliability can be realized by an inexpensive method.

  As described above, according to the first embodiment, by using bumps and an adhesive layer, an electronic component built-in substrate with high interlayer connection reliability can be realized only by a heating / pressurizing process.

(Embodiment 2)
Hereinafter, Embodiment 2 according to the present invention will be described with reference to the drawings. FIG. 10 is a manufacturing process sectional view of the electronic component built-in substrate according to the second embodiment of the present invention. Unless otherwise described, the same structure as that of the first embodiment is given the same number and the description thereof is omitted.

  The main difference between the second embodiment and the first embodiment is that bumps 118 are formed on both the first wiring layer 101 and the second wiring layer 104 as shown in FIGS. It is that. As the bumps 118a and 118b, Au stud bumps made of Au wire, Cu stud bumps made of Cu wire, and Al stud bumps made of Al wire can be used. Au stud bumps are particularly preferable because they are soft and have high connection stability. At this time, the surface of the second conductive pattern 106 for forming the bump 118a and the surface of the third conductive pattern 115 for forming the bump 118b are preliminarily coated with an Au plating film for good connection with the bumps 118a and 118b. Forming. The bumps 118a and 118b formed on both the first wiring layer 101 and the second wiring layer 104 are overlapped with each other facing each other as shown in FIG. 10G, and then shown in FIG. As described above, the bumps 118a and the bumps 118b are directly brought into contact with each other through a heating / pressurizing step and integrated while being crushed to make electrical connection. As an advantage of using the bump 118a and the bump 118b, in order to incorporate the electronic component 105, the bump 118 having a height higher than that of the electronic component 105 is required. However, by using two bumps of the bump 118a and the bump 118b, It is possible to use a small bump for each bump. Since the height of the built-in electronic component 105 is usually 100 μm or more, the height of the bump 118 necessary for the built-in layer is required to be at least 150 μm or more in consideration of the mounting height of the electronic component 105, as shown in FIG. With the structure shown, the bumps 118a and the bumps 118b can be used at a height of 100 μm or less. Bumps with a height of 100 μm or less are very easy to form and can be a manufacturing method rich in mass productivity.

  In addition, the figure which filled the 1st space | gap 103 with the thermosetting resin 107 by controlling the amount of the thermosetting resins contained in the contact bonding layer 108 using the same method as the manufacturing method shown in FIG. A structure similar to the structure shown in 1 (b) can be manufactured.

  Further, if the second wiring layer 104 in which the through holes 117 are formed in advance is used instead of the second wiring layer 104 shown in FIG. 10, it is similar to the electronic component built-in substrate shown in FIGS. 2 (a) and 2 (b). The structure can be manufactured.

(Embodiment 3)
Embodiment 3 according to the present invention will be described below with reference to the drawings. FIG. 11 is a manufacturing process sectional view of an electronic component built-in substrate according to Embodiment 3 of the present invention. Unless otherwise specified, the same structures as those in Embodiments 1 and 2 are given the same reference numerals and description thereof is omitted.

  The main difference between the first embodiment and the second embodiment in the third embodiment is that plating is performed as bumps 118a on the second wiring pattern 106 on the first wiring layer 101 as shown in FIG. A plating bump is formed by a film, and the bump 118b made of the stud bump formed in FIG. 11E is overlapped with each other as shown in FIG. 11G, and then shown in FIG. 11H. In this way, electrical connection is made by direct contact through a heating / pressurizing process. The effect similar to that of the second embodiment can be obtained by using the plating bump. However, as a further advantage, when the bumps are crushed from the vertical direction, which occurs when soft stud bumps are connected to each other. It is possible to prevent connection failure due to falling and falling. In this case, the plating bump serves as a pillar in the heating / pressurizing process to prevent the bump from falling down. Further, in this case, the plating bump made of the metal plating film can be easily increased in diameter as compared with the stud bump using the metal wire. By increasing the diameter, it becomes possible to play the role of a pillar in the heating and pressurizing process more reliably, and when the bumps 118a and 118b as shown in FIG. Position accuracy can be relaxed, and a manufacturing method rich in mass productivity can be obtained. In addition, it becomes possible to stabilize the electrical connection with the stud bump by forming an Au plating film on the surface of the plating bump or roughening the surface.

  In FIG. 11, the structure is such that plating bumps are formed as bumps 118a on the first wiring layer 101 side and stud bumps are formed as bumps 118b on the second wiring layer 104 side, but studs are formed on the first wiring layer 101 side. A structure in which bumps are formed and plating bumps are formed on the second wiring layer 104 side may be employed.

  In addition, the figure which filled the 1st space | gap 103 with the thermosetting resin 107 by controlling the quantity of the thermosetting resin contained in the contact bonding layer 108 using the same method as the manufacturing method shown in FIG. A structure similar to the structure shown in 1 (b) can be manufactured.

  If the second wiring layer 104 in which the through-hole 117 is formed in advance is used instead of the second wiring layer 104 shown in FIG. 11, it is similar to the electronic component built-in substrate shown in FIGS. 2 (a) and 2 (b). The structure can be manufactured.

(Embodiment 4)
Embodiment 4 according to the present invention will be described below with reference to the drawings. FIG. 12 is a cross-sectional view of the manufacturing process of the electronic component built-in substrate according to the fourth embodiment of the present invention. Unless otherwise specified, the same structure as that of the above-described embodiment is given the same number and the description thereof is omitted.

  The main difference between the first embodiment, the second embodiment, and the third embodiment in the fourth embodiment is that the third wiring pattern 115 on the second wiring layer 104 is as shown in FIG. A plating bump made of a plating film is formed as a bump 130, and a bump 118 made of a stud bump is formed on the bump 130 as shown in FIG. Thereafter, as shown in FIG. 12 (f), the first wiring layer 101, the adhesive layer 108, and the second wiring layer 104 are overlaid so that the bump 118 is sandwiched between the first wiring layer 101 and the second wiring layer 104. After the alignment, as shown in FIG. 12 (g), the first wiring layer 101, the adhesive layer 108, and the second wiring layer 104 are integrated while the bumps 118 are crushed through a heating / pressurizing process, so that the first wiring Electrical connection is made between the layer 101 and the second wiring layer 104. With the structure described above, the same effects as those of the second and third embodiments can be obtained. However, as a further advantage, the positional accuracy between the bump 130 and the bump 118 can be perfectly matched. Therefore, it is possible to prevent a conduction failure due to bump deviation at the time of stacking.

  In FIG. 12, the bump 130 and the bump 118 are formed on the first wiring layer 102 side, but the structure may be formed on the first wiring layer 101 side.

  In addition, the figure which filled the 1st space | gap 103 with the thermosetting resin 107 by controlling the amount of thermosetting resins contained in the contact bonding layer 108, using the same method as the manufacturing method shown in FIG. A structure similar to the structure shown in 1 (b) can be manufactured.

  If the second wiring layer 104 in which the through holes 117 are formed in advance is used instead of the second wiring layer 104 shown in FIG. 12, it is similar to the electronic component built-in substrate shown in FIGS. The structure can be manufactured.

(Embodiment 5)
Embodiment 5 according to the present invention will be described below with reference to the drawings. FIG. 13 is a cross-sectional view of a manufacturing process for an electronic component built-in substrate according to Embodiment 5 of the present invention. Unless otherwise specified, the same structure as that of the above-described embodiment is denoted by the same reference numeral and description thereof is omitted.

  The main difference of the fifth embodiment from the first embodiment is that in the first embodiment, when the first wiring layer 101 and the second wiring layer 104 are superimposed on the adhesive layer later, the electronic component 105 and the bump 118 are used. The first gap 103 that is a larger space than the electronic component 105 and the second gap 135 that is substantially equal to or larger than the bump 118 are formed at positions corresponding to In other words, the gap 103a is enlarged to 135 and integrated. Thus, by making one gap 103a, the gap 103a can be easily processed, the distance between the electronic component 105 and the inner wall of the gap 103a is increased, and the distance between the electronic component 105 and the inner wall of the gap 103a is increased. Since the bump 118 exists between them, it is possible to prevent the pressure from the adhesive layer 108 from being applied directly to the electronic component 105 during heating and pressurization, and the connection reliability of the electronic component 105 can be stabilized. Become. Although FIG. 13C shows a structure in which the bump 118 is formed on the second wiring layer 104, the bump 118 may be formed on the second conductive pattern 106 side on the first wiring layer 101. good. It is also possible to employ a bump structure as shown in the second to fourth embodiments. However, regarding the fifth embodiment, as shown in FIG. 13F, it is important that the gap 103a is completely filled with the thermosetting resin 107 after the heating / pressurizing step. When the gap 103 a is not filled with the thermosetting resin 107, there is no thermosetting resin around the bump 118, so the bump 118 and the first wiring layer 101 or the second wiring layer 104 are not connected. This is because the connection becomes unstable.

  If the second wiring layer 104 in which the through holes 117 are formed in advance is used instead of the second wiring layer 104 shown in FIG. 13, the electronic component built-in substrate shown in FIG. 2B can be manufactured. . However, even in this case, it is important to completely fill the gap 103a with the thermosetting resin 107.

(Embodiment 6)
Embodiment 6 according to the present invention will be described below with reference to the drawings. FIG. 14 is a cross-sectional view of a manufacturing process of an electronic component built-in substrate according to Embodiment 6 of the present invention. Unless otherwise specified, the same structure as that of the above-described embodiment is given the same number and the description thereof is omitted.

  The sixth embodiment has a structure similar to that of the second and third embodiments. In the sixth embodiment, as shown in FIG. 14G, the anisotropic conductive film 138 is disposed in the inner layer of the adhesive layer 108, and as shown in FIG. The anisotropic conductive film 138 is sandwiched and electrically connected by bumps 118a and 118b made of stud bumps and / or plated bumps formed on both of the two wiring layers 104 by a heating / pressurizing process. The anisotropic conductive film 138 is a film in which fine conductive balls are dispersed in a thermosetting resin and processed into a film. The film itself is insulative, but the anisotropic conductive film 138 is a pair. When the electrode is sandwiched between the two electrodes and crushed, the conductive ball comes into contact with the pair of electrodes to conduct between the electrodes, and at the same time, the electrodes can be fixed. Conductive balls used for the anisotropic conductive film 138 are coated with a metal ball made of a single or alloy such as Au, Ag, Cu, or Ni, or a metal plating film such as Au, Ag, Cu, or Ni. Resin balls are used. Note that the conductive ball used is not limited to the above-described material, and any material may be used as long as it has a feature of being sandwiched between a pair of electrodes and conducting between the two electrodes. As the thermosetting resin, for example, an epoxy resin, a phenol resin, a cyanate resin, or the like can be used. However, regardless of the materials described above, various materials can be used as long as they are thermosetting resins.

  By using the anisotropic conductive film 138, each of the bumps 118a and 118b comes into contact with the anisotropic conductive film 138 individually, so that an adhesive force with the thermosetting resin can be obtained and the electrical conduction is stabilized. Is something that can be done.

  In addition, the figure which filled the 1st space | gap 103 with the thermosetting resin 107 by controlling the quantity of the thermosetting resin contained in the contact bonding layer 108, using the same method as the manufacturing method shown in FIG. A structure similar to the structure shown in 1 (b) can be manufactured.

  Further, if the second wiring layer 104 in which the through holes 117 are formed in advance is used instead of the second wiring layer 104 shown in FIG. 14, it is similar to the electronic component built-in substrate shown in FIGS. 2 (a) and (b). The structure can be manufactured.

(Embodiment 7)
Embodiment 7 according to the present invention will be described below with reference to the drawings. 3 and 4 are sectional views of the electronic component built-in substrate according to the seventh embodiment of the present invention, and FIG. 15 is a manufacturing process sectional view of the electronic component built-in substrate according to the seventh embodiment of the present invention. Unless otherwise specified, the same structure as that of the above-described embodiment is given the same number and the description thereof is omitted.

  In the seventh embodiment, the third wiring layer 114 is arranged in the adhesive layer 108 as shown in FIG. 3A with respect to the electronic component built-in substrate structure shown in the first embodiment. As a method of disposing the third wiring layer 114 in the adhesive layer 108, as shown in FIG. 15C, the third wiring layer 114 having a space 131 larger than the size of the electronic component 105 is used, and the adhesive layer 108 is used. 2 sets are prepared, and as shown in FIG. 15 (f), the adhesive layer 108 is disposed above and below the third wiring layer 114 and sandwiched between the first wiring layer 101 and the second wiring layer 104 and heated.・ Pressure to be integrated. The bump 118c that connects the first wiring layer 101 and the third wiring layer 114 and the bump 118d that connects the second wiring layer 104 and the third wiring layer 114 are formed on the third wiring layer 114 in FIG. In addition, the bump 118d is formed on the second wiring layer 104. In addition, a combination in which the bump 118c is formed on the first wiring layer 101 and the bump 118d is formed on the third wiring layer 114, and A combination in which the bump 118 c is formed on the third wiring layer 114 and the bump 118 d is formed on the second wiring layer 104 may be used. As the bumps 118c and 118d, an Au stud bump made of Au wire, a Cu stud bump made of Cu wire, and an Al stud bump made of Al wire can be used. Au stud bumps are particularly preferable because they are soft and have high connection stability.

  By using the third wiring layer 114, it is possible to use minute stud bumps for the bumps 118c and 118d regardless of the height of the built-in electronic component 105. Even if the height of the built-in electronic component 105 is increased, by controlling the thickness of the third wiring layer 114, the bumps 118c and 118d have minute stud bumps with a height of about 50 μm that are always easy to manufacture. This is because it can be adopted. In addition, since the bumps 118c and 118d can be sandwiched between the first wiring layer 101, the second wiring layer 104, and the third wiring layer 114, respectively, the bumps 118c and 118d are surely crushed. Therefore, the electrical continuity can be stabilized, and the electronic component built-in substrate with high connection reliability can be obtained.

  Similar to the above-described embodiment, all the first gaps 103 are formed by controlling the amount of the thermosetting resin contained in the adhesive layer 108 while using the same method as the manufacturing method shown in FIG. The structure shown in FIG. 3B filled with the thermosetting resin 107 can be manufactured.

  If the second wiring layer 104 in which the through holes 117 are formed in advance is used in place of the second wiring layer 104 shown in FIG. 15, the electronic component built-in substrate shown in FIGS. 4A and 4B is manufactured. can do.

(Embodiment 8)
Embodiment 8 according to the present invention will be described below with reference to the drawings. 5, FIG. 6, FIG. 7 and FIG. 8 are sectional views of the electronic component built-in substrate of the present invention, and FIG. 16 is a sectional view of the manufacturing process of the electronic component built-in substrate according to the eighth embodiment of the present invention. Unless otherwise specified, the same structure as that of the above-described embodiment is denoted by the same reference numeral and description thereof is omitted.

  As shown in FIGS. 5 to 8, the eighth embodiment is an electronic component built-in substrate in which an electronic component 105 and a second electronic component 119 are built. The second electronic component 119 is mounted on either the first wiring layer 101 or the second wiring layer 104, but is arranged so that the electronic component 105 and the second electronic component 119 do not overlap with each other in the stacking direction. It is important to. In particular, it is particularly preferable that the electronic component 105 and the second electronic component 119 are separately mounted on the first wiring layer 101 and the second wiring layer 104, respectively. When dissimilar components are embedded, such as the two-electronic component 119, the mounting methods are different, and thus it is possible to manufacture an electronic component-embedded substrate with high productivity by dividing the mounting layers. Even when it is desired to separate electrical characteristics, separating the layers to be mounted is a very effective means.

  Note that the second electronic component 119 can be incorporated in various structures by combining with the above-described embodiment.

(Embodiment 9)
Embodiment 9 according to the present invention will be described below with reference to the drawings. FIG. 17 is a cross-sectional view of an electronic apparatus using the electronic component built-in substrate of the present invention. Unless otherwise specified, the same structure as that of the above-described embodiment is given the same number and the description thereof is omitted.

  In the ninth embodiment, as shown in FIG. 17, the electronic component built-in substrate manufactured in the above-described embodiment is used, and the electronic components 140a and 140b and the metal case 141 are mounted on the surface using solder. Thus, an electronic device is manufactured. As an electronic device, as shown in FIG. 17A, a structure in which the electronic components 140a and 140b are mounted on the back side of the first wiring layer 101 of the electronic component built-in substrate, as shown in FIG. Either of the structures in which the electronic components 140a and 140b are mounted on the two-wiring layer 104 can be implemented. The structure shown in FIG. 17A is suitable particularly when a thin substrate is required as the electronic component built-in substrate, and the electrical components 105 and the electronic components 140a and 140b mounted on the surface layer are electrically connected. In order to prevent excessive interference, the structure shown in FIG. 17B is suitable. Note that the electronic component built-in substrate used in the ninth embodiment can be any of the electronic component built-in substrates manufactured in the above-described embodiment. According to the ninth embodiment, it is possible to reduce the size of the electronic receiving device as compared with the case where the electronic component built-in substrate is not used.

  The electronic component built-in substrate according to the present invention, the electronic device using the same, and the method for manufacturing the same can produce the electronic component built-in substrate in which the semiconductor bare chip IC is built in the substrate in a simple process. Since the connection reliability of electronic components can be improved, it can be used, for example, in the manufacture of an ultra-small three-dimensional mounting module.

(a) (b) is sectional drawing of the electronic component built-in board | substrate in Embodiment 1 of this invention. (a) (b) is sectional drawing of the electronic component built-in board | substrate in Embodiment 1 of this invention. (a) (b) is sectional drawing of the electronic component built-in board | substrate in Embodiment 7 of this invention. (a) (b) is sectional drawing of the electronic component built-in board | substrate in Embodiment 7 of this invention. (a) (b) is sectional drawing of the electronic component built-in board | substrate in Embodiment 8 of this invention. (a) (b) is sectional drawing of the electronic component built-in board | substrate in Embodiment 8 of this invention. (a) (b) is sectional drawing of the electronic component built-in board | substrate in Embodiment 8 of this invention. (a) (b) is sectional drawing of the electronic component built-in board | substrate in Embodiment 8 of this invention. (a)-(f) is manufacturing process sectional drawing of the electronic circuit device in Embodiment 1 of this invention. (a)-(h) is manufacturing process sectional drawing of the electronic circuit device in Embodiment 2 of this invention. (a)-(h) is manufacturing process sectional drawing of the electronic circuit device in Embodiment 3 of this invention. (a)-(g) is manufacturing process sectional drawing of the electronic circuit device in Embodiment 4 of this invention. (a)-(f) is manufacturing process sectional drawing of the electronic circuit device in Embodiment 5 of this invention. (a)-(h) is manufacturing process sectional drawing of the electronic circuit device in Embodiment 6 of this invention. (a)-(g) is manufacturing process sectional drawing of the electronic circuit device in Embodiment 7 of this invention. (a)-(g) is manufacturing process sectional drawing of the electronic circuit device in Embodiment 8 of this invention. (a) (b) is sectional drawing of the electronic device in Embodiment 9 of this invention Sectional view of a conventional electronic component built-in substrate

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 1st wiring layer 102 1st electroconductive pattern 103 1st space | gap 104 2nd wiring layer 105 Electronic component 106 2nd electroconductive pattern 107 Thermosetting resin 108 Adhesive layer 110 Bump 111 Mounting auxiliary material 113 Inner via | veer 115 3rd electroconductivity Pattern 116 Fourth conductive pattern 118 Bump

Claims (25)

A first wiring layer;
An electronic component mounted on the upper surface of the first wiring layer;
A second wiring layer electrically connected to the first wiring layer via a bump on the first wiring layer;
An adhesive layer disposed between the first wiring layer and the second wiring layer and penetrated by the bump;
The adhesive layer is made of a fiber material and an insulating resin included in the fiber material,
The fiber material has a first gap larger than the size of the electronic component, and the electronic component-embedded substrate in which the electronic component is disposed in the first gap. The adhesive layer has a third wiring layer as an inner layer of the adhesive layer,
The first wiring layer and the third wiring layer are electrically connected via bumps, and the second wiring layer and the third wiring layer are electrically connected via bumps. The electronic component built-in substrate described. 3. The electronic component built-in substrate according to claim 1, wherein the second wiring layer has a through hole penetrating between an upper surface of the second wiring layer and the first gap. 4. The electronic device according to claim 1, further comprising a second electronic component mounted on the upper surface of the first wiring layer or the lower surface of the second wiring layer and disposed in the first gap. Electronic component built-in substrate. The electronic component built-in substrate according to claim 1, wherein the insulating resin is filled in the first gap between the fiber material and the electronic component. The electronic component built-in substrate according to claim 1, wherein a gas is filled in the first gap between the fiber material and the electronic component. 5. The electronic component built-in substrate according to claim 1, wherein the bump includes a metal bump using a metal wire and / or a plating bump formed by metal plating. The electronic component built-in substrate according to any one of claims 1 to 7,
An electronic device on which a display device connected to the electronic component built-in substrate is mounted. Mounting an electronic component on the first wiring layer;
Forming bumps on the first wiring layer and / or the second wiring layer;
Preparing an adhesive layer comprising a fiber material and an insulating resin included in the fiber material and having a first gap larger than the mounting area of the electronic component and a second gap larger than the bump formation area;
Stacking the adhesive layer and the second wiring layer at desired positions on the first wiring layer in order so that the bumps are inside the first wiring layer and the second wiring layer;
The first wiring layer, the adhesive layer, and the second wiring layer are pressed and integrated while being heated, and the first wiring layer and the second wiring layer are electrically connected through the bumps. A method of manufacturing an electronic component built-in substrate comprising the steps. The method for manufacturing a substrate with built-in electronic components according to claim 9, wherein the second wiring layer has a through hole penetrating between an upper surface of the second wiring layer and the first gap. 11. The electronic component-embedded substrate according to claim 9, further comprising a second electronic component mounted on the upper surface of the first wiring layer or the lower surface of the second wiring layer and disposed in the first gap. Production method. The manufacturing of the electronic component built-in substrate according to any one of claims 9 to 11, wherein the insulating resin is filled in the first gap and the second gap between the fiber material and the electronic component. Method. The manufacturing method of the electronic component built-in substrate according to any one of claims 9 to 11, wherein the first gap between the fiber material and the electronic component is filled with gas. The method for manufacturing a substrate with built-in electronic components according to claim 9, wherein the bumps are metal bumps using metal wires and / or plated bumps by metal plating. The method for manufacturing a substrate with a built-in electronic component according to any one of claims 9 to 11, wherein the bump is formed by forming a metal bump using a metal wire on a plating bump formed by metal plating. The method for manufacturing a substrate with built-in electronic components according to claim 9, wherein the first gap and the second gap formed in the adhesive layer are a single integrated gap. The method for manufacturing an electronic component built-in substrate according to claim 9, wherein an anisotropic conductive film is disposed in an inner layer of the adhesive layer. Mounting an electronic component on the first wiring layer;
Forming a first bump on a third wiring layer having a space larger than a mounting area of the first wiring layer and / or the electronic component;
Forming a second bump on the second wiring layer and / or the third wiring layer;
A first adhesive comprising a fiber material and an insulating resin included in the fiber material and having a first gap larger than the mounting area of the electronic component and a second gap larger than the formation area of the first bump or the second bump. Preparing a layer and a second adhesive layer;
The first adhesive layer, the third wiring layer, the second adhesive layer, and the second wiring layer are placed at desired positions on the first wiring layer after the electronic component is mounted. Stacking in order such that the second bump is inside the third wiring layer and the third wiring layer, and the second bump is inside the third wiring layer and the second wiring layer;
The first wiring layer, the first adhesive layer, the third wiring layer, the second adhesive layer, and the second wiring layer are pressed and integrated while being heated, and the first wiring layer and the third wiring layer are integrated. A method of manufacturing an electronic component built-in substrate, comprising: electrically connecting a wiring layer and the second wiring layer via the first bump and the second bump. The method for manufacturing a substrate with built-in electronic components according to claim 18, wherein the second wiring layer has a through hole penetrating between an upper surface of the second wiring layer and the first gap. 20. The electronic component according to claim 18, further comprising a second electronic component mounted on the upper surface of the first wiring layer or the lower surface of the second wiring layer and disposed in the first gap and the space. A method for manufacturing a built-in substrate. The electronic component built-in according to any one of claims 18 to 20, wherein the insulating resin is filled in the first gap, the second gap, and the space between the fiber material and the electronic component. A method for manufacturing a substrate. The method for manufacturing an electronic component built-in substrate according to any one of claims 18 to 20, wherein the first gap and the space between the fiber material and the electronic component are filled with gas. 21. The method for manufacturing an electronic component built-in substrate according to claim 18, wherein the first bump and the second bump are a metal bump using a metal wire and / or a plating bump by metal plating. 21. The method of manufacturing an electronic component built-in substrate according to claim 18, wherein the first bump and the second bump are formed by forming a metal bump using a metal wire on a plating bump formed by metal plating. The electronic component according to any one of claims 18 to 24, wherein the first gap and the second gap formed in the first adhesive layer and the second adhesive layer are a single gap, respectively. A method for manufacturing a built-in substrate.

Images