TW202109489A - Pixel array substrate - Google Patents

Abstract

A pixel array substrate includes a first-stage scan line to an nth-stage scan line extending in a first direction, a first-stage transmission line to an nth-stage transmission line extending in a second direction, data lines and sub-pixels, where n is an integer greater than 3. The first-stage transmission line to the nth-stage transmission line are electrically connected to the first-stage scan line to the nth-stage scan line, respectively. The first, second, and third sub-pixels are electrically connected to the third-stage scan line. The capacitance between the drain and gate of the first switching element of the first sub-pixel is Cgd1. The capacitance between the drain and gate of the second switching element of the second sub-pixel is Cgd2. The capacitance between the drain and gate of the third switching element of the third sub-pixel is Cgd3. Cgd2 is greater than Cgd3, and Cgd3 is greater than Cgd1.

Description

Pixel array substrate

The present invention relates to a pixel array substrate, and more particularly to a pixel array substrate including scan lines and data lines.

Since the display panel has the advantages of small size and low radiation, the display panel has been widely used in various electronic products. In the existing display panel, a large area of the driving circuit area is usually reserved at the periphery of the display area to install the driving circuit, and the sub-pixels are controlled by the driving circuit. However, the driving circuit area located outside the display area makes the display panel have a very wide frame and limits the screen-to-body ratio of the product. With the advancement of technology, consumers have higher and higher requirements for the appearance of display panels. In order to increase consumers' willingness to buy, how to increase the screen ratio of display panels has become one of the problems that manufacturers want to solve.

Some manufacturers concentrate the driving circuits in the display panel on the same side of the display area, thereby reducing the area of the driving circuit area. However, the aforementioned method requires a wire transfer structure in the display area to adjust the signal transmission path. These line transfer structures easily make the voltage distribution of the sub-pixels uneven, leading to the problem of uneven brightness of the picture.

The present invention provides a pixel array substrate, which can solve the problem of uneven brightness of a display screen.

At least one embodiment of the present invention provides a pixel array substrate including multiple scan lines, multiple transmission lines, multiple data lines, and multiple sub-pixels. The scan line, the transmission line and the data line are located on the substrate. The scan lines of level 1 to level n extend along the first direction, where n is an integer greater than 3. The first-level transmission lines to the n-th level transmission lines extend along the second direction and are electrically connected to the first-level scan lines to the n-th level scan lines, respectively. The data line extends along the second direction. Each sub-pixel is electrically connected to a corresponding scan line and a corresponding data line. The first sub-pixel overlaps the third-level transmission line. The first switching element of the first sub-pixel is electrically connected to the third level scan line, and the capacitance between the drain of the first switching element and the gate of the first switching element is Cgd1. The second sub-pixel overlaps the 3+x level transmission line, where x is an integer less than 3. The second switching element of the second sub-pixel is electrically connected to the third-level scan line, and the capacitance between the drain of the second switching element and the gate of the second switching element is Cgd2. The third sub-pixel overlaps the 3-x level transmission line. The third switching element of the third sub-pixel is electrically connected to the third-level scan line. The capacitance between the drain of the third switching element and the gate of the third switching element is Cgd3. Cgd2 is greater than Cgd3 and Cgd1.

At least one embodiment of the present invention provides a pixel array substrate, including a substrate, a driving circuit, a plurality of scan lines, a plurality of transmission lines, a plurality of data lines, a first sub-pixel, and a second sub-pixel. The scan lines are located on the substrate and include the first level scan lines to the nth level scan lines. The scan lines of level 1 to level n extend along the first direction, where n is an integer greater than 3. The transmission line is located on the substrate and includes the first level transmission line to the nth level transmission line. The first level transmission line to the nth level transmission line extend along the second direction, and the first level transmission line to the nth level transmission line are electrically connected to the driving circuit to the first level scan line to the nth level scan line, respectively. One of the first level transmission line to the nth level transmission line is electrically connected to one of the first level scan line to the nth level scan line, and the driving circuit and the first level scan line to the nth level scan line The length of one of the level 1 transmission line to the n level transmission line between one of them is Y1. The other one of the first level transmission line to the nth level transmission line is electrically connected to the other one of the first level scan line to the nth level scan line, and the driving circuit and the first level scan line to the nth level The length of the other one of the first level transmission line to the nth level transmission line between the other one of the scan lines is Y2, wherein the length Y2 is greater than the length Y1. The data line is located on the substrate and extends along the second direction. The first sub-pixel includes a first switching element and a first pixel electrode electrically connected to the first switching element. The first switching element is electrically connected to one of the first-level transmission line to the n-th level transmission line, and the overlap area of the drain and gate of the first switching element is A1, and the gate of the first switching element and the first The overlapping area of the pixel electrode is B1. The second sub-pixel includes a second switching element and a second pixel electrode electrically connected to the second switching element. The second switching element is electrically connected to the other one of the first transmission line to the nth transmission line, and the overlap area of the drain and the gate of the second switching element is A2, and the gate of the second switching element is The overlapping area of the second pixel electrode is B2. Area A1>area A2, and/or area B1>area B2.

Throughout the specification, the same reference numerals indicate the same or similar elements. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to another element," it can be directly on or connected to another element, or There may be other elements between the element and the other element. In contrast, when an element is referred to as being "directly on another element" or "directly connected to another element", there are no other elements between the element and the other element. As used herein, "connection" can refer to physical and/or electrical connection. Furthermore, two elements are "electrically connected" or "coupled" to each other because there are other elements between the two elements.

It should be understood that although the terms "first" and "second" etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or parts should not be affected by Limitations of these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section.

FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the invention. FIG. 1 illustrates the substrate, scan lines, data lines, transmission lines, and driving circuits of the pixel array substrate, and other components are omitted.

Please refer to FIG. 1, the pixel array substrate 10 includes a substrate SB, a scan line SL, a data line DL, a transmission line TL, and a driving circuit DC. The scan line SL, the data line DL, the transmission line TL, and the driving circuit DC are located on the substrate SB.

The substrate SB has a display area AA and a peripheral area BA located outside the display area AA. The driving circuit DC is provided in the peripheral area BA. The scan line SL is located in the display area AA and extends along the first direction DR1. The data line DL and the transmission line TL extend along the second direction DR2, and extend from the driving circuit DC into the display area AA. Each transmission line TL is electrically connected to a corresponding scan line SL. In this embodiment, the transmission line TL is electrically connected to the corresponding scan line SL through the switching structure CS.

2 is a schematic top view of a display area of a pixel array substrate according to an embodiment of the invention. For example, FIG. 2 is a partial enlarged schematic diagram of the display area AA of the pixel array substrate 10 of FIG. 1.

Please refer to FIG. 2, the pixel array substrate includes multiple scan lines, multiple transmission lines, multiple data lines, and multiple sub-pixels. In this embodiment, the pixel array substrate further includes common signal lines CL1 and CL2 extending along the first direction DR1 and common signal lines CL3 extending along the second direction DR2.

The scan lines include the first level scan line SL1 to the nth level scan line SLn, where n is an integer greater than 3. In FIG. 2, only the first level scan line SL1 to the fifth level scan line SL5 are drawn, but the present invention is not limited to this. The number of scan lines can be adjusted according to requirements. In this embodiment, the first level scan line SL1 to the nth level scan line SLn and the common signal lines CL1 and CL2 belong to the same conductive layer (for example, the first conductive layer).

The transmission line includes a first-level transmission line TL1 to an n-th level transmission line TLn. In FIG. 2, only the first-level transmission line TL1 to the fifth-level transmission line TL5 are drawn, but the present invention is not limited to this. The number of transmission lines can be adjusted according to requirements. The first level transmission line TL1 to the nth level transmission line TLn are electrically connected to the first level scan line SL1 to the nth level scan line SLn, respectively. For example, the first-level transmission line TL1 is electrically connected to the first-level scan line SL1, the second-level transmission line TL2 is electrically connected to the second-level scan line SL2, and the third-level transmission line TL3 is electrically connected to the third-level scan line SL3, other transmission lines and scan lines are electrically connected in a similar manner. In this embodiment, the first level transmission line TL1 to the nth level transmission line TLn, the data line DL, and the common signal line CL3 belong to the same conductive layer (for example, the second conductive layer). An insulating layer is sandwiched between the first conductive layer and the second conductive layer, and the switching structure CS penetrates the aforementioned insulating layer.

Each sub-pixel is electrically connected to a corresponding scan line and a corresponding data line. FIG. 2 is used to illustrate the positional relationship of different sub-pixels, and the structure of the sub-pixels can refer to the embodiments in FIG. 4A to FIG. 4F.

Please continue to refer to FIG. 2. In this embodiment, the component symbol A marks the sub-pixels overlapping the transmission line of the corresponding class. For example, the sub-pixels that are electrically connected to the third level scan line SL3 and overlap the third level transmission line TL3 are marked by the component symbol A, and are electrically connected to the fourth level scan line SL4 and overlap the fourth level transmission line The sub-pixels of TL4 are marked by component symbol A, and the sub-pixels marked by other component symbols A can be deduced by analogy.

In this embodiment, the component symbol B marks the sub-pixels superimposed on the post-stage transmission line. For example, the sub-pixels that are electrically connected to the third level scan line SL3 and overlap the fourth level transmission line TL4 are marked by the component symbol B, and are electrically connected to the fourth level scan line SL4 and overlap the fifth level transmission line The sub-pixels of TL4 are marked by component symbol B, and the sub-pixels marked by other component symbols B can be deduced by analogy.

In this embodiment, the component symbol C marks the sub-pixels overlapping the transmission lines of the latter two stages. For example, the sub-pixels that are electrically connected to the level 3 scan line SL3 and overlap the level 5 transmission line TL5 are marked by the component symbol C, and are electrically connected to the level 4 scan line SL4 and overlap the level 6 transmission line The sub-pixels of TL6 are marked by component symbol C, and the sub-pixels marked by other component symbols C can be deduced by analogy.

In this embodiment, the component symbol D marks the sub-pixels superimposed on the pre-stage transmission line. For example, the sub-pixels that are electrically connected to the third-level scan line SL3 and overlap the second-level transmission line TL2 are marked by the component symbol D, and are electrically connected to the fourth-level scan line SL4 and overlap the third-level transmission line The sub-pixels of TL3 are marked by the component symbol D, and the sub-pixels marked by other component symbols D can be deduced by analogy.

In this embodiment, the component symbol E marks the sub-pixels overlapping the transmission lines of the first two levels. For example, the sub-pixels that are electrically connected to the third level scan line SL3 and overlap the first level transmission line TL1 are marked by the element symbol E, are electrically connected to the fourth level scan line SL4 and overlap the second level transmission line The sub-pixels of TL2 are marked by the component symbol E, and the sub-pixels marked by other component symbols E are deduced by analogy.

3 is a waveform diagram of scan line signals of a pixel array substrate according to an embodiment of the present invention.

2 and 3, in this embodiment, the sub-pixels are precharged so that the sub-pixels can reach a predetermined voltage instantly. The charging time of each scan line will partially overlap the charging time of the previous scan line and the charging time of the subsequent scan line. For example, the charging time t3 of the third level scan line SL3 partially overlaps the charging time of the 3+x level scan line SL3+x and the charge time of the 3-x level scan line SL3-x, where x is less than 3. Integer. In this embodiment, the charging time t3 of the third-level scan line SL3 partially overlaps the charging time t1 of the first-level scan line SL1, the charging time t2 of the second-level scan line SL2, and the charging time of the fourth-level scan line SL4. t4 and the charging time t5 of the fifth-level scan line SL5. In this embodiment, the charging time of the scan lines of each level does not overlap with the charging time of the scan lines of more than 3 levels. For example, the charging time t3 of the scan line SL3 at the third level does not overlap with the charging time t6 of the scan line SL6 at the sixth level.

The pre-charging time of each scan line can be adjusted according to requirements. In other words, how many scan lines overlap each other with the charging time can be adjusted according to requirements.

In this embodiment, multiple sub-pixels electrically connected to the same scan line overlap different transmission lines, and the signals on different transmission lines are different from each other. Therefore, different sub-pixels may have uneven brightness distribution. The problem. In some embodiments, sub-pixel A, sub-pixel B, sub-pixel C, sub-pixel D, and sub-pixel E have a compensation design, thereby reducing the problem of uneven brightness distribution. For related designs, please refer to subsequent implementations. Example description.

In this embodiment, the sub-pixels that do not have a compensation design are marked by the component symbol N. In some embodiments, the level of the transmission line overlapped by the standard sub-pixel N is quite different from the transmission line of the corresponding level. For example, the sub-pixels that are electrically connected to the first-level scan line SL1 and overlap the fourth-level scan line SL4 can be marked by the element symbol N. In some embodiments, the standard sub-pixel N overlaps the common signal line CL3 instead of the transmission line.

4A to 4F are schematic top views of different sub-pixels according to an embodiment of the present invention. Fig. 5 is a schematic cross-sectional view taken along the line aa' of Fig. 4A.

2, 4A and 5, the standard sub-pixel N includes a standard switching element T and a pixel electrode PE, and the standard switching element T includes a gate GE, a channel layer CH, a source SE, and a drain DE.

The gate electrode GE is located on the substrate SB and is electrically connected to the corresponding scan line. In this embodiment, it is taken as an example that the gate electrode GE is electrically connected to the third-level scan line SL3. The channel layer CH overlaps the gate electrode GE, and a gate insulating layer GI is sandwiched between the channel layer CH and the gate electrode GE.

The source SE and the drain DE are electrically connected to the channel layer CH, and the source SE is electrically connected to the data line DL. The capacitance between the drain DE of the standard switching element T and the gate GE of the standard switching element T (or the third-level scan line SL1) is Cgd0. The insulating layer PL is disposed on the source SE and the drain DE. In some embodiments, the insulating layer PL is a color filter layer and constitutes a color filter on array (COA) structure, but the invention is not limited to this. In other embodiments, the color filter layer is disposed on other substrates.

The insulating layer U is disposed on the insulating layer PL, and the insulating layer U is, for example, an organic material or an inorganic material. The pixel electrode PE is disposed on the insulating layer U, and is electrically connected to the drain electrode DE through the opening O penetrating the insulating layer U and the insulating layer PL.

Although in this embodiment, in the schematic top view, the opening area of each sub-pixel is located above the corresponding scan line, the present invention is not limited to this. In other embodiments, by adjusting the extension direction of the pixel electrode PE, the opening area of each sub-pixel is located below the corresponding scan line.

The standard sub-pixel N overlaps the common signal line CL3 and/or the m-th level transmission line TLm, and the third-level scan line SL3 in the standard sub-pixel N also overlaps the common signal line CL3 and/or the m-th level transmission line TLm. 1<m<n. In this embodiment, the charging time of the m-th level transmission line TLm (or the m-th level scan line) does not overlap with the charging time of the third level scan line SL3.

Please refer to FIGS. 4A and 4B. The sub-pixel A in FIG. 4B has a similar structure to the standard sub-pixel N in FIG. 4A. The difference is that the sub-pixel A overlaps the third-level transmission line TL3, and the drain of the sub-pixel A is The length L1 of the pole DE overlapping the gate GE is smaller than the length L of the drain DE of the standard switching element T of the standard sub-pixel N overlapping the gate GE.

In this embodiment, the gate GE of the switching element T1 of the sub-pixel A is electrically connected to the third level scan line SL3, and the drain DE of the switching element T1 and the gate GE of the switching element T1 (or the third level The capacitance between the scan lines SL3) is Cgd1.

In this embodiment, the length L1 that the drain DE of the switching element T1 overlaps the gate GE is smaller than the length L that the drain DE of the standard switching element T overlaps the gate GE, so that the drain DE of the switching element T1 and the gate GE The overlap area between GE is smaller than the overlap area between the drain DE and the gate GE of the standard switching element T. Therefore, the capacitance Cgd1 of the switching element T1 is smaller than the capacitance Cgd0 of the standard switching element T.

In addition to the capacitance Cgd1 between the drain DE of the switching element T1 and the gate GE of the sub-pixel A, a capacitance Cvg1 is also generated between the pixel electrode PE of the sub-pixel A and the third-level transmission line TL3. However, the pixel electrode PE of the standard sub-pixel N is not overlapped with the third-level transmission line TL3, which causes the problem of brightness inconsistency between the sub-pixel A and the standard sub-pixel N. In this embodiment, by making the capacitance Cgd1 of the switching element T1 smaller than the capacitance Cgd0 of the standard switching element T, the aforementioned problem of inconsistency in brightness can be improved.

6 is a waveform diagram of scan line signals and pixel electrode signals of a pixel array substrate according to an embodiment of the present invention.

Please refer to FIG. 4A, FIG. 4B and FIG. 6, the sub-pixel A and the standard sub-pixel N are electrically connected to the third-level scan line SL3. In this embodiment, the sub-pixel A overlaps the third-level transmission line TL3, and the standard sub-pixel N overlaps the m-th level transmission line TLm, where 1<m<n.

The m-th level transmission line TLm is electrically connected to the m-th level scan line SLm, and the charging time of the m-th level scan line SLm does not overlap the charging time of the third level transmission line TL3.

In FIG. 6, the pixel electrode PE of the sub-pixel A has a voltage P(A), and the pixel electrode PE of the standard sub-pixel N has a voltage P(N). When the third-level scan line SL3 is activated, the pixel electrode PE of the sub-pixel A and the pixel electrode PE of the standard sub-pixel N start to be charged. When the third level scanning line SL3 is turned off (in the time range x), the voltage on the pixel electrode PE of the sub-pixel A and the voltage on the pixel electrode PE of the standard sub-pixel N will drop.

When the compensation design is not applied to the sub-pixel A (that is, before compensation), the voltage drop of the pixel electrode PE of the sub-pixel A will be different from the voltage drop of the pixel electrode PE of the standard sub-pixel N , So that the voltage P(A) and the voltage P(N) are different from each other in the subsequent voltage holding time (holding time), which easily leads to the problem of uneven brightness distribution of the display panel.

When the compensation design is applied to the sub-pixel A (that is, after compensation), since the capacitance Cgd1 of the sub-pixel A is smaller than the capacitance Cgd0 of the standard sub-pixel N, the pixel electrode PE of the sub-pixel A is turning off the third level scanning When line SL3 (in the time range x), the voltage drop can be close to the voltage drop of the pixel electrode PE of the standard sub-pixel N, so that the voltage P(A) and the voltage P(N) remain at the subsequent voltages The holding time is similar to each other, thereby improving the problem of uneven brightness distribution of the display panel.

Please refer to FIGS. 4A and 4C. The sub-pixel D in FIG. 4C has a similar structure to the standard sub-pixel N in FIG. 4A. The difference is that the sub-pixel D overlaps the 3-y-level transmission line TL3-y, and the sub-pixel D overlaps the transmission line TL3-y. The length L5 of the drain DE of the element D overlapping the gate GE is less than the length L of the drain DE of the standard sub-pixel N overlapping the gate GE. In this embodiment, y is equal to 1, and the sub-pixel D overlaps the second-level transmission line TL2.

In this embodiment, the gate GE of the switching element T5 of the sub-pixel D is electrically connected to the third level scan line SL3, and the drain DE of the switching element T5 and the gate GE of the switching element T5 (or the third level The capacitance between the scan lines SL3) is Cgd5.

The length L5 of the drain DE of the switching element T5 that overlaps the gate GE is smaller than the length L of the drain DE of the standard switching element T that overlaps the gate GE, so that the overlap area between the drain DE of the switching element T5 and the gate GE is It is smaller than the overlap area between the drain DE and the gate GE of the standard switching element T. Therefore, the capacitance Cgd5 of the switching element T5 is smaller than the capacitance Cgd0 of the standard switching element T.

In addition to the capacitance Cgd5 between the drain DE of the switching element T5 and the gate GE of the sub-pixel D, a capacitance Cvg2 is also generated between the pixel electrode PE of the sub-pixel D and the second-level transmission line TL2. However, the pixel electrode PE of the standard sub-pixel N is not overlapped with the second-level transmission line TL2, resulting in the problem of brightness inconsistency between the sub-pixel D and the standard sub-pixel N. In this embodiment, by making the capacitance Cgd5 of the switching element T5 smaller than the capacitance Cgd0 of the standard switching element T, the aforementioned problem of inconsistency in brightness can be improved.

4B and 4C, the length L1 of the drain DE of the switching element T1 overlapping the gate GE is smaller than the length L5 of the drain DE of the switching element T5 overlapping the gate GE, so that the drain DE of the switching element T1 and the gate GE The overlap area between the poles GE is smaller than the overlap area between the drain DE and the gate GE of the switching element T5. Therefore, the capacitance Cgd1 of the switching element T1 is smaller than the capacitance Cgd5 of the switching element T5.

Please refer to FIGS. 4A and 4D. The sub-pixel E in FIG. 4D has a similar structure to the standard sub-pixel N in FIG. 4A. The difference is that the sub-pixel E overlaps the 3-x-level transmission line TL3-x, and the sub-pixel E overlaps the transmission line TL3-x. The length L3 of the drain DE of the element E overlapping the gate GE is smaller than the length L of the drain DE of the standard sub-pixel N overlapping the gate GE. In this embodiment, x is equal to 2, and the sub-pixel E overlaps the first-level transmission line TL1.

In this embodiment, the gate GE of the switching element T3 of the sub-pixel E is electrically connected to the third level scan line SL3, and the drain DE of the switching element T3 and the gate GE of the switching element T3 (or the third level The capacitance between the scan lines SL3) is Cgd3.

The length L3 of the drain DE of the switching element T3 that overlaps the gate GE is smaller than the length L of the drain DE of the standard switching element T that overlaps the gate GE, so that the overlap area between the drain DE of the switching element T3 and the gate GE is It is smaller than the overlap area between the drain DE and the gate GE of the standard switching element T. Therefore, the capacitance Cgd3 of the switching element T3 is smaller than the capacitance Cgd0 of the standard switching element T.

In addition to the capacitance Cgd3 between the drain DE of the switching element T3 and the gate GE of the sub-pixel E, a capacitance Cvg3 is also generated between the pixel electrode PE of the sub-pixel E and the first-level transmission line TL1. However, the pixel electrode PE of the standard sub-pixel N is not overlapped with the first-level transmission line TL1, which leads to the problem of brightness inconsistency between the sub-pixel E and the standard sub-pixel N. In this embodiment, by making the capacitance Cgd3 of the switching element T3 smaller than the capacitance Cgd0 of the standard switching element T, the aforementioned problem of inconsistent brightness can be improved.

4C and 4D, the length L5 of the drain DE of the switching element T5 overlapping the gate GE is less than the length L3 of the drain DE of the switching element T3 overlapping the gate GE, so that the drain DE of the switching element T5 and the gate The overlap area between the poles GE is smaller than the overlap area between the drain DE and the gate GE of the switching element T3. Therefore, the capacitance Cgd5 of the switching element T5 is smaller than the capacitance Cgd3 of the switching element T3.

Please refer to FIGS. 4A and 4E. The sub-pixel B in FIG. 4E has a similar structure to the standard sub-pixel N in FIG. 4A. The difference is that the sub-pixel B overlaps the 3+y-level transmission line TL3+y, and the sub-pixel The length L6 of the drain DE of the switching element T6 of the element B overlapping the gate GE is smaller than the length L of the drain DE of the standard switching element T of the standard sub-pixel N overlapping the gate GE. In this embodiment, y is equal to 1, and the sub-pixel B overlaps the fourth-level transmission line TL4.

In this embodiment, the gate GE of the switching element T6 of the sub-pixel B is electrically connected to the third level scan line SL3, and the drain DE of the switching element T6 and the gate GE of the switching element T6 (or the third level The capacitance between the scan lines SL3) is Cgd6.

The length L6 of the drain DE of the switching element T6 that overlaps the gate GE is smaller than the length L of the drain DE of the standard switching element T that overlaps the gate GE, so that the overlap area between the drain DE of the switching element T6 and the gate GE is It is smaller than the overlap area between the drain DE and the gate GE of the standard switching element T. Therefore, the capacitance Cgd6 of the switching element T6 is smaller than the capacitance Cgd0 of the standard switching element T.

In addition to the capacitance Cgd6 between the drain DE of the switching element T6 and the gate GE of the sub-pixel B, a capacitance Cvg4 is also generated between the pixel electrode PE of the sub-pixel B and the fourth-level transmission line TL4. However, the pixel electrode PE of the standard sub-pixel N does not overlap the fourth-level transmission line TL4, which causes the problem of brightness inconsistency between the sub-pixel B and the standard sub-pixel N. In this embodiment, by making the capacitance Cgd6 of the switching element T6 smaller than the capacitance Cgd0 of the standard switching element T, the aforementioned problem of inconsistent brightness can be improved.

4D and 4E, the length L3 of the drain DE of the switching element T3 is less than the length L6 of the drain DE of the switching element T6, so that the overlap area between the drain DE of the switching element T3 and the gate GE is smaller than that of the switching element T6 The overlap area between the drain DE and the gate GE. Therefore, the capacitance Cgd3 of the switching element T3 is smaller than the capacitance Cgd6 of the switching element T6.

Please refer to FIGS. 4A and 4F. The sub-pixel C in FIG. 4F has a similar structure to the standard sub-pixel N in FIG. 4A. The difference is that the sub-pixel C overlaps the 3+x-level transmission line TL3+x, and the sub-pixel C overlaps the transmission line TL3+x. The length L2 of the drain DE of the switching element T2 of the element C overlapping the gate GE is smaller than the length L of the drain DE of the standard switching element T of the standard sub-pixel N overlapping the gate GE. In this embodiment, x is equal to 2, and the sub-pixel C overlaps the fifth-level transmission line TL5.

In this embodiment, the gate GE of the switching element T2 of the sub-pixel C is electrically connected to the third level scan line SL3, and the drain DE of the switching element T2 and the gate GE of the switching element T2 (or the third level The capacitance between the scan lines SL3) is Cgd2.

The length L2 that the drain DE of the switching element T2 overlaps the gate GE is smaller than the length L that the drain DE of the standard switching element T overlaps the gate GE, so that the overlap area between the drain DE and the gate GE of the switching element T2 It is smaller than the overlap area between the drain DE and the gate GE of the standard switching element T. Therefore, the capacitance Cgd2 of the switching element T2 is smaller than the capacitance Cgd0 of the standard switching element T.

In addition to the capacitance Cgd2 between the drain DE of the switching element T2 and the gate GE of the sub-pixel C, a capacitance Cvg2 is also generated between the pixel electrode PE of the sub-pixel C and the fifth-level transmission line TL5. However, the pixel electrode PE of the standard sub-pixel N does not overlap the fifth-level transmission line TL5, which causes the problem of brightness inconsistency between the sub-pixel C and the standard sub-pixel N. In this embodiment, by making the capacitance Cgd2 of the switching element T2 smaller than the capacitance Cgd0 of the standard switching element T, the aforementioned problem of inconsistent brightness can be improved.

4E and 4F, the length L6 of the drain DE of the switching element T6 overlapping the gate GE is less than the length L2 of the drain DE of the switching element T2 overlapping the gate GE, so that the drain DE of the switching element T6 and the gate The overlap area between the poles GE is smaller than the overlap area between the drain DE and the gate GE of the switching element T2. Therefore, the capacitance Cgd3 of the switching element T6 is smaller than the capacitance Cgd2 of the switching element T2.

In this embodiment, the length L1 is less than the length L5, and the length L3 is less than the length L6, and the length L2 is less than the length L. The difference between the length L1 and the length L is between 0.5 μm and 1 μm. The difference between the length L1 and the length L2 is between 0.5 μm and 1 μm.

The capacitance Cgd1 of the sub-pixel A is smaller than the capacitance Cgd5 of the sub-pixel D and the capacitance Cgd3 of the sub-pixel E is smaller than the capacitance Cgd6 of the sub-pixel B is smaller than the capacitance Cgd2 of the sub-pixel C, thereby reducing the capacitance distribution of the pixel array substrate The problem of unevenness.

In some embodiments, the overlapping area between the pixel electrode of the sub-pixel and the overlapping transmission line is the same, so the capacitor Cvg1, the capacitor Cvg2, the capacitor Cvg3, the capacitor Cvg4, and the capacitor Cvg5 are approximately the same as each other.

7A and 7B are schematic top views of different sub-pixels according to an embodiment of the present invention. It must be noted here that the embodiments of FIGS. 7A and 7B follow the element numbers and part of the content of the embodiments of FIGS. 4A to 4F, wherein the same or similar numbers are used to denote the same or similar elements, and the same elements are omitted. Description of technical content. For the description of the omitted parts, reference may be made to the foregoing embodiment, which will not be repeated here.

Referring to FIGS. 7A and 7B, in this embodiment, the standard switching element T of the standard sub-pixel N and the first switching element T1 of the first sub-pixel A are electrically connected to the third-level scan line SL3. The first sub-pixel A overlaps the third-level transmission line TL3, and the standard sub-pixel N overlaps the m-th level transmission line TLm, where 1<m<n. The charging time of the scan line SLm of the mth level does not overlap the charging time of the scan line SL3 of the third level.

In this embodiment, the width W1 of the drain DE of the standard switching element T is greater than the width W2 of the drain DE of the first switching element T1. In this way, the capacitance Cgd1 of the switching element T1 is smaller than the capacitance Cgd0 of the standard switching element T, and the problem of inconsistent brightness of the display panel is improved.

8A and 8B are schematic top views of different sub-pixels according to an embodiment of the present invention. It must be noted here that the embodiments of FIGS. 8A and 8B follow the element numbers and part of the content of the embodiments of FIGS. 4A to 4F, wherein the same or similar numbers are used to denote the same or similar elements, and the same elements are omitted. Description of technical content. For the description of the omitted parts, reference may be made to the foregoing embodiment, which will not be repeated here.

8A and 8B, in this embodiment, the standard switching element T of the standard sub-pixel N and the first switching element T1 of the first sub-pixel A are electrically connected to the third-level scan line SL3. The first sub-pixel A overlaps the third-level transmission line TL3, and the standard sub-pixel N overlaps the m-th level transmission line TLm, where 1<m<n. The charging time of the scan line SLm of the mth level does not overlap the charging time of the scan line SL3 of the third level.

In this embodiment, the area where the pixel electrode PE of the first sub-pixel A overlaps the gate GE of the first switching element T1 is smaller than the pixel electrode PE of the standard sub-pixel N overlaps the gate of the standard switching element T The area of GE. For example, the pixel electrode PE has an extension EP overlapping the gate GE, and the area of the extension EP of the standard sub-pixel N is larger than the area of the extension EP of the first sub-pixel A.

In some embodiments, the pixel electrode PE of the standard sub-pixel N overlaps the gate of the standard switching element T, and the pixel electrode PE of the first sub-pixel A does not overlap the gate GE of the first switching element T1 . For example, the pixel electrode PE of the first sub-pixel A does not have the extension EP.

By adjusting the area of the pixel electrode PE, the capacitance Cgd1 of the switching element T1 is smaller than the capacitance Cgd0 of the standard switching element T, and the problem of inconsistent brightness of the display panel is improved.

FIG. 9 is a schematic top view of a display area of a pixel array substrate according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 9 uses the element numbers and part of the content of the embodiment of FIGS. 4A to 4F, wherein the same or similar reference numbers are used to represent the same or similar elements, and the same technical content is omitted. Description. For the description of the omitted parts, reference may be made to the foregoing embodiment, which will not be repeated here.

Please refer to FIG. 9, in this embodiment, the pixel array substrate 20 further includes a sub-pixel F. The sub-pixel F overlaps both of the transmission lines. For example, in this embodiment, part of the sub-pixels F electrically connected to the third-level scan line SL3 overlaps the third-level transmission line SL3 and the second transmission line SL2, and is electrically connected to the third-level scan line SL3 Another part of the sub-pixel F overlaps the fourth-level transmission line SL4 and the fifth transmission line SL5.

Taking the sub-pixel electrically connected to the third-level scan line SL3 as an example, the capacitance between the drain and the gate of the switching element of the sub-pixel F is Cgd4, and the drain of the switching element of the standard sub-pixel N The capacitance between the gate and the gate is Cgd0. The capacitor Cgd4 is adjusted by the compensation design of any of the foregoing embodiments so that the capacitor Cgd4 is smaller than the capacitor Cgd0, thereby improving the problem of uneven brightness distribution of the display screen.

In some embodiments, taking the sub-pixels electrically connected to the third-level scan line SL3 as an example, the capacitance Cgd1 of the sub-pixel A is greater than the capacitance Cgd4 of the sub-pixel F, thereby further improving the uneven brightness distribution of the display screen. The problem.

FIG. 10 is a schematic top view of a pixel array substrate according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 10 uses the element numbers and part of the content of the embodiment of FIG. 1, wherein the same or similar reference numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiment, which will not be repeated here.

Referring to FIG. 10, in the pixel array substrate 30, each scan line SL is electrically connected to a plurality of transmission lines TL. For example, the first-level scan lines are electrically connected to three first-level transmission lines, and the three first-level transmission lines are electrically connected to different driving circuits DR, respectively.

Using multiple transmission lines to provide signals to the same scan line can improve the problem caused by excessive scan line resistance.

Although in this embodiment, each scan line is electrically connected to three transmission lines, the invention is not limited to this. In other embodiments, each scan line is electrically connected to more than four transmission lines.

11A and 11B are schematic top views of different sub-pixels according to an embodiment of the present invention. It must be noted here that the embodiments of FIGS. 11A and 11B follow the element numbers and part of the content of the embodiments of FIGS. 4A to 4F, wherein the same or similar numbers are used to denote the same or similar elements, and the same elements are omitted. Description of technical content. For the description of the omitted parts, reference may be made to the foregoing embodiment, which will not be repeated here.

For the convenience of description, FIGS. 11A and 11B illustrate switching elements, scan lines, and data lines, and omit other components. For the description of other components, refer to the foregoing embodiment, which will not be repeated here.

The sub-pixel A in FIG. 11B has a similar structure to the standard sub-pixel N in FIG. 11A. The difference is that the drain DE of the sub-pixel A overlaps the gate GE and the length L1 is smaller than the standard switching element T of the standard sub-pixel N. The drain electrode DE overlaps the length L of the gate electrode GE.

In this embodiment, the width X1 of the gate GE of the sub-pixel A is smaller than the width X of the gate GE of the standard switching element T of the standard sub-pixel N. By adjusting the width X1 of the gate GE, the length L1 of the drain DE overlapping with the gate GE is changed.

In this embodiment, the length L1 that the drain DE of the switching element T1 overlaps the gate GE is smaller than the length L that the drain DE of the standard switching element T overlaps the gate GE, so that the drain DE of the switching element T1 and the gate GE The overlap area between GE is smaller than the overlap area between the drain DE and the gate GE of the standard switching element T. Therefore, the capacitance Cgd1 of the switching element T1 is smaller than the capacitance Cgd0 of the standard switching element T.

In this embodiment, by making the capacitance Cgd1 of the switching element T1 smaller than the capacitance Cgd0 of the standard switching element T, the problem of inconsistent brightness of the display device can be improved.

FIG. 12 is a schematic top view of a pixel array substrate according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 12 uses the element numbers and part of the content of the embodiment of FIG. 10, wherein the same or similar reference numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiment, which will not be repeated here.

For the convenience of description, FIG. 12 shows transmission lines, scan lines, and data lines, and other components are omitted. For the description of other components, reference may be made to the foregoing embodiment, which will not be repeated here.

12, in this embodiment, the transmission line T1a of the pixel array substrate 40 is electrically connected to the driving circuit DR to the corresponding scan line SL, and the length of the transmission line T1a between the driving circuit DR and the corresponding scan line SL is Y1. In this embodiment, the transmission line Tlb is electrically connected to the driving circuit DR to the corresponding scan line SL, and the length of the transmission line Tlb between the driving circuit DR and the corresponding scan line SL is Y2. In this embodiment, the transmission line Tlc is electrically connected to the driving circuit DR to the corresponding scan line SL, and the length of the transmission line Tlc between the driving circuit DR and the corresponding scan line SL is Y3. In this embodiment, the length Y3 is greater than the length Y2 and is greater than the length Y1.

Since the length Y3, the length Y2, and the length Y1 are different from each other, the sub-pixels that are electrically connected to the transmission line T1a, the sub-pixels that are electrically connected to the transmission line Tlb, and the sub-pixels that are electrically connected to the transmission line Tlc have different degrees of Compensation design. In some embodiments, the degree of compensation design of the sub-pixels electrically connected to the transmission line Tlc is greater than the degree of compensation design of the sub-pixels electrically connected to the transmission line Tlb, and the compensation of the sub-pixels electrically connected to the transmission line Tlb The degree of design is greater than the degree of compensation design of the sub-pixels electrically connected to the transmission line Tlc. For example, the overlap area of the drain and gate of the first switching element electrically connected to the transmission line T1a is A1, and the overlap area of the drain and gate of the second switching element electrically connected to the transmission line Tlb is A2, The overlap area of the drain and the gate of the third switching element electrically connected to the transmission line Tlc is A3. By adjusting the length of the drain, the width of the drain and/or the width of the gate, the area A1>A2> Area A3. In other words, the larger the compensation value of the sub-pixel compensation design, the smaller the overlap area of the drain and the gate. For example, the length of the drain of the first switching element is greater than the length of the drain of the second switching element than the length of the drain of the third switching element. For example, the width of the drain of the first switching element is greater than the width of the drain of the second switching element than the width of the drain of the third switching element.

For example, the capacitance between the drain and the gate of the first switching element electrically connected to the transmission line T1a is Cgda, and the capacitance between the drain and the gate of the second switching element electrically connected to the transmission line Tlb is Cgdb, the capacitance between the drain and the gate of the second switching element electrically connected to the transmission line Tlb is Cgdc, where Cgda>Cgdb>Cgdc.

In other embodiments, the extent of the compensation design of the sub-pixels can also be changed by adjusting the area of the pixel electrode overlapping the gate of the switching element (as shown in FIG. 8A and FIG. 8B). For example, the overlap area of the gate electrode of the first switching element and the first pixel electrode electrically connected to the transmission line T1 is B1, and the gate electrode and the second pixel electrode of the second switching element electrically connected to the transmission line Tlb are The overlap area of is B2, the overlap area of the gate of the third switching element electrically connected to the transmission line Tlc and the third pixel electrode is B3, area B1>area B2>area B3. In other words, the larger the compensation value of the sub-pixel compensation design, the smaller the overlap area of the pixel electrode and the gate electrode.

10, 20, 30, 40: pixel array substrate A, C, D, E: sub-pixels AA: Display area BA: Surrounding area CL1, CL2, CL3: Shared signal line CH: Channel layer CS: transfer structure DL: Data line DE: Dip pole DC, DR: drive circuit DR1, DR2: direction EP: Extension GE: Gate GI: Gate insulation layer L, L1~L3, L5, L6, Y1, Y2, Y3: length N: Standard sub-pixel O: opening PE: pixel electrode PL: insulating layer SB: Substrate SE: Source SL, SL1~SL5: scan line T: Standard switching element TL, TL1~TL9, TLm, TLa, TLb, TLc: transmission line T1~T3, T5, T6: switching elements U: Insulation layer W1, W2, X, X1: width

FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the invention. 2 is a schematic top view of a display area of a pixel array substrate according to an embodiment of the invention. 3 is a waveform diagram of scan line signals of a pixel array substrate according to an embodiment of the present invention. 4A to 4F are schematic top views of different sub-pixels according to an embodiment of the present invention. Fig. 5 is a schematic cross-sectional view taken along the line aa' of Fig. 4A. 6 is a waveform diagram of scan line signals and pixel electrode signals of a pixel array substrate according to an embodiment of the present invention. 7A and 7B are schematic top views of different sub-pixels according to an embodiment of the present invention. 8A and 8B are schematic top views of different sub-pixels according to an embodiment of the present invention. FIG. 9 is a schematic top view of a display area of a pixel array substrate according to an embodiment of the present invention. FIG. 10 is a schematic top view of a pixel array substrate according to an embodiment of the invention. 11A and 11B are schematic top views of different sub-pixels according to an embodiment of the present invention. FIG. 12 is a schematic top view of a pixel array substrate according to an embodiment of the invention.

A: Sub-pixel

CL1, CL3: Shared signal line

CH: Channel layer

CS: transfer structure

DE: Dip pole

GE: Gate

L1: length

PE: pixel electrode

SE: Source

SL3: scan line

TL3: Transmission line

T1: switching element

Claims (20)

A pixel array substrate includes: Multiple scan lines are located on a substrate, including: The scan lines from level 1 to level n extend along a first direction, where n is an integer greater than 3; Multiple transmission lines are located on the substrate, including: The first-level transmission line to the n-th level transmission line extend along a second direction, and are electrically connected to the first-level scan line to the n-th level scan line, respectively; A plurality of data lines are located on the substrate and extend along the second direction; A plurality of sub-pixels, each of the sub-pixels is electrically connected to a corresponding scan line and a corresponding data line, wherein the sub-pixels include: A first sub-pixel overlaps the third-level transmission line, wherein a first switching element of the first sub-pixel is electrically connected to the third-level scan line, and the drain of the first switching element and the first The capacitance between the gates of the switching element is Cgd1; A second sub-pixel overlaps the 3+x-level transmission line, where x is an integer less than 3, wherein a second switching element of the second sub-pixel is electrically connected to the third-level scan line, and The capacitance between the drain of the second switching element and the gate of the second switching element is Cgd2; and A third sub-pixel overlaps the 3-x level transmission line, wherein a third switching element of the third sub-pixel is electrically connected to the third level scan line, and the drain of the third switching element and The capacitance between the gates of the third switching element is Cgd3, where Cgd2 is greater than Cgd3 and Cgd1. The pixel array substrate according to claim 1, wherein the capacitance between the drain of the first switching element and the third-level transmission line is Cvg1, and the drain of the second switching element is connected to the third+x-level transmission line The capacitance therebetween is Cvg2, the capacitance between the drain of the third switching element and the 3-x-th stage transmission line is Cvg3, and Cvg1, Cvg2, and Cvg3 are approximately the same as each other. The pixel array substrate according to claim 1, wherein the sub-pixels further include: A fourth sub-pixel overlaps the third-level transmission line and the second transmission line, wherein the fourth sub-pixel is electrically connected to the third-level scan line. The pixel array substrate according to claim 3, wherein the capacitance between the drain of the fourth switching element and the gate of the fourth switching element is Cgd4, and Cgd1 is greater than Cgd4. The pixel array substrate according to claim 1, wherein x is equal to 2, and the sub-pixels further include: A fifth sub-pixel overlaps the second-level transmission line, wherein a fifth switch element of the fifth sub-pixel is electrically connected to the third-level scan line, and the drain of the fifth switch element is The capacitance between the gates of the five switching elements is Cgd5, and Cgd1 is smaller than Cgd5 and smaller than Cgd3. The pixel array substrate according to claim 1, wherein x is equal to 2, and the sub-pixels further include: A sixth sub-pixel overlaps the fourth-level transmission line, wherein a sixth switching element of the sixth sub-pixel is electrically connected to the third-level scan line, and the drain of the sixth switching element is The capacitance between the gates of the six switching elements is Cgd6, and Cgd1 is smaller than Cgd6 and smaller than Cgd2. The pixel array substrate according to claim 1, further comprising: A standard sub-pixel overlaps the m-th level transmission line, where 1<m<n, and a standard switching element of the standard sub-pixel is electrically connected to the third level scan line, wherein the m-th level scan line is charged The time does not overlap with the charging time of the third-level scan line, and the drain of the first switching element overlaps with the gate of the first switching element for a length of L1, and the drain of the standard switching element overlaps with the standard switch The length of the gate of the element is L, and L1 is less than L. The pixel array substrate according to claim 7, wherein the difference between L1 and L is between 0.5 μm and 1 μm. The pixel array substrate according to claim 1, wherein the charging time of the third level scan line partially overlaps the charging time of the 3+x level scan line and the charging time of the 3-x level scan line. The pixel array substrate according to claim 1, further comprising: A standard sub-pixel overlaps the m-th level transmission line, where 1<m<n, and a standard switching element of the standard sub-pixel is electrically connected to the third level scan line, wherein the m-th level scan line is charged The time does not overlap with the charging time of the third level scan line, and the width of the drain of the standard switching element is greater than the width of the drain of the first switching element. The pixel array substrate according to claim 1, further comprising: A standard sub-pixel overlaps the m-th level transmission line, where 1<m<n, and a standard switching element of the standard sub-pixel is electrically connected to the third level scan line, wherein the m-th level scan line is charged The time does not overlap with the charging time of the third level scan line, wherein the first sub-pixel further includes a first pixel electrode electrically connected to the first switching element, and the standard sub-pixel further includes electrical A second pixel electrode connected to the standard switching element, wherein the area where the first pixel electrode overlaps the gate electrode of the first switching element is different from the area where the second pixel electrode overlaps the gate electrode of the standard switching element Area. The pixel array substrate according to claim 1, further comprising: A driving circuit, the first level transmission line to the nth level transmission line are respectively electrically connected to the driving circuit to the first level scan line to the nth level scan line; wherein One of the first level transmission line to the nth level transmission line is electrically connected to one of the first level scan line to the nth level scan line, and the driving circuit and the first level scan line The length of the first level transmission line to the one of the nth level transmission line between the nth level scan line and the one of the nth level scan lines is Y1, which is electrically connected to the first level transmission line to the first level transmission line. The overlap area of the drain and the gate of a seventh switching element of the one of the n-level transmission lines is A1; The other one of the first level transmission line to the nth level transmission line is electrically connected to the other one of the first level scan line to the nth level scan line, and the driving circuit and the first level The length of the first level transmission line between the scan line to the other one of the nth level scan lines to the other one of the nth level transmission lines is Y2, and is electrically connected to the first level The overlap area between the drain and the gate of an eighth switching element from the transmission line to the other one of the nth-level transmission lines is A2; The other one of the first level transmission line to the nth level transmission line is electrically connected to the other one of the first level scan line to the nth level scan line, and the driving circuit and the first level scan line The length of the first level transmission line to the other one of the nth level scan lines between the level 1 scan line and the other one of the nth level scan lines is Y3, which is electrically connected to The overlap area of the drain and the gate of a ninth switching element of the one of the first transmission line to the nth transmission line is A3, wherein the length Y3 is greater than the length Y2 is greater than the length Y1, and the area A1 >Area A2>Area A3. The pixel array substrate according to claim 1, further comprising: A driving circuit, the first level transmission line to the nth level transmission line are respectively electrically connected to the driving circuit to the first level scan line to the nth level scan line; wherein One of the first level transmission line to the nth level transmission line is electrically connected to one of the first level scan line to the nth level scan line, and the driving circuit and the first level scan line The length of the first level transmission line to the one of the nth level transmission line between the nth level scan line and the one of the nth level scan lines is Y1, which is electrically connected to the first level transmission line to the first level transmission line. The overlap area of the gate of a seventh switching element and the seventh pixel electrode of the one of the n-level transmission lines is B1; The other one of the first level transmission line to the nth level transmission line is electrically connected to the other one of the first level scan line to the nth level scan line, and the driving circuit and the first level The length of the first level transmission line between the scan line to the other one of the nth level scan lines to the other one of the nth level transmission lines is Y2, and is electrically connected to the first level The overlap area between the gate electrode of the eighth switching element and the eighth pixel electrode from the transmission line to the other one of the n-th level transmission lines is B2; The other one of the first level transmission line to the nth level transmission line is electrically connected to the other one of the first level scan line to the nth level scan line, and the driving circuit and the first level scan line The length of the first level transmission line to the other of the nth level scan line between the level 1 scan line and the other one of the n level scan lines is Y3, which is electrically connected to The overlapping area of the gate of a ninth switching element and a ninth pixel electrode of the one of the first transmission line to the nth transmission line is B3, wherein the length Y3 is greater than the length Y2 is greater than Length Y1, and area B1>area B2>area B3. A pixel array substrate includes: A drive circuit; Multiple scan lines are located on a substrate, including: The scan lines from level 1 to level n extend along a first direction, where n is an integer greater than 3; Multiple transmission lines are located on the substrate, including: The first level transmission line to the nth level transmission line extend along a second direction, and the first level transmission line to the nth level transmission line are electrically connected to the driving circuit to the first level scan line to the nth level scan line, respectively Line, wherein one of the first level transmission line to the nth level transmission line is electrically connected to one of the first level scan line to the nth level scan line, and the driving circuit and the first The length of the one of the first level transmission line to the nth level transmission line between the first level scan line and the one of the nth level scan line is Y1, and the first level transmission line to the nth level The other one of the level transmission lines is electrically connected to the other one of the first level scan line to the nth level scan line, and the driving circuit and the first level scan line to the nth level scan line The length of the first level transmission line between the other one of the transmission lines to the other one of the nth level transmission lines is Y2, wherein the length Y2 is greater than the length Y1; A plurality of data lines are located on the substrate and extend along the second direction; A first sub-pixel includes a first switching element and a first pixel electrode electrically connected to the first switching element, wherein the first switching element is electrically connected to the first-level transmission line to the n-th The one of the level transmission lines, and the overlap area of the drain and gate of the first switching element is A1, and the overlap area of the gate of the first switching element and the first pixel electrode is B1; and A second sub-pixel includes a second switching element and a second pixel electrode electrically connected to the second switching element, wherein the second switching element is electrically connected to the first-level transmission line to the n-th The other one of the level transmission lines, and the overlap area of the drain and gate of the second switching element is A2, and the overlap area of the gate of the second switching element and the second pixel electrode is B2, where : Area A1>A2, and/or Area B1>area B2. The pixel array substrate according to claim 14, wherein the capacitance between the drain of the first switching element and the gate of the first switching element is Cgda, and the drain of the second switching element and the second switch The capacitance between the gates of the element is Cgdb, where Cgda>Cgdb. The pixel array substrate according to claim 14, wherein the width of the drain of the first switching element is greater than the width of the drain of the second switching element. The pixel array substrate according to claim 14, wherein the length of the drain of the first switching element is greater than the length of the drain of the second switching element. The pixel array substrate according to claim 15, wherein another one of the first level transmission line to the nth level transmission line is electrically connected to the first level scan line to the nth level scan line One of the other one, and the one of the first level transmission line to the nth level transmission line between the driving circuit and the other one of the first level scan line to the nth level scan line The length of the other one is Y3, the length Y3 is greater than the length Y2, and the pixel array substrate further includes: A third sub-pixel, including a third switching element and a third pixel electrode electrically connected to the third switching element, wherein the third switching element is electrically connected to the first-level transmission line to the n-th The other one of the level transmission lines, and the overlap area of the drain and gate of the third switching element is A3, and the overlap area of the gate of the third switching element and the third pixel electrode is B3, among them: Area A2>area A3, and/or Area B2>area B3. The pixel array substrate according to claim 18, wherein the capacitance between the drain of the third switching element and the gate of the third switching element is Cgdc, and Cgdb>Cgdc. The pixel array substrate according to claim 18, wherein the length of the drain of the second switching element is greater than the length of the drain of the third switching element.

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