DE112020003922T5 - DISPLAY DEVICE - Google Patents

Abstract

A display device having data lines, first gate lines, pixel structures, second gate lines, and first common lines is provided. The data lines are arranged in a first direction. The first gate lines are arranged in a second direction. Pixel structures are electrically connected to the data lines and the first gate lines. The data lines and the second gate lines are arranged in the first direction, and the second gate lines are electrically connected to the first gate lines. The pixel structures are arranged in pixel columns arranged in the first direction. Each of the first common lines and the corresponding second gate line are arranged between two adjacent columns of pixels. The first common line and the corresponding second gate line are respectively configured on opposite sides of the first gate line electrically connected to the corresponding second gate line. The first common line and the corresponding second gate line are structurally separated.

Description

BACKGROUND

technical field

The disclosure relates to an electronic device, in particular to a display device.

Description of the prior art

With the development of display technology, people demand more from display devices than optical properties, such as high resolution, high contrast and wide viewing angles. People also expect elegant appearance from display devices. For example, the display device is expected to have a narrow bezel or bezel, or even no bezel.

In general, a display device includes pixel structures configured in a display area, data driver circuitry configured below the display area, and gate driver circuitry configured to the left, right, or both sides of the display area. In order to reduce the widths of the left and right sides of the front frame of the display device, both the gate drive circuit and the data drive circuit can be arranged on the lower side of the display area. When the gate driver circuit is configured on the lower side of the display area, the horizontal gate lines must be electrically connected to the gate driver circuit through the vertical gate line. However, the gate-on pulse signal of the vertical gate lines may affect the potentials of some pixel structures, thereby causing an abnormal display.

SUMMARY OF THE INVENTION

The disclosure provides a display device with excellent performance.

The disclosure also provides another display device with excellent performance.

A display device of the disclosure includes a first substrate, a plurality of data lines, a plurality of first gate lines, a plurality of pixel structures, a plurality of second gate lines, a plurality of first common lines, a second substrate, and a display medium. The data lines are configured on the first substrate and arranged in a first direction. The first gate lines are configured on the first substrate and configured in a second direction, the first direction crossing the second direction. The pixel structures are configured on the first substrate and are electrically connected to the data lines and the first gate lines. The second gate lines are configured on the first substrate with the data lines and the second gate lines arranged in the first direction, and the second gate lines are electrically connected to the first gate lines. The first common lines are configured on the first substrate with the pixel structures arranged in pixel columns, and the pixel columns are arranged in the first direction. Each of the first common lines and the corresponding second gate line are configured between two adjacent pixel columns of the pixel columns. The first common line and the corresponding second gate line are respectively configured on opposite sides of the first gate line electrically connected to the second gate line. And the first common line and the corresponding second gate line are structurally separated. The second substrate is configured to face the first substrate. The display medium is configured between the first substrate and the second substrate.

Another display device of the disclosure includes a first substrate, a plurality of data lines, a plurality of first gate lines, a plurality of pixel structures, a plurality of second gate lines, a second substrate, and a display medium. The data lines are configured on the first substrate and arranged in a first direction. The first gate lines are configured on the first substrate and arranged in a second direction, the first direction crossing the second direction. The pixel structures are configured on the first substrate, electrically connected to the data lines and the first gate lines, and arranged in a number of x pixel columns and y pixel rows. The x columns of pixels are arranged in the first direction, the y rows of pixels are arranged in the second direction, x and y are positive integers greater than 2, and the pixel structure has a first width a1 and a second width a2, each in the first direction and in the second direction. The second gate lines are configured on the first substrate, the data lines and the second gate lines are arranged in the first direction, and the second gate lines are electrically connected to the first gate lines. The second substrate is configured to face the first substrate. The display medium is configured between the first substrate and the second substrate. Each of the first gate lines is electronically connected to a number n of the second gate lines. (a1*x+a2*y)<2000000, and n=2; or 2000000<(a1 x+a2 y)<2400000, and n=3; or 2400000<(a1 x +a2*y)<3000000, and n=4; or (a1 x+a2 y)>3000000, and n=5.

In an embodiment of the disclosure, a first common line signal as described above and a gate-off signal of the second gate line are substantially the same.

In an embodiment of the disclosure, each of the first gate lines is electrically connected to the n second gate lines as described above, where n is a positive integer. Each of the first gate lines and the n second gate lines has the first to n-th connection points sequentially arranged in the first direction. The second gate lines include the first to n-th second gate line groups sequentially arranged in the first direction. The second gate lines of the m-th second gate line group of the first to n-th second gate line groups and the corresponding first gate lines have the m-th connection point of the first to n-th connection points, where m is a positive integer and n≥m≥1. The display device further includes a common electrode, a plurality of common pad groups, a plurality of first transfer elements, a number of n second common pads, and a number of n second transfer elements. The common electrode is configured on the second substrate and is located between the second substrate and the display medium. The common pad groups are configured on the first substrate and are configured to correspond to the first to n-th second gate line groups, respectively, with the pixel structures having a first side and a second side opposite to each other. The common pad groups are configured on the second side of the pixel structures, and each of the common pad groups includes multiple first common pads. The first transmission elements are configured on the first common pads of the common pad groups, respectively, and are electrically connected to the first common pads of the common pad groups and the common electrode. The n second common pads are configured on the first substrate and are configured to correspond to the first to n th second gate line groups, respectively, and are located on the first side of the pixel structures. The n second transmission elements are respectively configured on the n second common pads and electrically connected to the n second common pads and the common electrode. A common pad group and a second common pad correspond to the same second gate line group, and the potential of the second common pad is larger than the potentials of the first common pads of the common pad group.

As described above, in an embodiment of the disclosure, the display device further includes a third common pad configured on the first substrate and located on the first side of the pixel structures. The third common pad and the second common pads are sequentially arranged in the first direction and are structurally separated from each other. The third common pad is configured to correspond to the first second gate line group of the first to n-th second gate line groups. And the potential of the third common pad is larger than the potentials of the corresponding second common pads.

In an embodiment of the disclosure, the display device described above also includes a plurality of second common lines, a first peripheral line, and a second peripheral line. The second common lines are configured on the first substrate, and the second gate lines and the second common lines are arranged in the first direction, each of the second common lines being configured between two adjacent pixel columns of the pixel columns. The first peripheral line is configured on the first substrate and is on the first side of the pixel structures, with the first common lines being electrically connected to the first peripheral line. The second peripheral line is configured on the first substrate and is located on the second side of the pixel structures, with both ends of each of the second common lines being electrically connected to the first peripheral line and the second peripheral line, respectively.

In an embodiment of the disclosure, as described above, the first gate lines include an odd number of first gate lines and an even number of first gate lines Number. The odd-numbered first gate lines include the (1+2*K)th first gate lines, where K=0, 1,..., p and p is a positive integer 2 or greater. The even-numbered first gate lines include the 2L-th first gate lines, where L=1, 2, . . . q and q is a positive integer 3 or greater. The second gate lines include the first through (p+1)th second gate lines and the (p+2)th through (p+q+1)th second gate lines sequential in the first direction are arranged. The first through (p+1)th second gate lines are electrically connected to the (1+2*K)th first gate line, and the (p+2) through (p+q +1)-th second gate lines are electrically connected to the 2L-th first gate line.

In an embodiment of the disclosure, the connection points of the first to (p+1)th second gate lines and the (1+2*K)th first gate line and the connection points of the (p+2) to (p+ q+1)-th second gate lines and the 2L-th first gate line are substantially distributed along a plurality of diagonal lines parallel to each other.

In an embodiment of the disclosure, the connection points of the first to the (p+1)-th second gate lines and the (1+2*K)-th first gate line and the connection points of the (p+2) to distributed between the (p+q+1)-th second gate lines and the 2L-th first gate line in a substantially V-shape.

In an embodiment of the disclosure, the display device described above further includes a plurality of first common lines configured on the first substrate. Each of the first common lines and the corresponding second gate line are configured between two adjacent pixel columns out of x of the pixel columns. The first common line and the corresponding second gate line are each configured on opposite sides of the first gate line and electrically connected to the second gate line. And the first common line and the corresponding second gate line are structurally separated.

character list

• 1 1 is a schematic cross-sectional view of a display device 10 according to an embodiment of the disclosure.
• 2 12 is a schematic plan view of a pixel array substrate 100, a first transfer element T1, a second transfer element T2, and a third transfer element T3 according to an embodiment of the disclosure.
• 3 12 is a schematic plan view of an opposing substrate 200, a first transfer member T1, a second transfer member T2, and a third transfer member T3 according to an embodiment of the disclosure.
• 4 10 is a schematic plan view of a pixel array substrate 100A, a first transfer element T1, a second transfer element T2, and a third transfer element T3 according to an embodiment of the disclosure.
• 5 10 is a schematic plan view of a pixel array substrate 100B and a first transmission element T1 according to an embodiment of the disclosure.
• 6 10 is a schematic plan view of a pixel array substrate 100C and a first transmission element T1 according to an embodiment of the disclosure.
• 7 100D is a schematic plan view of a pixel array substrate 100D and a first transmission element T1 according to an embodiment of the disclosure.

Reference List

10

display device

100, 100A, 100B, 100C, 100D

pixel array substrate

110

first substrate

120

element layer

200

opposite substrate

210

second substrate

220

common electrode

221

first part

222

second part

223

third part

300

display medium

a1

first latitude

a2

second latitude

cpx

pixel column

C, C1, C2, C3

connection point

CL1, CL11, CL12, CL13, CL14, CL15, CL16

first joint line

CL2

second common line

D1

first direction

D2

second direction

DL

data line

Gvg, Gcf, Gvg2, Gvg3

second gate line group

Gpla, Gplb, Gplc

common pad group

HG, HG1, HG2, HG3, HG4, HG5, HG6

first gate line

K

diagonal line

LI

first peripheral line

L2:

second peripheral line

Lp1a, Lplb, Lplc, Lp2a, Lp2b, Lp2c, Lp3, Ll1, Ll2

wire

PX

pixel structure

p1a, p1b, p1c

first common pad

p2a, p2b, p2c

second common pad

p3

third common pad

Rpx

pixel line

S1

first page

S2

second page

T1

first transmission element

T2

second transmission element

T3

third transmission element

VG, VG1, VG2, VG3, VG4, VG5, VG6

second gate line

DESCRIPTION OF THE EMBODIMENTS

The exemplary embodiments of the disclosure should be referred to in detail. Examples of the exemplary embodiments are illustrated in the drawings. Where appropriate, the same reference numbers in the drawings and the descriptions refer to the same or like parts.

It should be understood that when an element such as a layer, film, region or substrate is indicated as being "on" or "connected to" another element, it is meant directly on another element, connected to another element or an element may exist in the middle. On the other hand, if an element is specified as "directly on top of another element" or "connected directly to" another element, then no middle element exists. For example, the term “connect (connected)” given in the description may indicate a physical and/or electrical connection. In addition, the expression "electrically connect(connected)" or "couple(coupled)" can also be used when there are other elements between two elements.

Uses of "approximately," "similar," "substantially," or "substantially" throughout the specification include the stated value and an average, with an acceptable range of deviation, i.e., a specific value confirmed by those skilled in the art, and is certain amount that is considered the discussed measurement and measurement-related error (i.e. the limitations of the measurement system). For example, "approximately" may mean that it is within one or more standard deviations of the displayed value, such as within ±30%, ±20%, ±10%, or ±5%. Additionally, the use of "approximately," "similar," or "substantially" throughout the specification may refer to a more acceptable range of deviation or standard deviation depending on optical properties, etching properties, or other properties, and all properties cannot be compared with one standard deviation are applied.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art. It should further be understood that terms, as defined in common dictionaries, should be construed in the context of the relevant technology and the present disclosure with which the meanings of the terms are consistent, and the terms should not be idealized or overly formalized construed unless expressly defined as such herein.

1 1 is a schematic cross-sectional view of a display device 10 according to an embodiment of the present disclosure.

As in 1 As shown, the display device 10 includes a pixel array substrate 100, an opposing substrate 200, and a display medium 300, with the display medium 300 being disposed between the pixel array substrate 100 and the opposing substrate 200. FIG. The pixel array substrate 100 includes a first substrate 110 and an element layer 120, wherein the element layer 120 is configured on the first substrate 110 and is located between the display medium 300 and the first substrate 110. FIG. The opposing substrate 200 includes a second substrate 210, where the second substrate 210 is configured to face the first substrate 110, and the display medium 300 is interposed between the first substrate 110 and the second substrate 210. FIG.

In the present embodiment, a material of the first substrate 110 may be glass, quartz, organic polymer or other applicable materials; a material of the second substrate 210 may be glass, quartz, organic polymer, or other applicable materials.

In the present embodiment, the display medium 300 may be a liquid crystal, for example. However, the present embodiment is not limited to this. In other embodiments, the display medium 300 can also be an organic electroluminescent layer or other applicable materials.

2 12 is a schematic plan view of a pixel array substrate 100, a first transfer element T1, a second transfer element T2, and a third transfer element T3 according to an embodiment of the disclosure.

As in 1 and 2 1, the element layer 120 of the pixel array substrate 100 includes a plurality of data lines DL, a plurality of first gate lines HG, a plurality of pixel structures PX, and a plurality of second gate lines VG.

As in 2 As shown, the data lines DL are configured on the first substrate 110 and arranged in a first direction D1. The first gate lines HG are configured on the first substrate 110 and arranged in a second direction D2, where the first direction D1 crosses the second direction D2. For example, in the present embodiment, the first direction D1 and the second direction D2 may be substantially perpendicular to each other, but the present disclosure is not limited thereto.

In the present embodiment, the data lines DL and the first gate lines HG belong to different film layers. For example, in the present embodiment, the first gate lines HG may belong to a first metal layer while the data lines DL may belong to a second metal layer, but the present disclosure is not limited thereto. In the present embodiment, based on the consideration of conductivity, the data lines DL and the first gate lines HG are made of metallic materials, but the disclosure is not limited thereto. In other embodiments, the data lines DL and/or the first gate lines HG can also be made of other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials Materials.

The pixel structures PX are configured on the first substrate 110 and electrically connected to the data lines DL and the first gate lines HG. Specifically, in the present embodiment, each of the pixel structures PX may include a thin film transistor (not shown) and a pixel electrode (not shown), the thin film transistor having a first end, a second end, and a control end. The first end of the thin film transistor is electrically connected to a corresponding data line DL. The control end of the thin film transistor is electrically connected to a corresponding first gate line HG. And the second end of the thin film transistor is electrically connected to the pixel electrode.

The second gate lines VG are configured on the first substrate 110 with the data lines DL and the second gate lines VG arranged in the first direction, and the second gate lines VG are electrically connected to the first gate lines HG.

Concretely, in the present embodiment, the pixel structures PX are arranged in a plurality of pixel columns Cpx and a plurality of pixel rows Rpx. The pixel columns Cpx are arranged in the first direction D1, and the pixel structures PX of each of the pixel columns Cpx are arranged in the second direction D2. The pixel rows Rpx are arranged in the second direction D2, and the pixel structures PX of each of the pixel rows Rpx are arranged in the first direction D1. In the plan view of the pixel array substrate 100, each of the second gate lines VG is arranged between two adjacent pixel columns Cpx. In other words, the second gate lines VG are intertwined in an active area of the pixel array substrate 100, and each of the second gate lines VG is electrically connected to at least one corresponding first gate line HG in the active area.

For example, in the present embodiment, the first gate lines HG include a first gate line HG1, a first gate line HG2, a first gate line HG3, a first gate line HG4, a first gate line HG5, and a first gate - line HG6 arranged consecutively in the second direction D2; and the second gate lines VG include a second gate line VG1, a second gate line VG2, a second gate line VG3, a second gate line VG4, a second gate line VG5 and a second gate line VG6, which are sequentially arranged in the first direction D1 and respectively connected to the first gate line HG1, the first gate line HG2, the first gate line HG3, the first gate HG4, the first gate Line HG5 and the first gate line HG6 may be electrically connected. However, the invention is not limited to this. In other embodiments, the second gate lines VG can also be connected to the first gate lines HG in other ways.

In 1 and 2 note that the element layer 120 of the pixel array substrate 100 further includes a plurality of first common lines CL1. As in 2 As shown, the first common lines CL1 are configured on the first substrate 110 . In a plan view of the pixel array substrate 100, each of the first common lines CL1 and the corresponding second gate line VG are configured between two adjacent pixel columns Cpx. The first common line CL1 and the corresponding second gate line VG are respectively configured on opposite sides of the first gate line HG electrically connected to the second gate line VG. And the first common line CL1 is structurally separated from the corresponding second gate line VG.

For example, in the present embodiment, the second gate lines VG include the second gate line VG1, the second gate line VG2, the second gate line VG3, the second gate line VG4, the second gate line VG5, and the second Gate line VG6 electrically connected to the first gate line HG1, the first gate line HG2, the first gate line HG3, the first gate line HG4, the first gate line HG5 and the first gate line HG6 are connected. The first common lines CL1 include a first common line CL11, a first common line CL12, a first common line CL13, a first common line CL14, a first common line CL15, and a first common line CL16 corresponding to the second gate line VG1 , the second gate line VG2, the second gate line VG3, the second gate line VG4, the second gate line VG5 and the second gate line VG6. In a plan view of the pixel array substrate 100, the first common line CL11 and the second gate line VG1 are respectively configured on the opposite sides of the first gate line HG1 electrically connected to the second gate line VG1 and the first common line CL11 is structurally separate from second gate line VG1; the first common line CL12 and the second gate line VG2 are respectively configured on the opposite sides of the first gate line HG2 electrically connected to the second gate line VG2, and the first common line CL12 is structurally different from the second gate -Line VG2 disconnected; the first common line CL13 and the second gate line VG3 are respectively configured on the opposite sides of the first gate line HG3 electrically connected to the second gate line VG3, and the first common line CL13 is structurally different from the second gate -Line VG3 disconnected; the first common line CL14 and the second gate line VG4 are respectively configured on the opposite sides of the first gate line HG4 electrically connected to the second gate line VG4, and the first common line CL14 is structurally different from the second gate -Line VG4 disconnected; the first common line CL15 and the second gate line VG5 are respectively configured on the opposite sides of the first gate line HG5 electrically connected to the second gate line VG5, and the first common line CL15 is structurally different from the second gate -Line VG5 disconnected; and the first common line CL16 and the second gate line VG6 are respectively configured on the opposite sides of the first gate line HG6 electrically connected to the second gate line VG6, and the first common line CL16 is structurally different from the second Gate line VG6 disconnected.

It should be noted that regardless of whether the second gate lines VG are provided next to the pixel structures PX or not, with the configuration of the first common lines CL1, the pixel structures PX capture the same or similar electric field distribution and thereby the display quality can improve.

In the present embodiment, a signal of the first common lines CL1 and a gate-off signal of the second gate lines VG are substantially the same. In particular, in the present embodiment, regardless of whether a signal of the second gate lines VG is a gate-off signal or a gate-up signal, a signal of the first common lines CL1 can be set as a gate-off signal. For example, in the present embodiment, the gate-off signal may be a DC signal between -9 volts and -10 volts, but the disclosure is not so limited.

In the present embodiment, the first common lines CL1 and the first gate lines HG belong to different film layers. For example, in the present embodiment, the first gate lines HG may belong to a first metal layer while the first common lines CL1 may belong to a second metal layer, but the disclosure is not limited thereto. In the present embodiment, based on the consideration of conductivity, the material of the first common lines CL1 is a metal material. However, the disclosure is not limited to this. In other embodiments, the first common lines CL1 may also be made of other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or a stacked layer of metal materials and other conductive materials.

As in 1 and 2 1, in the present embodiment, the element layer 120 of the pixel array substrate 100 additionally includes a first peripheral line L1. As in 2 As shown, the first peripheral line L1 is configured on the first substrate 110 and is located on a first side S1 of the pixel structures PX. The first common lines CL1 are electrically connected to the first peripheral line L1.

As in 1 and 2 As illustrated, the element layer 120 of the pixel array substrate 100 in the present embodiment further includes a plurality of second common lines CL2. As in 2 As illustrated, the second common lines CL2 are configured on the first substrate 110, the second gate lines VG and the second common lines CL2 are arranged in the first direction D1, and each of the second common lines CL2 is configured between two adjacent pixel columns Cpx. More specifically, there are multiple layout areas between the pixel columns Cpx, and the second common lines CL2 are configured on the layout areas where the second gate lines VG and the first common lines CL1 are not provided.

In the present embodiment, the second common lines CL2 and the first gate lines HG may belong to different film layers. For example, in the present embodiment, the first gate lines HG may belong to a first metal layer while the second common lines CL2 may belong to a second metal layer, but the disclosure is not limited thereto. In the present embodiment, based on the consideration of conductivity, the material of the second common lines CL2 is a metal material. However, the disclosure is not limited to this. In other embodiments, the second common lines CL2 may also be made of other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or a stacked layer of metal materials and other conductive materials.

As in 1 and 2 1, in the present embodiment, the element layer 120 of the pixel array substrate 100 additionally includes a second peripheral line L2. As in 2 As shown, the second peripheral line L2 is configured on the first substrate 110 and is located on a second side S2 of the pixel structures PX, and the second common lines CL2 are electrically connected to the second peripheral line L2.

In the present embodiment, one end of each of the second common lines CL2 that is close to the second peripheral line L2 is electrically connected to the second peripheral line L2, and the other end of each of the second common lines CL2 that is close to the second peripheral line L2 remote may be selectively disconnected from the first peripheral line L1, but the disclosure is not limited thereto.

As in 2 1, each of the first gate lines HG is electrically connected to a number n of the second gate lines VG, where n is a positive integer, and each of the first gate lines HG and the n second gate lines VG have the first to n-th connection points (or contact points) C sequentially arranged in the first direction D1. And the second gate lines VG include the first to n-th second line groups Gvg sequentially arranged in the first direction D1, and the second gate lines VG of the m-th second gate line groups Gvg of the first to n-th second gate line groups Gvg and the corresponding first gate lines HG have the m-th connection point C of the first through n-th connection points C, where m is a positive integer, and n≥m≥1.

For example, in the present embodiment, n=3; thus, each of the first gate lines HG is electrically connected to three corresponding second gate lines VG, and each of the first gate lines HG and the three corresponding second gate lines VG have the first to third connection points C1, C2, and C3, the are sequentially arranged in the first direction D1. And the second gate lines VG include the first to third second gate line groups Gvergleich, Gvg2 and Gvg3, which are sequentially arranged in the first direction D1, the second gate lines VG1 to VG6 of the first second gate line group Gvergleich and the corresponding first gate lines HG1 to HG6 have the first connection points C1, the second gate lines VG1 to VG6 of the second second gate line group Gvg2 and the corresponding first gate lines HG1 to HG6 the second connection have connection points C2, and the second gate lines VG1 to VG6 of the third second gate line group Gvg3 and the corresponding first gate lines HG1 to HG6 have the third connection points C3.

3 12 is a schematic plan view of an opposing substrate 200, a first transfer member T1, a second transfer member T2, and a third transfer member T3 according to an embodiment of the disclosure.

As in 1 and 3 As illustrated, in the present embodiment, the opposing substrate 200 of the display device 10 may selectively include a common electrode 220, where the common electrode 220 is configured on the second substrate 210 and is located between the second substrate 210 and the display medium 300. As in 2 and 3 As illustrated, the common electrode 220 in the present embodiment is a full electrode layer that overlaps all of the pixel structures PX, but the disclosure is not limited thereto.

In the present embodiment, the common electrode 220 may be, for example, a transparent conductive layer containing metal oxides such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or other suitable oxides, or a stacked layer of at least two of the above, but the disclosure is not limited to that.

As in 1 and 2 1, in the present embodiment, the element layer 120 of the pixel array substrate 100 further includes a plurality of common pad groups Gpla, Gplb, and Gplc, and an n number of a plurality of second common pads p2a, p2b, and p2c. As in 2 1, the common pad groups Gpla, Gplb, and Gplc are configured on the first substrate 110 and configured to correspond to the first to n-th second gate line groups Gvergleich, Gvg2, and Gvg3, respectively, and located on the second side S2 of the Pixel structures PX are located. Each of the common pad groups Gpla, Gplb, and Gplc includes a plurality of first common pads p1a, p1b, and p1c that are structurally separate. And the n second common pads p2a, p2b and p2c are configured on the first substrate 110 and configured to correspond to the first to n-th second gate line groups Gvergleich, Gvergleich2 and Gvergleich3, respectively, and located on the first side S1 of the pixel structures PX located.

For example, in the present embodiment, n=3; Thus, the pixel array substrate 100 includes three common pad groups Gpla, Gplb, and Gplc, and three second common pads p2a, p2b, and p2c. The three common pad groups Gpla, Gplb, and Gplc are configured to correspond to the first through third second gate line groups Gvergleich, Gvergleich2, and Gvergleich3, respectively, and are located on the second side S2 of the pixel structures PX. The three second common pads p2a, p2b and p2c are configured on the first substrate 110 and configured to correspond to the first to third second gate line groups Gvergleich, Gvergleich2 and Gvergleich3, respectively, and are located on the first side S1 of the pixel structures PX.

In the present embodiment, the first common pads p1a of the same common pad group Gpla are distributed on a side of the second gate lines VG1 to VG6 of the corresponding second gate line group Gcf; the second common pad p2a corresponding to the second gate line group Gvergleich is configured on the other side of the second gate lines VG1 to VG6 of the second gate line group Gvergleich; and the second common pad p2a can be located next to the longest second gate line VG6 of the second gate line group Gvergleich.

As in 1 , 2 and 3 As illustrated, in the present embodiment, the display device 10 further includes the first transfer elements T1 arranged between the element layer 120 of the pixel array substrate 100 and the common electrode 220 of the opposing substrate 200. As shown in FIG. The first transmission elements T1 are respectively configured on the first common pads p1a, p1b and p1c of the common pad groups Gp1a, Gp1b and Gp1c and electrically connected to the first common pads p1a, p1b and p1c and a first part 221 of the common electrode 220.

In the present embodiment, the display device 10 further includes n number of second transfer elements T2 arranged between the element layer 120 of the pixel array substrate 100 and the common electrode 220 of the opposite substrate 200 . And the n second transmission elements T2 are respectively configured on the n second common pads p2a, p2b and p2c and electrically connected to the n second common pads p2a, p2b and p2c and a second part 222 of the common electrode 220.

In the present embodiment, the common pad group Gpla and the second common pad p2a correspond to the same second gate line group Gvergleich, and the potential of the second common pad p2a is larger than the potentials of the first common pads p1a of the common pad group Gp1a. This will a potential distribution is formed between the first part 221 and the second part 222 of the common electrode 220, which are respectively electrically connected to the first transmission element T1 configured on the first common pad p1a and the second transmission element T2 configured on the second common pad p2a. The potential distribution can compensate for the difference in brightness caused by the different impedances of the second gate lines VG1 to VG6 of the second gate line group Gvergleich.

In the present embodiment, the first common pads p1a, p1b, and p1c are electrically connected to a driving element (not shown) via a plurality of wires Lp1a, Lp1b, and Lp1c, respectively, and the second common pads p2a, p2b, and p2c are respectively connected via a A plurality of wires Lp2a, Lp2b and Lp2c are electrically connected to a driving member (not shown), and the wires Lp1a, Lp1b, Lp1c, Lp2a, Lp2b and Lp2c are structurally separated from each other. In other words, the potentials of the first common pads p1a, p1b, and p1c and the second common pads p2a, p2b, and p2c can be controlled independently of each other. The magnitude of the potentials of the first common pads p1a, p1b, and p1c and the second common pads p2a, p2b, and p2c can be adjusted according to actual needs.

As in 1 and 2 1, in the present embodiment, the element layer 120 of the pixel array substrate 100 further includes a third common pad p3. As in 2 shown, the third common pad p3 is configured on the first substrate 110 and is located on the first side S1 of the pixel structures PX. The third common pad p3 and the second common pads p2a, p2b, and p2c are arranged sequentially in the first direction D1 and are structurally separated from each other. The third common pad p3 is configured to correspond to the first second gate line group Gvergleich. And the potential of the third common pad p3 is larger than the potentials of the second common pads p2a, p2b and p2c. In the present embodiment, the potential of the third common pad p3 is also larger than the potentials of the first common pads p1a, p1b and p1c. For example, the potential difference between the third common pad p3 and any one of the first common pads p1a, p1b, and p1c may be one volt or more, but the disclosure is not limited thereto.

As in 1 , 2 and 3 As illustrated, the display device 10 in the present embodiment further includes the third transfer element T3 interposed between the element layer 120 of the pixel array substrate 100 and the common electrode 220 of the opposing substrate 200 . The third transmission element T3 is configured on the third common pad p3 and electronically connected to the third common pad p3 and a third part 223 of the common electrode 220 .

In the present embodiment, the third common pad p3 is electrically connected to the driving element through a wire Lp3, and the wire Lp3 is structurally separate from the wires Lp1a, Lp1b, Lp1c, Lp2a, Lp2b, and Lp2c electrically connected to the first common pads p1a , p1b and p1c and the second common pads p2a, p2b and p2c. In other words, the potential of the third common pad p3 can be controlled independently. And the size of the potential of the third common pad p3 can be adjusted according to actual needs.

In the present embodiment, the first transmission element T1, the second transmission element T2, and the third transmission element T3 include a conductive ball (for example, a gold ball), but the disclosure is not limited thereto.

It should be noted that in the following embodiments, the reference numbers and part of the content of the above embodiments are used, and the same reference numbers are used to denote the same or similar elements, with the description of the same technical content being omitted. For the description of the omitted part, the above embodiments can be referred to, and the details thereof will not be described in the following embodiments.

4 10 is a schematic plan view of a pixel array substrate 100A, a first transfer element T1, a second transfer element T2, and a third transfer element T3 according to an embodiment of the disclosure.

The pixel array substrate 100A of FIG 4 is the pixel array substrate 100 of 2 similar. The difference between the two is that in the embodiment of 4 both ends of each second common line CL2 may be electrically connected to a first peripheral line L1 and a second peripheral line L2.

As in 4 1, in the present embodiment, a signal input to the first peripheral line L1 and a signal in gang on the second peripheral line L2 are controlled independently. More specifically, the first peripheral line L1 and the second peripheral line L2 are electrically connected to the driving element via the respective wires L11 and L12, and the wires L11 and L12 are structurally separated from each other. In the present embodiment, for example, a signal input to the first peripheral line L1 and a signal input to the second peripheral line L2 may be selectively the same. For example, a signal input on the first peripheral line L1 and a signal input on the second peripheral line L2 can both be equal to a gate-off signal of the second gate line VG. However, the disclosure is not limited to this. In other embodiments, a signal input on the first peripheral line L1 and a signal input on the second peripheral line L2 can also be different.

5 10 is a schematic plan view of a pixel array substrate 100B and a first transmission element T1 according to an embodiment of the disclosure.

The pixel array substrate 100B 5 is the pixel array substrate 100 from 2 similar. The difference between the two is that in the embodiment of 2 n is equal to 3, that is, each of the first gate lines HG is electrically connected to three second gate lines VG. In the embodiment of 5 however, when n is 4, that is, each of a plurality of first gate lines HG is electrically connected to four second gate lines VG. However, the disclosure is not limited to this. The number (ie, n) of the second gate lines VG electrically connected to each of the first gate lines HG can be determined according to actual requirements.

Specifically, the pixel structures PX are arranged with a number x of pixel columns Cpx and a number y of pixel rows Rpx, the x pixel columns Cpx being arranged in a first direction D1 and the y pixel rows Rpx being arranged in a second direction D2. In the above arrangement, x and y are positive integers greater than 2. Each pixel structure PX has a first width a1 and a second width a2 in the first direction D1 and the second direction D2, respectively. The first width a1 can refer to the following distances: the distance between two adjacent second gate lines VG located respectively on the left and right side of the same pixel structure PX, the distance between a second gate line VG and a first one common line CL1 adjacent to each other and located respectively on the left and right sides of the same pixel structure PX, the distance between two adjacent first common lines CL1 respectively located on the left and right sides of the same pixel structure PX, the distance between a first common line CL1 and a second common line CL2 which are adjacent to each other and located respectively on the left and right sides of the same pixel structure PX, or the distance between a second gate line VG and a second common line CL2 which are adjacent to each other and are each on either side of the same pixel structure PX. The second width a2 may refer to the distance between two adjacent first gate lines HG located on the top and bottom of the same pixel structure PX. If (a1 x+a2 y)< 2000000, then n is preferably 2. If 2000000<(a1 x+a2 y)< 2400000, then n is preferably 3. If 2400000<(a1 x+a2 y)< 3000000, then n is preferably equal to 4. If (a1 x+a2 y)>3000000, then n is preferably equal to 5.

6 10 is a schematic plan view of a pixel array substrate 100C and a first transmission element T1 according to an embodiment of the disclosure.

The pixel array substrate 100C 6 is the pixel array substrate 100 from 2 similar. The difference between the two is that the methods of connecting the second gate lines VG and the first gate lines HG are different.

As in 6 concretely illustrated, in the present embodiment, a plurality of first gate lines HG are sequentially arranged in a second direction D2, the first gate lines HG being an odd number of the first gate lines HG (or first gate lines HG with odd number, odd-number first gate lines) and an even number of the first gate lines HG (or first gate lines HG with an even number, even-number first gate lines). The odd-numbered first gate line HG includes the (1+2*K)-th first gate line HG, where K=0, 1, . . . , p and p is a positive integer 2 or greater. The even-numbered first gate line HG includes the 2L-th first gate line HG, where L=1, 2,..., q and q is a positive integer 3 or more. The second gate lines VG include the first through (p+1)-th second gate lines VG and the (p+2) through (p+q+1)-th second gate lines VG sequentially in the first Are arranged towards D1. The first through (p+1)th second gate lines VG are electrically connected to the (1+2*K)th first gate line HG, respectively, and the (p+2) through (p+q+1 )-th second gate lines VG are electrically connected to the 2L-th first gate line HG, respectively.

For example, in the present embodiment, p=2, K=0, 1, and 2, and the odd-numbered first gate lines HG include the first, third, and fifth first gate lines HG1, HG3, and HG5; q=3, L=1, 2 and 3, the even-numbered first gate lines HG includes the second, fourth and sixth first gate lines HG2, HG4 and HG6; the second gate lines VG include the first to third second gate lines VG1 to VG3 and the fourth to sixth second gate lines VG4 to VG6 arranged in sequence in the first direction D1; the first through third second gate lines VG1 through VG3 are electrically connected to the first, third, and fifth first gate lines HG1, HG3, and HG5, respectively, and the fourth through sixth second gate lines VG4 through VG6 are electrically connected to the second, respectively , fourth and sixth gate lines HG2, HG4 and HG6 are connected. In other words, in the present embodiment, the connection points C of the second gate lines VG among the same second gate line group Gvg and the first gate lines HG (for example, the connection points C of the first to third second gate lines VG1 to VG3 and the first, third and fifth first gate lines HG1, HG3 and HG5 and the connection points C of the fourth to sixth second gate lines VG4 to VG6 and the second, fourth and sixth first gate lines HG2, HG4 and HG6) generally along plural mutually parallel diagonal lines K be distributed.

7 100D is a schematic plan view of a pixel array substrate 100D and a first transmission element T1 according to an embodiment of the disclosure.

The pixel array substrate 100D 7 is the pixel array substrate 100 from 2 similar. The difference between the two is that the methods of connecting the second gate lines VG and the first gate lines HG are different.

In particular, as in 7 1, in the present embodiment, a plurality of first gate lines HG are sequentially arranged in a second direction D2, the first gate lines HG including odd-numbered first gate lines HG and even-numbered first gate lines HG . The odd-numbered first gate lines HG include the (1+2*K)th first gate line HG, where K=0, 1, . . . , p and p is a positive integer 2 or greater. The even-numbered first gate lines HG include the 2Lth first gate line HG, where L=1, 2,..., q and q is a positive integer 3 or more. The second gate lines VG include the first through (p+1)-th second gate lines VG and the (p+2) through (p+q+1)-th second gate lines VG sequentially in the first Are arranged towards D1. The first to (p+1)-th second gate lines VG are electrically connected to the (1+2*K)-th first gate lines HG, respectively, and the (p+1) to (p+q+1 )-th second gate lines VG are electrically connected to the 2L-th first gate line HG, respectively.

For example, in the present embodiment, p=2, K=0, 1, and 2, and the odd-numbered first gate lines HG include the first, third, and fifth first gate lines HG1, HG3, and HG5; q=3, L=1, 2, and 3, the even-numbered first gate lines HG include second, fourth, and sixth first gate lines HG2, HG4, and HG6; the second gate lines VG include the first to third second gate lines VG1 to VG3 and the fourth to sixth second gate lines VG4 to VG6, which are sequentially arranged in the first direction D1; the first through third second gate lines VG1 through VG3 are electrically connected to the first, third, and fifth first gate lines HG1, HG3, and HG5, respectively; and the sixth through fourth second gate lines VG6 through VG4 are electrically connected to the second, respectively , fourth and sixth first gate lines HG2, HG4 and HG6 are connected. In other words, in the present embodiment, a plurality of connection points C of the second gate lines VG between the same second gate line group Gvg and the first gate lines HG (for example, the connection points C of the first to third second gate lines VG1 to VG3 and the first, third and fifth first gate lines HG1, HG3 and HG5 and the connection points C of the sixth to fourth second gate lines VG6 to VG4 and the second, fourth and sixth first gate lines HG2, HG4 and HG6) im Generally distributed in a V-shaped pattern.

Claims (17)

A display device comprising: a first substrate; a plurality of data lines configured on the first substrate and arranged in a first direction; a plurality of first gate lines configured on the first substrate and arranged in a second direction, the first direction crossing the second direction; a plurality of pixel structures configured on the first substrate and electrically connected to the data lines and the first gate lines; a plurality of second gate lines configured on the first substrate, the data lines and the second gate lines being arranged in the first direction and the second gate lines being electrically connected to the first gate lines; a plurality of first common lines configured on the first substrate, wherein the pixel structures are arranged in a plurality of pixel columns, the pixel columns are arranged in the first direction, each of the first common lines and the corresponding second gate line between two adjacent ones pixel columns of the pixel columns are configured, the first common line and the corresponding second gate line are respectively configured on the opposite sides of the first gate line electrically connected to the second gate line, and the first common line and the corresponding second gate line are structurally separated; a second substrate configured to face the first substrate; and a display medium configured between the first substrate and the second substrate. Display device according to claim 1 , wherein a signal of the first common line and a gate-off signal of the second gate line are substantially the same. Display device according to claim 1 , wherein each of the first gate lines is electrically connected to a number n of the second gate lines, n is a positive integer, each of the first gate lines and the n second gate lines have first to n-th connection points, which are sequentially arranged in the first direction, the second gate lines comprise first to n-th second gate line groups sequentially arranged in the first direction, the second gate lines of the m-th second gate line group being the first to n-th second gate line groups and the corresponding first gate lines have an m-th connection point of the first to n-th connection points, where m is a positive integer, and n≥m≥1, and the display device further comprises: a common electrode configured on the second substrate and located between the second substrate and the display medium; a plurality of common pad groups configured on the first substrate and configured to correspond to the first to n-th second gate line groups, respectively, wherein the pixel structures have a first side and a second side corresponding to each other opposite, the common pad groups are configured on the second side of the pixel structures, and each of the common pad groups includes a plurality of first common pads; a plurality of first transmission elements each configured on the first common pads of the common pad groups and electrically connected to the first common pads of the common pad groups and the common electrode; a number of n second common pads configured on the first substrate and configured to correspond to the first to n-th second gate line groups, respectively, and located on the first side of the pixel structures; and a number of n second transmission elements each configured on the n second common pads and electrically connected to the n second common pads and the common electrode, wherein a common pad group of the common pad groups and a second common pad of the n second common pads correspond to the same second gate line group and a potential of the second common pad is larger than a plurality of potentials of the first common pads of the common pad group. Display device according to claim 3 , further comprising: a third common pad configured on the first substrate and located on the first side of the pixel structures, the third common pad and the second common pads being sequentially arranged in the first direction and structurally separated from each other, the third common pad is configured to correspond to the first second gate line group of the first to n-th second gate line groups, and a potential of the third common pad is larger than a plurality of potentials of the corresponding second common pads; and a third transmission element configured on the third common pad and electrically connected to the third common pad and the common electrode. Display device according to claim 1 , further comprising: a plurality of second common lines configured on the first substrate, and the second gate lines and the second common lines are arranged in the first direction, each of the second common lines being configured between two adjacent pixel columns of the pixel columns is; a first peripheral line configured on the first substrate and located on a first side of the pixel structures, the first common lines being electrically connected to the first peripheral line; and a second peripheral line configured on the first substrate and located on a second side of the pixel structures, wherein two ends of each of the second common lines are electrically connected to the first peripheral line and the second peripheral line, respectively. Display device according to claim 1 , the first gate lines comprising odd-numbered first gate lines and even-numbered first gate lines, the odd-numbered first gate lines comprising (1+2*K)th first gate lines, where K =0, 1,..., p and p is a positive integer greater than or equal to 2, the even-numbered first gate lines include 2L-th first gate lines, where L=1, 2,...q and q is a positive integer greater than or equal to 3, wherein the second gate lines are first to (p+1)th second gate lines and (p+2)th to (p+q+1)th second comprise gate lines sequentially arranged in the first direction; wherein the first through (p+1)th second gate lines are electrically connected to the (1+2*K)th first gate line, and the (p+2) through (p+q+1)- th second gate lines are electrically connected to the 2L-th first gate line. Display device according to claim 6 , wherein a plurality of connection points of the first to (p+1)-th second gate lines and the (1+2·K)-th first gate line and a plurality of connection points of the (p+2) to (p+ q+1)-th second gate lines and the 2L-th first gate line are generally distributed along a plurality of diagonal lines parallel to each other. Display device according to claim 6 , wherein a plurality of connection points of the first to (p+1)-th second gate lines and the (1+2·K)-th first gate line and a plurality of connection points of the (p+2) to (p+ q+1)-th second gate lines and the 2L-th first gate line are distributed generally in a V-shaped pattern. A display device comprising: a first substrate; a plurality of data lines configured on the first substrate and arranged in a first direction; a plurality of first gate lines configured on the first substrate and arranged in a second direction, the first direction crossing the second direction; a plurality of pixel structures configured on the first substrate, electrically connected to the data lines and the first gate lines, and arranged in x number of pixel columns and y number of pixel rows, the x pixel columns arranged in the first direction are, the y rows of pixels are arranged in the second direction, x and y being positive integers greater than 2, and the pixel structure has a first width a1 and a second width a2 in the first direction and in the second direction, respectively; a plurality of second gate lines configured on the first substrate, the data lines and the second gate lines being arranged in the first direction and the second gate lines being electrically connected to the first gate lines; a second substrate configured to face the first substrate; and a display medium configured between the first substrate and the second substrate, wherein each of the first gate lines is electronically connected to an n number of the second gate lines; $$\left(\text{a}1\cdot \text{x}+\text{a}2\cdot \text{y}\right)<\mathrm{2000000,}\text{and n}=2;$$

or $$2000000<\left(\text{a}1\cdot \text{x}+\text{a}2\cdot \text{y}\right)<\mathrm{2400000,}\text{and n}=3;$$

or $$2400000<\left(\text{a}1\cdot \text{x}+\text{a}2\cdot \text{y}\right)<\mathrm{3000000,}\text{and n}=4;$$

or $$\left(\text{a}1\cdot \text{x}+\text{a}2\cdot \text{y}\right)>\mathrm{3000000,}\text{and n}=5.$$

Display device according to claim 9 , further comprising: a plurality of first common lines configured on the first substrate, each of the first common lines and the corresponding second gate line being configured between two adjacent pixel columns of the x pixel columns, the first common line and the corresponding second gate line are respectively configured on opposite sides of the first gate line electrically connected to the second gate line, and the first common line and the corresponding second gate line are structurally separated. Display device according to claim 10 , wherein a signal of the first common line and a gate-off signal of the second gate line are substantially the same. Display device according to claim 9 , wherein each of the first gate lines is electrically connected to the n of the second gate lines, n is a positive integer, each of the first gate lines and the n second gate lines have first through n-th connection points, which are in the first direction are sequentially arranged, the two th gate lines comprise first to n-th second gate line groups arranged sequentially in the first direction, the second gate lines of the m-th second gate line group of the first to n-th second gate line groups and the corresponding first gate lines have an mth connection point of the first to nth connection points, where m is a positive integer, and n≥m≥1, and the display device further comprises: a common electrode configured on the second substrate and is located between the second substrate and the display medium; a plurality of common pad groups configured on the first substrate and configured to correspond to the first to n-th second gate line groups, respectively, wherein the pixel structures have a first side and a second side corresponding to each other opposite, the common pad groups are configured on the second side of the pixel structures, and each of the common pad groups includes a plurality of first common pads; a plurality of first transmission elements each configured on the first common pads of the common pad groups and electrically connected to the first common pads of the common pad groups and the common electrode; a number of n second common pads configured on the first substrate and configured to correspond to the first to n-th second gate line groups, respectively, and located on the first side of the pixel structures; and n number of a plurality of second transmission elements each configured on the n second common pads and electrically connected to the n second common pads and the common electrode, wherein a common pad group of the common pad groups and a second common pad of the n second common pads correspond to the same second gate line group and a potential of the second common pad is larger than a plurality of potentials of the first common pads of the common pad group. Display device according to claim 12 , further comprising: a third common pad configured on the first substrate and located on the first side of the pixel structures, the third common pad and the second common pads being sequentially arranged in the first direction and structurally separated from each other, the third common pad is configured to correspond to the first second gate line group of the first to n-th second gate line groups, and a potential of the third common pad is larger than a plurality of potentials of the corresponding second common pads; and a third transmission element configured on the third common pad and electrically connected to the third common pad and the common electrode. Display device according to claim 10 , further comprising: a plurality of second common lines configured on the first substrate, and the second gate lines and the second common lines are arranged in the first direction, each of the second common lines being configured between two adjacent pixel columns of the pixel columns is; a first peripheral line configured on the first substrate and located on a first side of the pixel structures, the first common lines being electrically connected to the first peripheral line; and a second peripheral line configured on the first substrate and located on a second side of the pixel structures, wherein two ends of each of the second common lines are electrically connected to the first peripheral line and the second peripheral line, respectively. Display device according to claim 9 , the first gate lines comprising odd-numbered first gate lines and even-numbered first gate lines, the odd-numbered first gate lines comprising (1+2*K)th first gate lines, where K =0, 1,..., p and p is a positive integer greater than or equal to 2, the even-numbered first gate lines include 2L-th first gate lines, where L=1, 2,...q and q is a positive integer greater than or equal to 3, wherein the second gate lines are first to (p+1)th second gate lines and (p+2)th to (p+q+1)th second comprise gate lines sequentially arranged in the first direction; wherein the first through (p+1)th second gate lines are electrically connected to the (1+2*K)th first gate line, and the (p+2) through (p+q+1)- th second gate lines are electrically connected to the 2L-th first gate line. Display device according to claim 15 , wherein a plurality of connection points of the first to (p+1)-th second gate lines and the (1+2·K)-th first gate line and a plurality of connection points of the (p+2) to (p+ q+1)-th second gate lines and the 2L-th first gate line are generally distributed along a plurality of diagonal lines parallel to each other. Display device according to claim 15 , where a plurality of connection points of the first to (p+1)-th second gate lines and the (1+2·K)-th first gate line, and a plurality of connection points of the (p+2) to (p+q+1)-th second gates lines and the 2L-th first gate line are distributed generally in a V-shaped pattern.

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