TW202044551A - Flash memory with assistant gate and method of fabricating the same - Google Patents

Abstract

A flash memory with assistant gates, including two floating gates disposed on a substrate, an insulating layer formed on the two floating gates and the substrate, an assistant gate disposed between the two floating gates, wherein a portion of the assistant gate wraps around the two floating gates, and two select gates disposed respectively outside the two floating gates and partially overlap the two floating gates.

Description

Flash memory with auxiliary gate and manufacturing method thereof

The present invention relates to a flash memory, and more specifically, it relates to a flash memory structure with an auxiliary gate, which can reduce the operating voltage required by the flash memory.

Flash memory has been in existence for more than 30 years. Unlike volatile memory such as dynamic random access memory (DRAM) or static random access memory (SRAM), flash memory is a kind of Non-volatile memory has a wide range of applications, especially in consumer electronic products, including personal computers, mobile communication products, digital cameras, etc., which need to have the characteristics of small size, large capacity, low power consumption, and modification. Flash memory undoubtedly meets all the above requirements.

Generally, the principle of flash memory writing data (program) is to use hot electron injection or source side injection to write electrons into the floating gate of the memory cell. The gate stores electrons in it like a potential energy well; and erasing data is usually achieved by using the reverse FN tunneling effect. The above-mentioned writing or erasing state will determine the amount of electrons in the floating gate, and then affect the electric field of the channel under the floating gate. Therefore, the data state of the memory cell can be determined according to the magnitude of the read current.

In the operation of flash memory, the coupling ratio of the floating gate will affect the read/write speed of the flash memory, which is related to the overlap area between the floating gate and the source. The greater the coupling rate, the better the operating voltage required by the storage unit. However, with the advancement of process technology, the size of floating gates today is constantly shrinking and has reached the level of nanoscale. Although the cell size of the floating gate continues to shrink, the voltage required for writing and erasing operations has not decreased proportionally. In the advanced generation of process technology, this burden is getting heavier, especially for embedded non-volatile memory applications, the production of high-voltage transistors related to peripheral circuits becomes more and more difficult and expensive, and if Adopting the method of increasing the size of the floating gate to increase the coupling rate will undoubtedly increase the size of the storage unit, which goes against the development premise of the size reduction of electronic components.

In view of the fact that the flash memory in the prior art requires high operating voltage and is not easy to shrink in size, the present invention hereby proposes a novel flash memory structure, which has an additional auxiliary gate to share the required operating voltage, and then Can reduce the size of the memory unit.

One aspect of the present invention is a flash memory with auxiliary gates, comprising a substrate, two floating gates, disposed on the substrate, an insulating layer, and conformally formed on the two floating gates and the substrate, The auxiliary gate is arranged on the insulating layer between the two floating gates, wherein the auxiliary gate partially covers the two floating gates and two selective gates, which are respectively arranged on the insulating layer outside the two floating gates, Part of the selective gate overlaps the floating gate.

Another aspect of the present invention is a method for fabricating a flash memory with auxiliary gates, including providing a substrate with a tunnel oxide layer and a first polysilicon layer in sequence, and performing a first etching The process etches the polysilicon layer and the tunnel oxide layer to form two floating gates, forming a conformal insulating layer on the two floating gates and the substrate, forming a second polysilicon layer on the insulating layer, and performing A second etching process etches the second polysilicon layer to form an auxiliary gate and two selective gates, wherein the auxiliary gate is formed on the insulating layer between the two floating gates, and the auxiliary gate is partially covered To hold the two floating gates, the two selection gates are respectively formed on the insulating layer outside the two floating gates, and the selection gate partially overlaps the floating gate.

Such objects and other objects of the present invention will inevitably become more apparent after readers have read the detailed description of the preferred embodiments described below with various illustrations and drawings.

The exemplary embodiments of the present invention will now be described in detail below, which will illustrate the described features with reference to the accompanying drawings so that the reader can understand and achieve technical effects. Readers will understand that the description in the text is only done by way of illustration, and is not intended to limit the case. The various embodiments of this case and various features in the embodiments that do not conflict with each other can be combined or reset in various ways. Without departing from the spirit and scope of the present invention, modifications, equivalents or improvements to this case are understandable to those skilled in the art and are intended to be included in the scope of this case.

Readers should be able to easily understand that the meaning of "on", "on" and "on" in this case should be interpreted in a broad way, so that "on" not only means "directly on "Something is "on" but also includes something "on" with the meaning of intermediate features or layers in between, and "on" or "on" not only means "on" or "on" something The meaning of "above" can also include the meaning of "above" or "above" something without intervening features or layers (that is, directly on something).

In addition, space-related terms such as "below", "below", "lower", "above", "upper" and other space-related terms may be used herein to describe one element or feature and another for convenience of description. The relationship of one or more elements or features is as shown in the drawings.

As used herein, the term "substrate" refers to a material on which subsequent materials are added. The substrate itself can be patterned. The material added on the top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the whole of the lower or upper structure, or may have a range smaller than the range of the lower or upper structure. In addition, the layer may be a region of a homogeneous or non-homogeneous continuous structure whose thickness is less than that of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal faces at the top and bottom surfaces. The layers can extend horizontally, vertically and/or along inclined surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers on, above, and/or below it. The layer may include multiple layers. For example, the interconnection layer may include one or more conductor and contact layers (where contacts, interconnection lines, and/or vias are formed) and one or more dielectric layers.

In addition, the following methods and structures focus on the formation and characteristics of a single memory cell. In actual production, an entire array of these memory cells is simultaneously formed in the memory cell area of the substrate. Preferably, these memory cells are formed in columns of active areas, which are separated by insulating areas, and the formation of these active areas and insulating areas is a conventional technique.

[Memory structure]

Please refer now to FIG. 1, which is a schematic cross-sectional view of an exemplary flash memory according to a preferred embodiment of the present invention. The flash memory 1 can be constructed on an active area of a cell area in a semiconductor substrate 100. For example, the semiconductor substrate 100 may be a P-type silicon substrate with a plurality of active regions defined by shallow trench isolation (STI) or field oxide structures. Flash memory 1 is formed on these active areas. However, it should be understood that other semiconductor substrates such as silicon-on-insulator (SOI) or epitaxial substrates can also be used in the present invention.

Each flash memory 1 includes two floating gates 102 arranged in pairs on the substrate 100, presenting a mirrored cell group structure. The two floating gates 102 are separated from each other by a certain distance to provide a space for arranging auxiliary gates. A tunnel oxide 104 is formed between the floating gates 102 and the substrate 100 to electrically isolate the floating gates 102 and the substrate 100 from each other. The floating gate 102 may be made of polysilicon material, and the tunnel oxide layer 104 may be a silicon oxide layer. A source electrode 106 is formed in the substrate 100 between the two floating gates 102, and a part of the source electrode 106 overlaps the two floating gates 102 to provide a better coupling ratio of the floating gates 102.

An insulating layer 108 is conformally formed on the two floating gates 102 and the substrate 100. An auxiliary gate 110 is disposed on the insulating layer 108 between the two floating gates 102 and is electrically isolated from the two floating gates 102 by the insulating layer 108. It should be noted that in this embodiment, part of the auxiliary gate 110 will be embedded in the space between the two floating gates 102, and some of the auxiliary gate 110 will overlap the two floating gates 102, so that the auxiliary gate 110 will cover the adjacent residence. Part of the two floating gates 102, so that the auxiliary gate 110 can further improve the coupling rate of the floating gate 102.

The two selection gates 112 are respectively disposed on the insulating layer 108 outside the two floating gates 102, and part of the selection gate 112 overlaps the floating gate 102 to provide an electronic erasing path. Two drain electrodes 114 are respectively formed in the substrate 100 outside the two selector gates 112. Both the auxiliary gate 110 and the selection gate 112 can be formed of polysilicon material, and because they are formed in the same manufacturing process, their top surfaces may be high. The insulating layer 108 can be a silicon oxide layer, which has the same tunneling characteristics as the tunneling oxide layer 104. It should be noted that in this embodiment, the outer corners of the floating gate 102 are formed with upwardly protruding tip parts 116 by a special process. The tip portion 116 overlaps the selector gate 112, which can facilitate the erasing operation of the flash memory.

The foregoing embodiment is the basic structure of the flash memory 1 of the present invention, and its parts are further electrically connected to other external structures to achieve read/write/erase operations. Referring again to Figure 1, in this embodiment, the source 106 of the flash memory 1 is a source line, which is electrically connected to a source line voltage control circuit SLC to control the source line Voltage. The auxiliary gate 110 of the flash memory 1 is electrically connected to an operating voltage control circuit OC to control the voltage of the auxiliary gate 110. In this embodiment, the selector gate 112 of the flash memory 1 is a word line, and the selector gate 112 of each row of memory cells collectively serves as a single word line, which is electrically connected to a word line. The cell line voltage control circuit WLC controls the voltage of the selection gate 112. The drain 114 of the flash memory 1 is electrically connected to a bit line BL, which may be arranged above the entire flash memory 1, and each bit line BL is further connected to a bit line BL. The bit line voltage control circuit (not shown) controls the voltage of the bit line BL and the drain 114 connected to it.

[Mode of operation]

In the program operation of the memory, when the selected memory cell is to be written, 0 volt is applied to its drain 114, and a positive voltage is applied to the select gate 112, which is close to the select gate. The threshold voltage of the MOS structure defined by 112 is approximately 3.3 volts. Both the source 106 and the auxiliary gate 110 are applied with a positive voltage of about 6 volts. The electrons generated from the drain 114 flow from the drain 114 to the source 106 through the channel under the select gate 112 due to the positive voltage of the source 106 and the auxiliary gate 110. When electrons come to the area under the floating gate 102, since the floating gate 102 has a strong capacitive coupling with the source 106 with a higher positive voltage and the auxiliary gate 110, the electrons will be accelerated and pass through the tunnel oxide layer 104 is injected into the floating gate 102, so that the electrons are stored in the selected memory cell, as shown in the path j in Figure 1, which is the principle of source test injection or hot electron injection. In this operation, the source 106 and the auxiliary gate 110 can share the high positive voltage required for writing to the floating gate 102, so the required positive pressure only needs to be half of the conventional technology, which is about 6 volts. In this way, the memory requirements for peripheral high-voltage circuits are not so strict, and the size of the storage unit can be further reduced.

In the read operation of the memory, the source 106 and the auxiliary gate 110 are grounded, the drain 114 is applied with a read voltage of about 1 volt, and the select gate 112 is applied with the supply voltage (Vcc) of the device . In this case, if the floating gate 102 is positively charged (that is, no electrons are stored in the floating gate 102), the channel under the floating gate 102 will be opened, and the channel under the selective gate 112 will also be pressured. The relationship is opened, allowing electrons to flow from the source 106 to the drain 114, so that the memory will be measured as a "1" data state. On the other hand, if the floating gate 102 is negatively charged, the channel under the floating gate 102 will be closed, and no electrons will flow from the source 106 to the drain 114, so the memory will be measured as a "0" data state.

Finally, during the erasing operation of the memory, both the source 106 and the drain 114 are grounded, and a positive voltage of about 6 volts is applied to the selector gate 112. More specifically, a negative pressure is applied to the auxiliary gate 110, which is about -5V. The positive pressure of the selection gate 112 and the negative pressure of the auxiliary gate 110 will cause the electrons in the floating gate 102 to pass through the insulating layer between the floating gate 102 and the selection gate 112 due to the reverse FN tunneling mechanism, as shown in Figure 1. The path k is such that the electrons in the floating gate 102 are emptied and become positively charged. The sharp tip 116 of the floating gate 102 can enhance the reverse FN tunneling mechanism and make the erasing faster. It is worth noting that in this operation, the auxiliary gate 110 also has the effect of sharing the voltage in the same way as the write operation. It is different from the conventional technology which only applies a high positive pressure (such as 10- 12 volts) to erase electrons. The auxiliary gate 110 in this case provides half of the negative pressure on the other side, so that only about half of the positive pressure (ie 6 volts) on the side of the selector gate 112 can achieve FN tunneling. Reduce the demand for peripheral high voltage circuits and further reduce the size of the storage unit.

[Production Method]

Now please refer to FIGS. 2-9 in order, which illustrate a schematic cross-sectional view of the manufacturing process of the flash memory 1 shown in FIG. 1 according to a preferred embodiment of the present invention. First, please refer to Figure 2 to provide a substrate 100, such as a P-type silicon substrate or other semiconductor substrates such as a silicon-coated insulating layer substrate or an epitaxial substrate, on which there may be a plurality of shallow trench isolation structures or field oxidation Active area defined by the structure. Since the fabrication of the above-mentioned active region and isolation structure is not the focus of the present invention, the fabrication process will be omitted here. The substrate shown in the figure is all the active region in the memory cell area. An oxide layer 104a, such as silicon oxide, is formed on the substrate 100. The oxide layer 104a can be formed on the substrate 100 using conventional techniques such as oxidation or deposition (such as chemical vapor deposition, CVD). A polysilicon layer 102a is formed on the top surface of the oxide layer 104a. The polysilicon layer 102a can be deposited on the oxide layer 104a using conventional techniques such as low pressure chemical vapor deposition (LPCVD). A silicon nitride layer 118 is formed on the top surface of the polysilicon layer 102a, which is preferably formed by CVD. In an embodiment, the silicon nitride layer 118 is used to define the floating gate, and an opening 118a is formed on it using photolithography technology to expose the underlying polysilicon layer 102a.

Please refer to Figure 3 next. A thermal oxidation process is performed to oxidize the polysilicon layer 102a exposed from the opening 118a to become the sacrificial oxide layer 120. The sacrificial oxide layer 120 formed by this thermal oxidation step will have a lens-shaped appearance, and the surrounding area close to the silicon nitride layer 118 will gradually shrink and extend slightly below the silicon nitride layer 118. Because of the formation of the sacrificial oxide layer 120, the remaining polysilicon layer 102a will have an inclined surface 102c.

Please refer to Figure 4 next. A selective etching step is performed to remove the silicon nitride layer 118 and the sacrificial oxide layer 120 formed in the foregoing process, and expose the underlying polysilicon layer 102a. In this way, the polysilicon layer 102a will have a surface 102c that is concave downward from both sides, even if the polysilicon layer 102a forms a relatively protruding part.

Please refer to Figure 5 next. An anisotropic etching process is performed using photoresist to define the floating gate 102. This anisotropic etching step will remove the part outside the concave surface 102c of the polysilicon layer 102a and the middle part of the concave surface 102c, so that a mirror image pair as shown in Figure 5 can be formed with sharp tips on the outside. Floating gate 102 at location 116. It should be noted that this step will also remove the portion of the oxide layer 104a under the polysilicon layer 102a, forming a tunnel oxide layer 104 between the floating gate 102 and the substrate 100.

Please refer to Figure 6 next. An ion implantation process is performed to form a source 106 (ie, a source line) in the substrate 100 between the two floating gates 102. During this process, a thermal diffusion process can be used to make the doped source 106 diffuse and extend to the floating gate 102, so that part of the The source 106 overlaps the two floating gates 102 to achieve capacitive coupling. After that, a conformal insulating layer 108 is formed on the surfaces of the two floating gates 102 and the substrate 100. The insulating layer 108 may be formed using processes such as thermal oxidation and/or high temperature oxidation deposition.

Please refer to Figure 7 next. Another thick polysilicon layer 122 is formed on the insulating layer 108, which can be formed by low pressure chemical vapor deposition, and a photoresist 124 is formed on the polysilicon layer 122, wherein the photoresist 124 has predetermined auxiliary gate patterns and select gate patterns , Which exposes part of the polysilicon layer 122.

Please refer to Figure 8 next. Using the photoresist 124 as a mask, perform an anisotropic etching process to remove the exposed polysilicon layer 122, thus forming the auxiliary gate 110 and the selection gate 112 as shown in FIG. 8. It can be seen that the auxiliary gate 110 is formed between the two floating gates 102 and is electrically isolated from the two floating gates 102 by the insulating layer 108. A part of the auxiliary gate 110 is embedded in the space between the two floating gates 102, and a part of the auxiliary gate 110 overlaps the two floating gates 102, so that the auxiliary gate 110 covers the two floating gates 102 adjacent to the residence. The auxiliary gate 110 further improves the coupling rate of the floating gate 102. The two selection gates 112 are respectively disposed on the insulating layer 108 outside the two floating gates 102, and part of the selection gate 112 overlaps the floating gate 102 to provide an electronic erasing path. Due to the formation in the same manufacturing process, the top surfaces of the auxiliary gate 110 and the selection gate 112 may be level. The photoresist 124 can be removed after the auxiliary gate 110 and the selection gate 112 are formed.

Finally, please refer to Figure 9. After the selection gate 112 is formed, another ion implantation process is performed to form the drain electrode 114 in the substrate 100 outside the two selection gates 112, thus completing the basic structure of the flash memory 1 of the present invention. Afterwards, interconnection structures such as contact structures and metal wires can be fabricated to connect the source 106, drain 114, auxiliary gate 110, and select gate 112 to the required voltage control circuits such as bit lines BL, word The cell line voltage control circuit WLC, the source line voltage control circuit SLC, the working voltage control circuit OC, etc., have completed the production of the flash memory 1. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

1: flash memory 100: base 102: Floating gate 102a: Polysilicon layer 102c: surface 104: Tunneling oxide layer 104a: oxide layer 106: Source 108: insulating layer 110: auxiliary brake 112: Select gate 114: Drain 116: Tip 118: silicon nitride layer 118a: opening 120: Sacrificial oxide layer 122: polysilicon layer 124: photoresist BL: bit line OC: Operating voltage control circuit SLC: source line voltage control circuit WLC: Character line voltage control circuit

This specification contains drawings and constitutes a part of this specification in the text, so that readers have a further understanding of the embodiments of the present invention. These figures depict some embodiments of the present invention and together with the description herein explain the principles. In these illustrations: Figure 1 is a schematic cross-sectional view of an exemplary flash memory according to a preferred embodiment of the present invention; and Figures 2-9 are schematic cross-sectional views of the manufacturing process of the flash memory shown in Figure 1 according to a preferred embodiment of the present invention. It should be noted that all the illustrations in this manual are illustrations in nature. For clarity and convenience of illustration, the components in the illustrations may be exaggerated or reduced in size and proportion. Generally speaking, the figures The same reference symbols will be used to indicate corresponding or similar element features in modified or different embodiments.

1: flash memory

100: base

102: Floating gate

104: Tunneling oxide layer

106: Source

108: insulating layer

110: auxiliary brake

112: Select gate

114: Drain

116: Tip

BL: bit line

OC: Operating voltage control circuit

SLC: source line voltage control circuit

WLC: Character line voltage control circuit

Claims (12)

A flash memory with auxiliary gate, including: A base Two floating gates are set on the base; An insulating layer is conformally formed on the two floating gates and the substrate; An auxiliary gate is arranged on the insulating layer between the two floating gates, wherein the auxiliary gate partially covers the two floating gates; Two selective gates are respectively arranged on the insulating layer outside the two floating gates, wherein the selective gate partially overlaps the floating gate. The flash memory with auxiliary gate as described in item 1 of the scope of patent application, further includes: A source electrode formed in the substrate between the two floating gates, wherein the source electrode partially overlaps the two floating gates; and Two drain electrodes are respectively formed in the substrate outside the two selector gates. The flash memory with auxiliary gate as described in the second item of the patent application, wherein the source is a source line, the drain is connected to a bit line, the select gate is a word line, and the auxiliary gate is connected to a Working voltage control circuit. The flash memory with auxiliary gate described in item 3 of the scope of patent application, wherein in the writing operation of the flash memory, the auxiliary gate is connected to the positive voltage provided by the operating voltage control circuit, and the In the erasing operation of the flash memory, the auxiliary gate is connected to the negative voltage provided by the operating voltage control circuit. The flash memory with auxiliary gates as described in the first item of the patent application further includes a tunnel oxide layer formed between the two floating gates and the substrate. As described in the first item of the scope of patent application, the flash memory with auxiliary gate, wherein the corner of the overlapping part of the floating gate and the selective gate has a tip portion protruding upward. As described in the first item of the scope of patent application, the flash memory with auxiliary gate, wherein the auxiliary gate and the two selective gates are composed of the same polysilicon layer and the top surfaces of the two are flush. As described in the first item of the scope of patent application, the flash memory with auxiliary gate, wherein the materials of the floating gate, the auxiliary gate and the selective gate are all polysilicon. A method of making a flash memory with auxiliary gate, including: Providing a substrate with a tunnel oxide layer and a first polysilicon layer in sequence; Performing a first etching process to etch the polysilicon layer and the tunnel oxide layer to form two floating gates; Forming a conformal insulating layer on the two floating gates and the substrate; Forming a second polysilicon layer on the insulating layer; and Perform a second etching process to etch the second polysilicon layer to form an auxiliary gate and two selective gates, wherein the auxiliary gate is formed on the insulating layer between the two floating gates, and the auxiliary gate is partially covered Covering the two floating gates, the two selection gates are respectively formed on the insulating layer outside the two floating gates, and the selection gate partially overlaps the floating gate. The method for manufacturing a flash memory with auxiliary gates as described in item 9 of the scope of patent application, wherein the step of forming the two floating gates further includes: Forming a silicon nitride layer on the first polysilicon layer, wherein the silicon nitride layer has an opening to expose the first polysilicon layer; Performing a thermal oxidation process to oxidize the first polysilicon layer exposed from the opening into a sacrificial oxide layer; and A selective etching process is performed to remove the silicon nitride layer and the sacrificial oxide layer, so that the first polysilicon layer has a surface recessed from both sides. The method for fabricating a flash memory with auxiliary gates as described in claim 10, wherein the first etching process removes a portion of the first polysilicon layer with a concave surface to form an upward protrusion on the outside The two floating gates at the tip. The method of manufacturing a flash memory with auxiliary gate as described in item 9 of the scope of patent application further includes: Performing a first ion implantation process to form a source electrode in the substrate between the floating gates, wherein the source electrode partially overlaps the two floating gates; and A second ion implantation process is performed to respectively form a drain electrode in the substrate outside the two selector gates.

Images