JP2005340297A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a non-volatile memory with a sufficient data retention characteristic and to provide manufacturing technology. <P>SOLUTION: A gate electrode 7A, a contact hole 17 which is opened in a region where a p-type well 4 and an n-type well 5 are separated in a plane and reaches a silicon oxide film 3 in an element separation groove 2, a plug 22 arranged in the contact hole 17, and wiring 25 which is electrically connected to the plug 22, are formed. Thus, the plug 22 and wiring 25 connected to the plug 22 are set to be floating gate electrodes. The gate electrode 7A is set to be a control gate electrode, and a thick silicon oxide film 3 below the plug 22 is set to be a tunnel insulating film in a non-volatile storage element. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and is particularly effective when applied to a semiconductor device having a nonvolatile memory such as an electric batch erase type EEPROM (Electric Erasable Programmable Read Only Memory; hereinafter referred to as a flash memory). It is about technology.

  For example, there is a technique for forming a non-volatile memory without adding another process to a manufacturing process for forming a complementary MISFET (Metal Insulator Semiconductor Field Effect Transistor) (see, for example, Patent Document 1 and Patent Document 2).

Further, there is a technique using a field insulating film for forming an element isolation region as a gate insulating film of a high voltage MISFET (see, for example, Patent Document 3).
JP 9-36261 A JP 2001-257324 A Japanese Patent Laid-Open No. 11-177091

  The inventor is examining a technique for forming a nonvolatile memory without adding another process to the manufacturing process for forming a complementary MISFET. Among them, the present inventors have found the following problems.

  That is, in a semiconductor device in which a complementary MISFET and a nonvolatile memory are mixed on the same semiconductor substrate, in order to make the manufacturing process of the nonvolatile memory completely compatible with the manufacturing process of the complementary MISFET, As the tunnel insulating film between the floating gate electrode and the semiconductor substrate, the same insulating film as the gate insulating film in the complementary MISFET is used. Since the complementary MISFET is being formed more finely, the gate insulating film is also made thinner, and the tunnel insulating film is made thinner as the gate insulating film is made thinner. It is expected that the data retention characteristics of the memory will be insufficient. As a result of examination by the present inventor, for example, in order to guarantee data retention characteristics for about 10 years, it is found that when the tunnel insulating film is a silicon oxide film, it is necessary to have a thickness of about 6 nm at the minimum. It was. Further, as a result of studies by the present inventors, in a complementary MISFET having a gate length of about 90 nm or less, even when the gate insulating film is thick, it is about 7 nm or less, and it is expected that the gate length is about 6 nm or less. Therefore, when the gate insulating film is about 6 nm or less, there is a problem that the film thickness of the tunnel insulating film cannot be secured sufficiently.

  An object of the present invention is to provide a nonvolatile memory having good data retention characteristics and a manufacturing technique thereof.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A semiconductor device according to the present invention includes:
Comprising a non-volatile memory element;
A first well of the first conductivity type and a second well of the second conductivity type formed on the main surface of the semiconductor substrate;
A first insulating film forming an element isolation region on the main surface of the semiconductor substrate;
A first conductive film patterned on the first insulating film;
A second conductive film disposed on the first conductive film via a second insulating film and patterned on the second insulating film;
The first insulating film is a tunnel insulating film of the nonvolatile memory element.

A method for manufacturing a semiconductor device according to the present invention includes:
A method for manufacturing a semiconductor device including a nonvolatile memory element,
(A) forming a first insulating film to be an element isolation region on the main surface of the semiconductor substrate;
(B) forming a first conductivity type first well and a second conductivity type second well on the main surface of the semiconductor substrate;
(C) forming a first conductive film on the main surface of the semiconductor substrate and patterning the first conductive film so as to remain on the first insulating film;
(D) forming a second insulating film on the main surface of the semiconductor substrate in the presence of the first conductive film;
(E) etching the second insulating film to form a first hole reaching the first insulating film in the second insulating film;
(F) forming a second conductive film in the first hole and on the second insulating film, and patterning the second conductive film;
Including
The first well and the second well are formed so as to be separated from each other in a first region under the first insulating film.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, it is possible to manufacture a nonvolatile memory with good data retention characteristics.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
The semiconductor device of the first embodiment has, for example, a nonvolatile memory. The structure of the nonvolatile memory according to the first embodiment will be described together with its manufacturing process with reference to FIGS. In each cross-sectional view in FIG. 1 to FIG.

  First, as shown in FIGS. 1 and 2, an element isolation trench having a depth of about 250 μm to 350 μm is formed in an element isolation region of a main surface of a semiconductor substrate (hereinafter simply referred to as a substrate) 1 made of, for example, p-type single crystal silicon. (Element isolation region) 2 is formed. In order to form the element isolation trench 2, for example, the main surface of the substrate 1 is dry etched to form a trench, and then a silicon oxide film (CVD) is formed on the substrate 1 including the inside of the trench by a CVD (Chemical Vapor Deposition) method. After depositing an insulating film such as the first insulating film 3), unnecessary silicon oxide film 3 outside the groove is polished and removed by a chemical mechanical polishing (CMP) method, thereby removing the inside of the groove. The silicon oxide film 3 is left. By forming the element isolation trench 2, an active region L whose periphery is defined by the element isolation trench 2 is formed on the main surface of the substrate 1. That is, in a region other than the non-volatile memory region described in the first embodiment, for example, a region where a complementary MISFET constituting a logical operation circuit or the like is formed, the silicon oxide film 3 is an element isolation region. Is functioning as

  Next, for example, an n-type (first conductivity type) impurity (for example, P (phosphorus)) is ion-implanted into a part of the substrate 1, and a p-type (second conductivity type) impurity (for example, B (for example, B)) is implanted into the other part. After ion implantation of (boron)), the substrate 1 is heat-treated to diffuse these impurities into the substrate 1, so that a p-type well (second well) 4 and an n-type well (second well) are formed on the main surface of the substrate 1. 1 well) 5 is formed. In FIG. 1, only the outer edge of the p-type well 4 and the n-type well 5 is shown by dotted lines. At this time, in the portion that becomes the channel of the nonvolatile memory element that forms the nonvolatile memory of the first embodiment under the silicon oxide film 3, the p-type well is used in order to lower the threshold voltage of the nonvolatile memory element. 4 and the n-type well 5 are separated from each other. Further, looking at the AA cross section (the cross section in the gate width direction of the n-channel type MISFET Qn) in the Y direction (up and down direction in FIG. 1) in FIG. 1, the p type well 4 is formed up to the bottom of the silicon oxide film 3 in FIG. However, the illustration is omitted in FIG. 1 for the sake of simplicity. Note that the p-type well 4 formed under the silicon oxide film 3 in the A-A cross section in the Y direction suppresses parasitic MOS capacitance generated between the control gate electrode 7A and the semiconductor substrate 1 described later. Is formed.

  In the first embodiment, the example in which the active region is defined by the element isolation trench 2 has been described. However, instead of the element isolation trench 2, a field insulating film 3A as shown in FIG. May be defined. Such a field insulating film 3A is formed by a so-called LOCOS (Local Oxidation of Silicon) method in which a silicon nitride film pattern as an oxidation resistant film is formed on the surface of the substrate 1 serving as an active region, and the surface of the substrate 1 is thermally oxidized. It is possible to form. Further, in the following first embodiment, description will be given using a cross-sectional view in the case where the active region is defined by the element isolation trench 2.

  Next, as shown in FIG. 4, the substrate 1 is thermally oxidized to form gate insulating films 6 made of, for example, silicon oxide on the surfaces of the p-type well 4 and the n-type well 5, respectively. Subsequently, a polycrystalline silicon film 7 is deposited as a first conductive film on the gate insulating film 6 by, eg, CVD.

  Next, as shown in FIGS. 5 and 6, the polycrystalline silicon film 7 is patterned by dry etching using a photoresist film (not shown) patterned by the photolithography technique as a mask to form a gate electrode (first conductive material). ) 7A is formed. Further, by the patterning, the gate electrode 7A is formed in, for example, a planar comb shape. The gate electrode 7A serves as a control gate electrode of the nonvolatile memory element forming the nonvolatile memory according to the first embodiment. Thus, by making the control electrode 7A have a planar comb shape, the coupling capacitance between the control electrode 7A and the floating gate electrode can be set large.

Next, as shown in FIG. 7, phosphorus or arsenic is ion-implanted as an n-type impurity into the n-type well 5 in the active region L, thereby forming a high concentration n ⁺ -type semiconductor region 10. Subsequently, as shown in FIG. 8, a silicon oxide film is deposited on the substrate 1 by the CVD method, and then the silicon oxide film is anisotropically etched, so that the side wall spacer 12 is formed on the side wall of the gate electrode 7A. Form. Subsequently, as shown in FIG. 9, for example, a Co (cobalt) film is deposited on the substrate 1 by a sputtering method. Subsequently, the substrate 1 is heat-treated to cause a silicide reaction at the interface between the Co film and the gate electrode 7A and the interface between the Co film and the n ⁺ type semiconductor region 10, and then the unreacted Co film is removed by etching. To do. Silicide layer 13 is formed on the surface of gate electrode 7A and the surface of n ⁺ type semiconductor region 10. In the first embodiment, the case where the silicide layer 13 is formed using a Co film has been described. However, a silicide layer is formed using a Ti (titanium) film or a Ni (nickel) film instead of the Co film. Also good.

  Next, as shown in FIGS. 10 and 11, as an insulating film covering the gate electrode 7A, a silicon oxide film 15 is deposited by, for example, a CVD method, and then the surface of the silicon oxide film 15 is formed by a chemical mechanical polishing method. Flatten.

Subsequently, the silicon oxide film (second insulating film) 15 is dry-etched using the photoresist film as a mask, so that the contact hole 16 reaching the silicide layer 13 on the surface of the n ⁺ type semiconductor region 10 and the element isolation trench 2 Contact holes 17 and 18 reaching the silicon oxide film 3 therein and a contact hole 19 reaching the silicide layer 13 on the surface of the gate electrode 7A are formed. The contact hole (first hole) 17 is opened in a region (first region) where the p-type well 4 and the n-type well 5 are separated from each other on a plane. When these contact holes 16 to 19 are opened, the silicon oxide film 3 under the contact holes 17 and 18 is also etched by a predetermined amount by over-etching even after the silicon oxide film 15 is etched. , 18 so that the thickness of the silicon oxide film 3 is about 150 μm. Further, as shown in FIG. 12, the contact holes 18 may be formed at a plurality of positions between the gate electrodes 7A having a planar comb shape.

  Next, as shown in FIG. 13, plugs 21 to 24 (the plug 23 is not shown in FIG. 13) are formed in the contact holes 16 to 19, respectively. In order to form the plugs 21 to 24, for example, a Ti (titanium) film and a TiN (titanium nitride) film are deposited on the silicon oxide film 15 including the inside of the contact holes 21 to 24 by a sputtering method, and subsequently, a CVD method is used. After the W (tungsten) film is deposited as the TiN film and the metal film, the W film, the TiN film, and the Ti film outside the contact holes 16 to 19 are removed by a chemical mechanical polishing method. Through the steps so far, the plug (second conductive film) 22 is used as the gate electrode, the n-type well 5 is used as the source and drain, the silicon oxide film 3 is used as the gate insulating film, and the two n-type wells 5 are formed below the plug 22. It is possible to form an n-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a channel in a region where is spaced apart.

  Next, as shown in FIGS. 14 and 15, a plurality of wirings 25 are formed on the silicon oxide film 15 and the plugs 21 to 24. In order to form the wiring 25, for example, a Ti film, an Al (aluminum) alloy film, and a TiN film are sequentially deposited on the silicon oxide film 15 by a sputtering method, and then the Ti film is formed by dry etching using a photoresist film as a mask. Then, the Al alloy film and the TiN film are patterned. By forming the wiring 25, the plug 22 and the wiring (second conductive film) 25 connected to the plug 22 are used as a floating gate electrode, the gate electrode 7A is used as a control gate electrode (control gate electrode), and the silicon oxide film 15 Can be formed as a capacitive insulating film between the floating gate electrode and the control electrode, and a silicon oxide film 3 under the plug 22 as a tunnel insulating film. That is, since a nonvolatile memory element using the thick silicon oxide film 3 as a tunnel insulating film can be formed, a nonvolatile memory with good data retention characteristics can be realized, and for example, data retention characteristics of about 50 years or more are guaranteed. It becomes possible. In addition, the wiring C and the gate electrode 7A as a capacitor electrode, the capacitor C1 using the silicon oxide film 15 as a capacitor insulating film, the plug 23, the plug 22 and the gate electrode 7A as capacitor electrodes, and the silicon oxide film 15 as a capacitor insulating film. Capacitor C2 to be formed. In addition, since the gate electrode 7A is formed in a planar comb shape, the coupling capacitance C2 between the plug 23 (floating gate electrode) and the gate electrode 7A (control gate electrode) can be set large. ing.

  As described above, since the contact hole 17 in which the plug 22 is formed is formed by etching (overetching) the silicon oxide film 3 by a predetermined amount, the film thickness of the silicon oxide film 3 under the plug 22 is as follows. It is thinner than the thickness of the silicon oxide film 3 in other regions. If the silicon oxide film 3 under the plug 22 is not etched by a predetermined amount, the thick silicon oxide film 3 becomes a gate insulating film. Therefore, the control gate is used to turn on or off the n-channel MISFET. Although it is necessary to apply a large voltage (about 20 V or more) to the gate electrode 7A to be an electrode, according to the first embodiment, the gate oxide 7A is small as the film thickness of the silicon oxide film 3 under the plug 22 is reduced. The voltage (about 15V or more) may be sufficient.

  Here, FIG. 16 is an equivalent circuit diagram of the nonvolatile memory element according to Embodiment 1. FIG. In FIG. 16, the capacitance value of the capacitor C is the sum of the capacitance value of the capacitor C1 and the capacitance value of the capacitor C2. The n-channel MISFET Qn is an n-channel MISFET having the plug 22 as a gate electrode and the n-type well 5 as a source and drain. Since the capacitor C3 is also formed between the gate electrode (plug 22) of the n-channel type MISFET Qn and the substrate 1, and the capacitor C and the capacitor C3 are connected in series, the capacitance value of the capacitor C is the capacitance value of the capacitor C3. Is X times (X is an arbitrary number), the voltage applied to the capacitor C is 1 / X of the voltage applied to the capacitor C3. In other words, as the capacitance value of the capacitor C is increased, the voltage applied to the capacitor C3 (the gate electrode (plug 22) of the n-channel MISFET Qn) can be increased. Thereby, the operation speed of the n-channel type MISFET Qn can be improved. As described above, in the first embodiment, the gate electrode 7A has a planar comb shape, and the contact hole 18 reaching the silicon oxide film 3 is opened between the planar comb-shaped gate electrodes 7A. A plug 23 is formed in the hole 18. As a result, it is possible to ensure a sufficiently large capacity electrode for forming the capacity C, and therefore it is possible to ensure a sufficiently large capacity value of the capacity C.

  Next, a data write operation and a read operation in the nonvolatile memory element according to Embodiment 1 will be described with reference to FIGS.

  First, the write operation will be described. At the time of data writing, with the voltage Vd applied to the drain, the voltage Vcd is applied to the control gate (gate electrode 7A), and a current flows between the source and drain of the n-channel MISFET Qn. At this time, hot carriers generated at the drain end penetrate the gate insulating film of the MISFET Qn and are accumulated in the floating gate electrode (the plug 22 and the wiring 25 connected to the plug 22). At this time, Vcd needs to be a bias larger than the threshold voltage (about 10 V) of the n-channel MISFET Qn when carriers are accumulated in the floating gate electrode, for example, about 30 V or more. Further, the efficiency of hot carrier generation can be improved by increasing the voltage Vd applied to the drain to, for example, about 10 V, so that the writing speed can be improved.

  Next, the reading operation will be described. At the time of data reading, a bias slightly larger than the threshold voltage (about 5 V to 6 V) of the n-channel type MISFET Qn at the time of non-writing (when hot carriers are not accumulated in the floating gate electrode (neutral state)), for example A voltage Vcd of about 10 V is applied, and a voltage Vd of about 5 V is applied to the drain to monitor the current flowing between the source and drain. At this time, if the data is erased (neutral), the n-channel MISFET Qn is turned on, and a current flows between the source and drain. On the other hand, in a data write state (a state where hot carriers are accumulated in the floating gate electrode), the threshold voltage of the n-channel MISFET Qn becomes higher than the voltage Vcd, the n-channel MISFET Qn is not turned on, No current flows between the drains. Thereby, the data writing state or the data erasing state is discriminated.

  As an application of the non-volatile memory formed from the non-volatile memory element of the first embodiment, the repair of defective memory cells of a DRAM (Dynamic Random Access Memory) by a redundant configuration can be exemplified. At this time, the memory cell formed from the nonvolatile memory element according to the first embodiment becomes a unit information cell, and a plurality of the unit information cells are collected, and an electrical program for the nonvolatile memory element of the plurality of unit information cells is performed. A circuit is formed, and a plurality of unit information cells serve as storage circuits for repair information for the circuit to be repaired. Thereby, the reliability of defect relief can be increased. It can also be mounted as a relief circuit in a liquid crystal display drive circuit element (LCD driver).

  Further, as another repair information storage circuit for the circuit to be repaired, a fuse program circuit for storing repair information according to the blown state of the fuse element may be further provided. Rescue of defects detected at the wafer stage is performed by a fuse program circuit, and the above-described electrical program circuit is used for defects detected after burn-in, thereby improving the repair efficiency.

  Further, as another use of the nonvolatile memory formed from the nonvolatile memory element of Embodiment 1, it can be exemplified that it is used for gradation adjustment such as luminance of an LCD (Liquid Crystal Display).

(Embodiment 2)
Next, the semiconductor device of the second embodiment will be described. Similar to the semiconductor device of the first embodiment, the semiconductor device of the second embodiment has a nonvolatile memory. Further, the manufacturing process of the semiconductor device according to the second embodiment is almost the same as the manufacturing process of the semiconductor device according to the first embodiment. Therefore, the description of the manufacturing process is omitted in the second embodiment. .

  FIG. 18 is a plan view of a principal part of the semiconductor device according to the second embodiment, and FIG. 19 shows a cross section taken along the line AA in FIG. The second embodiment corresponds to the case where the contact hole 17 (see FIG. 14) cannot be formed in a desired opening shape (opening area) due to the planar pattern of the plurality of wirings 25. In the first embodiment, the contact hole 17 is opened in a pattern that is rectangular in plan (see FIG. 14). However, when the contact hole 17 is opened, the contact hole 17 is made conductive in the contact hole 17 by an etch back or damascene process. In the case of using the process of filling the material, there is a concern that a desired opening area cannot be secured if the contact hole 17 is only allowed to have a specific shape, for example, a pattern that is square on a plane. Therefore, in the second embodiment, the contact hole 17 and the plug 22 are omitted, and a part of the planar comb-like gate electrode 7A is extended to the region where the contact hole 17 was opened in the first embodiment. Thus, the gate electrode 7A is used as a floating gate electrode, and the wiring 25 that has been the floating gate electrode in the first embodiment is used as a control gate electrode. Further, the plug 24 and the wiring 25 that are electrically connected to the gate electrode 7A in the first embodiment are also omitted. As a result, even when the contact hole 17 shown in the first embodiment cannot be formed in a desired opening shape (opening area), a desired nonvolatile memory element can be formed.

  According to the second embodiment as described above, the same effect as in the first embodiment can be obtained.

(Embodiment 3)
Next, the third embodiment will be described.

  FIG. 20 is a main part circuit diagram of the nonvolatile memory element included in the semiconductor device according to the third embodiment of the present invention. As shown in FIG. 20, in the third embodiment, one nonvolatile memory cell is formed by two nonvolatile memory elements, and two nonvolatile memories are connected by connecting two control gates in parallel. The same data can be written to the element. Regarding the reading of data, the logical sum of each nonvolatile memory element is taken. Further, the structure of the nonvolatile memory element of the third embodiment may be either the structure of the nonvolatile memory element of the first embodiment or the nonvolatile memory element of the second embodiment. With such a structure, even if a defect occurs in one of the two nonvolatile memory elements and the written data is volatilized, the data is read if the other nonvolatile memory element is normal. Can do. Thereby, it is possible to improve the reliability of the semiconductor device according to the third embodiment.

(Embodiment 4)
Next, the fourth embodiment will be described.

  FIG. 21 is a main part circuit diagram of the nonvolatile memory element included in the semiconductor device according to the fourth embodiment of the present invention. As shown in FIG. 21, in the fourth embodiment, in addition to the structure shown in the third embodiment, an n-channel MISFET Qn (see FIG. 20) is written and erased by an n-channel MISFET QnW and a read-out. The n-channel MISFETs QnR are divided according to their use, and each of them is arranged, so that one bit portion is obtained from the first nonvolatile memory element used for writing and erasing data and the second nonvolatile memory element used for reading data. The non-volatile memory element (nonvolatile memory cell) is formed. In the configuration in which the write (erase) operation and the read operation are performed by the same n-channel MISFET Qn, the characteristics of the n-channel MISFET Qn deteriorate due to stress applied to the n-channel MISFET Qn during write (erase), and the drain current is reduced during the read operation. There is a concern that the defect may decrease or the leakage current of the gate insulating film of the n-channel type MISFET Qn may increase and the written data may volatilize. Therefore, by performing the write (erase) operation and the read operation with separate n-channel type MISFETs as the structure of the fourth embodiment, it is possible to prevent such a problem.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The semiconductor device and the manufacturing method thereof of the present invention can be applied to, for example, a semiconductor device having a nonvolatile memory and a manufacturing process thereof.

It is a principal part top view explaining the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. It is principal part sectional drawing explaining the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; It is a principal part top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; It is a principal part top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; It is a principal part top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; It is a principal part top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; 1 is an equivalent circuit diagram of a nonvolatile memory element included in a semiconductor device according to a first embodiment of the present invention. It is explanatory drawing which shows the relationship between the gate voltage and drain current in the non-volatile memory element which the semiconductor device which is Embodiment 1 of this invention has. It is a principal part top view of the semiconductor device which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor device which is Embodiment 2 of this invention. It is a principal part circuit diagram of the non-volatile memory element which the semiconductor device which is Embodiment 3 of this invention has. It is a principal part circuit diagram of the non-volatile memory element which the semiconductor device which is Embodiment 4 of this invention has.

Explanation of symbols

1 Semiconductor substrate 2 Element isolation groove (element isolation region)
3 Silicon oxide film (first insulating film)
3A field insulating film 4 p-type well (second well)
5 n-type well (first well)
6 Gate insulating film 7 Polycrystalline silicon film 7A Gate electrode (first conductive film)
10 n ⁺ type semiconductor region 12 Side wall spacer 13 Silicide layer 15 Silicon oxide film (second insulating film)
16 Contact hole 17 Contact hole (1st hole)
18 Contact hole 19 Contact hole 21 Plug 22 Plug (second conductive film)
23 plug 24 plug 25 wiring (second conductive film)
C1, C2 capacitance L active region Qn n-channel type MISFET
QnR n-channel MISFET
QnW n-channel MISFET

Claims (18)

A semiconductor device including a nonvolatile memory element,
A first well of the first conductivity type and a second well of the second conductivity type formed on the main surface of the semiconductor substrate;
A first insulating film forming an element isolation region on the main surface of the semiconductor substrate;
A first conductive film patterned on the first insulating film;
A second conductive film disposed on the first conductive film via a second insulating film and patterned on the second insulating film;
The semiconductor device according to claim 1, wherein the first insulating film is a tunnel insulating film of the nonvolatile memory element. The semiconductor device according to claim 1,
A semiconductor device comprising: a capacitor element having the first conductive film and the second conductive film as capacitive electrodes, and the second insulating film as a capacitive insulating film. The semiconductor device according to claim 2,
The second conductive film is further disposed in a first hole formed in the second insulating film so as to reach the first insulating film,
The first hole is disposed on a first region between the first well and the second well in a plane,
The second conductive film is a floating gate electrode of the nonvolatile memory element;
The semiconductor device, wherein the first conductive film is a control gate electrode of the nonvolatile memory element. The semiconductor device according to claim 3.
The semiconductor device, wherein the second conductive film is disposed so as to surround a side surface and an upper surface of the first conductive film. The semiconductor device according to claim 3.
Under the first hole portion, the thickness of the first insulating film is thinner than other regions. The semiconductor device according to claim 3.
During the write operation of the nonvolatile memory element, a voltage of 30 V or more is applied to the second conductive film,
In the read operation of the nonvolatile memory element, a voltage that is larger than the threshold voltage of the nonvolatile memory element when not written and is about 10 V or less is applied to the second conductive film. Semiconductor device. The semiconductor device according to claim 2,
A portion of the first conductive film is disposed on a first region between the first well and the second well in a plane,
The first conductive film is a floating gate electrode of the nonvolatile memory element;
The semiconductor device, wherein the second conductive film is a control gate electrode of the nonvolatile memory element. The semiconductor device according to claim 7.
The semiconductor device, wherein the second conductive film is disposed so as to surround a side surface and an upper surface of the first conductive film. The semiconductor device according to claim 8.
The semiconductor device, wherein the second conductive film is further disposed in a first hole formed in the second insulating film so as to reach the first insulating film. The semiconductor device according to claim 7.
During the write operation of the nonvolatile memory element, a voltage of 30 V or more is applied to the first conductive film,
In the read operation of the nonvolatile memory element, a first voltage that is higher than the threshold voltage of the nonvolatile memory element when not written and is about 10 V or less is applied to the first conductive film. A featured semiconductor device. The semiconductor device according to claim 2,
A semiconductor device, wherein a plurality of the non-volatile memory elements whose control gate electrodes are connected in parallel form a 1-bit memory cell. The semiconductor device according to claim 2,
The nonvolatile memory element is formed of a first nonvolatile memory element used for writing and erasing data and a second nonvolatile memory element used for reading the data,
The semiconductor device, wherein the first control gate electrode of the first nonvolatile memory element and the second control gate electrode of the second nonvolatile memory element are connected in parallel. The semiconductor device according to claim 11.
A plurality of the nonvolatile memory elements;
The drains of the plurality of first nonvolatile memory elements in the plurality of nonvolatile memory elements are respectively connected in parallel,
The drains of the plurality of second nonvolatile memory elements in the plurality of nonvolatile memory elements are respectively connected in parallel. A method of manufacturing a semiconductor device including a nonvolatile memory element,
(A) forming a first insulating film to be an element isolation region on the main surface of the semiconductor substrate;
(B) forming a first conductivity type first well and a second conductivity type second well on the main surface of the semiconductor substrate;
(C) forming a first conductive film on the main surface of the semiconductor substrate and patterning the first conductive film so as to remain on the first insulating film;
(D) forming a second insulating film on the main surface of the semiconductor substrate in the presence of the first conductive film;
(E) etching the second insulating film to form a first hole reaching the first insulating film in the second insulating film;
(F) forming a second conductive film in the first hole and on the second insulating film, and patterning the second conductive film;
Including
The method of manufacturing a semiconductor device, wherein the first well and the second well are formed so as to be separated from each other in a first region under the first insulating film. 15. The method of manufacturing a semiconductor device according to claim 14,
The method of manufacturing a semiconductor device, wherein the first hole is formed on the first region. In the manufacturing method of the semiconductor device according to claim 15,
In the step (e), overetching is performed so that the first insulating film below the first hole is thinner than the first insulating film in other regions. 15. The method of manufacturing a semiconductor device according to claim 14,
In the step (c), the semiconductor device is manufactured by patterning the first conductive film so as to remain on the first region. 15. The method of manufacturing a semiconductor device according to claim 14,
The method of manufacturing a semiconductor device, wherein the second conductive film is patterned so as to surround a side surface and an upper surface of the first conductive film.

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