JP2007059554A - Semiconductor memory device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device and a manufacturing method therefor which suppress an increase in a parasitic capacity hampering the high-speed operation of a semiconductor memory device in a mask ROM even if the mask ROM is miniaturized in structure, and achieve stable high-speed operation without increasing manufacturing costs. <P>SOLUTION: In the semiconductor memory device, memory cells are formed in a matrix shape, and the output side of each memory cell and a bit line are connected selectively. The semiconductor memory device includes a diode 40 which is formed between the output side 4 of a transistor composing the memory cell and the bit line 8c, and a metal silicide layer 51 which selectively short-circuits the pn junction of the diode 40. The diode 40 and the silicide layer 51 are formed on a semiconductor board 100. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof, and more particularly to a semiconductor memory device having a mask ROM structure and a manufacturing method thereof.

  Mask ROM is known as a semiconductor memory device that can be formed on the same substrate as a semiconductor substrate on which a CMOS transistor circuit is formed without adding a complicated manufacturing process to a general CMOS (Complementary Metal Oxide Semiconductor) process. Yes. The mask ROM is a semiconductor memory device in which a program requested by a user is incorporated by a physical structure by selectively making electrical connection between each memory cell and a bit line in the manufacturing process.

  The mask ROM includes a NAND type that is excellent in high integration and a NOR type that is excellent in high speed. As described above, the mask ROM into which the program is incorporated at the manufacturing stage is formed mainly for the purpose of reading and using the program, so that the NOR type that is advantageous for high-speed operation is often selected.

  FIG. 4 is a circuit diagram showing a memory cell array constituting a NOR type mask ROM. As shown in FIG. 4, in the memory cell array 30, memory cells 31 made of field effect transistors such as MOS (Metal Oxide Semiconductor) type are arranged in a matrix on a semiconductor substrate, and the gates of the columns of the memory cells 31 are arranged. The electrodes are connected to the word line WLk (k is 0 to n), and the drain of each row of the memory cells 31 is selectively, that is, the bit line BLk (k is 0 to n) according to the program to be incorporated. Connected to. Note that the source region of the field effect transistor constituting each memory cell 31 is grounded.

  When reading the program (data) built in the mask ROM configured as described above, an arbitrary transistor constituting the memory cell 31 is selected by the word line WLk and the bit line BLk.

  Here, referring to FIG. 5, a signal of “High (for example, 5V)” is applied to the word line WL1 and the bit line BL1, and a signal of “Low (for example, 0V)” is applied to the other word lines and bit lines. Data reading will be described by taking the transistor T11 located at the coordinates (WL1, BL1), which is selected in this case, as an example. The transistor T11 at the coordinate is turned on because the word line WL1 is “High”, and the bit line BL1 is grounded through the transistor T11. Therefore, a current (broken line in the drawing) flows due to a potential difference generated between the potential of the “High” signal applied to the bit line BL1 and the ground potential of the source region of the transistor T11. As a result, a “Low” signal is output to the output side of the bit line BL1 via the sense amplifier circuit SA1.

  FIG. 6 is a diagram for explaining data reading when a “High” signal is applied to the word line WL1 and the bit line BL2, and a “Low” signal is applied to the other word lines and bit lines. . As shown in FIG. 6, since the transistor T12 located at the selected coordinates (WL1, BL2) is not electrically connected to the bit line BL2, the signal applied to the word line WL1 is “High”. Even if it is “Low”, the bit line BL2 is not grounded via the transistor T12. Therefore, when the transistor T12 is selected, a “High” signal is output to the output side of the bit line BL1 via the sense amplifier circuit SA2.

  As described above, this type of mask ROM determines the data incorporated in the memory cell 31 based on the potential of the bit line BLk, and restores the information written in the memory cell by repeating the above operation. Yes.

  FIG. 7A is a principal circuit diagram of a memory cell array of a semiconductor memory device having a mask ROM having a conventional structure, and FIG. 7B is a schematic cross-sectional view of the circuit portion shown in FIG. is there.

  As shown in FIG. 7B, a common source region 5 for two pairs of MOS transistors is formed in an element region 20 partitioned by an element isolation region 1 such as STI (Shallow Trench Isolation) formed on a semiconductor substrate. A drain region 4 (4a, 4b) corresponding to each MOS transistor is formed. Between the source region 5 and each drain region 4, gate electrodes 3 (3a, 3b) to be word lines WLk are formed. Further, sidewalls 2 made of, for example, a silicon oxide film are formed on both sides of the gate electrode 3.

  In addition, on the element region 20 and the element isolation region 1, the interlayer insulating film 6 (6 a, 6 b, 6 c), the metal wiring 8 (8 a, 8 b, 8 c), and the via holes formed in the interlayer insulating film 6 are filled. The wiring process for forming the contact plugs 7 (7a, 7b, 7c) to be performed is repeated to form a multilayer wiring structure. In this configuration, the mask ROM is configured by selectively connecting the uppermost metal wiring 8c used as the bit line BLk to the drain region 4 of the memory cell 31 according to the program to be stored.

  That is, when the uppermost layer wiring 8c is connected to the drain region 4, via holes and contact plugs 7c are formed in the uppermost interlayer insulating film 6c, and when not connected, the via holes and contact plugs 7c are formed in the uppermost interlayer insulating film 6c. It is the structure which is not formed. With this configuration, when the contact plug 7c exists in the uppermost interlayer insulating film 6c, the uppermost layer wiring 8c used as the bit line BLk and the drain region 4 of the transistor are connected, and the corresponding memory cell 31 is The uppermost layer wiring 8c can be grounded. On the other hand, when the contact plug 7c does not exist in the uppermost interlayer insulating film 6c, the uppermost layer wiring 8c used as the bit line BLk and the drain region 4 of the corresponding transistor are not connected, so that the corresponding memory cell 31 Cannot ground the uppermost layer wiring 8c.

  In this configuration, data can be written into the mask ROM only in one photolithography process using a photomask for forming a via hole in which the contact plug 7c is formed in the uppermost interlayer insulating film 6c. This is a general method for manufacturing a mask ROM.

  By the way, when the miniaturization of the semiconductor device proceeds, the via hole diameter formed in the interlayer insulating film 6 is naturally reduced. At this time, if the via hole diameter is reduced without reducing the thickness of the interlayer insulating film 6, the via hole has an increased aspect ratio, so that the via hole can be completely buried with the conductive film to be the contact plug 7. It becomes difficult. For this reason, the interlayer insulating film 6 is made thinner as the via hole diameter is reduced.

  As described above, whether or not the drain region 4 of a specific transistor is connected to the bit line BLk is determined by whether or not the contact plug 7c is formed in the uppermost interlayer insulating film 6c. Here, when the contact plug 7c is not formed, when the interlayer insulating film 6c is thinned, the parasitic capacitance 9 formed between the uppermost layer wiring 8c (bit line BLk) and the second layer wiring 8b. The capacity value increases. Such a parasitic capacitance 9 reduces the signal propagation speed of the uppermost layer wiring 8c, and thus becomes a problem particularly when access to the memory at a high speed is required. Whether or not the uppermost contact plug 7c is to be formed depends on the data written to the mask ROM. Therefore, the place where the contact plug 7c is not formed (the place where the parasitic capacitance 9 is formed) is uniform over the entire surface of the mask ROM. It is not always distributed. For this reason, the signal propagation speed also varies depending on the position in the mask ROM, and the operation stability of the semiconductor device may be impaired.

  As a countermeasure, as shown in FIG. 8, in the memory cell 31b in which the uppermost layer wiring 8c is not grounded, data writing to the ROM in the manufacturing process is performed not only in the uppermost contact plug 7c but also in the lower layer contact plug 7a, A configuration in which 7b is not formed is also conceivable. According to this configuration, the thickness of the insulating film between the uppermost layer wiring 8c and the drain region 4 of the memory cell is increased, and the parasitic capacitance 9 is reduced.

  As another countermeasure, as shown in FIG. 9, in the memory cell that grounds the uppermost layer wiring 8c and the memory cell that is not grounded, the configuration of the contact plug 7 is the same from the lowermost layer to the uppermost layer. A configuration in which transistors having different threshold voltages are employed for each memory cell 31 has been proposed (see, for example, Patent Document 1). That is, a transistor 12 having a high threshold voltage that does not turn on even when a “High” signal is input to the gate electrode 3 is used as a transistor that constitutes a memory cell in which the bit line is not grounded. A transistor 11 having a threshold voltage that is turned on when a “High” signal is input to the gate electrode 3 is used as a transistor that forms a memory cell that grounds the bit line.

  In this configuration, even if a “High” signal is applied to the word line WLk, the transistor having a higher threshold voltage is not turned on. As a result, the voltage applied to the bit line BLk is output from the sense amplifier circuit SAk. Will be. Therefore, even if the memory cell that grounds the bit line BLk and the memory cell that is not grounded have the same contact plug 7 configuration, a circuit equivalent to the circuit shown in FIG. 4 can be configured.

  In order to increase the threshold voltage of the memory cells, all the memory cells are once formed as the transistors 11 operating at the normal voltage, and then additional ions (N) are passed through the gate electrode 3 from the gate electrode 3 only to a specific transistor. Impurity diffusion regions 13 are formed by implanting P-type impurities in the case of channel type MOS transistors (see FIG. 9). In this process, data is written by adjusting the impurity concentration of the channel region in the transistor formation process, not in the wiring process on the interlayer insulating film 6 as in the above example. Such a parasitic capacitance 9 does not occur.

In the CMOS process in which fine transistors are formed as described above, a P-type silicon film is used as the gate material of the P-channel transistor for the purpose of suppressing the short channel effect generated in the P-channel transistor, and the N-channel A dual gate structure in which an N-type silicon film is used for the gate electrode of the transistor is employed (see, for example, Patent Document 2).
Japanese Patent No. 2542951 Japanese Patent No. 3501211

  In a semiconductor memory device including a mask ROM, a photomask used in photolithography is changed according to the contents of data to be written. In the case shown in FIG. 8, when the data to be written is changed, it is necessary to change the photomask for forming the via hole for a plurality of layers (interlayer insulating films 6a, 6b, 6c). Therefore, when this method is adopted, there arises a problem that the manufacturing cost increases.

  Further, in the method of forming transistors having different threshold voltages shown in FIG. 9, a process for forming a transistor having a large threshold voltage peculiar to the formation of the mask ROM is added to the manufacturing process of the normal CMOS process. Similar to the above, there is a problem that the manufacturing cost increases.

  The present invention has been proposed in view of the above-described conventional circumstances, and in the mask ROM, even when the structure is reduced, the parasitic capacitance that hinders the high-speed operation of the semiconductor memory device is increased. It is an object of the present invention to provide a semiconductor memory device and a method for manufacturing the same, which can suppress the above-described problem and can realize a stable high-speed operation without increasing the manufacturing cost.

  In order to solve the above problems, the present invention employs the following technical means. First, the present invention is premised on a semiconductor memory device in which memory cells are formed in a matrix on a semiconductor substrate, and the output side of each memory cell and a lead-out line are selectively connected. The semiconductor memory device according to the present invention selectively short-circuits the diode formed between the output side of the memory cell and the lead-out line (bit line) on the semiconductor substrate and the PN junction of the diode. A structure including a conductive film.

  When the memory cell is formed of a transistor whose source region is grounded, the diode can be disposed between the drain region of the transistor and a lead-out line.

  The diode is preferably formed on an element isolation region formed on a semiconductor substrate. The diode can be made of a material whose main component is silicon such as polysilicon or amorphous silicon. At this time, the conductive film may be formed of a metal silicide film. For example, the metal silicide film may be a metal silicide containing at least one metal element selected from tungsten, titanium, cobalt, and nickel.

  The above configuration is suitable when the memory cell is mounted on the same semiconductor substrate as the transistor circuit configured by a CMOS process having a dual gate structure.

  According to this configuration, when a memory cell is selected by a word line and a bit line in order to read data written in the mask ROM, the memory cell is connected to the bit line via a diode short-circuited by a conductive film. If they are connected, the bit line is grounded, so that a “Low” signal is output. On the other hand, when the selected memory cell is connected to the bit line through a diode that is not short-circuited by the conductive film, the bit line is not grounded by the diode, so that a signal of “High” is output. Is output.

  In each memory cell, the structural difference is whether or not a conductive film is disposed on the diode. That is, data can be written with one mask that defines whether or not a conductive film is formed over the diode. For this reason, data can be written from a general CMOS process without increasing the number of steps, so that the manufacturing cost does not increase. Furthermore, even if the structure is miniaturized, the parasitic capacitance does not increase with the miniaturization, so that the bit delay of the bit line does not increase unnecessarily, and the mask ROM suitable for high-speed operation A semiconductor memory device including the above can be provided.

  On the other hand, in another aspect, the present invention can provide a method for manufacturing a semiconductor memory device having the above-described configuration. In other words, the method for manufacturing a semiconductor memory device according to the present invention is a method for manufacturing a semiconductor memory device in which memory cells are formed in a matrix on a semiconductor substrate, and the output side of each memory cell and a lead-out line are selectively connected. A step of forming a silicon film on an insulating film formed on a semiconductor substrate; a step of forming a diode made of the silicon film between an output side of each memory cell and the lead-out line; and And selectively forming a conductive film for short-circuiting the PN junction of the diode on the diode.

  According to the present invention, data can be stored in a memory cell depending on whether or not a conductor film is formed on a diode disposed in the opposite direction between the output side of the memory cell and the bit line. For this reason, since each memory cell is connected to the bit line by the same wiring structure, parasitic capacitance is unnecessarily increased even when the structure is miniaturized and the interlayer insulating film is thinned. There is no. In addition, since the parasitic capacitance does not vary depending on the data stored in the memory cell, stable high-speed operation is possible.

  The diode can be formed by a general CMOS process gate electrode forming step, and the conductive film is formed by forming a metal silicide layer on a gate electrode of a general CMOS process and a source region and a drain region of a transistor. Can be formed. Therefore, it can be formed without adding a new process to the manufacturing process of a general CMOS process.

  Furthermore, since the change of the photomask according to the contents of the data to be written is only one mask change for forming the conductor film, the manufacturing cost does not increase.

  Hereinafter, a semiconductor memory device to which the present invention is applied will be described in detail with reference to the drawings. Here, FIG. 1A is a principal circuit diagram of the memory cell portion of the semiconductor memory device according to the embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of the memory cell portion. In the present embodiment, the N-channel transistor includes a gate electrode made of N-type silicon and the P-channel transistor forms a dual gate structure having a gate electrode made of P-type silicon. The apparatus will be described.

  As shown in FIG. 1B, the memory cell of the semiconductor memory device according to the present embodiment has an element region 20 defined by an element isolation region 1 made of STI or the like formed on a semiconductor substrate 100, as in the conventional case. A source region 5 common to a pair of two memory cells and a drain region 4 (4a, 4b) corresponding to a transistor constituting each memory cell are formed. Further, a gate electrode 3 (3a, 3b) to be the word line WLk is formed between the source region 5 and the two drain regions 4a, 4b. Side walls 2 are formed on both sides of the gate electrode 3. In this embodiment, the memory cell is composed of an N channel type transistor.

  Also, a wiring structure comprising a plurality of layers (in this case, three layers) of insulating films 6 (6a, 6b, 6c), metal wirings 8 (8a, 8b, 8c) and contact plugs 9 (9a, 9b, 9c) is also conventional. The same.

  In the present invention, the connection structure between the drain region 4 of the transistors constituting the memory array and the uppermost metal layer 8c (hereinafter referred to as the bit line 8c as appropriate) is different from the conventional one.

  That is, as shown in FIG. 1A and FIG. 1B, in addition to the above-described configuration, a diode 40 (40a, 40b) made of a PN junction is formed on the element isolation region 1, and each diode 40 A sidewall 21 is formed of an insulating film. The drain region 4a has contact plugs 71a and 72a formed in a via hole that penetrates the lowermost interlayer insulating film 6a, and an anode 41 (P-type impurity diffusion) of the diode 40a through an upper wiring 81a of the interlayer insulating film 5a. Connected to region 41). Similarly, the drain region 4b has contact plugs 71b and 72b formed in via holes penetrating the interlayer insulating film 5a, and an anode 41 (P-type impurity diffusion) of the diode 40b via the upper wiring 81b of the interlayer insulating film 6a. Connected to region 41).

  The bit line 8c is disposed in the uppermost layer with a plurality of interlayer insulating films 6 interposed therebetween, and the cathode 42 (N-type impurity diffusion region 42) of the diode 40 is connected to the contact plug 7 penetrating the interlayer insulating film 6. It is configured to be connected to the bit line 8c via the interlayer metal wirings 8a and 8b. Note that the diode 40 is disposed in a state where a reverse voltage is applied when a “High” signal is applied to the bit line.

  Furthermore, in this embodiment, in order to reduce the resistance of the gate electrode 3 composed of a silicon film such as polysilicon or amorphous silicon, and to reduce the contact resistance of the drain region 4 and the source region 5, in the present embodiment, 4 and a metal silicide layer 51 is formed on the upper surface of the source region 5. In addition, the metal silicide layer 51 is selectively formed across the anode 41 and the cathode 42 of the diode 40 according to the stored program. This determines whether or not to connect the drain region 4 of each transistor constituting the memory cell and the bit line 8c. That is, when the metal silicide layer 51 is formed on the diode 40 (in this case, the diode 40a), the anode 42 and the bit line 8c are connected, and as a result, the drain region 4 and the bit line 8c are connected. . On the other hand, when the metal silicide layer 51 is not formed (in this case, the diode 40b), even if the “High” signal is applied to the bit line 8c, a reverse voltage is applied to the diode 40. Thus, a state in which the drain region 4 and the bit line 8c are not connected is formed.

  2 and 3 are process cross-sectional views illustrating the manufacturing process of the semiconductor memory device according to the present embodiment.

As shown in FIG. 2A, first, gate insulation made of silicon nitride (Si ₃ N ₄ ), silicon oxide (SiO ₂ ), or the like is formed on the surface of the semiconductor substrate 100 in which the element isolation region 1 is formed by STI or the like. A film 101 is formed. Thereafter, a polycrystalline silicon film 102 containing no impurity of 150 to 300 nm in thickness is deposited on the element region 20 surrounded by the element isolation region 1 by a normal CVD (Chemical Vapor Deposition) method (FIG. 2B). ). Next, after a resist pattern 103 corresponding to the gate electrodes 3a and 3b and the diodes 40a and 40b is formed on the polycrystalline silicon film 102 by photolithography or the like, the resist pattern 103 is used as an etching mask to make the resist pattern 103 different from the polycrystalline silicon film 102. Isotropic etching is performed to form a pattern 113 corresponding to the gate electrode 3 (hereinafter referred to as the gate portion 113) and a pattern 140 corresponding to the diode 40 (hereinafter referred to as the diode portion 140) (FIG. 2 (FIG. 2). b) → (c)).

  Next, a silicon oxide film 104 having a thickness of 100 to 200 nm is deposited on the entire surface of the semiconductor substrate 100 by LP-CVD (Low Presser-CVD), and this oxide film 104 is anisotropically etched (etched back). Thus, the side wall 2 is formed on the side surface of the gate portion 113 and the side wall 21 is imposed on the side surface of the diode portion 140 (FIG. 2 (d) → (e)).

Subsequently, a resist pattern 105 is formed so as to cover a portion corresponding to a P-type impurity diffusion region 41 (hereinafter referred to as a P layer 41) of the diode 40 and a formation region of a P channel MOS transistor (not shown). N-type impurity ions such as arsenic are ion-implanted with a dose of about 3e15 atoms / cm ^{2 using the} pattern 105, the sidewall 2 and the gate portion 113 as a mask. Thus, an N-type impurity diffusion region 42 (hereinafter referred to as an N layer 42) is formed in the diode portion 140, and a drain region 4 and a source region 5 of the N-channel MOS transistor are formed. At this time, N-type impurities are also introduced into the gate portion 113 to form the gate electrode 3 made of N-type silicon (FIG. 2F).

Next, in order to form a P-type impurity diffusion region on the semiconductor substrate 100, a resist pattern 106 that covers the N channel transistor formation region and the N layer 42 of the diode 40 is formed, and then the resist pattern 106 is used as a mask. P-type impurity ions such as boron are ion-implanted at a dose of about 3e15 atoms / cm ² .

  Through the above process, the source 5 region, the drain region 4 and the gate electrode 3 of each of the N channel transistor and the P channel transistor are formed on the semiconductor substrate 100, and the diode 40 having a PN junction is formed. (FIG. 3A).

  Next, a silicon oxide film having a film thickness of 30 to 50 nm is deposited on the entire surface by LP-CVD, and photolithography and etching are performed on the oxide film, which is selected depending on the transistor formation region and data to be stored. An oxide film pattern 107 having an opening in a region straddling both the P layer 41 and the N layer 42 of the predetermined diode 40 is formed. Thereafter, a silicide forming material 108 made of a refractory metal such as Ti, W, Co, or Ni is deposited on the entire surface, and then a heat treatment is performed to form a metal silicide layer 51 (FIG. 3 (b) → (c)). .

  The process of forming the metal silicide layer 51 on the diode 40 is a process that is necessarily performed in a semiconductor device that forms silicide, and is not a process that is added specifically in the present invention.

  Subsequently, a BPSG (Boro-Phospho-Silicate Glass) film to be the lowermost interlayer insulating film 6a is deposited on the entire surface with a film thickness of 1000 to 2000 nm and flattened by a CMP (Chemical Mechanical Polishing) method or the like. Is done. Then, via holes are formed on the interlayer insulating film 6a by anisotropic etching using a resist pattern having an opening at a via hole forming position as an etching mask, and then tungsten of 200 to 500 nm, for example, is formed on the semiconductor substrate 100 by a CVD method. Deposited on the entire surface. Thereafter, unnecessary tungsten other than tungsten filled in the via hole is removed by CMP to form contact plugs 7, 71, 72 made of tungsten (FIG. 3D).

  Next, a metal film mainly composed of Al and Cu having a film thickness of 300 to 500 nm is deposited on the entire surface by sputtering. At this time, it goes without saying that the upper and lower layers of the metal film are provided with a barrier metal mainly composed of Ti. Next, the metal film is patterned by photolithography and etching to form the lowermost metal wirings 8a and 81 (FIG. 3E). At this time, the P layer 41 of the diode 40 on the element isolation region 1 and the drain region 4 of the transistor constituting the memory cell are connected. Here, as described above, the P layer 41 and the N layer 42 of the diode 40 may or may not be connected by the metal silicide layer 51.

  Next, after a silicon oxide film having a film thickness of 1000 to 3000 nm is deposited on the entire surface by plasma CVD, planarization by CMP is performed to form a second interlayer insulating film 6b. Thereafter, a contact plug 7b made of a via hole, tungsten, or the like is formed in the interlayer insulating film 6b by a method similar to the procedure for forming the contact plug 7a, and further a second-layer metal wiring 8b is formed. The

  Similarly, the uppermost interlayer insulating film 6c and the contact plug 7c are formed, and the uppermost metal wiring 8c is formed thereon, whereby the semiconductor memory device having the structure shown in FIG. 1B is completed. .

  Thereby, the N layer 42 of the diode 40 and the bit line 8c are connected. Here, when the metal silicide layer 51 is formed on the diode 40 across the P layer 41 and the N layer 42, the drain region 4 is directly connected to the bit line 8c. On the other hand, when the metal silicide layer 51 is not formed, a reverse voltage is applied to the diode 40, so that the memory cell and the bit line 8c are disconnected. Therefore, when the metal silicide layer 51 is not formed, the bit line 8c is not grounded when the memory cell is selected.

  As described above, according to the present invention, data is stored in the memory cell depending on whether or not a conductor film is formed on the diode disposed in the reverse direction between the output side of the memory cell and the bit line. Can be made. For this reason, since each memory cell is connected to the bit line by the same wiring structure, parasitic capacitance is unnecessarily increased even when the structure is miniaturized and the interlayer insulating film is thinned. There is no. In addition, since the parasitic capacitance does not vary depending on the data stored in the memory cell, stable high-speed operation is possible.

  The diode can be formed by a general CMOS process gate electrode forming step, and the conductive film is formed by forming a metal silicide layer on a gate electrode of a general CMOS process and a source region and a drain region of a transistor. Can be formed. Therefore, it can be formed without adding a new process to the manufacturing process of a general CMOS process.

  Furthermore, since the change of the photomask according to the contents of the data to be written is only one mask change for forming the conductor film, the manufacturing cost does not increase.

  The present invention is not limited to the embodiments described above, and various modifications and applications are possible within the scope of the effects of the present invention. For example, in the above description, the memory cell is configured by an N-channel transistor, but may be configured by a P-channel transistor. In this case, the diode is formed in a direction in which a reverse bias is applied relatively by a potential applied to the bit line. From the viewpoint of suppressing an increase in parasitic capacitance due to the thinning of the interlayer insulating film when the structure is miniaturized, the diode is not limited to a PN junction diode, and may be a Schottky barrier diode. Any conductive film may be used in place of the metal silicide film.

  In addition, the processes employed in the above steps can be replaced with other equivalent processes without departing from the technical idea of the present invention.

1 is a circuit diagram of a principal part and a schematic cross-sectional view of a semiconductor memory device according to an embodiment of the present invention; Process sectional drawing which shows the manufacturing process of the semiconductor memory device based on one embodiment of this invention Process sectional drawing which shows the manufacturing process of the semiconductor memory device based on one embodiment of this invention Circuit diagram showing a conventional mask ROM Circuit diagram showing read operation of conventional mask ROM Circuit diagram showing read operation of conventional mask ROM Main circuit diagram and schematic cross-sectional view showing a conventional mask ROM Schematic sectional view showing a conventional mask ROM Schematic sectional view showing a conventional mask ROM

Explanation of symbols

1 Device isolation region (STI)
2 Side wall 3 Gate electrode 4 Drain region 5 Source region 6 Interlayer insulating film 7 Contact plug 8 Metal wiring 9 Parasitic capacitance 40 Diode 41 P layer (P-type polycrystalline silicon)
42 N layer (N-type polycrystalline silicon)
51 Metal Silicide Layers BL0 to BLn Bit Lines WL0 to WLn Word Lines SA0 to SAn Sense Amplifier Circuit

Claims (8)

In a semiconductor memory device in which memory cells are formed in a matrix on a semiconductor substrate, and the output side of each memory cell and a lead-out line are selectively connected,
A diode formed on the semiconductor substrate between the output side of the memory cell and a lead-out line;
A conductive film that selectively short-circuits the cathode and anode of the diode;
A semiconductor memory device comprising:   2. The semiconductor memory device according to claim 1, wherein the memory cell is formed of a transistor having a source region grounded, and the diode is disposed between a drain region of the transistor and a lead-out line.   The semiconductor memory device according to claim 1, wherein the diode is formed on an element isolation region formed on the semiconductor substrate.   The semiconductor memory device according to claim 1, wherein a main component of the diode is silicon.   The semiconductor memory device according to claim 4, wherein the conductive film is a metal silicide film.   The semiconductor memory device according to claim 5, wherein the metal silicide film includes at least one metal element selected from tungsten, titanium, cobalt, and nickel.   The semiconductor memory device according to claim 1, wherein the memory cell is mounted on the same semiconductor substrate as a circuit configured by a CMOS transistor having a dual gate structure. A method of manufacturing a semiconductor memory device in which memory cells are formed in a matrix on a semiconductor substrate, and an output side of each memory cell and a lead-out line are selectively connected,
Forming a silicon film on an insulating film formed on a semiconductor substrate;
Forming a diode made of the silicon film between the output side of each memory cell and the lead-out line;
Selectively forming, on the diode, a conductive film that short-circuits the cathode and anode of the diode;
A method for manufacturing a semiconductor memory device.

Images