JPH11297861A - Transistor, transistor array, and semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory cell which is excellent in writing characteristics and capable of minutely produced. SOLUTION: A memory cell 1 comprises source.drain regions 3, a channel region 4, floating gate electrodes 5 and 6, and a control gate electrode 7. The floating gate electrodes 5 and 6 are disposed on the channel region 4 through a gate insulating film 8. A control gate electrode 7 is formed on the floating gate electrodes 5 and 6 through an insulating film 9 and a tunnel insulating film 10 which are formed by a LOCOS (local oxidation of silicon) method. Projections 5a and 6a are formed of an insulating film 9 respectively at the upper centers of the floating gate electrodes 5 and 6. The center of the control gate electrode 7 is arranged on the channel region 4 through the insulating films 8 and 10 to form a selection gate 11. A selection transistor 12 is composed of each source.drain region 3 which sandwich the selection gate 11 between them and the selection gate 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor, a transistor array, and a semiconductor memory.

[0002]

2. Description of the Related Art In recent years, a flash EEPROM (Electrically Erasable and Programmable) has been used as a memory for storing programs and data in portable telephones and portable information terminals.
The range of use of mmableRead Only Memory) is expanding.

[0003] There are a split gate type, a stacked gate type and the like as memory cells constituting a flash EEPROM. FIG. 23 shows a cross-sectional view of a conventional split gate memory cell 201. As shown in FIG. The split gate memory cell (split gate transistor) 201 includes a source region 203, a drain region 204, and a channel region 2
05, a floating gate electrode 206, and a control gate electrode 207.

An N-type source region 203 and a drain region 204 are formed on a P-type single crystal silicon substrate 202. On the channel region 205 sandwiched between the source region 203 and the drain region 204, a floating gate electrode 206 is formed with a gate insulating film 208 interposed. LOCOS (Local Oxidation of Sil
The control gate electrode 207 is formed via an insulating film 209 and a tunnel insulating film 210 formed by the (icon) method. With the insulating film 209, the floating gate electrode 206
A protrusion 206a is formed on the left and right upper edges of the.

Here, part of the control gate electrode 207 is
It is arranged on the channel region 205 via each of the insulating films 208 and 210, and forms a selection gate 211. The select gate 211 and the source region 203 and the drain region 204 form a select transistor 212. That is, the split gate memory cell 201
Are the gate electrodes 206 and 207 and the regions 203 and 20
4 and a select transistor 2
12 are connected in series.

Next, the split gate type memory cell 20
The write operation of writing data, the read operation of reading written data, and the erasing operation of erasing written data will now be described. (A) Write operation (see FIG. 23A) The drain region 204 of the selected memory cell 201
Grounded via a constant current source 310a provided in the sense amplifier 310, and its potential is set to about 1.2V. In addition, each memory cell 2 other than the selected memory cell 201
The potential of the drain region 204 of 01 is set to 3V.

The potential of the control gate electrode 207 of the selected memory cell 201 is set to 2V. The potential of the control gate electrode 207 of each memory cell 201 other than the selected memory cell 201 is set to 0V. All memory cells 2
The potential of the source region 203 of 01 is set to 12V.

[0008] In the memory cell 201, the threshold voltage Vth of the selection transistor 212 is about 0.5V. Therefore, in the selected memory cell 201, the drain region 2
The electrons in 04 move into the channel region 205 in the inverted state. Therefore, the source region 203 moves to the drain region 2
A cell current flows toward 04. On the other hand, source region 2
Since the potential of 03 is 12 V, the potential of the floating gate electrode 206 is raised to near 12 V by the coupling between the source region 203 and the floating gate electrode 206 via the capacitance. Therefore, the channel region 205
A high electric field is generated between the gate electrode 206 and the floating gate electrode 206. Accordingly, the electrons in the channel region 205 are accelerated to become hot electrons, and are injected into the floating gate electrode 206 as shown by an arrow A in FIG. As a result, charges are accumulated in the floating gate electrode 206 of the selected memory cell 201, and 1-bit data is written and stored.

This write operation can be performed for each selected memory cell 201. (B) Read operation (see FIG. 23B) The potential of the drain region 204 of the selected memory cell 201 is set to 2V. In addition, the selected memory cell 201
The potential of the drain region 204 of each of the other memory cells 201 is set to 0V.

The potential of the control gate electrode 207 of the selected memory cell 201 is set to 4V. The potential of the control gate electrode 207 of each memory cell 201 other than the selected memory cell 201 is set to 0V. All memory cells 2
The potential of the source region 203 of 01 is set to 0V.

As will be described later, no charge is stored in the floating gate electrode 206 of the memory cell 201 in the erased state. On the other hand, as described above, charges are accumulated in the floating gate electrode 206 of the memory cell 201 in the written state. Therefore, the channel region 2 immediately below the floating gate electrode 206 of the memory cell 201 in the erased state
05 is on, and the channel region 205 immediately below the floating gate electrode 206 of the memory cell 201 in the written state is off. Therefore, when 4 V is applied to the control gate electrode 207, the drain region 2
The cell current flowing from 04 to the source region 203 is larger in the erased memory cell 201 than in the written memory cell 201.

The value of the data stored in the memory cell 201 can be read by determining the magnitude of the cell current between the memory cells 201 by the sense amplifier 310. For example, reading is performed with the data value of the memory cell 201 in the erased state set to “1” and the data value of the memory cell 201 in the written state set to “0”. In other words, in each memory cell 201, two values of the data value "1" in the erased state and the data value "0" in the written state can be stored, and the data values can be read.

(C) Erasing Operation (See FIG. 23 (c)) The potentials of the drain regions 204 of all the memory cells 201 are set to 0V. The potential of the control gate electrode 207 of the selected memory cell 201 is set to 15V. The potential of the control gate electrode 207 of each memory cell 201 other than the selected memory cell 201 is set to 0V.

Source regions 20 of all memory cells 201
The potential of No. 3 is set to 0V. When the capacitance between the source region 203 and the substrate 202 and the floating gate electrode 206 is compared with the capacitance between the control gate electrode 207 and the floating gate electrode 206, the former is overwhelmingly larger. That is, the floating gate electrode 206 is strongly coupled to the source region 203 and the substrate 202. Therefore, the control gate electrode 207 has a voltage of 15 V and the drain region 204 has a voltage of 0 V.
Even when the potential becomes V, the potential of the floating gate electrode 206 does not change much from 0 V, and the potential difference between the control gate electrode 207 and the floating gate electrode 206 increases, so that each of the electrodes 207, 206
A high electric field is generated therebetween.

As a result, Fowler-Nordheim Tunnel Current (hereinafter, referred to as Fowler-Nordheim Tunnel Current)
FN tunnel current flows, and electrons in the floating gate electrode 206 are drawn out to the control gate electrode 207 side as shown by an arrow B in FIG.
Is erased.

At this time, since the projections 206a are formed at the upper left and right edges of the floating gate electrode 206, electrons in the floating gate electrode 206 jump out of the projections 206a and move to the control gate electrode 207 side. Therefore, the movement of the electrons is facilitated, and the electrons in the floating gate electrode 206 can be efficiently extracted.

Here, a common word line is formed by the control gate electrodes 207 of the memory cells 201 arranged in the row direction. Therefore, the erase operation is performed on all the memory cells 201 connected to the selected word line.

[0018]

In the split gate type memory cell 201, the side wall of the floating gate electrode 206 and the control gate electrode 207 face each other with the tunnel insulating film 210 interposed therebetween. (A)
The capacitance is formed in the portion α) shown in FIG. The coupling between the respective gate electrodes 206 and 207 via the capacitance is caused by the coupling via the capacitance between the source region 203 and the floating gate electrode 206 in the writing operation, whereby the potential of the floating gate electrode 206 is reduced. Acts to prevent lifting. Therefore, it is necessary to reduce the capacitance between each of the gate electrodes 206 and 207 in order to obtain good writing characteristics.
6, the area of the side wall must be reduced. But,
In order to efficiently extract electrons in the floating gate electrode 206 during the erasing operation, a protrusion 206a is formed at the upper left and right edges of the floating gate electrode 206, so that the area of the side wall of the floating gate electrode 206 is reduced. Has limitations.
As described above, the split gate memory cell 201 has a problem that it is difficult to improve the write characteristics.

Further, in order to reduce the chip area of the flash EEPROM, it is necessary to miniaturize each split gate type memory cell constituting the flash EEPROM. However, the split gate memory cell 201
In forming the protrusion 206 a on the floating gate electrode 206, the LOC is formed on the floating gate electrode 206.
When the insulating film 209 is formed by using the OS method, the insulating film 2
A bird's beak formed at the end of the step 09 is used.
Therefore, in order to miniaturize the split gate memory cell 201, it is necessary to narrow the width of the insulating film 209.
It is difficult to form a narrow insulating film 209 using a general LOCOS method. As described above, the split gate memory cell 201 has a problem that miniaturization is difficult.

The present invention relates to a method for manufacturing a transistor, a transistor array, and a semiconductor memory, and an object thereof is to solve the above problems.

[0021]

According to a first aspect of the present invention, there is provided a floating gate electrode having a cross-sectional area larger than a cross-sectional area at one end on a semiconductor substrate; A control gate electrode formed through an insulating film, wherein a capacitance between the floating gate electrode and the semiconductor substrate is set to be larger than a capacitance between the floating gate electrode and the control gate electrode. The gist is that it was done.

According to a second aspect of the present invention, the first and second floating gates share one control gate electrode and are juxtaposed on a channel region between two source / drain regions formed in a semiconductor substrate. An electrode, wherein a capacitance between the first or second floating gate electrode and the semiconductor substrate is larger than a capacitance between the first or second floating gate electrode and the control gate electrode. Set, the first and second
The gist of the present invention is that the floating gate electrode has a portion having a larger cross-sectional area than a cross-sectional area at one end in one direction.

According to a third aspect of the present invention, there is provided a semiconductor device comprising: first and second source / drain regions formed in a semiconductor substrate; and a channel region sandwiched between the first and second source / drain regions. First and second floating gate electrodes juxtaposed on the channel region with a gate insulating film interposed therebetween; and first and second floating gate electrodes formed on the first and second floating gate electrodes with an insulating film interposed therebetween. A control gate electrode shared by a second floating gate electrode, wherein the first floating gate electrode is disposed near a first source / drain region, and wherein the second floating gate electrode is connected to a second source / drain region.・
The capacitance between the first or second floating gate electrode and the semiconductor substrate is arranged in the vicinity of the drain region, and the capacitance between the first or second floating gate electrode and the control gate electrode is The gist of the invention is that the first and second floating gate electrodes are set to have a larger cross-sectional area than a cross-sectional area at one end in one direction.

The gist of the present invention is that a projection is formed on an upper portion of the floating gate electrode except for a peripheral portion, and a control gate electrode is formed on the projection via an insulating film. I do. The invention according to claim 5 is the invention according to claims 1 to 3.
The gist is that in the transistor according to any one of the above, a protrusion is formed on an upper portion except a peripheral portion of the floating gate electrode, and a control gate electrode is formed on the protrusion via an insulating film. .

According to a sixth aspect of the present invention, there is provided a transistor according to any one of the first to fifth aspects, wherein the plurality of transistors are arranged in a matrix and the transistors are arranged in a row direction in the matrix. And a bit line commonly connecting each source / drain region of a plurality of transistors arranged in the matrix in the column direction.

According to a seventh aspect of the present invention, there is provided a semiconductor memory for writing data by injecting electric charge into a floating gate electrode, wherein the transistor according to any one of the first to fifth aspects is used as a memory cell. Then, when performing the data erasing operation by extracting the charge injected into the floating gate electrode to the control gate electrode, it is possible to prevent electrons from jumping out from the protrusion of the floating gate electrode and moving to the control gate electrode side. This is the gist.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings. FIG.
2A shows a memory cell array 10 in a flash EEPROM 101 using the memory cell 1 of the first embodiment.
FIG. 2 is a partial cross-sectional view of FIG.

The memory cell (transistor) 1 includes two source / drain regions 3, a channel region 4, two floating gate electrodes 5, 6, and a control gate electrode 7. An N-type source / drain region 3 is formed on a P-type single crystal silicon substrate 2. On a channel region 4 sandwiched between two symmetrical source / drain regions 3, two floating gate electrodes 5, 6 of the same size and shape are arranged side by side via a gate insulating film 8. The control gate electrode 7 is formed on the floating gate electrodes 5 and 6 via an insulating film 9 and a tunnel insulating film 10 formed by the LOCOS method.
Are formed. The projections 5a and 6a are formed in the upper center of the floating gate electrodes 5 and 6 by the insulating film 9, respectively.

Here, a part of the control gate electrode 7 is disposed on the channel region 4 via the respective insulating films 8 and 10 to form the select gate 11. Each of the source / drain regions 3 sandwiching the selection gate 11 and the selection gate 11 form a selection transistor 12. That is, the memory cell 1 includes floating gate electrodes 5 and 6, a control gate electrode 7, and each source / drain region 3.
One transistor and a selection transistor 12 formed between the transistors are connected in series.

Memory cell array (transistor array)
Reference numeral 102 denotes a plurality of memory cells 1 formed on the substrate 2. For the purpose of keeping the occupied area on the substrate 2 small, each adjacent memory cell 1
The drain regions 3 are arranged in common.

FIG. 1B is a partial plan view of the memory cell array 102 of the first embodiment. In addition, FIG.
FIG. 2 is a sectional view taken along line YY in FIG. A field insulating film 13 is formed on the substrate 2, and the field insulating film 13 performs element isolation between the memory cells 1.

The source / drain regions 3 of the respective memory cells 1 arranged in the vertical direction in FIG.
The source / drain region 3 forms a bit line. The control gate electrode 7 of each memory cell 1 arranged in the horizontal direction in FIG. 1B is common, and the control gate electrode 7 forms a word line.

FIG. 2 shows the overall configuration of a flash EEPROM 101 using the memory cells 1. The memory cell array 102 includes a plurality of memory cells 1 arranged in a matrix. The common word line WL is controlled by the control gate electrodes 7 of the memory cells 1 arranged in the row direction.
1 to WLn are formed. Common bit lines BL1 to BLn are formed by the source / drain regions 3 of each memory cell 1 arranged in the column direction.

That is, in the memory cell array 102, the floating gate electrodes 5 and 6 of the respective memory cells 1 connected to the common word lines WL1 to WLn are arranged in series, and the circuit is arranged in parallel with the common bit lines BL1 to BLn. Connected to the AN
It has a D-NOR type configuration. Each word line WL1 to WLn is connected to a row decoder 103, and each bit line BL1 to BLn
Are connected to the column decoder 104.

A row address and a column address specified from the outside are input to an address pin 105. The row address and the column address are transferred from the address pins 105 to the address latch 107. Of the addresses latched by the address latch 107, the row address is transferred to the row decoder 103 via the address buffer 106, and the column address is transferred to the column decoder 104 via the address buffer 106.

The address latch 107 may be omitted as appropriate. The row decoder 103 includes the address latch 10
7, one word line WL1 to WLn (for example, WLm) corresponding to the row address latched is selected, and the potential of each word line WL1 to WLn is controlled in accordance with each operation mode described later. That is, by controlling the potentials of the word lines WL1 to WLn, the potential of the control gate electrode 7 of each memory cell 1 is controlled.

The column decoder 104 selects one of the bit lines BL1 to BLn (for example, BLm (not shown)) corresponding to the column address latched by the address latch 107, and selects one of the bit lines BL1 to BLn. The potential or the open state is controlled in accordance with each operation mode described later. That is, by controlling the potential or the open state of each of the bit lines BL1 to BLn, the potential or the open state of the source / drain region 3 of each memory cell 1 is controlled.

Data specified externally is input to the data pin 108. The data is transferred to data pin 108
From the column decoder 104 via the input buffer 109
Transferred to The column decoder 104 is connected to each bit line B
The potential or the open state of L1 to BLn is controlled in accordance with the data as described later.

Data read from an arbitrary memory cell 1 is supplied to the column decoder 104 from the bit lines BL1 to BLn.
Is transferred to the sense amplifier 110 via The sense amplifier 110 is a current sense amplifier. Column decoder 1
Reference numeral 04 connects the selected bit lines BL1 to BLn to the sense amplifier 110. The data determined by the sense amplifier 110 is output from the output buffer 111 to the outside via the data pin 108.

The operation of each of the circuits (103 to 111) is controlled by the control core circuit 112. next,
FIG. 1 shows the operation modes (write operation, read operation, and erase operation) of the flash EEPROM 101.
A description will be given with reference to FIGS. 3 to 5 showing only the main part of FIG.

(A) Write operation (see FIG. 3) The memory cell 1 (hereinafter referred to as "1m (m)") connected to the intersection of the word line WLm and each bit line BLm, BLm + 1 is selected. A case where data is written to the floating gate electrode 6 among the floating gate electrodes 5 and 6 of the memory cell 1m (m) will be described.

The bit line BLm corresponding to the source / drain region 3 (hereinafter referred to as “3a”) on the side closer to the floating gate electrode 5 among the source / drain regions 3 of the memory cell 1m (m) is Grounded via a constant current source 110a provided in the sense amplifier 110, the potential of which is about 1.2
V.

The bit line BLm + 1 corresponding to the source / drain region 3 (hereinafter referred to as "3b") on the side closer to the floating gate electrode 6 among the source / drain regions 3 of the memory cell 1m (m). Is set to 10V. In addition, the source of each memory cell 1 other than the selected memory cell 1m (m) is
Each bit line corresponding to the drain region 3 (BL1... BLm-
1, BLm + 2... BLn) are set to 3V.

The potential of word line WLm corresponding to control gate electrode 7 of memory cell 1m (m) is set to 2V. In addition, each word line (WL1... WLm-1,..., WL1) corresponding to the control gate electrode 7 of each memory cell 1 other than the selected memory cell 1m (m).
WLn) are set to 0V.

In the memory cell 1m (m), the threshold voltage Vth of the selection transistor 12 is about 0.5V. Therefore, in the memory cell 1m (m), the source / drain region 3a
The electrons inside move into the channel region 4 in the inverted state. Therefore, cell current Iw flows from source / drain region 3b toward source / drain region 3a. On the other hand, since the potential of the source / drain region 3b is 10 V, the coupling between the source / drain region 3b and the floating gate electrode 6 via the capacitance causes the floating gate electrode 6
Is raised to approach 10V. for that reason,
A high electric field is generated between the channel region 4 and the floating gate electrode 6. Accordingly, the electrons in the channel region 4 are accelerated to become hot electrons, and as shown by an arrow C in FIG.
It is injected into the floating gate electrode 6. As a result, charges are accumulated in the floating gate electrode 6 of the memory cell 1m (m), and 1-bit data is written and stored.

At this time, the potential of the floating gate electrode 5 is raised to about 1.2 V by the coupling between the source / drain region 3a and the floating gate electrode 5 via the capacitance. However, at such a low potential, hot electrons are not substantially injected into the floating gate electrode 5. That is, in the memory cell 1m (m), hot electrons are injected only into the floating gate electrode 6.

The word line WLm and each bit line BLm-
1, a memory cell 1 connected to the intersection with BLm (hereinafter, referred to as a memory cell 1).
The cell current Iw also flows between the source / drain regions 3 of "1 m (m-1)". However, the memory cell 1m (m-
In 1), since the potential of the source / drain region 3 corresponding to the bit line BLm-1 is 3 V, the potentials of the floating gate electrodes 5 and 6 are not raised. for that reason,
Hot electrons are not injected into the floating gate electrodes 5 and 6 of the memory cell 1m (m-1).
No data is written to (m-1). In this case, the cell current Iw may be prevented from flowing by opening only the bit line BLm-1 in advance.

Then, the word line WLm and each bit line BLm
+1 and BLm + 2, the memory cell 1 (hereinafter referred to as “1m (m + 1)”) is connected to the bit line B
The potential of the source / drain region 3 corresponding to Lm + 2 is 3 V
Since the potential is higher than the potential (= 2 V) of the control gate electrode 7 (word line WLm), no cell current flows between the source / drain regions 3. Therefore, the memory cell 1m (m + 1)
Hot electrons are not injected into the respective floating gate electrodes 5 and 6, and no data is written into the memory cell 1m (m + 1).

The memory cells 1 other than the memory cells 1m (m), 1m (m-1) and 1m (m + 1) connected to the word line WLm are also referred to as memory cells 1m (m + 1). For the same reason, no data is written. Therefore, the above-described write operation is performed only on the floating gate electrode 6 of the selected memory cell 1m (m).

Here, the source / drain regions 3b, 3a
By optimizing the value of the cell current Iw flowing therebetween and the time of the write operation (time for injecting hot electrons into the floating gate electrode 6), the value is accumulated in the floating gate electrode 6 of the memory cell 1m (m). Optimize the charge.

More specifically, the amount of electric charge stored in the floating gate electrode 6 of the memory cell 1m (m) is
The amount is set to be smaller than the amount of charge stored in one floating gate electrode 206 so that an overwriting state is not caused. In the write operation, the potential of the source region 203 of the conventional memory cell 201 is set to 12 V, whereas the potential of the source / drain region 3b (bit line BLm + 1) of the memory cell 1m (m) of the present embodiment is set. The potential is set as low as 10 V in order to prevent an overwriting state.

When data is written to the floating gate electrode 6 of the memory cell 1m (m), data may already be written to the floating gate electrode 5. In this case, if a large amount of electric charge is accumulated in the floating gate electrode 5 and the overwriting state occurs, the channel region 4 immediately below the floating gate electrode 5 is completely turned off, and the source-drain regions 3b and 3a No cell current Iw flows. Therefore, when data is written to the floating gate electrode 5, similarly to the case of the floating gate electrode 6, the amount of charge accumulated in the floating gate electrode 5 is reduced so that an overwriting state does not occur. Then, the floating gate electrode 5
Even if data is written in the channel region 4, the channel region 4 immediately below the floating gate electrode 5 is not completely turned off, and the cell current I between the source and drain regions 3b and 3a is not changed.
w flows.

To put it the other way around, the cell current Iw of a value necessary for writing data to the floating gate electrode 6 flows so that
That is, the amount of charge stored in the floating gate electrode 5 is set in advance. That is, the amount of charge stored in the floating gate electrode 6 is set to be small enough to allow the cell current Iw of a value necessary for writing data to the floating gate electrode 5 to flow.

The floating gate electrode 5 of the memory cell 1m (m)
When writing data to the source / drain region 3b
Is grounded via a constant current source 110a provided in the sense amplifier 110, and the potential of the bit line BLm corresponding to the source / drain region 3a is set to 10V. Other potential conditions are the same as in the case where data is written to the floating gate electrode 6 of the memory cell 1m (m).

Therefore, this write operation can be performed for each of the floating gate electrodes 5 and 6 for one selected memory cell 1. (B) Read operation (see FIG. 4) A case where the memory cell 1m (m) is selected and data is read from the floating gate electrode 6 among the floating gate electrodes 5 and 6 of the memory cell 1m (m) will be described. I do.

The potential of the bit line BLm corresponding to the source / drain region 3a of the memory cell 1m (m) is set to 3V.
The potential of the bit line BLm + 1 corresponding to the source / drain region 3b of the memory cell 1m (m) is set to 0V.

Each bit line (BL1... BLm-1, BLm + 2... BLn) corresponding to the source / drain region 3 of each memory cell 1 other than the selected memory cell 1m (m) is opened. Is done. The potential of the word line WLm corresponding to the control gate electrode 7 of the memory cell 1m (m) is set to 4V. In addition, each memory cell 1 other than the selected memory cell 1m (m)
Of the word lines (WL1... W
Lm + 1, WLm + 1... WLn) are set to 0V.

In the memory cell 1m (m), when the source / drain region 3a is set at 3V, the floating gate electrode is coupled by coupling between the source / drain region 3a and the floating gate electrode 5 via the capacitance. The potential of 5 is raised to near 3V. As a result, the channel region 4 immediately below the floating gate electrode 5 is turned on irrespective of the presence or absence of the charge stored in the floating gate electrode 5.

As will be described later, no charge is accumulated in the floating gate electrode 6 in the erased state. On the other hand,
As described above, the floating gate electrode 6 in the written state
Has accumulated electric charge. Therefore, the channel region 4 immediately below the floating gate electrode 6 in the erased state is in the ON state, and the channel region 4 immediately below the floating gate electrode 6 in the written state is close to the OFF state.

Therefore, when 4 V is applied to the control gate electrode 7, the cell current Ir flowing from the source / drain region 3a toward the source / drain region 3b is larger when the floating gate electrode 6 is in the erased state. , In the writing state.

The value of the cell current Ir is applied to the sense amplifier 11
By detecting 0, the value of the data stored in the floating gate electrode 6 of the memory cell 1m (m) can be read. For example, reading is performed with the data value of the floating gate electrode 6 in the erased state being “1” and the data value of the floating gate electrode 6 in the written state being “0”. In this case, the sense amplifier 110 may be connected to the source / drain region 3b to detect the cell current Ir.

The floating gate electrode 5 of the memory cell 1m (m)
When reading data from the source / drain region 3,
The potential of bit line BLm + 1 corresponding to b is set to 3V, and the potential of bit line BLm corresponding to source / drain region 3a is set to 0V. Other potential conditions or open states are the same as in the case where data is read from the floating gate electrode 6 of the memory cell 1m (m).

That is, with respect to the selected memory cell 1m (m), one of the floating gate electrodes 5 and 6 has
Two values (= 1 bit) of the data value “1” in the erased state and the data value “0” in the written state are stored, and the data values can be read. (C) Erasing Operation (See FIG. 5) A case where data stored in the floating gate electrodes 5 and 6 of all the memory cells 1 connected to the word line WLm is erased will be described.

The potential of all bit lines BL1 to BLn is 0V
To be. The potential of the word line WLm is set to 15V. Each word line (WL1... WLm +
1, WLm + 1... WLn) are set to 0V. Comparing the capacitance between each of the source / drain regions 3a and 3b and the substrate 2 and each of the floating gate electrodes 5 and 6, and the capacitance between the control gate electrode 7 and each of the floating gate electrodes 5 and 6, The former is overwhelmingly large. That is, the floating gate electrodes 5 and 6 are strongly coupled to the source / drain regions 3a and 3b and the substrate 2, respectively. Therefore, the control gate electrode 7 has a voltage of 15V and the source / drain regions 3a, 3b
Becomes 0V, the potentials of the floating gate electrodes 5 and 6 remain at 0V.
V, the potential difference between the control gate electrode 7 and each of the floating gate electrodes 5 and 6 increases, and the control gate electrode 7
And a high electric field is generated between the floating gate electrodes 5 and 6.

As a result, an FN tunnel current flows, and FIG.
As shown by the arrow D, electrons in the floating gate electrodes 5 and 6 are extracted to the control gate electrode 7 side, and the data stored in each memory cell 1 is erased. At this time, since the projections 5a and 6a are formed at the upper centers of the floating gate electrodes 5 and 6, electrons in the floating gate electrodes 5 and 6 jump out of the projections 5a and 6a and are controlled. It moves to the gate electrode 7 side. Therefore, the movement of the electrons is facilitated, and the electrons in the floating gate electrodes 5, 6 can be efficiently extracted.

By simultaneously selecting a plurality of word lines WL1 to WLn, an erasing operation can be performed on all the memory cells 1 connected to each word line. The erasing operation of dividing the memory cell array 102 into arbitrary blocks for each of a plurality of sets of word lines WL1 to WLn and erasing data in each block is called block erasing.

Next, a method of manufacturing the memory cell array 102 will be described step by step with reference to FIGS. In addition, FIG.
In FIG. 10, (a) and (b) are (a ′) respectively.
It is a sectional view on the YY line of (b '). Step 1 (see FIGS. 6A and 6A); a field insulating film 13 is formed on the substrate 2 by using the LOCOS method. Next, a gate insulating film 8 made of a silicon oxide film is formed using a thermal oxidation method in a portion (element region) where the field insulating film 13 is not formed on the substrate 2. continue,
On the gate insulating film 8, a doped polysilicon film 21 serving as the floating gate electrodes 5 and 6 is formed. And LPCVD
A silicon nitride film 22 is formed on the entire surface of the doped polysilicon film 21 using a (Low Pressure Chemical Vapor Deposition) method. Next, after applying a photoresist on the entire surface of the silicon nitride film 22, an etching mask 23 is formed by using ordinary photolithography technology.

Step 2 (see FIGS. 6B and 6B): Anisotropic etching using the etching mask 23
The silicon nitride film 22 is etched in a stripe shape.
Then, the etching mask 23 is peeled off. Step 3 (see FIG. 7): The insulating film 9 is formed by oxidizing the doped polysilicon film 21 using the LOCOS method with the striped silicon nitride films 22 as oxidation masks.

At this time, as shown in FIG. 7A, first, the doped silicon film 21 exposed from each of the silicon nitride films 22 etched in a stripe shape is thermally oxidized to form a stripe-shaped insulating film 9. Is done. Then, when the thermal oxidation of the doped silicon film 21 progresses, FIG.
As shown in FIG. 5, the ends of the insulating film 9 penetrate from both ends of each of the silicon nitride films 22 etched in a stripe shape to form a bird's beak 9a. At this time,
When the tips of the bird's beaks 9a that have entered from both ends of each silicon nitride film 22 come into contact with each other, the LOCOS
The thermal oxidation by the method is stopped. Here, each bird's beak 9
a is almost the same, so that each bird's beak 9
The tips of “a” are in contact with each other at the lower surface substantially at the center in the width direction of each silicon nitride film 22 etched in a stripe shape. As a result, the doped polysilicon film 21
Has a wavy shape along the shape of the insulating film 9,
Sharp projections 5a and 6a are formed at portions where the tips of the bird's beaks 9a are in contact with each other.

Step 4 (see FIGS. 8A and 8A): The insulating film 9 and the doped polysilicon are formed by anisotropic etching using each of the silicon nitride films 22 etched in a stripe shape as an etching mask. The film 21 is etched to form a film 24 serving as the floating gate electrodes 5 and 6. Then, each silicon nitride film 22 is removed. The film 24 has a stripe shape in which the floating gate electrodes 5 and 6 arranged in parallel with the source / drain regions 3 are continuous. That is, both side walls of the film 24 become both side walls of the floating gate electrodes 5 and 6. Here, since the projections 5a and 6a are formed on the lower surface of the silicon nitride film 22 etched in a stripe shape at substantially the center in the width direction, the projections 5a and 6a are formed in the width of each film 24 having a stripe shape. It will be formed in the upper center of the direction. Since the upper surface of the doped polysilicon film 21 has a wavy shape along the shape of the insulating film 9, the projection 24 is formed in the film 24 formed by etching the doped polysilicon film 21 in a stripe shape. It will have a shape that is gently inclined from 5a, 6a toward both ends of the film 24 and becomes lower.

Step 5 (see FIGS. 8B and 8B): After a photoresist is applied to the entire surface of the device formed in the above steps, the source / drain region 3 is formed using ordinary photolithography. Is formed with an ion implantation mask 25 for forming a mask. Next, the source / drain regions 3 are formed by implanting N-type impurity ions (phosphorus ions, arsenic ions, etc.) into the surface of the substrate 2 using a normal ion implantation method. After that, the ion implantation mask 25 is peeled off.

At this time, the ion implantation mask 25 is formed so as to cover at least a portion of the substrate 2 where the source / drain regions 3 are not formed, and so as not to protrude from the film 24. As a result, the positions of the source / drain regions 3 are defined by the side walls of the film 24 (that is, the ends of the floating gate electrodes 5 and 6). Step 6 (see FIGS. 9A and 9A); a tunnel insulating film 10 made of a silicon oxide film is formed on the entire surface of the device formed in the above-described steps by using a thermal oxidation method, an LPCVD method, or a combination thereof. I do. Then, the laminated insulating films 8 and 10 and the insulating films 9 and 10 are respectively integrated.

Step 7 (see FIGS. 9B and 9B): A doped polysilicon film 26 serving as the control gate electrode 7 is formed on the entire surface of the device formed in the above steps. still,
The method of forming each of the doped polysilicon films 21 and 26 is as follows. Method 1: When a polysilicon film is formed by using the LPCVD method, a gas containing impurities is mixed into a source gas.

Method 2: After forming a non-doped polysilicon film by using the LPCVD method, an impurity diffusion source layer (such as POCl ₃ ) is formed on the polysilicon film, and an impurity is diffused from the impurity diffusion source layer to the polysilicon film. To spread. Method 3: After forming a non-doped polysilicon film by using the LPCVD method, impurity ions are implanted.

Step 8 (see FIGS. 10A and 10A): After a photoresist is applied to the entire surface of the device formed in the above-described step, each floating gate electrode 5 is formed by using ordinary photolithography technology. , 6 and an etching mask 27 for forming the control gate electrode 7 are formed.

Step 9 (see FIGS. 10B and 10B): The doped polysilicon film 26 and the tunnel insulating film 1 are anisotropically etched using the etching mask 27.
0, the insulating film 9, and the film 24 are simultaneously etched while controlling the etching gas. As a result, the control gate electrode 7 is formed from the doped polysilicon film 26, and the floating gate electrodes 5 and 6 are formed from the film 24.

Then, when the etching mask 27 is removed, the memory cell array 102 is completed. As described above, according to the present embodiment, the following operations and effects can be obtained.

[1] The memory cell 1 has two floating gate electrodes 5 and 6, and each floating gate electrode 5 and 6 is juxtaposed on a channel region 4 sandwiched between two source / drain regions 3. . Each floating gate electrode 5 and 6 shares one control gate electrode 7. One memory cell 1 can store 1-bit data for each of the floating gate electrodes 5 and 6, and can store 2-bit data in total.

Therefore, according to the same design rule, according to the memory cell 1, compared with the conventional memory cell 201,
The occupied area on the substrate per bit can be reduced to about 66%. [2] The common word lines WL1 to WLn are formed by the control gate electrodes 7 of the memory cells 1 arranged in the row direction. That is, each memory cell 1 arranged in the row direction
Are continuous without being separated. Therefore, it is not necessary to consider the dimensional accuracy of the floating gate electrodes 5 and 6 and the control gate electrode 7, so that miniaturization of the memory cell 1 due to the dimensional accuracy is prevented. can do.

[3] Flash E Using Memory Cell 1
Since the EPROM 101 is provided with the selection transistor 12, each of the memory cells 1 has a function of selecting itself. In other words, the floating gate electrode 5,
Even if the charge is extracted too much when extracting the charge from 6,
The channel region 4 can be turned off by the selection gate 12. Therefore, even if excessive erasure occurs, the ON / OFF state of the memory cell 1 can be controlled by the selection transistor 12, and excessive erasure does not pose a problem. That is, the on / off state of the memory cell itself can be selected by the selection transistor 12 provided inside the memory cell 1.

[4] In the memory cell 1, the side walls of the floating gate electrodes 5 and 6 and the control gate electrode 7 face each other with the tunnel insulating film 10 interposed therebetween. ), A capacitance is formed. The coupling between the floating gate electrodes 5 and 6 and the control gate electrode 7 via the capacitance is performed by the coupling between the source region 3 and the floating gate electrodes 5 and 6 via the capacitance in the write operation. The ring acts to prevent the potential of the floating gate electrodes 5 and 6 from being raised. Therefore, it is necessary to reduce the capacitance between the floating gate electrodes 5 and 6 and the control gate electrode 7 in order to obtain good write characteristics.
For that purpose, the area of the side walls of the floating gate electrodes 5 and 6 must be reduced.

In the memory cell 1, the protrusions 5a and 6a formed to efficiently extract electrons from the floating gate electrodes 5 and 6 during the erase operation are arranged at the upper center of the floating gate electrodes 5 and 6. The height is gradually reduced from the protrusions 5a and 6a toward both ends of the floating gate electrodes 5 and 6. Therefore, the height of the side walls of the floating gate electrodes 5 and 6 is
6 is lower than the height from the bottom surface to the vertices of the protrusions 5a, 6a.

On the other hand, in the conventional split gate type memory cell 201, a protrusion 206 a is formed at the upper left and right edges of the floating gate electrode 206. Therefore, the area of the side wall of the floating gate electrodes 5 and 6 in the memory cell 1 is smaller than the area of the side wall of the floating gate electrode 206 in the split gate memory cell 201. Therefore, the capacitance between the floating gate electrodes 5 and 6 in the memory cell 1 and the control gate electrode 7 is equal to the capacitance between the floating gate electrode 206 and the control gate electrode 207 in the split gate memory cell 201. It is smaller than that. As a result, in the memory cell 1, the write characteristics can be improved as compared with the split gate memory cell 201.

[5] As shown in FIG.
Each insulating film 9 formed by the S method is in contact with the lower surface of the silicon nitride film 22 etched in a stripe shape at a substantially central portion in the width direction. Further, as shown in FIG. 8A, the film 24 to be the floating gate electrodes 5 and 6 is formed by anisotropic etching using each silicon nitride film 22 as an etching mask. Therefore, FIG.
The width of each insulating film 9 shown in FIG.
6 is equal to the width between the central portions.

On the other hand, in the conventional split gate memory cell 201, the width of the insulating film 209 is equal to the width of the floating gate electrode 206. Therefore, when the widths of the floating gate electrodes 5 and 6 are equal to the width of the floating gate electrode 206, the width of the insulating film 9 shown in FIG. it can. When the width of the insulating film 9 is equal to the width of the insulating film 209 shown in FIG. 7B, the memory cell 1 can be miniaturized as compared with the split gate memory cell 201. That is, according to the present embodiment, the general LOCOS
The memory cell 1 that can be miniaturized can be obtained while using the method.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to the drawings. In this embodiment, the same components as those in the first embodiment have the same reference numerals, and a detailed description thereof will be omitted.

FIG. 11A is a partial cross-sectional view of a memory cell array 102 in a flash EEPROM 101 using the memory cell 1 of the second embodiment. FIG.
(B) is a partial plan view of the memory cell array 102 of the second embodiment. FIG. 11A is a sectional view taken along line YY in FIG. 11B.

The second embodiment differs from the first embodiment only in that a control gate electrode 7 is formed on each floating gate electrode 5, 6 via an insulating film 31 and a tunnel insulating film 10. is there. Therefore, the operation modes (write operation, read operation, and erase operation) of the flash EEPROM 101 according to the second embodiment are the same as those of the first embodiment, and a description thereof will be omitted.

Next, a method of manufacturing the memory cell array 102 according to the second embodiment will be described step by step with reference to FIGS. In FIGS. 12 to 14, (a)
(B) is a sectional view taken along line YY of (a ') and (b'). Step 1 (not shown); Step 1 of the first embodiment (FIG. 6A)
(See (a ′)) and Step 2 (see FIGS. 6B and 6B).

Step 2 (see FIG. 12): The doped polysilicon film 21 is etched by isotropic etching using each of the silicon nitride films 22 etched in a stripe shape as an etching mask. At this time, FIG.
As shown in (a), first, the doped silicon film 21 exposed from each silicon nitride film 22 etched in a stripe shape is isotropically etched.

Then, as the isotropic etching of the doped silicon film 21 proceeds, as shown in FIG.
Each silicon nitride film 22 etched in a stripe shape
Is etched to form an undercut portion 21a. At this time, the isotropic etching is stopped when the ends of the undercut portions 21a formed at both ends of each silicon nitride film 22 come into contact with each other. Here, since the formation speeds of the respective undercut portions 21a are substantially the same, the end portions of the respective undercut portions 21a are formed on the lower surface of the silicon nitride film 22 etched in a stripe shape at the substantially central portion in the width direction. Will be in contact with you. As a result, the upper surface of the doped polysilicon film 21 is
Of the undercut portions 21a, and the sharp protrusions 5a,
6a is formed.

Step 3 (see FIGS. 13A and 13A); C
Using a VD method, an insulating film 31 made of a silicon oxide film is formed on the entire surface of the device formed in the above steps, and each undercut portion 21a is buried with the insulating film 31. Step 4 (see FIGS. 13B and 13B); an insulating film 31 formed on each silicon nitride film 22 by using the entire surface etch-back method or the CMP (Chemical Mechanical Polish) method.
Is removed, the surface of the device formed in the above process is flattened while each silicon nitride film 22 is left.

Step 5 (see FIGS. 14A and 14A): The insulating film 31 and the doped polysilicon are formed by anisotropic etching using each of the silicon nitride films 22 etched in a stripe shape as an etching mask. The film 21 is etched to form a film 24 serving as the floating gate electrodes 5 and 6. Then, each silicon nitride film 22 is removed. Here, since the upper surface of the doped polysilicon film 21 has a wavy shape along the shape of the undercut portion 21a,
In the film 24 formed by etching the doped polysilicon film 21 in a stripe shape, the protrusions 5a, 6
a is gradually inclined toward both ends of the film 24 from a.

Step 6 (see FIGS. 14 (b) and (b ')); the same as step 5 (see FIGS. 8 (b) and (b')) of the first embodiment. Thereafter, Step 6 of the first embodiment (FIG. 9A)
(See (a ')) to Step 9 (see FIGS. 10 (b) and (b'))
By performing the same processing as described above, the memory cell array 102 of the second embodiment is completed.

As described in detail above, also in the second embodiment, it is possible to obtain the same functions and effects as the above-mentioned [1] to [4] of the first embodiment. Further, since it is easy to form a fine undercut portion 21a in the doped polysilicon film 21 by isotropic etching, according to the second embodiment, it is possible to obtain the memory cell 1 that can be miniaturized. it can.

The above embodiments may be modified as follows, and even in such a case, the same operation and effect can be obtained. (1) As a third embodiment, the method of manufacturing the memory cell array 102 in the first embodiment is changed as follows.

That is, after the protrusions 5a and 6a are formed by forming the insulating film 9 in step 3 of the first embodiment, as shown in FIGS. 15A and 15A, each silicon nitride film 22 is formed. Is removed. Next, FIG.
As shown in (b '), after applying a photoresist on the insulating film 9, an etching mask 32 is formed by using a usual photolithography technique. Here, the etching mask 32 may be formed at the same width and the same position as each silicon nitride film 22, or may be formed at an appropriate width and position. Subsequently, the etching mask 3
The insulating film 9 and the doped polysilicon film 21 are etched by anisotropic etching using 2 to form a film 24 serving as the floating gate electrodes 5 and 6. Subsequent steps are the same as in the first embodiment.

That is, in the step 4 of the first embodiment, the insulating film 9 and the doped polysilicon film 21 are etched using the silicon nitride film 22 as an etching mask, whereas in the third embodiment, the silicon nitride film 22 is After the removal, an etching mask 32 is formed, and the insulating film 9 and the doped polysilicon film 21 are etched using the etching mask 32.

(2) As the fourth embodiment, the method of manufacturing the memory cell array 102 in the first embodiment is changed as follows. That is, after forming the source / drain regions 3 in Step 5 of the first embodiment, FIG.
(A) As shown in (a ′), the insulating film 9 is removed. Next, as shown in FIGS. 16B and 16B, a tunnel insulating film 10 and a doped polysilicon film 26 are sequentially formed on the entire surface of the device formed in the above steps. Subsequent steps are the same as in the first embodiment.

That is, while the insulating film 9 is left in the first embodiment, the tunnel insulating film 10 and the control gate electrode 7 are formed after the insulating film 9 is removed in the fourth embodiment. FIG. 17A shows the fourth manufactured as described above.
Flash EEPROM using the memory cell 1 of the embodiment
FIG. 3 is a partial cross-sectional view of the memory cell array 102 in M101. FIG. 17B is a partial plan view of the memory cell array 102 according to the fourth embodiment. Incidentally, FIG.
FIG. 18 is a sectional view taken along line YY in FIG.

(3) As the fifth embodiment, the method of manufacturing the memory cell array 102 in the first embodiment is changed as follows. That is, after forming the source / drain regions 3 in Step 5 of the first embodiment, FIG.
(A) As shown in (a ′), the insulating film 9 is removed. Next, as shown in FIGS. 18B and 18B, a tunnel insulating film 33 made of a silicon oxide film is formed on the entire surface of the device formed in the above process by using the CVD method. At this time, the tunnel insulating film 33 is deposited until each film 24 is completely covered with the tunnel insulating film 33. Then, the surface of the tunnel insulating film 33 is planarized by using the entire surface etch back method or the CMP method. At this time,
The thickness of the tunnel insulating film 33 remaining on the protrusions 5a and 6a is adjusted so that a favorable erase operation can be performed. Subsequently, a doped polysilicon film 26 is formed on the tunnel insulating film 33. Subsequent steps are the same as in the first embodiment.

That is, in the first embodiment, the tunnel insulating film 10 is formed with the insulating film 9 left, whereas in the fifth embodiment, the tunnel insulating film 33 is formed after removing the insulating film 9. The device surface is flattened by the tunnel insulating film 33. Therefore, according to the fifth embodiment, it is possible to eliminate the step of the control gate electrode 7 formed on the tunnel insulating film 33, and the control gate electrode 7
Disconnection can be prevented.

FIG. 19A shows a flash EEP using the memory cell 1 of the fifth embodiment manufactured as described above.
FIG. 2 is a partial cross-sectional view of a memory cell array 102 in a ROM 101. FIG. 19B is a partial plan view of the memory cell array 102 according to the fifth embodiment. FIG. 19 (a)
FIG. 20 is a sectional view taken along line YY in FIG.

(4) As the sixth embodiment, the method of manufacturing the memory cell array 102 in the first embodiment is changed as follows. That is, after forming the source / drain regions 3 in Step 5 of the first embodiment, FIG.
(A) As shown in (a ′), a tunnel insulating film 33 made of a silicon oxide film is formed on the entire surface of the device formed in the above-described process by using the CVD method. At this time, the tunnel insulating film 33 is deposited until the films 24 and the insulating film 9 are completely covered by the tunnel insulating film 33. Next, as shown in FIGS. 20 (b) and 20 (b '), each insulating film 1 is etched by using the whole-surface etch-back method or the CMP method.
The surface of 0,33 is flattened. At this time, the thickness of the tunnel insulating film 33 remaining on the protrusions 5a and 6a is adjusted so that a good erase operation can be performed. Subsequently, each insulating film 10,
A doped polysilicon film 26 is formed on 33. Subsequent steps are the same as in the first embodiment.

That is, in the fifth embodiment, the tunnel insulating film 33 is formed with the insulating film 9 removed, while
In the sixth embodiment, the tunnel insulating film 33 is formed with the insulating film 9 left. Therefore, also in the sixth embodiment,
By flattening the device surface with the tunnel insulating film 33, it is possible to eliminate a step of the control gate electrode 7 formed on the tunnel insulating film 33, and to prevent disconnection of the control gate electrode 7.

FIG. 21A shows a flash EEPROM using the memory cell 1 of the sixth embodiment manufactured as described above.
FIG. 2 is a partial cross-sectional view of a memory cell array 102 in a ROM 101. FIG. 21B is a partial plan view of the memory cell array 102 according to the sixth embodiment. FIG. 21 (a)
FIG. 22 is a sectional view taken along line YY in FIG.

(5) As a seventh embodiment, as shown in FIG. 22, a projection 206 is formed at the upper center of the floating gate electrode 206 in the conventional split gate memory cell 201.
a is formed. The method of forming the protrusion 206a is the first or second method.
This is the same as the protrusions 5a and 6a in the second embodiment.
The operation modes (write operation, read operation, erase operation) in the seventh embodiment are the same as those of the conventional split gate memory cell 201. By doing so, the same operation and effect as the above [4] and [5] of the first embodiment can be obtained.

(6) Each of the insulating films 8, 10, and 33 is replaced with another insulating film containing at least one of silicon oxide, silicon oxynitride, and silicon nitride as a main component. The insulating film is formed by thermal oxidation, thermal nitridation, thermal oxynitridation, CV
At least one of the methods D may be used. Further, a structure in which a plurality of these different insulating films are stacked is replaced.

(7) The tunnel insulating film 33 is replaced with a coating insulating film (an SOG (Spin On Glass) film, a polyimide film, or the like). This makes it possible to omit the step of flattening the surface of the tunnel insulating film 33 in the fifth embodiment. (8) The material of each of the gate electrodes 5 to 7 is replaced with a conductive material other than doped polysilicon (amorphous silicon, single crystal silicon, various metals including refractory metals, metal silicide, etc.).

(9) The P-type single crystal silicon substrate 2 is replaced with a P-type well. (10) The P-type single-crystal silicon substrate 2 is replaced with an N-type single-crystal silicon substrate or an N-type well, and P ions are implanted to form the source / drain regions 3.
Type impurity ions (boron, indium, etc.) are used.

(11) In the method of manufacturing the memory cell array 102 of the first, second, fourth to sixth embodiments, after the ion implantation for forming the source / drain regions 3 is completed,
Each silicon nitride film 22 etched in a stripe shape
Is removed. (12) In the first to seventh embodiments, the protrusions 5a, 6a,
206a, the floating gate electrodes 5, 6,
The protrusions 5a, 6a, and 206a may be provided at arbitrary positions above the floating gate electrodes 5, 6, 206 except for the upper left and right edges so that the area of the side wall of the floating gate 206 does not increase.

(13) In the first to seventh embodiments, the protrusions 5a, 6a, 206a of the floating gate electrodes 5, 6, 206
Need not necessarily be sharp, and the floating gate electrode 5,
As long as the electrons in 6, 206 can move to the control gate electrodes 7, 207, the tips of the projections 5a, 6a, 206a may have a gentle shape.

(14) In the first to seventh embodiments, protrusions 5a, 6a, 206a of floating gate electrodes 5, 6, 206
Is not always necessary, and the floating gate electrodes 5, 6, 20
6 has a portion having a cross-sectional area larger than the cross-sectional area at one end in one direction, so that the floating gate electrodes 5, 6,
The capacitance between the control gate electrode 206 and the control gate electrodes 7 and 207 may be reduced. For example, the floating gate electrodes 5, 6, and 206 may have a trapezoidal cross section, a semicircular cross section, or a triangular cross section.

The embodiments have been described above. However, technical ideas other than the claims that can be grasped from the embodiments will be described. (A) first and second symmetrical source / drain regions formed in a semiconductor substrate, a channel region sandwiched between the first and second source / drain regions, and First and second floating gate electrodes of the same size and shape juxtaposed via a gate insulating film, and first and second floating gate electrodes formed on the first and second floating gate electrodes via an insulating film; And a control gate electrode shared by the first floating gate electrode, the first floating gate electrode is disposed near a first source / drain region, and the second floating gate electrode is connected to a second source / drain A capacitance between the first or second floating gate electrode and the semiconductor substrate, and a capacitance between the first or second floating gate electrode and the control gate electrode. Set larger than Is, transistor protrusion is formed on the upper excluding the peripheral edge portion of the first and second floating gate electrodes.

(B) The transistor according to any one of claims 1 to 5, wherein a part of said control gate is arranged on a channel region to form a selection gate. (C) An AND-NOR type configuration in which each floating gate electrode of each transistor connected to the common word line is arranged in series and its circuit is connected in parallel to a common bit line. The transistor array according to claim 1.

(D) A semiconductor memory in which data is written by injecting electric charge into a floating gate electrode, wherein the transistor according to any one of (1) to (c) is used as a memory. When used as a cell, when the charge injected into the floating gate electrode is drawn out to the control gate electrode to perform a data erase operation, electrons jump out of the protrusion of the floating gate electrode and move to the control gate electrode side. Semiconductor memory.

(E) The steps of forming a gate insulating film on a semiconductor substrate, forming a silicon film on the gate insulating film, and forming a plurality of insulating films on the silicon film by using the LOCOS method Stopping the thermal oxidation when the tips of the bird's beaks of the insulating films come into contact with each other, thereby forming a projection in the portion of the silicon film where the tips of the bird's beaks are in contact, and patterning the silicon film. Forming a floating gate electrode having a projection formed thereon except for a peripheral portion, forming an insulating film on the floating gate electrode, and forming a control gate electrode on the insulating film. Method of manufacturing a transistor.

(F) a step of forming a gate insulating film on a semiconductor substrate, a step of forming a silicon film on the gate insulating film, and forming a plurality of etching masks on the silicon film; When performing isotropic etching by using, the isotropic etching is stopped when the ends of the undercut portions formed under the respective etching masks come into contact with each other, so that the under film in the silicon film is removed. Forming a protruding portion at a portion where the ends of the cut portions are in contact with each other; patterning the silicon film to form a floating gate electrode having a protruding portion formed at an upper portion excluding a peripheral portion; A method for manufacturing a transistor, comprising: a step of forming an insulating film thereon; and a step of forming a control gate electrode on the insulating film.

(G) When writing data by injecting charges into the second floating gate electrode, a cell current flows from the second source / drain region to the first source / drain region, 2 source / drain regions and 2nd
A high electric field is generated between the channel region and the second floating gate electrode due to coupling between the floating gate electrode and the second floating gate electrode, and electrons are accelerated to become hot electrons, so that the second floating gate electrode is formed. The charge is stored in the second floating gate electrode by being injected into the gate electrode, and data corresponding to the charge is written and stored. 14. The transistor according to item 5.

(H) The coupling between the first source / drain region and the first floating gate electrode via the capacitance causes the presence or absence of the electric charge accumulated in the first floating gate electrode to be determined. Irrespective of this, the channel region immediately below the first floating gate electrode is turned on, and the second floating region is set based on the value of the cell current flowing from the first source / drain region to the second source / drain region. 4. The transistor according to claim 2, wherein a value of data stored in the gate electrode is read.

(6) A sixth voltage is applied to the first and second source / drain regions, and a seventh voltage higher than the sixth voltage is applied to the control gate electrode. Due to the first and second floating gate electrodes strongly coupled to the first and second source / drain regions, the potential of the first and second floating gate electrodes is increased to the sixth.
Of the control gate electrode and the first
And the potential difference with the second floating gate electrode increases,
Since a high electric field is generated between the control gate electrode and the first and second floating gate electrodes and a Fowler-Nordheim tunnel current flows, electrons in the first and second floating gate electrodes are controlled by the control gate electrode. 4. The method according to claim 2, wherein the data stored in the first and second floating gate electrodes is erased by being pulled out to the electrode side.
(B) The transistor according to any one of the above.

Incidentally, in the present specification, the members according to the constitution of the present invention are defined as follows. (A) The semiconductor substrate includes not only a single crystal silicon semiconductor substrate but also a well, a single crystal silicon film, a polycrystalline silicon film, an amorphous silicon film, a compound semiconductor substrate, and a compound semiconductor film.

(B) The silicon film includes not only a doped polysilicon film but also an amorphous silicon film, a single crystal silicon film, a metal silicide film, and the like. (C) The capacitance between the floating gate electrode and the substrate includes the capacitance between the floating gate electrode and one or both of the source / drain region and the channel region formed on the substrate. Shall be considered.

[0124]

According to the first to fifth aspects of the present invention, it is possible to provide a transistor which can obtain good writing characteristics and can be miniaturized. According to the sixth aspect of the present invention, it is possible to provide a transistor array including transistors capable of achieving good writing characteristics and being miniaturized.

According to the seventh aspect of the present invention, it is possible to provide a semiconductor memory using a transistor capable of obtaining good write characteristics and capable of miniaturization as a memory cell.

[Brief description of the drawings]

FIG. 1B is a partial plan view of the first embodiment, FIG.
1A is a sectional view taken along line YY in FIG.

FIG. 2 is a block circuit diagram of the first to sixth embodiments.

FIG. 3 is an essential part cross-sectional view for explaining the operation of the first embodiment.

FIG. 4 is a main part circuit diagram for explaining the operation of the first embodiment.

FIG. 5 is an essential part cross sectional view for explaining the operation of the first embodiment.

FIGS. 6 (a ′) and (b ′) are plan views of a main part for describing a manufacturing method of the first embodiment. FIGS. 6A and 6B are cross-sectional views taken along the line YY of FIGS. 6A and 6B.

FIGS. 7 (a ′) and (b ′) are plan views of an essential part for describing a manufacturing method of the first embodiment. 7A and 7B are cross-sectional views taken along the line YY of FIGS. 7A and 7B.

FIGS. 8 (a ′) and (b ′) are plan views of a main part for describing a manufacturing method of the first embodiment. FIGS. 8A and 8B are cross-sectional views taken along the line YY of FIGS. 8A and 8B.

FIGS. 9A and 9B are plan views of an essential part for explaining a manufacturing method according to the first embodiment; FIGS. 9A and 9B are cross-sectional views taken along the line YY in FIGS. 9A and 9B.

FIGS. 10 (a ′) and (b ′) are essential part plan views for explaining the manufacturing method of the first embodiment. FIG. 10 (a)
(B) is a sectional view taken along line YY in FIGS. 10 (a ′) and (b ′).

FIG. 11B is a partial plan view of the second embodiment,
FIG. 11A is a sectional view taken along line YY of FIG. 11B.

FIGS. 12 (a ′) and (b ′) are plan views of a main part for describing a manufacturing method according to a second embodiment. FIG. 12 (a)
(B) is a sectional view taken along line YY in FIGS. 12 (a ′) and (b ′).

FIGS. 13 (a ′) and (b ′) are essential part plan views for explaining the manufacturing method of the second embodiment. FIG. 13 (a)
(B) is a sectional view taken along line YY of FIGS. 13 (a ′) and (b ′).

FIGS. 14 (a ′) and (b ′) are essential part plan views for explaining a manufacturing method according to a second embodiment. FIG. 14 (a)
(B) is a sectional view taken along line YY in FIGS. 14 (a ′) and (b ′).

FIGS. 15 (a ′) and (b ′) are essential part plan views for explaining the manufacturing method of the third embodiment. FIG. 15 (a)
(B) is a sectional view taken along line YY in FIGS. 15 (a ′) and (b ′).

FIGS. 16 (a ′) and (b ′) are essential part plan views for explaining the manufacturing method of the fourth embodiment. FIG. 16 (a)
(B) is a sectional view taken along line YY of FIGS. 16 (a ′) and (b ′).

FIG. 17 (b) is a partial plan view of the fourth embodiment,
FIG. 17A is a cross-sectional view taken along line YY of FIG.

FIGS. 18 (a ′) and (b ′) are essential part plan views for explaining the manufacturing method of the fifth embodiment. FIG. 18 (a)
(B) is a sectional view taken along line YY in FIGS. 18 (a ′) and (b ′).

FIG. 19 (b) is a partial plan view of the fifth embodiment,
FIG. 19A is a sectional view taken along line YY of FIG. 19B.

FIGS. 20 (a ′) and (b ′) are plan views of relevant parts for describing a manufacturing method according to a sixth embodiment. FIG. 20 (a)
(B) is a sectional view taken along line YY in FIGS. 20 (a ′) and (b ′).

FIG. 21 (b) is a partial plan view of the sixth embodiment,
FIG. 21A is a sectional view taken along line YY of FIG. 21B.

FIG. 22 is a sectional view of a main part of a seventh embodiment.

FIG. 23 is an essential part cross-sectional view for explaining a conventional mode.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory cell (transistor) 2 single crystal silicon substrate 3 source / drain region 4 channel region 5 6 floating gate electrode 5 a, 6 a projection 7 control gate electrode 8 gate insulating film 9 insulating film 9a ... Bird's beak 10, 33 ... Tunnel insulating film 21 ... Doped polysilicon film 21a ... Undercut part 22 ... Silicon nitride film 24 ... Film 26 ... Doped polysilicon film 31 ... Insulating film 32 ... Etching mask 101 ... Flash EEPROM 102: memory cell array (transistor array) WL1 to WLn: word line BL1 to BLn: bit line

Claims (7)

[Claims] 1. A floating gate electrode having a cross-sectional area larger than a cross-sectional area at one end in one direction on a semiconductor substrate, and a control gate electrode formed on the floating gate electrode via an insulating film. A transistor, wherein a capacitance between the floating gate electrode and a semiconductor substrate is set to be larger than a capacitance between the floating gate electrode and a control gate electrode. 2. A semiconductor device comprising: first and second floating gate electrodes sharing one control gate electrode and juxtaposed on a channel region between two source / drain regions formed in a semiconductor substrate; Alternatively, the capacitance between the second floating gate electrode and the semiconductor substrate is set to be larger than the capacitance between the first or second floating gate electrode and the control gate electrode, and A transistor in which the second floating gate electrode has a portion having a larger cross-sectional area than a cross-sectional area at one end in one direction. 3. A first and a second formed on a semiconductor substrate.
And a channel region sandwiched between the first and second source / drain regions, and first and second floating gates juxtaposed on the channel region via a gate insulating film. An electrode, and a control gate electrode formed on the first and second floating gate electrodes via an insulating film and shared by the first and second floating gate electrodes, wherein the first floating gate An electrode is disposed near the first source / drain region, and the second floating gate electrode is
The capacitance between the first or second floating gate electrode and the semiconductor substrate is between the first or second floating gate electrode and the control gate electrode. Wherein the first and second floating gate electrodes have a portion having a larger cross-sectional area than a cross-sectional area at one end. 4. A transistor in which a projection is formed on an upper portion of a floating gate electrode except for a peripheral portion, and a control gate electrode is formed on the projection via an insulating film. 5. The transistor according to claim 1, wherein a projection is formed on an upper portion of the floating gate electrode except for a peripheral portion thereof, and the control gate electrode is formed on the projection with an insulating film interposed therebetween. Formed with the transistor. 6. The transistor according to claim 1, wherein the transistors are arranged in a matrix, and the control gate electrodes of a plurality of transistors arranged in a row in the matrix are shared. A transistor array comprising: a word line to be connected; and a bit line that commonly connects source / drain regions of a plurality of transistors arranged in a column direction in the matrix. 7. A semiconductor memory for writing data by injecting charges into a floating gate electrode, wherein the transistor according to claim 1 is used as a memory cell, A semiconductor memory in which when a data erase operation is performed by extracting an injected charge to the control gate electrode, electrons jump out of the protrusion of the floating gate electrode and move to the control gate electrode side.