TW202038408A - Lead frame and method for manufacturing same, semiconductor device and method for manufacturing same - Google Patents

Lead frame and method for manufacturing same, semiconductor device and method for manufacturing same Download PDF

Info

Publication number
TW202038408A
TW202038408A TW109118480A TW109118480A TW202038408A TW 202038408 A TW202038408 A TW 202038408A TW 109118480 A TW109118480 A TW 109118480A TW 109118480 A TW109118480 A TW 109118480A TW 202038408 A TW202038408 A TW 202038408A
Authority
TW
Taiwan
Prior art keywords
lead
wire
die pad
terminal
outer peripheral
Prior art date
Application number
TW109118480A
Other languages
Chinese (zh)
Other versions
TWI719905B (en
Inventor
永田昌博
矢崎雅樹
冨田幸治
Original Assignee
日商大日本印刷股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商大日本印刷股份有限公司 filed Critical 日商大日本印刷股份有限公司
Publication of TW202038408A publication Critical patent/TW202038408A/en
Application granted granted Critical
Publication of TWI719905B publication Critical patent/TWI719905B/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A lead frame (10), provided with: a die pad (11) on which a semiconductor element (21) is mounted; a plurality of long outer periphery lead parts (12A) and short outer periphery lead parts (12B) provided around the die pad (11), each of the long outer periphery lead parts (12A) and the short outer periphery lead parts (12B) including a first terminal part (53); and a connection ring (14) disposed between the die pad (11) and the long outer periphery lead parts (12A) and the short outer periphery lead parts (12B), the connection ring (14) enclosing the die pad (11). A plurality of inside leads (26A-26D) include long inside leads (26A, 26C) and short inside leads (26B, 26D). The long inside leads (26A, 26C) and the short inside leads (26B, 26D) are arranged alternatingly along the connection ring (14).

Description

導線框架及其製造方法、以及半導體裝置及其製造方法 Lead frame and its manufacturing method, and semiconductor device and its manufacturing method

本發明，係有關於導線框架及其製造方法、以及半導體裝置及其製造方法 The present invention relates to a lead frame and its manufacturing method, and a semiconductor device and its manufacturing method

近年來，係對於被安裝在基板上之半導體裝置的小型化以及薄型化有所要求。為了對應於此種要求，於先前技術中，係對於使用導線框架，並將搭載於其之搭載面上的半導體元件藉由密封樹脂來作密封，且在背面側使導線的一部分露出，而構成的所謂QFN(Quad Flat Non-lead)形態之半導體裝置作了各種的提案。 In recent years, there has been a demand for miniaturization and thinning of semiconductor devices mounted on substrates. In order to meet this requirement, in the prior art, a lead frame is used, and the semiconductor element mounted on the mounting surface is sealed with a sealing resin, and a part of the lead is exposed on the back side. Various proposals have been made for semiconductor devices in the so-called QFN (Quad Flat Non-lead) form.

然而，在由先前技術之一般構造所成之QFN的情況時，伴隨著端子數量的增加，由於封裝係會變大，因此係有著會變得難以確保安裝信賴性的課題。相對於此，作為用以實現作了多銷化之QFN的技術，對於將外部端子配列成2列的封裝之開發係有所進展(例如專利文獻1)。此種封裝，係亦被稱作DR-QFN(Dual Row QFN)封裝。 However, in the case of the QFN formed by the general structure of the prior art, as the number of terminals increases, the package system becomes larger, and therefore, there is a problem that it becomes difficult to ensure the reliability of the installation. In contrast, as a technology for realizing QFN with multiple pins, there has been progress in the development of packages in which external terminals are arranged in two rows (for example, Patent Document 1). This kind of package is also called DR-QFN (Dual Row QFN) package.

〔先前技術文獻〕 [Prior technical literature]

〔專利文獻〕 〔Patent Literature〕

〔專利文獻1〕日本特開2006-19767號公報 [Patent Document 1] Japanese Patent Application Publication No. 2006-19767

近年來，在生產DR-QFN封裝時，係要求能夠並不對於晶片尺寸作變更地而增加導線部之數量(銷數)。針對此，於先前技術中，為了增加銷數，係採用有將封裝尺寸增大的手法。然而，由於係存在有需要將封裝搭載於電子機器上一事所導致的限制，因此在將封裝尺寸增大一事上係存在有極限。又，伴隨著封裝尺寸之增大，由於內導線的長度也會變長，因此係亦存在著會變成易於在內導線處產生變形的問題。 In recent years, when DR-QFN packages are produced, it is required to increase the number of lead parts (the number of pins) without changing the chip size. In response to this, in the prior art, in order to increase the number of pins, a method of increasing the package size is adopted. However, due to the limitation caused by the need to mount the package on the electronic device, there is a limit to increasing the package size. In addition, as the package size increases, the length of the inner wire also becomes longer, so there is also a problem that it becomes easy to deform at the inner wire.

本發明，係為對於此種問題作考慮所進行者，其目的，係在於提供一種能夠將與外部作連接之端子部的數量(銷數)增加之導線框架及其製造方法、以及半導體裝置及其製造方法。 The present invention was made in consideration of such problems, and its purpose is to provide a lead frame capable of increasing the number of externally connected terminal portions (number of pins), a manufacturing method thereof, and a semiconductor device and其制造方法。 Its manufacturing method.

本發明，係為一種導線框架，其係為半導體裝置用之導線框架，其特徵為，係具備有：晶粒墊，係搭載有半導體元件；和複數之外周導線部，係被設置於前述晶粒墊之周圍，並分別包含有第1端子部；和連接環，係被配置在前述晶粒墊和前述外周導線部之間，並包圍前述晶粒墊；和複數之內側導線部，係藉由前述連接環而被支持，並分別包含有第2端子部，前述複數之內側導線部，係包含有長內側導線部和短內側導線部，前述長內側導線 部和前述短內側導線部，係沿著前述連接環而被交互作配置。 The present invention is a lead frame, which is a lead frame for a semiconductor device, and is characterized in that it is provided with: die pads on which semiconductor elements are mounted; and a plurality of outer peripheral lead parts are provided on the aforementioned crystal The periphery of the die pad includes a first terminal portion; and a connecting ring, which is arranged between the die pad and the outer peripheral wire portion, and surrounds the die pad; and a plurality of inner wire portions, by It is supported by the aforementioned connecting ring, and each includes a second terminal part, the aforementioned plural inner lead parts include a long inner lead part and a short inner lead part, and the aforementioned long inner lead part The part and the short inner wire part are alternately arranged along the connecting ring.

本發明，係為一種導線框架，其中，前述複數之內側導線部，係從前述連接環之內側以及外側的雙方而延伸。 The present invention is a lead frame in which the plurality of inner lead portions extend from both the inner and outer sides of the connecting ring.

本發明，係為一種導線框架，其中，前述複數之內側導線部中的從前述連接環之內側所延伸之前述短內側導線部、和從前述連接環之外側所延伸之前述長內側導線部，係隔著前述連接環而被配置在互為相反側之位置。 The present invention is a lead frame in which, among the plurality of inner lead parts, the short inner lead part extending from the inner side of the connecting ring and the long inner lead part extending from the outer side of the connecting ring, They are arranged on opposite sides of each other via the connecting ring.

本發明，係為一種導線框架，其中，在前述連接環之表面上，係沿著前述連接環而被形成有凹溝。 The present invention is a lead frame in which grooves are formed on the surface of the connecting ring along the connecting ring.

本發明，係為一種導線框架，其中，前述內側導線部，係具備有被與前述連接環作連結之連接導線，前述連接導線，係從背面側起而作了厚度薄化。 The present invention is a lead frame in which the inner lead part is provided with a connecting lead connected to the connecting ring, and the connecting lead is thinned from the back side.

本發明，係為一種導線框架，其中，前述內側導線部，係具備有被與前述連接環作連結之連接導線，前述連接導線，係從表面側起而作了厚度薄化。 The present invention is a lead frame in which the inner lead part is provided with a connecting lead connected to the connecting ring, and the connecting lead is thinned from the surface side.

本發明，係為一種導線框架，其中，前述複數之外周導線部，係包含有長外周導線部和短外周導線部，前述長外周導線部和前述短外周導線部係被交互配置，前述複數之內側導線部，係從前述連接環之至少外側而延伸，前述長外周導線部和前述短內側導線部係相互對向，前述短外周導線部和前述長內側導線部係相互對向。 The present invention is a lead frame, wherein the plurality of outer peripheral lead parts include a long outer peripheral lead part and a short outer peripheral lead part, the long outer peripheral lead part and the short outer peripheral lead part are alternately arranged, and the plurality of The inner lead part extends from at least the outside of the connecting ring, the long outer peripheral lead part and the short inner lead part are opposed to each other, and the short outer peripheral lead part and the long inner lead part are opposed to each other.

本發明，係為一種導線框架，其中，係由具備有750Mpa~1100Mpa之拉張強度的金屬材料所構成。 The present invention is a lead frame, which is composed of a metal material with a tensile strength of 750Mpa to 1100Mpa.

本發明，係為一種導線框架，其係為半導體裝置用之導線框架，其特徵為，係具備有：晶粒墊，係搭載有半導體元件；和複數之外周導線部，係被設置於前述晶粒墊之周圍，並分別包含有第1端子部；和導線連接部，係被配置在前述晶粒墊和前述外周導線部之間；和複數之內側導線部，係藉由前述導線連接部而被支持，並分別包含有第2端子部，前述複數之內側導線部，係包含有長內側導線部和短內側導線部，前述長內側導線部和前述短內側導線部，係沿著前述導線連接部而被交互作配置。 The present invention is a lead frame, which is a lead frame for a semiconductor device, and is characterized in that it is provided with: die pads on which semiconductor elements are mounted; and a plurality of outer peripheral lead parts are provided on the aforementioned crystal The periphery of the die pad includes a first terminal portion; and a wire connection portion, which is arranged between the die pad and the outer peripheral wire portion; and a plurality of inner wire portions are formed by the wire connection portion Are supported and respectively include a second terminal part, the aforementioned plural inner lead parts include a long inner lead part and a short inner lead part, and the long inner lead part and the short inner lead part are connected along the aforementioned lead Departments are interactively configured.

本發明，係為一種半導體裝置，其特徵為，係具備有：晶粒墊；和複數之外周導線部，係被設置在前述晶粒墊之周圍，並分別包含有第1端子部；和複數之第2端子部，係被配置在前述晶粒墊和前述外周導線部之間，並從前述晶粒墊以及前述外周導線部而作了分離；和半導體元件，係被搭載於前述晶粒墊上；和連接構件，係將前述半導體元件和各外周導線部作電性連接，並且將前述半導體元件和各第2端子部作電性連接；和密封樹脂，係將前述晶粒墊和前述複數之外周導線部和前述複數之第2端子部和前述半導體元件以及前述連接構件作密封，前述複數之外周導線部，係包含有使前述第1端子部相對性地位置於內側之長外周導線部、和使前述第1端子部相對性地位置於外側之短外周導線部，前述長外周導線部和前 述短外周導線部係被交互作配置，在前述密封樹脂的背面中之前述外周導線部與前述晶粒墊之間的區域處，係以包圍前述晶粒墊的方式而被形成有凹部。 The present invention is a semiconductor device characterized in that it is provided with: a die pad; and a plurality of outer peripheral lead portions, which are provided around the die pad and each include a first terminal portion; and The second terminal portion is arranged between the die pad and the outer peripheral lead portion, and is separated from the die pad and the outer peripheral lead portion; and the semiconductor element is mounted on the die pad ; And the connecting member, which electrically connects the aforementioned semiconductor element and each outer peripheral lead portion, and electrically connects the aforementioned semiconductor element and each second terminal portion; and a sealing resin, which combines the aforementioned die pad and the aforementioned plural The outer peripheral lead part and the aforementioned plural second terminal parts are sealed with the aforementioned semiconductor element and the aforementioned connecting member, and the aforementioned plural outer peripheral lead parts include a long outer peripheral lead part that makes the first terminal part relatively positioned inside, And the short outer peripheral lead part that makes the first terminal part opposite to the outside, the aforementioned long outer peripheral lead part and the front The short outer peripheral lead portions are alternately arranged, and a recessed portion is formed in a region between the outer peripheral lead portion and the die pad on the back surface of the sealing resin to surround the die pad.

本發明，係為一種半導體裝置，其特徵為，係具備有：晶粒墊；和複數之外周導線部，係被設置在前述晶粒墊之周圍，並分別包含有第1端子部；和複數之第2端子部，係被配置在前述晶粒墊和前述外周導線部之間，並從前述晶粒墊以及前述外周導線部而作了分離；和半導體元件，係被搭載於前述晶粒墊上；和連接構件，係將前述半導體元件和各外周導線部作電性連接，並且將前述半導體元件和各第2端子部作電性連接；和密封樹脂，係將前述晶粒墊和前述複數之外周導線部和前述複數之第2端子部和前述半導體元件以及前述連接構件作密封，前述複數之外周導線部，係包含有使前述第1端子部相對性地位置於內側之長外周導線部、和使前述第1端子部相對性地位置於外側之短外周導線部，前述長外周導線部和前述短外周導線部係被交互作配置，在前述密封樹脂的背面中之前述外周導線部與前述晶粒墊之間的區域處，係被形成有凹部。 The present invention is a semiconductor device characterized in that it is provided with: a die pad; and a plurality of outer peripheral lead portions, which are provided around the die pad and each include a first terminal portion; and The second terminal portion is arranged between the die pad and the outer peripheral lead portion, and is separated from the die pad and the outer peripheral lead portion; and the semiconductor element is mounted on the die pad ; And the connecting member, which electrically connects the aforementioned semiconductor element and each outer peripheral lead portion, and electrically connects the aforementioned semiconductor element and each second terminal portion; and a sealing resin, which combines the aforementioned die pad and the aforementioned plural The outer peripheral lead part and the aforementioned plural second terminal parts are sealed with the aforementioned semiconductor element and the aforementioned connecting member, and the aforementioned plural outer peripheral lead parts include a long outer peripheral lead part that makes the first terminal part relatively positioned inside, In addition to the short outer peripheral lead part that makes the first terminal part opposite to the outside, the long outer peripheral lead part and the short outer peripheral lead part are alternately arranged, and the outer peripheral lead part and the aforementioned outer lead part on the back of the sealing resin The area between the die pads is formed with recesses.

本發明，係為一種導線框架之製造方法，其特徵為，係具備有：準備金屬基板之工程；和藉由對於前述金屬基板進行蝕刻加工，而在前述金屬基板上形成前述晶粒墊、前述外周導線部、前述連接環以及前述內側導線部之工程。 The present invention is a method of manufacturing a lead frame, which is characterized by including: a process of preparing a metal substrate; and forming the die pad and the die pad on the metal substrate by etching the metal substrate The engineering of the outer peripheral lead part, the aforementioned connecting ring and the aforementioned inner lead part.

本發明，係為一種半導體裝置之製造方法，其特徵為，係具備有：準備導線框架之工程；和在前述導線框架之前述晶粒墊上搭載前述半導體元件之工程；和將前述半導體元件和各外周導線部藉由連接構件來作電性連接之工程；和將前述晶粒墊和前述複數之外周導線部和前述半導體元件以及前述連接構件藉由密封樹脂來作密封之工程；和藉由從前述導線框架之背面側來將前述連接環之至少一部分除去，而將前述複數之第2端子部分別個別地作分離之工程。 The present invention is a method of manufacturing a semiconductor device, which is characterized by comprising: a process of preparing a lead frame; and a process of mounting the semiconductor element on the die pad of the lead frame; and combining the semiconductor element and each The process of making the electrical connection of the outer peripheral lead part by a connecting member; and the process of sealing the aforementioned die pad and the plurality of outer peripheral lead parts, the aforementioned semiconductor element and the aforementioned connecting member by a sealing resin; and by On the back side of the lead frame, at least a part of the connecting ring is removed, and the plural second terminal portions are individually separated.

本發明，係為一種導線框架之製造方法，其特徵為，係具備有：準備金屬基板之工程；和藉由對於前述金屬基板進行蝕刻加工，而在前述金屬基板上形成前述晶粒墊、前述外周導線部、前述導線連接部以及前述內側導線部之工程。 The present invention is a method of manufacturing a lead frame, which is characterized by including: a process of preparing a metal substrate; and forming the die pad and the die pad on the metal substrate by etching the metal substrate The engineering of the outer peripheral lead part, the aforementioned lead connection part, and the aforementioned inner lead part.

本發明，係為一種半導體裝置之製造方法，其特徵為，係具備有：準備導線框架之工程；和在前述導線框架之前述晶粒墊上搭載前述半導體元件之工程；和將前述半導體元件和各外周導線部藉由連接構件來作電性連接之工程；和將前述晶粒墊和前述複數之外周導線部和前述半導體元件以及前述連接構件藉由密封樹脂來作密封之工程；和藉由從前述導線框架之背面側來將前述導線連接部之至少一部分除去，而將前述複數之第2端子部分別個別地作分離之工程。 The present invention is a method of manufacturing a semiconductor device, which is characterized by comprising: a process of preparing a lead frame; and a process of mounting the semiconductor element on the die pad of the lead frame; and combining the semiconductor element and each The process of making the electrical connection of the outer peripheral lead part by a connecting member; and the process of sealing the aforementioned die pad and the plurality of outer peripheral lead parts, the aforementioned semiconductor element and the aforementioned connecting member by a sealing resin; and by On the back side of the lead frame, at least a part of the lead connection part is removed, and the plural second terminal parts are individually separated.

若依據本發明，則係能夠將與外部作連接之 端子部的數量(銷數)增加。 According to the present invention, it can be connected to the outside The number of terminal parts (number of pins) increases.

本發明，係為一種導線框架，係包含有相互經由支持構件來作了連結的複數之單位導線框架，其特徵為：各單位導線框架，係具備有：晶粒墊，係搭載有半導體元件；和複數之導線部，係被設置於前述晶粒墊之周圍，並分別包含有端子部和從前述端子部起而朝向內側延伸之內導線，前述導線部，係藉由被設置在相鄰接之前述單位導線框架間之前述支持構件而被作支持，前述導線框架，係由具有850MPa~1100MPa之拉張強度的金屬材料所構成，各單位導線框架之前述導線部中的前述支持構件之近旁部分，其寬幅係為75μm~90μm，其厚度係為60μm~75μm。 The present invention is a lead frame, which includes a plurality of unit lead frames connected to each other via a supporting member, and is characterized in that: each unit lead frame is provided with a die pad and is equipped with a semiconductor element; And a plurality of lead parts are arranged around the die pad, and each includes a terminal part and an inner lead extending from the terminal part toward the inside. The lead part is arranged adjacent to The aforementioned supporting members between the aforementioned unit lead frames are supported. The aforementioned lead frames are made of a metal material with a tensile strength of 850MPa~1100MPa. The aforementioned supporting members in the aforementioned lead parts of each unit lead frame are nearby For the part, its width is 75μm~90μm, and its thickness is 60μm~75μm.

本發明，係為一種導線框架，其中，前述複數之導線部的前述端子部，係以在相鄰接之前述導線部間而位置在內側以及外側處的方式，來在作平面觀察時而被交互地配置為交錯狀。 The present invention is a lead frame in which the terminal parts of the plural lead parts are positioned at the inner and outer sides between the adjacent lead parts, when viewed in plan. It is alternately arranged in a staggered shape.

本發明，係為一種導線框架，其中，前述內導線，其厚度係較前述端子部而更薄。 The present invention is a lead frame, wherein the thickness of the inner lead is thinner than the terminal part.

本發明，係為一種導線框架，其中，前述導線部，係包含有從前述端子部起而朝向外側延伸之連接導線，前述連接導線，其厚度係較前述端子部而更薄。 The present invention is a lead frame, wherein the wire portion includes a connecting wire extending outward from the terminal portion, and the thickness of the connecting wire is thinner than that of the terminal portion.

本發明，係為一種導線框架，其中，前述導線部之前述內導線中的前述端子部之近旁部分，其寬幅係為75μm~90μm，其厚度係為60μm~75μm。 The present invention is a lead frame, wherein the width of the part near the terminal part in the inner lead of the lead part is 75 μm to 90 μm, and the thickness is 60 μm to 75 μm.

本發明，係為一種導線框架，其中，前述金屬材料，係身為卡遜系合金(Cu-Ni-Si)、鎳錫銅合金(Cu-Ni-Sn)或者是鈦銅合金(Cu-Ti)。 The present invention is a lead frame, wherein the aforementioned metal material is Carson alloy (Cu-Ni-Si), nickel-tin-copper alloy (Cu-Ni-Sn) or titanium-copper alloy (Cu-Ti ).

本發明，係為一種導線框架，係包含有相互經由支持構件來作了連結的複數之單位導線框架，其特徵為：各單位導線框架，係具備有：晶粒墊，係搭載有半導體元件；和複數之導線部，係被設置於前述晶粒墊之周圍，並分別包含有端子部和從前述端子部起而朝向內側延伸之內導線，前述導線部，係藉由被設置在相鄰接之前述單位導線框架間之前述支持構件而被作支持，前述導線框架，係由具有750MPa~1100MPa之拉張強度的金屬材料所構成，各單位導線框架之前述導線部中的前述支持構件之近旁部分，其寬幅係為60μm~90μm，其厚度係為50μm~75μm。 The present invention is a lead frame, which includes a plurality of unit lead frames connected to each other via a supporting member, and is characterized in that: each unit lead frame is provided with a die pad and is equipped with a semiconductor element; And a plurality of lead parts are arranged around the die pad, and each includes a terminal part and an inner lead extending from the terminal part toward the inside. The lead part is arranged adjacent to The aforementioned supporting members between the aforementioned unit lead frames are supported. The aforementioned lead frames are made of a metal material with a tensile strength of 750MPa~1100MPa. The aforementioned supporting members in the aforementioned lead parts of each unit lead frame are nearby For the part, its width is 60μm~90μm, and its thickness is 50μm~75μm.

本發明，係為一種使用導線框架而製作的半導體裝置，其特徵為，係具備有：前述晶粒墊；和複數之前述導線部，係被設置在前述晶粒墊之周圍，並分別包含有前述端子部和從前述端子部起而朝向內側延伸之前述內導線；和半導體元件，係被搭載於前述晶粒墊上；和連接構件，係將前述半導體元件和各導線部之前述內導線作電性連接；和密封樹脂，係將前述晶粒墊和前述複數之導線部和前述半導體元件以及前述連接構件作密封。 The present invention is a semiconductor device manufactured using a lead frame, which is characterized in that it is provided with: the aforementioned die pad; and a plurality of the aforementioned wire portions are provided around the aforementioned die pad and each includes The terminal portion and the inner lead extending inwardly from the terminal portion; and the semiconductor element, which is mounted on the die pad; and the connecting member, which electrically connects the semiconductor element and the inner lead of each lead part Sexual connection; and sealing resin, the aforementioned die pad and the aforementioned plurality of lead parts and the aforementioned semiconductor element and the aforementioned connecting member for sealing.

本發明，係為一種導線框架之製造方法，其特徵為：該導線框架，係包含有相互經由支持構件來作了 連結的複數之單位導線框架，各單位導線框架，係具備有：晶粒墊，係搭載有半導體元件；和複數之導線部，係被設置於前述晶粒墊之周圍，並分別包含有端子部和從前述端子部起而朝向內側延伸之內導線，該導線框架之製造方法，係具備有：準備藉由具備850MPa~1100MPa之拉張強度之金屬材料所構成之金屬基板之工程；和藉由對於前述金屬基板進行蝕刻加工，而在前述金屬基板上形成前述晶粒墊以及前述導線部之工程，當在前述金屬基板上形成前述晶粒墊以及前述導線部時，各單位導線框架之前述導線部中的前述支持構件之近旁部分，其寬幅係為75μm~90μm，其厚度係為60μm~75μm。 The present invention is a method of manufacturing a lead frame, which is characterized in that the lead frame includes a mutual support member made The connected plural unit lead frames, each unit lead frame is provided with: die pads, which are equipped with semiconductor components; and plural lead parts, which are arranged around the aforementioned die pads, and respectively include terminal parts And the inner wire extending inward from the aforementioned terminal part, the method of manufacturing the lead frame includes: preparing a metal substrate made of a metal material with a tensile strength of 850MPa~1100MPa; and by The process of etching the metal substrate to form the die pad and the wire portion on the metal substrate. When the die pad and the wire portion are formed on the metal substrate, the wire of each unit lead frame The part near the aforementioned support member in the section has a width of 75 μm to 90 μm and a thickness of 60 μm to 75 μm.

本發明，係為一種導線框架之製造方法，其特徵為：該導線框架，係包含有相互經由支持構件來作了連結的複數之單位導線框架，各單位導線框架，係具備有：晶粒墊，係搭載有半導體元件；和複數之導線部，係被設置於前述晶粒墊之周圍，並分別包含有端子部和從前述端子部起而朝向內側延伸之內導線，該導線框架之製造方法，係具備有：準備藉由具備750MPa~1100MPa之拉張強度之金屬材料所構成之金屬基板之工程；和藉由對於前述金屬基板進行蝕刻加工，而在前述金屬基板上形成前述晶粒墊以及前述導線部之工程，當在前述金屬基板上形成前述晶粒墊以及前述導線部時，各單位導線框架之前述導線部中的前述支持構件之近旁部分，其寬幅係為60μm~90μm，其厚度係為50μm~75μm。 The present invention is a method of manufacturing a lead frame, which is characterized in that the lead frame includes a plurality of unit lead frames connected to each other via a supporting member, and each unit lead frame is provided with: a die pad , Is equipped with semiconductor elements; and a plurality of lead parts are arranged around the aforementioned die pad, and each includes a terminal part and inner leads extending from the aforementioned terminal part toward the inner side, the manufacturing method of the lead frame , Is equipped with: the process of preparing a metal substrate composed of a metal material with a tensile strength of 750MPa~1100MPa; and forming the die pad on the metal substrate by etching the metal substrate, and In the process of the aforementioned lead part, when the die pad and the aforementioned lead part are formed on the metal substrate, the width of the vicinity of the support member in the lead part of each unit lead frame is 60μm~90μm, which The thickness is 50μm~75μm.

本發明，係為一種半導體裝置之製造方法，其特徵為，係具備有：藉由導線框架之製造方法來製造導線框架之工程；和在前述導線框架之前述晶粒墊上搭載前述半導體元件之工程；和將前述半導體元件和各導線部之前述內導線藉由連接構件來作電性連接之工程；和將前述晶粒墊和前述複數之導線部和前述半導體元件以及前述連接構件藉由密封樹脂來作密封之工程。 The present invention is a method of manufacturing a semiconductor device, characterized in that it includes: a process of manufacturing a lead frame by a method of manufacturing a lead frame; and a process of mounting the semiconductor element on the die pad of the lead frame And the process of electrically connecting the aforementioned semiconductor element and the aforementioned inner lead of each lead part by a connecting member; and the aforementioned die pad and the aforementioned plural lead parts, the aforementioned semiconductor element and the aforementioned connecting member by a sealing resin Come for the sealing project.

若依據本發明，則由於係能夠對於導線部之強度降低的情形作抑制，因此係能夠防止在導線部處產生變形的情況，且能夠將相鄰接之導線部彼此的間隔縮窄。 According to the present invention, it is possible to suppress the decrease in the strength of the wire portion, and therefore it is possible to prevent the wire portion from being deformed, and it is possible to narrow the interval between adjacent wire portions.

本發明，係為一種半導體裝置用之導線框架，其特徵為，係具備有：晶粒墊，係搭載有半導體元件；和複數之導線部，係被設置於前述晶粒墊之周圍，並分別包含有第1端子部和從前述第1端子部起而朝向內側延伸之內導線；和連接環，係被設置在前述內導線之前端側處，並包圍前述晶粒墊，前述連接環，係藉由至少1個的前述內導線而被作支持，沿著前述連接環，而規則性地設置凹部，在各凹部之間，形成有厚壁部。 The present invention is a lead frame for a semiconductor device, which is characterized in that it is provided with: die pads on which semiconductor elements are mounted; and a plurality of lead parts are arranged around the die pads and are respectively It includes a first terminal portion and an inner lead extending inward from the first terminal portion; and a connecting ring, which is provided at the front end side of the inner lead and surrounds the die pad, and the connecting ring is It is supported by at least one inner lead, and recesses are regularly provided along the connecting ring, and thick portions are formed between the recesses.

若依據本發明，則係能夠防止內導線之變形，並且能夠將與外部作連接之端子部的數量(銷數)增加。 According to the present invention, it is possible to prevent the deformation of the inner wire, and it is possible to increase the number of terminals (the number of pins) connected to the outside.

10:導線框架 10: Wire frame

10a:單位導線框架 10a: unit lead frame

10A:導線框架 10A: Wire frame

10B:導線框架 10B: Wire frame

10C:導線框架 10C: Wire frame

10D:導線框架 10D: Wire frame

10E:導線框架 10E: Wire frame

10F:導線框架 10F: Wire frame

10G:導線框架 10G: Wire frame

11:晶粒墊 11: Die pad

12A:長外周導線部 12A: Long outer peripheral wire part

12B:短外周導線部 12B: Short outer peripheral wire part

13:支持導線 13: Support wire

14:連接環 14: connecting ring

14a:凹溝 14a: groove

14b:堤部 14b: Embankment

14c:凹部 14c: recess

15A:內部端子 15A: Internal terminal

15B:內部端子 15B: Internal terminal

16:懸吊導線 16: suspension wire

17A:內側外部端子 17A: Internal external terminal

17B:外側外部端子 17B: Outer external terminal

17C:外部端子 17C: External terminal

17D:外部端子 17D: External terminal

17E:外部端子 17E: External terminal

17F:外部端子 17F: External terminal

18:第2端子部 18: The second terminal part

19:連結條 19: Link bar

20:半導體裝置 20: Semiconductor device

20A:半導體裝置 20A: Semiconductor device

20B:半導體裝置 20B: Semiconductor device

20D:半導體裝置 20D: Semiconductor device

20F:半導體裝置 20F: Semiconductor device

20G:半導體裝置 20G: Semiconductor device

20H:半導體裝置 20H: Semiconductor device

21:半導體元件 21: Semiconductor components

21a:電極 21a: Electrode

22:接合打線 22: Bonding wire

23:密封樹脂 23: Sealing resin

24:接著劑 24: Adhesive

25:電鍍部 25: Electroplating Department

26A:長內側導線部 26A: Long inner lead part

26B:短內側導線部 26B: Short inner wire part

26C:長內側導線部 26C: Long inner lead part

26D:短內側導線部 26D: Short inner lead part

27:凹部 27: recess

27a:突起部 27a: protrusion

28:第2端子部 28: The second terminal part

28a:厚壁部 28a: Thick-walled part

31:金屬基板 31: Metal substrate

32:蝕刻用光阻層 32: Photoresist layer for etching

32a:感光性光阻 32a: photosensitive photoresist

32b:開口部 32b: opening

33:蝕刻用光阻層 33: Photoresist layer for etching

33a:感光性光阻 33a: photosensitive photoresist

33b:開口部 33b: opening

34:蝕刻用光阻層 34: Photoresist layer for etching

34a:開口部 34a: opening

36:加熱塊 36: heating block

51:內導線 51: inner wire

52:連接導線 52: Connect the wires

53:第1端子部 53: The first terminal

55:近旁部分 55: Near part

56:近旁部分 56: Near part

57:連接導線 57: Connect the wires

61:內導線 61: inner wire

61a:傾斜部分 61a: Inclined part

61b:直線部分 61b: straight part

62:連接導線 62: connecting wire

63:端子部 63: Terminal

64:導線連接部 64: Wire connection part

65:連結部 65: Connection

66:連結部 66: Connection

67:凹部 67: recess

〔圖1〕圖1，係為對於由本發明之第1實施形態所致之導線框架作展示的平面圖。 [Figure 1] Figure 1 is a plan view showing the lead frame resulting from the first embodiment of the present invention.

〔圖2〕圖2，係為對於由本發明之第1實施形態所致之導線框架作展示的底面圖。 [Figure 2] Figure 2 is a bottom view showing the lead frame resulting from the first embodiment of the present invention.

〔圖3〕圖3(a)，係為對於由本發明之第1實施形態所致之導線框架作展示的剖面圖(圖1之IIIA-IIIA線剖面圖)，圖3(b)，係為對於由本發明之第1實施形態所致之導線框架作展示的剖面圖(圖1之IIIB-IIIB線剖面圖)。 [Fig. 3] Fig. 3(a) is a cross-sectional view showing the lead frame caused by the first embodiment of the present invention (the cross-sectional view along the line IIIA-IIIA in Fig. 1), and Fig. 3(b) is A cross-sectional view showing the lead frame caused by the first embodiment of the present invention (the cross-sectional view along the line IIIB-IIIB in FIG. 1)

〔圖4〕圖4，係為對於由本發明之第1實施形態所致之半導體裝置作展示的平面圖。 [FIG. 4] FIG. 4 is a plan view showing the semiconductor device according to the first embodiment of the present invention.

〔圖5〕圖5，係為對於由本發明之第1實施形態所致之半導體裝置作展示的剖面圖(圖4之V-V線剖面圖)。 [FIG. 5] FIG. 5 is a cross-sectional view showing the semiconductor device according to the first embodiment of the present invention (the V-V line cross-sectional view in FIG. 4).

〔圖6〕圖6(a)~(f)，係為對於由本發明之第1實施形態所致之導線框架之製造方法作展示的剖面圖。 [Figure 6] Figures 6 (a) to (f) are cross-sectional views showing the manufacturing method of the lead frame according to the first embodiment of the present invention.

〔圖7〕圖7(a)~(f)，係為對於由本發明之第1實施形態所致之半導體裝置之製造方法作展示的剖面圖。 [FIG. 7] FIGS. 7(a)~(f) are cross-sectional views showing the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

〔圖8〕圖8，係為對於由本發明之第2實施形態所致之導線框架作展示的平面圖。 [FIG. 8] FIG. 8 is a plan view showing the lead frame according to the second embodiment of the present invention.

〔圖9〕圖9，係為對於由本發明之第2實施形態所致之導線框架作展示的底面圖。 [Fig. 9] Fig. 9 is a bottom view showing the lead frame according to the second embodiment of the present invention.

〔圖10〕圖10(a)，係為對於由本發明之第2實施形態所致之導線框架作展示的剖面圖(圖8之XA-XA線 剖面圖)，圖10(b)，係為對於由本發明之第2實施形態所致之導線框架作展示的剖面圖(圖8之XB-XB線剖面圖)。 [Fig. 10] Fig. 10(a) is a cross-sectional view showing the lead frame caused by the second embodiment of the present invention (line XA-XA in Fig. 8 Cross-sectional view), Fig. 10(b) is a cross-sectional view showing the lead frame caused by the second embodiment of the present invention (XB-XB cross-sectional view in Fig. 8).

〔圖11〕圖11，係為對於由本發明之第2實施形態所致之半導體裝置作展示的平面圖。 [FIG. 11] FIG. 11 is a plan view showing a semiconductor device according to the second embodiment of the present invention.

〔圖12〕圖12，係為對於由本發明之第3實施形態所致之導線框架作展示的平面圖。 [FIG. 12] FIG. 12 is a plan view showing the lead frame according to the third embodiment of the present invention.

〔圖13〕圖13，係為對於由本發明之第3實施形態所致之導線框架作展示的底面圖。 [Fig. 13] Fig. 13 is a bottom view showing the lead frame according to the third embodiment of the present invention.

〔圖14〕圖14(a)，係為對於由本發明之第3實施形態所致之導線框架作展示的剖面圖(圖12之XIVA-XIVA線剖面圖)，圖14(b)，係為對於由本發明之第3實施形態所致之導線框架作展示的剖面圖(圖12之XIVB-XIVB線剖面圖)。 [Figure 14] Figure 14(a) is a cross-sectional view showing the lead frame produced by the third embodiment of the present invention (the XIVA-XIVA line cross-sectional view of Figure 12), and Figure 14(b) is A cross-sectional view showing the lead frame caused by the third embodiment of the present invention (XIVB-XIVB line cross-sectional view in FIG. 12).

〔圖15〕圖15，係為對於由本發明之第3實施形態所致之半導體裝置作展示的平面圖。 [FIG. 15] FIG. 15 is a plan view showing a semiconductor device according to the third embodiment of the present invention.

〔圖16〕圖16，係為對於由本發明之第3實施形態所致之半導體裝置作展示的剖面圖(圖15之XVI-XVI線剖面圖)。 [FIG. 16] FIG. 16 is a cross-sectional view showing a semiconductor device according to the third embodiment of the present invention (cross-sectional view taken along line XVI-XVI in FIG. 15).

〔圖17〕圖17，係為對於由本發明之第3實施形態之變形例所致之導線框架作展示的平面圖。 [FIG. 17] FIG. 17 is a plan view showing a lead frame according to a modification of the third embodiment of the present invention.

〔圖18〕圖18，係為對於由本發明之第4實施形態所致之導線框架作展示的平面圖。 [FIG. 18] FIG. 18 is a plan view showing the lead frame according to the fourth embodiment of the present invention.

〔圖19〕圖19，係為對於由本發明之第4實施形態 所致之導線框架作展示的底面圖。 [FIG. 19] FIG. 19 is a diagram for the fourth embodiment of the present invention Bottom view of the resulting lead frame for display.

〔圖20〕圖20，係為對於由本發明之第4實施形態所致之半導體裝置作展示的平面圖。 [FIG. 20] FIG. 20 is a plan view showing a semiconductor device according to the fourth embodiment of the present invention.

〔圖21〕圖21，係為對於由本發明之第4實施形態之變形例所致之導線框架作展示的平面圖。 [FIG. 21] FIG. 21 is a plan view showing a lead frame according to a modification of the fourth embodiment of the present invention.

〔圖22〕圖22，係為對於由本發明之第5實施形態所致之導線框架作展示的平面圖。 [Fig. 22] Fig. 22 is a plan view showing the lead frame according to the fifth embodiment of the present invention.

〔圖23〕圖23，係為對於由本發明之第5實施形態所致之導線框架作展示的剖面圖(圖22之XXIII-XXIII線剖面圖)。 [FIG. 23] FIG. 23 is a cross-sectional view showing the lead frame caused by the fifth embodiment of the present invention (the cross-sectional view along the line XXIII-XXIII in FIG. 22).

〔圖24〕圖24，係為對於由本發明之第5實施形態所致之導線框架作展示的擴大平面圖(圖22之部分擴大圖)。 [FIG. 24] FIG. 24 is an enlarged plan view showing the lead frame caused by the fifth embodiment of the present invention (partial enlarged view of FIG. 22).

〔圖25〕圖25(a)~(b)，係為導線部之剖面圖(分別為圖24之XXVA-XXVA線剖面圖、XXVB-XXVB線剖面圖)。 [Figure 25] Figures 25 (a) ~ (b) are cross-sectional views of the wire section (respectively the XXVA-XXVA line cross-sectional view and the XXVB-XXVB line cross-sectional view of Figure 24).

〔圖26〕圖26(a)~(c)，係為導線部之剖面圖(分別為圖24之XXVIA-XXVIA線剖面圖、XXVIB-XXVIB線剖面圖、XXVIC-XXVIC線剖面圖)。 [Figure 26] Figures 26(a)~(c) are the cross-sectional views of the wire (respectively the XXVIA-XXVIA line cross-sectional view, the XXVIB-XXVIB line cross-sectional view, and the XXVIC-XXVIC line cross-sectional view of Figure 24).

〔圖27〕圖27，係為對於由本發明之第5實施形態所致之半導體裝置作展示的平面圖。 [FIG. 27] FIG. 27 is a plan view showing a semiconductor device according to the fifth embodiment of the present invention.

〔圖28〕圖28，係為對於由本發明之第5實施形態所致之半導體裝置作展示的剖面圖(圖27之XXVIII-XXVIII線剖面圖)。 [FIG. 28] FIG. 28 is a cross-sectional view showing a semiconductor device according to the fifth embodiment of the present invention (a cross-sectional view taken along the line XXVIII-XXVIII in FIG. 27).

〔圖29〕圖29(a)~(f)，係為對於由本發明之第5實施形態所致之導線框架之製造方法作展示的剖面圖。 [Figure 29] Figures 29 (a) to (f) are cross-sectional views showing the manufacturing method of the lead frame according to the fifth embodiment of the present invention.

〔圖30〕圖30(a)~(e)，係為對於由本發明之第5實施形態所致之半導體裝置之製造方法作展示的剖面圖。 [FIG. 30] FIGS. 30(a) to (e) are cross-sectional views showing a method of manufacturing a semiconductor device according to the fifth embodiment of the present invention.

〔圖31〕圖31，係為對於由本發明之第6實施形態所致之導線框架作展示的平面圖。 [Fig. 31] Fig. 31 is a plan view showing the lead frame according to the sixth embodiment of the present invention.

〔圖32〕圖32(a)，係為對於由本發明之第5實施形態所致之導線框架作展示的剖面圖(圖31之XXXIIA-XXXIIA線剖面圖)，圖32(b)，係為對於由本發明之第6實施形態所致之導線框架作展示的剖面圖(圖31之XXXIIB-XXXIIB線剖面圖)。 [Figure 32] Figure 32(a) is a cross-sectional view showing the lead frame produced by the fifth embodiment of the present invention (the XXXIIA-XXXIIA line cross-sectional view of Figure 31), and Figure 32(b) is A cross-sectional view showing the lead frame caused by the sixth embodiment of the present invention (cross-sectional view taken along line XXXIIB-XXXIIB in FIG. 31).

〔圖33〕圖33，係為對於由本發明之第6實施形態所致之半導體裝置作展示的平面圖。 [FIG. 33] FIG. 33 is a plan view showing a semiconductor device according to the sixth embodiment of the present invention.

〔圖34〕圖34，係為對於由本發明之第6實施形態之變形例所致之半導體裝置作展示的平面圖。 [FIG. 34] FIG. 34 is a plan view showing a semiconductor device according to a modification of the sixth embodiment of the present invention.

〔第1實施形態〕 [First Embodiment]

以下，參考圖1~圖7，對本發明之第1實施形態作說明。另外，在以下之各圖中，針對相同的部份，係附加相同之元件符號，並會有省略一部分之詳細說明的情形。 Hereinafter, the first embodiment of the present invention will be described with reference to FIGS. 1 to 7. In addition, in the following figures, the same reference numerals are attached to the same parts, and some detailed descriptions may be omitted.

導線框架之構成 The composition of the lead frame

首先，根據圖1~圖3，對由本實施形態所致之導線框架的概略內容作說明。圖1，係為對於由本實施形態所致之導線框架作展示的平面圖，圖2，係為對於由本實施形態所致之導線框架作展示的底面圖。圖3(a)、(b)，係分別為對於由本實施形態所致之導線框架作展示的剖面圖。 First, based on FIGS. 1 to 3, the outline of the lead frame according to this embodiment will be described. Fig. 1 is a plan view showing the lead frame caused by this embodiment, and Fig. 2 is a bottom view showing the lead frame caused by this embodiment. Figures 3(a) and (b) are respectively cross-sectional views showing the lead frame resulting from this embodiment.

如圖1~圖3中所示一般，導線框架10，係具備有：晶粒墊11，係搭載有半導體元件21(於後再述)；和複數之細長的外周導線部12A、12B，係被設置於晶粒墊11之周圍，並分別與半導體元件21以及外部電路(未圖示)作連接；和連接環14，係被設置在晶粒墊11和外周導線部12A、12B之間。又，分別具備有第2端子部18之複數之內側導線部26A~26D，係藉由連接環14而被作支持。 As shown in FIGS. 1 to 3, the lead frame 10 is generally provided with: die pad 11, which is equipped with semiconductor elements 21 (described later); and plural slender outer peripheral lead parts 12A, 12B, It is arranged around the die pad 11 and is respectively connected to the semiconductor element 21 and an external circuit (not shown); and the connecting ring 14 is arranged between the die pad 11 and the outer peripheral lead portions 12A, 12B. In addition, a plurality of inner lead portions 26A to 26D each having the second terminal portion 18 are supported by the connecting ring 14.

此導線框架10，係包含有分別身為與半導體裝置20(於後再述)相對應之區域的複數之單位導線框架10a。單位導線框架10a，在圖1中係身為位置在假想線之內側處的區域。此些之複數之單位導線框架10a，係經由支持導線(支持構件)13而被相互作連結。此支持導線13，係為支持晶粒墊11和外周導線部12A、12B以及連接環14者，並分別沿著X方向以及垂直於X方向之Y方向而延伸。 The lead frame 10 includes a plurality of unit lead frames 10a respectively corresponding to the semiconductor device 20 (described later). The unit lead frame 10a is a region located inside the imaginary line in FIG. 1. These plural unit lead frames 10a are connected to each other via supporting wires (supporting members) 13. The supporting wire 13 is for supporting the die pad 11, the outer peripheral wire portions 12A, 12B, and the connecting ring 14, and respectively extends along the X direction and the Y direction perpendicular to the X direction.

晶粒墊11，係為平面略矩形狀，其之4邊係沿著X方向或Y方向之其中一者而延伸。又，在晶粒墊11之四角隅處，係被連結有懸吊導線16。而，晶粒墊11，係經由此4根的懸吊導線16而被連結支持於支持導線13處。 The die pad 11 is substantially rectangular in plane, and its four sides extend along either the X direction or the Y direction. In addition, suspension wires 16 are connected to the four corners of the die pad 11. However, the die pad 11 is connected and supported at the supporting wire 13 via the four suspension wires 16.

又，複數之外周導線部12A、12B，係沿著各單位導線框架10a之外周而設置，並包含有相對性而言為較長之長外周導線部12A、和相對性而言為較短之短外周導線部12B。在本說明書中，係亦將長外周導線部12A和短外周導線部12B總稱為外周導線部12A、12B。以下，針對此種外周導線部12A、12B之構成更進一步作說明。 In addition, the plurality of outer peripheral lead portions 12A, 12B are arranged along the outer circumference of each unit lead frame 10a, and include relatively long outer peripheral lead portions 12A and relatively short ones Short outer peripheral wire portion 12B. In this specification, the long outer peripheral lead portion 12A and the short outer peripheral lead portion 12B are collectively referred to as outer peripheral lead portions 12A and 12B. Hereinafter, the structure of such outer peripheral lead portions 12A, 12B will be further described.

如圖1~圖3中所示一般，各外周導線部12A、12B，係分別具備有連接導線52和第1端子部53。其中，第1端子部53係於其之表面上具備有內部端子15A。此內部端子15A，係如同後述一般，成為經由接合打線22而被與半導體元件21作電性連接之區域。因此，在內部端子15A上，係設置有用以提昇其與接合打線22之間的密著性之電鍍部25。又，連接導線52，係位置在較第1端子部53而更外側(支持導線13側)處，其之基端部係被連結於支持導線13處。此連接導線52，係相對於該連接導線52所被作連結之支持導線13而垂直地延伸。 Generally, as shown in FIGS. 1 to 3, each of the outer peripheral lead portions 12A, 12B is provided with a connecting lead 52 and a first terminal portion 53, respectively. Among them, the first terminal portion 53 is provided with an internal terminal 15A on its surface. This internal terminal 15A is a region that is electrically connected to the semiconductor element 21 via the bonding wire 22 as described later. Therefore, the internal terminal 15A is provided with a plating part 25 to improve the adhesion between the internal terminal 15A and the bonding wire 22. In addition, the connection lead 52 is located outside the first terminal 53 (on the side of the support lead 13), and its base end is connected to the support lead 13. The connecting wire 52 extends vertically relative to the supporting wire 13 to which the connecting wire 52 is connected.

又，如圖3(a)、(b)中所示一般，外周導線部12A、12B之連接導線52，係分別從背面側(與搭載 半導體元件21之面相反側)而藉由半蝕刻來形成為厚度較薄。另一方面，第1端子部53，係並不被作半蝕刻地而具備有與晶粒墊11以及支持導線13相同之厚度。如此這般，藉由使連接導線52之厚度成為較第1端子部53之厚度更薄，係能夠以良好精確度來形成寬幅為窄之外周導線部12A、12B，而能夠得到小型且銷數為多之半導體裝置20。另外，所謂半蝕刻，係指對於被蝕刻材料而一直蝕刻至直到其之厚度方向的途中為止。 In addition, as shown in Fig. 3(a) and (b), generally, the connecting lead wires 52 of the outer peripheral lead portions 12A and 12B are connected from the back side (and the mounting The side opposite to the surface of the semiconductor element 21) is formed with a thin thickness by half etching. On the other hand, the first terminal portion 53 is not half-etched but has the same thickness as the die pad 11 and the support wire 13. In this way, by making the thickness of the connecting wire 52 thinner than the thickness of the first terminal portion 53, it is possible to form the wide and narrow outer peripheral wire portions 12A, 12B with good accuracy, and a small and small pin can be obtained. There are a large number of semiconductor devices 20. In addition, the term "half etching" means that the material to be etched is etched until it is halfway in the thickness direction.

在各外周導線部12A、12B之第1端子部53的背面，係分別形成有被與外部之安裝基板(未圖示)作電性連接之外部端子17A、17B。各外部端子17A、17B，係在半導體裝置20(於後再述)之製造後，分別成為從半導體裝置20而露出於外部。 On the back surface of the first terminal portion 53 of each outer peripheral lead portion 12A, 12B, external terminals 17A, 17B electrically connected to an external mounting board (not shown) are respectively formed. The external terminals 17A and 17B are respectively exposed to the outside from the semiconductor device 20 after the semiconductor device 20 (described later) is manufactured.

此些之第1端子部53中的長外周導線部12A之第1端子部53，係相對性地位置於內側(晶粒墊11側)，短外周導線部12B之第1端子部53，係相對性地位置於外側(支持導線13側)。 The first terminal portion 53 of the long outer peripheral lead portion 12A of these first terminal portions 53 is relatively positioned on the inner side (the die pad 11 side), and the first terminal portion 53 of the short outer peripheral lead portion 12B is The relative position is placed on the outside (supporting the wire 13 side).

又，外周導線部12A、12B之外部端子17A、17B，係以在相鄰接之外周導線部12A、12B之間而位置於內側以及外側的方式，來在作平面性觀察時被交互地配置為交錯狀。亦即是，在晶粒墊11之周圍，具有相對性地位置於內側(晶粒墊11側)之外部端子(內側外部端子)17A的長外周導線部12A，和具有相對性地位置於外側(支持導線13側)之外部端子(外側外部端子)17B 的短外周導線部12B，係沿著支持導線13之各邊而被交互作配置。藉由此，就算是在將外周導線部12A和12B作近接設置的情況時，也能夠對於外部端子17A和17B相互接觸的問題作防止。於此情況，外部端子17A以及外部端子17B，係全部具備有相同之平面形狀。 In addition, the external terminals 17A, 17B of the outer peripheral lead portions 12A, 12B are alternately arranged in a plan view such that they are located inside and outside between the adjacent outer peripheral lead portions 12A, 12B. For staggered. That is, around the die pad 11, the long outer peripheral lead portion 12A of the external terminal (inner external terminal) 17A that has a relative position on the inner side (the die pad 11 side), and the long outer peripheral lead portion 12A that has a relative position on the outer side (Support lead 13 side) external terminal (outer external terminal) 17B The short outer peripheral wire portions 12B of φ are alternately arranged along each side of the supporting wire 13. With this, even when the outer peripheral lead portions 12A and 12B are arranged in close proximity, the problem of contact between the external terminals 17A and 17B can be prevented. In this case, the external terminal 17A and the external terminal 17B all have the same planar shape.

進而，如圖2中所示一般，複數之外部端子17A，係當作平面性觀察時，均為沿著與晶粒墊11之一邊相平行的直線而被配列。同樣的，複數之外部端子17B，係當作平面性觀察時，均為沿著與晶粒墊11之一邊相平行的直線而被配列。亦即是，複數之外部端子17A、17B，係沿著與X方向或者是Y方向之其中一者相平行的直線而被配列成2列。 Furthermore, generally, as shown in FIG. 2, the plural external terminals 17A are all arranged along a straight line parallel to one side of the die pad 11 when viewed as a planar view. Similarly, the plurality of external terminals 17B are all arranged along a straight line parallel to one side of the die pad 11 when viewed as a planar view. That is, the plural external terminals 17A and 17B are arranged in two rows along a straight line parallel to either the X direction or the Y direction.

於此情況，相互鄰接之外周導線部12A、12B之間的間隔，係以設為90μm~150μm為理想。如此這般，藉由將外周導線部12A、12B之間的間隔設為90μm以上，係能夠藉由蝕刻而確實地形成相互鄰接之外周導線部12A、12B之間的貫通部分。又，藉由將上述間隔設為150μm以下，係能夠將各半導體裝置20之外部端子17A、17B的數量(銷數)確保有一定數量以上。 In this case, the interval between the outer peripheral lead portions 12A and 12B adjacent to each other is preferably 90 μm to 150 μm. In this way, by setting the interval between the outer peripheral lead portions 12A, 12B to be 90 μm or more, it is possible to reliably form the penetration portion between the outer peripheral lead portions 12A, 12B adjacent to each other by etching. In addition, by setting the above-mentioned interval to 150 μm or less, the number of external terminals 17A and 17B (the number of pins) of each semiconductor device 20 can be secured to a certain number or more.

接著，針對連接環14以及內側導線部26A~26D之構成作說明。 Next, the configuration of the connecting ring 14 and the inner lead portions 26A to 26D will be described.

如圖1以及圖2中所示一般，連接環14，係在外周導線部12A、12B之前端側處，以包圍晶粒墊11的方式而被作配置。此連接環14，係作為全體而具備有 略矩形形狀，其之各邊係沿著X方向或Y方向而延伸。在連接環14之四角隅處，係分別被連接有懸吊導線16，連接環14，係經由4根的懸吊導線16而被支持於支持導線13處。 Generally, as shown in FIGS. 1 and 2, the connecting ring 14 is arranged on the front end side of the outer peripheral lead portions 12A, 12B so as to surround the die pad 11. This connecting ring 14 is provided as a whole Slightly rectangular shape, each side of which extends along the X direction or the Y direction. At the four corners of the connecting ring 14, suspension wires 16 are respectively connected, and the connecting ring 14 is supported by the supporting wires 13 via four suspension wires 16.

在連接環14之表面上，係沿著連接環14之長邊方向而被形成有凹溝14a。此凹溝14a，係為藉由半蝕刻所形成者，而在厚度方向上並不被作貫通地來具有一定之深度。又，凹溝14a，係被形成於連接環14之寬幅方向略中央部處，在凹溝14a之寬幅方向兩側處，係被形成有並未被作半蝕刻之堤部14b。於此情況，連接環14之與長邊方向相垂直的剖面，係成為略凹字形狀或略U字形狀。另外，在本實施形態中，凹溝14a，係被形成於連接環14之全周的除了四角隅以外之處，但是，係並不被限定於此，例如，亦可包含有連接環14之四角隅地而涵蓋全周來作設置。又，係亦可構成為：在連接環14處係並未被設置有凹溝14a，而使連接環14之全體維持為金屬基板之板厚的狀態。 On the surface of the connecting ring 14, a groove 14 a is formed along the longitudinal direction of the connecting ring 14. The groove 14a is formed by half-etching and is not penetrated in the thickness direction to have a certain depth. The groove 14a is formed at the center of the connecting ring 14 in the width direction. On both sides of the groove 14a in the width direction, bank portions 14b that are not half-etched are formed. In this case, the cross section of the connecting ring 14 perpendicular to the longitudinal direction has a slightly concave shape or a slightly U shape. In addition, in this embodiment, the groove 14a is formed on the entire circumference of the connecting ring 14 except for the four corners. However, the system is not limited to this. For example, it may include a connecting ring 14 Set in four corners and cover the whole week. In addition, it may be configured such that the connecting ring 14 is not provided with the groove 14a, and the entire connecting ring 14 is maintained at the thickness of the metal substrate.

藉由如此這般而設置凹溝14a，由於連接環14之體積係減少，因此，如同後述一般，在將複數之第2端子部18個別地分離時，係成為易於將連接環14藉由蝕刻來除去。 By providing the groove 14a in this way, the volume of the connecting ring 14 is reduced. Therefore, as described later, when the plurality of second terminal portions 18 are individually separated, it becomes easier to etch the connecting ring 14 To remove.

另一方面，從連接環14，係分別延伸出複數之內側導線部26A~26D。此些之複數之內側導線部26A~26D，係包含有相對性而言為較長之長內側導線部 26A、26C，和相對性而言為較短之短內側導線部26B、26D。在本說明書中，係亦將長內側導線部26A、26C和短內側導線部26B、26D總稱為內側導線部26A~26D。 On the other hand, from the connecting ring 14, a plurality of inner lead portions 26A to 26D respectively extend. These plural inner wire portions 26A~26D include relatively long inner wire portions 26A, 26C, and relatively short inner wire portions 26B, 26D. In this specification, the long inner wire portions 26A, 26C and the short inner wire portions 26B, 26D are collectively referred to as inner wire portions 26A to 26D.

各內側導線部26A~26D，係分別於其前端處具備有第2端子部18。第2端子部18，係如同後述一般，為經由接合打線22而被與半導體元件21作電性連接者。 Each of the inner lead portions 26A to 26D is provided with a second terminal portion 18 at its tip. The second terminal portion 18 is one that is electrically connected to the semiconductor element 21 via the bonding wire 22 as described later.

又，複數之第2端子部18，係沿著連接環14而相互空出有間隔地被作配列，並分別被連結支持於連接環14處。此第2端子部18，係如同後述一般，在製作半導體裝置20時，於將連接環14除去之後，被相互個別地分離。亦即是，各第2端子部18，於將連接環14除去之後，係成為會與晶粒墊11、連接環14以及其他之第2端子部18之全部均相互分離。 In addition, the plurality of second terminal portions 18 are arranged along the connection ring 14 with intervals therebetween, and are connected and supported at the connection ring 14 respectively. This second terminal portion 18 is generally separated from each other after the connection ring 14 is removed when the semiconductor device 20 is manufactured as described later. That is, each second terminal portion 18 is separated from all of the die pad 11, the connection ring 14 and the other second terminal portions 18 after the connection ring 14 is removed.

此些之複數之第2端子部18中的長內側導線部26A、26C之第2端子部18，係相對性地位置於從連接環14而分離了的部份處，短內側導線部26B、26D之第2端子部18，係相對性地位置於與連接環14相接近之部分處。 Among the plurality of second terminal portions 18, the long inner wire portions 26A, 26C and the second terminal portion 18 are placed in relative positions at the portions separated from the connecting ring 14. The short inner wire portions 26B, The second terminal portion 18 of 26D is placed at a relative position close to the connecting ring 14.

又，複數之內側導線部26A~26D中的長內側導線部26A和短內側導線部26B，係分別從連接環14之外側(支持導線13側)而延伸。此些之長內側導線部26A和短內側導線部26B，係在連接環14之外側處而被交互作配置。 In addition, the long inner wire portion 26A and the short inner wire portion 26B of the plurality of inner wire portions 26A to 26D respectively extend from the outer side of the connecting ring 14 (the supporting wire 13 side). The long inner wire portion 26A and the short inner wire portion 26B are arranged on the outer side of the connecting ring 14 and alternately arranged.

另一方面，長內側導線部26C和短內側導線部26D，係分別從連接環14之內側(晶粒墊11側)而延伸。此些之長內側導線部26C和短內側導線部26D，係在連接環14之內側處而被交互作配置。 On the other hand, the long inner lead portion 26C and the short inner lead portion 26D respectively extend from the inner side of the connecting ring 14 (the die pad 11 side). These long inner wire portions 26C and short inner wire portions 26D are arranged on the inner side of the connecting ring 14 and are alternately arranged.

如圖3(a)中所示一般，各內側導線部26A~26D，係分別具備有被與連接環14作連結之連接導線57，各連接導線57，係從背面側起而作了厚度薄化。如此這般，藉由將各內側導線部26A~26D之連接導線57作了厚度薄化，在藉由密封樹脂23而作了樹脂密封之後，密封樹脂23係從背面側起而朝向連接導線57作進入(參考圖5)。藉由此，在將連接環14藉由蝕刻而作了除去之後，係能夠對於第2端子部18脫落至背面側之問題作防止。 As shown in Figure 3(a), generally, each inner lead part 26A to 26D is provided with a connecting lead 57 connected to the connecting ring 14, and each connecting lead 57 is made thin from the back side.化. In this way, the thickness of the connecting lead 57 of each inner lead part 26A to 26D is thinned, and after resin sealing is performed by the sealing resin 23, the sealing resin 23 faces the connecting lead 57 from the back side. Make an entry (refer to Figure 5). With this, after the connection ring 14 is removed by etching, it is possible to prevent the problem that the second terminal portion 18 falls off to the back side.

又，各第2端子部18，係具備有被設置在表面側之內部端子15B、和被設置在背面側之外部端子17C~17F。其中，內部端子15B，係為經由接合打線22而被與半導體元件21作電性連接者。另外，在內部端子15B上，係與內部端子15A相同的，設置有用以提昇其與接合打線22之間的密著性之電鍍部25。又，外部端子17C~17F，係為被與外部之安裝基板(未圖示)作電性連接者，並分別被設置在內側導線部26A~26D之前端處。 In addition, each of the second terminal portions 18 is provided with internal terminals 15B provided on the front side and external terminals 17C to 17F provided on the back side. Among them, the internal terminal 15B is one that is electrically connected to the semiconductor element 21 via the bonding wire 22. In addition, the internal terminal 15B is the same as the internal terminal 15A, and is provided with a plating part 25 to improve the adhesion between the internal terminal 15B and the bonding wire 22. In addition, the external terminals 17C to 17F are electrically connected to an external mounting substrate (not shown), and are respectively provided at the front ends of the inner lead portions 26A to 26D.

如圖2中所示一般，位置在連接環14之外側(支持導線13側)處的內側導線部26A、26B之外部端子17C、17D，係以在相鄰接之內側導線部26A、26B之 間而位置於內側以及外側的方式，來在作平面性觀察時被交互地配置為交錯狀。亦即是，在晶粒墊11之周圍，相對性地位置於內側(晶粒墊11側)之外部端子17D，和相對性地位置於外側(支持導線13側)之外部端子17C，係沿著連接環14之各邊而被交互作配置。藉由此，就算是在將內側導線部26A和26B作近接設置的情況時，也能夠對於外部端子17C和17D相互接觸的問題作防止。 As shown in FIG. 2, generally, the external terminals 17C, 17D of the inner wire portions 26A, 26B located on the outer side of the connecting ring 14 (the side of the supporting wire 13) are located between the adjacent inner wire portions 26A, 26B The way they are located on the inside and outside are alternately arranged in a staggered shape during planar observation. That is, around the die pad 11, the external terminal 17D with a relative position on the inner side (on the side of the die pad 11) and the external terminal 17C with a relative position on the outer side (on the side of the support wire 13) are tied along The sides of the connecting ring 14 are alternately configured. With this, even when the inner lead portions 26A and 26B are arranged in close proximity, the problem of contact between the external terminals 17C and 17D can be prevented.

同樣的，位置在連接環14之內側(晶粒墊11側)處的內側導線部26C、26D之外部端子17E、17F，係以在相鄰接之內側導線部26C、26D之間而位置於內側以及外側的方式，來在作平面性觀察時被交互地配置為交錯狀。亦即是，在晶粒墊11之周圍，相對性地位置於內側(晶粒墊11側)之外部端子17E，和相對性地位置於外側(支持導線13側)之外部端子17F，係沿著連接環14之各邊而被交互作配置。藉由此，就算是在將內側導線部26C和26D作近接設置的情況時，也能夠對於外部端子17E和17F相互接觸的問題作防止。 Similarly, the external terminals 17E, 17F of the inner wire portions 26C, 26D located inside the connecting ring 14 (on the side of the die pad 11) are located between the adjacent inner wire portions 26C, 26D. The inner and outer methods are alternately arranged in a staggered shape for planar observation. That is, around the die pad 11, the external terminal 17E whose relative position is placed on the inner side (on the side of the die pad 11), and the external terminal 17F whose relative position is placed on the outside (the side of the support wire 13) are tied along The sides of the connecting ring 14 are alternately configured. With this, even when the inner lead portions 26C and 26D are arranged in close proximity, the problem of contact between the external terminals 17E and 17F can be prevented.

上述之複數之外部端子17C~17F，係當作平面性觀察時，均為沿著與晶粒墊11之一邊相平行的直線而被配列。亦即是，複數之外部端子17C~17F，係沿著與X方向或者是Y方向之其中一者相平行的直線而被配列成4列。 The aforementioned plural external terminals 17C-17F are all arranged along a straight line parallel to one side of the die pad 11 when viewed as a planar view. That is, the plural external terminals 17C-17F are arranged in 4 rows along a straight line parallel to either the X direction or the Y direction.

又，從連接環14之外側而延伸之短內側導線 部26B、和長外周導線部12A，係相互對向，從連接環14之外側而延伸之長內側導線部26A、和短外周導線部12B，係相互對向。藉由此，係能夠確保外部端子17A和外部端子17D之間的端子間距離、以及外部端子17B和外部端子17C之間的端子間距離，而能夠對於此些之端子彼此相互接觸的問題作防止。 Also, a short inner wire extending from the outer side of the connecting ring 14 The portion 26B and the long outer peripheral wire portion 12A are opposed to each other, and the long inner wire portion 26A and the short outer peripheral wire portion 12B extending from the outer side of the connecting ring 14 are opposed to each other. By this, it is possible to ensure the inter-terminal distance between the external terminal 17A and the external terminal 17D and the inter-terminal distance between the external terminal 17B and the external terminal 17C, and it is possible to prevent the problem of contact between these terminals. .

以上所說明了的導線框架10，作為全體，係由銅、銅合金、42合金(Ni42%之Fe合金)等的金屬所構成。又，導線框架10之厚度，雖亦係依存於所製造之半導體裝置20的構成，但是係可設為80μm~250μm。又，導線框架10，較理想，係由具備有750Mpa~1100Mpa之拉張強度的金屬材料所構成。在如同本實施形態一般之多銷構造之導線框架10中，係有必要將導線部12A、12B、26A~26D設為較先前技術者而更細，但是，藉由以上述一般之金屬來製作導線框架，係能夠得到具備有就算是細也難以變形之導線部12A、12B、26A~26D之導線框架10。 The lead frame 10 described above is, as a whole, composed of metals such as copper, copper alloy, 42 alloy (Ni42% Fe alloy). Also, the thickness of the lead frame 10 depends on the structure of the semiconductor device 20 to be manufactured, but it can be set to 80 μm to 250 μm. Moreover, the lead frame 10 is preferably composed of a metal material having a tensile strength of 750Mpa to 1100Mpa. In the lead frame 10 of the multi-pin structure as in the present embodiment, it is necessary to make the lead parts 12A, 12B, 26A~26D thinner than those of the prior art, but they are made of the above-mentioned general metal For the lead frame, it is possible to obtain the lead frame 10 having lead parts 12A, 12B, 26A to 26D that are difficult to deform even if they are thin.

另外，在圖1中，外周導線部12A、12B以及內側導線部26A~26D，雖係分別沿著晶粒墊11之4邊的全部而被作配置，但是，係並不被限定於此，例如，係亦可僅沿著晶粒墊11之相對向的2邊來作配置。又，內側導線部26A~26D，雖係從連接環14之外側(支持導線13側)以及內側(晶粒墊11側)的雙方而延伸，但是，係並不被限定於此，亦可僅從連接環14之外側或內側的 其中一方來延伸。 In addition, in FIG. 1, the outer peripheral lead portions 12A, 12B and the inner lead portions 26A to 26D are arranged along all the four sides of the die pad 11, but they are not limited to this. For example, it may be arranged only along the two opposite sides of the die pad 11. In addition, the inner lead portions 26A to 26D extend from both the outer side (supporting lead 13 side) and the inner side (die pad 11 side) of the connecting ring 14, but the system is not limited to this, and may only From the outside or inside of the connecting ring 14 One side to extend.

半導體裝置之構成 Structure of semiconductor device

接著，根據圖4以及圖5，對由本實施形態所致之半導體裝置作說明。圖4以及圖5係為對於由本實施形態所致之半導體裝置(DR-QFN(Dual Row QFN)型態)作展示之圖。 Next, the semiconductor device according to this embodiment will be described based on FIGS. 4 and 5. 4 and 5 are diagrams showing the semiconductor device (DR-QFN (Dual Row QFN) type) caused by this embodiment.

如圖4以及圖5中所示一般，半導體裝置(半導體封裝)20，係具備有：晶粒墊11、和被配置在晶粒墊11之周圍的複數之外周導線部12A、12B、和被配置在晶粒墊11與外周導線部12A、12B之間之複數之第2端子部18。其中，在晶粒墊11上，係搭載有半導體元件21，半導體元件21和各外周導線部12A、12B之第1端子部53以及各內側導線部26A~26D之第2端子部18，係分別藉由接合打線(連接構件)22而被作電性連接。又，晶粒墊11、外周導線部12A、12B、第2端子部18、半導體元件21以及接合打線22，係藉由密封樹脂23而被作樹脂密封。 As shown in FIGS. 4 and 5, in general, a semiconductor device (semiconductor package) 20 is provided with a die pad 11, and a plurality of peripheral lead portions 12A, 12B arranged around the die pad 11, and The plural second terminal portions 18 are arranged between the die pad 11 and the outer peripheral lead portions 12A, 12B. Among them, on the die pad 11, the semiconductor element 21, the semiconductor element 21, the first terminal portion 53 of each outer peripheral lead portion 12A, 12B, and the second terminal portion 18 of each inner lead portion 26A to 26D are mounted, respectively The electrical connection is made by bonding wires (connection members) 22. In addition, the die pad 11, the outer peripheral lead portions 12A, 12B, the second terminal portion 18, the semiconductor element 21, and the bonding wire 22 are resin-sealed by the sealing resin 23.

其中，晶粒墊11、外周導線部12A、12B以及內側導線部26A~26D，係為從上述之導線框架10所製作者。此晶粒墊11、外周導線部12A、12B以及內側導線部26A~26D之構成，除了並不被包含於單位導線框架10a中的區域以外，係為與上述之圖1~圖3中所示者略相同，於此係省略詳細之說明。 Among them, the die pad 11, the outer peripheral wire portions 12A, 12B, and the inner wire portions 26A to 26D are manufactured from the lead frame 10 described above. The structure of the die pad 11, the outer peripheral lead portions 12A, 12B, and the inner lead portions 26A to 26D, except for the area not included in the unit lead frame 10a, is similar to that shown in FIGS. 1 to 3 above. Those are slightly the same, and detailed description is omitted here.

另一方面，上述之連接環14，係在藉由密封樹脂23而被作了樹脂密封之後，從背面側起來藉由蝕刻而除去。因此，如同圖4以及圖5中所示一般，各內側導線部26A~26D之第2端子部18，係從晶粒墊11、外周導線部12A、12B以及其他之第2端子部18而分離，並與此些之構件相互電性獨立。 On the other hand, the above-mentioned connecting ring 14 is resin-sealed by the sealing resin 23 and then removed from the back side by etching. Therefore, as shown in FIGS. 4 and 5, the second terminal portions 18 of the inner lead portions 26A to 26D are separated from the die pad 11, the outer peripheral lead portions 12A, 12B, and other second terminal portions 18 , And electrically independent of these components.

如此這般，伴隨著連接環14被除去一事，在密封樹脂23之背面中的外周導線部12A、12B和晶粒墊11之間之內側導線部26A、26B與內側導線部26C、26D之間的區域處，係被形成有凹部27。此凹部27，係概略與連接環14之形狀相對應，並以包圍晶粒墊11的方式而具備有平面矩形形狀。另外，在凹部27內，係突出有由密封樹脂23之一部分所成的突起部27a(參考圖5)。此突起部27a，係具備有與上述之連接環14之凹溝14a相對應的形狀。另外，在凹部27中，係亦可填充有與密封樹脂23相同或者是相異種類之絕緣性樹脂。 In this way, as the connecting ring 14 is removed, between the inner wire portions 26A, 26B and the inner wire portions 26C, 26D between the outer peripheral wire portions 12A, 12B and the die pad 11 on the back of the sealing resin 23 A recessed portion 27 is formed in the area of ?? The recess 27 roughly corresponds to the shape of the connecting ring 14 and has a planar rectangular shape so as to surround the die pad 11. In addition, in the recess 27, a protrusion 27a formed by a part of the sealing resin 23 protrudes (refer to FIG. 5). The protrusion 27a has a shape corresponding to the groove 14a of the connecting ring 14 described above. In addition, the recess 27 may be filled with an insulating resin of the same or a different type as the sealing resin 23.

另一方面，作為半導體元件21，係可使用在先前技術中所一般使用之各種半導體元件，而並未特別限定，但是，例如係可使用積體電路、大規模積體電路、電晶體、閘流體、二極體等。此半導體元件21，係具備分別被安裝有接合打線22之複數之電極21a。又，半導體元件21，例如係藉由黏晶糊等之接著劑24而被固定在晶粒墊11之表面上。 On the other hand, as the semiconductor element 21, various semiconductor elements generally used in the prior art can be used without particular limitation. However, for example, integrated circuits, large-scale integrated circuits, transistors, and gates can be used. Fluids, diodes, etc. This semiconductor element 21 has a plurality of electrodes 21a on which bonding wires 22 are mounted, respectively. In addition, the semiconductor element 21 is fixed on the surface of the die pad 11 by, for example, an adhesive 24 such as die bonding paste.

各接合打線22，例如係由金、銅等之導電性 為佳的材料所成。各接合打線22，係分別使其之其中一端與半導體元件21之電極21a相連接，並且使其之另外一端分別與各外周導線部12A、12B之內部端子15A或者是第2端子部18之內部端子15B作連接。另外，在內部端子15A、15B處，係分別設置有用以提昇其與接合打線22之間的密著性之電鍍部25。 Each bonding wire 22 is made of gold, copper, etc. Made of good materials. Each bonding wire 22 has one end connected to the electrode 21a of the semiconductor element 21, and the other end is connected to the inner terminal 15A of the outer peripheral lead portions 12A, 12B or the inside of the second terminal portion 18. The terminal 15B is connected. In addition, the internal terminals 15A and 15B are respectively provided with plating parts 25 to improve the adhesion between the internal terminals 15A and 15B.

作為密封樹脂23，係可使用矽酮樹脂或環氧樹脂等之熱硬化性樹脂，或者是使用PPS樹脂等之熱可塑性樹脂。密封樹脂23全體之厚度，係可設為500μm~1000μm程度。另外，在圖4中，係將位置在較晶粒墊11、外周導線部12A、12B以及內側導線部26A~26D而更表面側的密封樹脂23之標示作省略。 As the sealing resin 23, a thermosetting resin such as silicone resin or epoxy resin, or a thermoplastic resin such as PPS resin can be used. The thickness of the entire sealing resin 23 can be set to about 500 μm to 1000 μm. In addition, in FIG. 4, the designation of the sealing resin 23 positioned on the surface side of the die pad 11, the outer peripheral lead portions 12A, 12B, and the inner lead portions 26A to 26D is omitted.

另外，半導體裝置20之一邊，例如係可設為8mm~16mm。 In addition, one side of the semiconductor device 20 can be set to 8 mm to 16 mm, for example.

導線框架之製造方法 Manufacturing method of lead frame

接下來，針對圖1乃至圖3中所示之導線框架10之製造方法，使用圖6(a)~(f)來作說明。另外，圖6(a)~(f)，係為對於導線框架10之製造方法作展示的剖面圖(與圖3(b)相對應之圖)。 Next, the manufacturing method of the lead frame 10 shown in FIG. 1 and FIG. 3 will be described using FIGS. 6(a) to (f). In addition, FIGS. 6(a) to (f) are cross-sectional views showing the manufacturing method of the lead frame 10 (a diagram corresponding to FIG. 3(b)).

首先，係如同圖6(a)中所示一般，準備平板狀之金屬基板31。作為此金屬基板31，係可使用由銅、銅合金、42合金(Ni42%之Fe合金)等的金屬所成之基板。另外，金屬基板31，較理想，係使用對於其之 兩面而進行脫脂等並施加了洗淨處理者。 First, as shown in FIG. 6(a), a flat metal substrate 31 is prepared. As the metal substrate 31, a substrate made of metal such as copper, copper alloy, 42 alloy (Ni42% Fe alloy), etc. can be used. In addition, the metal substrate 31 is ideally used for its Those who have been degreasing and cleaning both sides.

接著，在金屬基板31之表背面全體，分別塗布感光性光阻32a、33a，並使其乾燥(圖6(b))。另外，作為感光性光阻32a、33a，係可使用先前技術所公知之物。 Next, photosensitive resists 32a and 33a are applied to the entire front and back surfaces of the metal substrate 31 and dried (FIG. 6(b)). In addition, as the photosensitive resist 32a, 33a, what is known in the prior art can be used.

接著，隔著光罩來對此金屬基板31進行曝光並進行顯像，藉由此，來形成具備有所期望之開口部32b、33b之蝕刻用光阻層32、33(圖6(c))。 Next, this metal substrate 31 is exposed and developed through a photomask, thereby forming etching resist layers 32, 33 having desired openings 32b, 33b (FIG. 6(c) ).

接著，將蝕刻用光阻層32、33作為耐腐蝕膜，而藉由腐蝕液來對於金屬基板31施加蝕刻(圖6(d))。藉由此，係形成晶粒墊11、複數之外周導線部12A、12B、連接環14以及複數之內側導線部26A~26D的外形。腐蝕液，係可因應於所使用之金屬基板31的材質來適宜作選擇，例如，當作為金屬基板31而使用銅合金的情況時，通常，係可使用氯化鐵水溶液，並從金屬基板31之兩面起來藉由噴霧蝕刻而進行之。 Next, the photoresist layers 32 and 33 for etching are used as corrosion-resistant films, and the metal substrate 31 is etched by an etching solution (FIG. 6(d)). By this, the outer shape of the die pad 11, the plurality of outer peripheral wire portions 12A, 12B, the connection ring 14 and the plurality of inner wire portions 26A to 26D is formed. The etching solution can be appropriately selected according to the material of the metal substrate 31 used. For example, when a copper alloy is used as the metal substrate 31, usually an aqueous solution of ferric chloride can be used and the metal substrate 31 The two sides are raised by spray etching.

之後，將蝕刻用光阻層32、33剝離並除去(圖6(e))。 After that, the photoresist layers 32 and 33 for etching are peeled and removed (FIG. 6(e)).

另外，在上述內容中，雖係以從金屬基板31之兩面側來進行噴霧蝕刻的情況為例來作了說明，但是，係並不被限定於此。例如，係亦可對於金屬基板31而一次一面地來進行2個階段之噴霧蝕刻。具體而言，首先，係形成具有特定之圖案的蝕刻用光阻層32、33(參考圖6(c))，之後，在金屬基板31之背面側，設置具有耐蝕 刻性之密封層(未圖示)，並在此狀態下而僅對於金屬基板31之表面側實施蝕刻。接著，將該背面側之密封層剝離，並在金屬基板31之表面上設置密封層(未圖示)。此時，表面側之密封層，係亦會進入至被作了蝕刻加工的金屬基板31之表面側的凹部內。接著，僅對於金屬基板31之作了露出的背面進行蝕刻，之後，將表面側之密封層剝離，藉由此，而形成晶粒墊11、複數之外周導線部12A、12B、連接環14以及複數之內側導線部26A~26D的外形。藉由如此這般地對於金屬基板31而一次一面地進行噴霧蝕刻，係可得到下述之效果：亦即是，係容易避免發生外周導線部12A、12B以及內側導線部26A~26D之變形。 In addition, in the above, although the case where spray etching is performed from both sides of the metal substrate 31 is described as an example, the system is not limited to this. For example, the metal substrate 31 may be spray-etched in two stages, one surface at a time. Specifically, first, photoresist layers 32, 33 for etching with a specific pattern are formed (refer to FIG. 6(c)), and then, on the back side of the metal substrate 31, a corrosion-resistant A etched sealing layer (not shown) is etched only on the surface side of the metal substrate 31 in this state. Next, the sealing layer on the back side is peeled off, and a sealing layer (not shown) is provided on the surface of the metal substrate 31. At this time, the sealing layer on the surface side also enters the recesses on the surface side of the metal substrate 31 that has been etched. Next, only the exposed back surface of the metal substrate 31 is etched, and then the sealing layer on the front side is peeled off, thereby forming die pad 11, plural outer peripheral lead portions 12A, 12B, connecting ring 14, and The outer shape of the plural inner lead parts 26A~26D. By spray-etching the metal substrate 31 one side at a time in this way, the following effect can be obtained: that is, it is easy to avoid the deformation of the outer peripheral lead portions 12A, 12B and the inner lead portions 26A to 26D.

接著，為了將接合打線22和各內部端子15A、15B之間的密著性提昇，而對於各內部端子15A、15B分別施加電鍍處理，並形成電鍍部25(圖6(f))。於此情況，所選擇之電鍍種，只要是能夠確保有與接合打線22之間的密著性者，則係並不對其之種類作限定，但是，例如，係可為Ag或Au等之單層電鍍，亦可為將Ni/Pd或者是Ni/Pd/Au依此順序來作了層積的複數層電鍍。又，電鍍部25，係可僅對於外周導線部12A、12B以及內側導線部26A~26D中之與接合打線22之間的連接部作施加，亦可對於導線框架10之全面作施加。 Next, in order to improve the adhesion between the bonding wire 22 and the internal terminals 15A and 15B, the internal terminals 15A and 15B are respectively subjected to electroplating treatment to form the plated portions 25 (FIG. 6(f)). In this case, as long as the selected plating type is one that can ensure adhesion to the bonding wire 22, the type is not limited. However, for example, it may be a single type such as Ag or Au. The layer electroplating may also be a multiple layer electroplating in which Ni/Pd or Ni/Pd/Au is laminated in this order. In addition, the plating part 25 can be applied only to the connection part between the outer peripheral lead parts 12A, 12B and the inner lead parts 26A to 26D and the bonding wire 22, or can be applied to the entire surface of the lead frame 10.

如此這般，而能夠得到如圖1~圖3中所示之 導線框架10。 In this way, you can get the data shown in Figure 1~Figure 3. Wire frame 10.

半導體裝置之製造方法 Manufacturing method of semiconductor device

接下來，針對圖4以及圖5中所示之半導體裝置20之製造方法，使用圖7(a)~(f)來作說明。圖7(a)~(f)，係為對於半導體裝置20之製造方法作展示的剖面圖(與圖5相對應之圖)。 Next, the manufacturing method of the semiconductor device 20 shown in FIGS. 4 and 5 will be described using FIGS. 7(a) to (f). FIGS. 7(a) to (f) are cross-sectional views showing the manufacturing method of the semiconductor device 20 (a diagram corresponding to FIG. 5).

首先，例如藉由圖6(a)~(f)中所示之方法(如上所述)，來製作導線框架10。 First, for example, the lead frame 10 is manufactured by the method shown in FIGS. 6(a) to (f) (as described above).

接著，在導線框架10之晶粒墊11上，搭載半導體元件21。於此情況，例如係使用黏晶糊等之接著劑24，而將半導體元件21載置在晶粒墊11上並作固定(黏晶工程)(圖7(a))。 Next, the semiconductor element 21 is mounted on the die pad 11 of the lead frame 10. In this case, for example, an adhesive 24 such as a die bonding paste is used, and the semiconductor element 21 is placed on the die pad 11 and fixed (die bonding process) (FIG. 7(a)).

接著，將半導體元件21之各電極21a和各外周導線部12A、12B之電鍍部25(內部端子15A)分別藉由接合打線(連接構件)22而相互作電性連接。同樣的，將半導體元件21之各電極21a和各內側導線部26A~26D之電鍍部25(內部端子15B)分別藉由接合打線(連接構件)22而相互作電性連接(打線接合工程)(圖7(b))。 Next, the electrodes 21a of the semiconductor element 21 and the plating portions 25 (internal terminals 15A) of the outer peripheral lead portions 12A and 12B are electrically connected to each other by bonding wires (connecting members) 22, respectively. Similarly, each electrode 21a of the semiconductor element 21 and the plating portion 25 (internal terminal 15B) of each inner lead portion 26A to 26D are electrically connected to each other by bonding wires (connection members) 22 (wire bonding process) ( Figure 7(b)).

此時，係將導線框架10載置在打線接合裝置之加熱塊36上。接著，藉由加熱塊36，來對於各外周導線部12A、12B以及各內側導線部26A~26D而從該些之背面側來進行加熱。與此同時地，一面經由打線接合裝置之毛細管(未圖示)來施加超音波，一面將半導體元件 21之各電極21a和各外周導線部12A、12B以及各內側導線部26A~26D之電鍍部25分別使用接合打線22而作電性連接。 At this time, the lead frame 10 is placed on the heating block 36 of the wire bonding device. Next, the heating block 36 heats the outer peripheral lead portions 12A, 12B and the inner lead portions 26A to 26D from the back side. At the same time, while applying ultrasonic waves through the capillary (not shown) of the wire bonding device, the semiconductor device The electrodes 21a of 21, the outer peripheral lead portions 12A, 12B, and the plating portions 25 of the inner lead portions 26A to 26D are respectively electrically connected by bonding wires 22.

接著，藉由對於導線框架10而將熱硬化性樹脂或熱可塑性樹脂作射出成形或者是轉移成形，來形成密封樹脂23(圖7(c))。如此這般，晶粒墊11、複數之外周導線部12A、12B、複數之內側導線部26A~26D、半導體元件21以及接合打線22，係被作樹脂密封。 Next, by injection molding or transfer molding thermosetting resin or thermoplastic resin to the lead frame 10, the sealing resin 23 is formed (FIG. 7(c)). In this way, the die pad 11, the plurality of outer peripheral wire portions 12A, 12B, the plurality of inner wire portions 26A to 26D, the semiconductor element 21, and the bonding wire 22 are sealed with resin.

接著，在導線框架10以及密封樹脂23之背面，設置具備有特定之開口部34a的蝕刻用光阻層34((圖7(d))。 Next, on the back surfaces of the lead frame 10 and the sealing resin 23, a photoresist layer 34 for etching provided with a specific opening 34a is provided ((FIG. 7(d))).

於此期間中，首先係在導線框架10以及密封樹脂23之背面全體，分別塗布感光性光阻。接著，隔著光罩來對該感光性光阻進行曝光並進行顯像，藉由此，來形成具備有所期望之開口部34a之蝕刻用光阻層34。 During this period, first, a photosensitive photoresist is applied to the entire back surface of the lead frame 10 and the sealing resin 23, respectively. Next, the photosensitive photoresist is exposed and developed through a photomask, thereby forming a photoresist layer 34 for etching having a desired opening 34a.

於此情況，蝕刻用光阻層34，係將除了開口部34a以外的導線框架10以及密封樹脂23之背面全體作覆蓋。又，開口部34a，係具備有與連接環14之位置略對應的平面略矩形的帶形狀，連接環14之背面(金屬部分)係從開口部34a而露出。另外，作為蝕刻用光阻層34，例如係可使用周知之乾薄膜光阻。 In this case, the photoresist layer 34 for etching covers the entire back surface of the lead frame 10 and the sealing resin 23 except for the opening 34a. In addition, the opening 34a is provided with a substantially rectangular band shape in a plane corresponding to the position of the connecting ring 14, and the back surface (metal part) of the connecting ring 14 is exposed from the opening 34a. In addition, as the photoresist layer 34 for etching, for example, a well-known dry film photoresist can be used.

接著，將蝕刻用光阻層34作為耐腐蝕膜，而藉由腐蝕液來對於導線框架10施加蝕刻(圖7(e))。此時，從開口部34a所進入之腐蝕液，係將連接環14之 全體溶解並除去。此時，內側導線部26A~26D之連接導線57的一部分，係亦可被與連接環14一同地被除去。於此情況，由於在連接環14之表面上係被設置有凹溝14a，因此，從開口部34a所進入的腐蝕液，係並不會將第2端子部18和外周導線部12A、12B作必要以上之溶解，而能夠適當地將連接環14除去。 Next, the photoresist layer 34 for etching is used as a corrosion-resistant film, and the lead frame 10 is etched by an etching solution (FIG. 7(e)). At this time, the corrosive liquid entering from the opening 34a is used to connect the connecting ring 14 The whole is dissolved and removed. At this time, part of the connecting wire 57 of the inner wire portions 26A to 26D may be removed together with the connecting ring 14. In this case, since the groove 14a is provided on the surface of the connecting ring 14, the corrosive liquid entering from the opening 34a does not use the second terminal portion 18 and the outer peripheral lead portions 12A, 12B as The above dissolution is necessary, and the connecting ring 14 can be removed appropriately.

如此這般，連接環14係被除去，內側導線部26A~26D係被相互分離。其結果，各第2端子部18係被個別地分離，並與晶粒墊11、外周導線部12A、12B以及其他之第2端子部18相互電性獨立。另外，腐蝕液，係與上述相同的(參考圖6(d))，例如可使用氯化鐵水溶液。 In this way, the connecting ring 14 is removed, and the inner lead portions 26A to 26D are separated from each other. As a result, the second terminal portions 18 are individually separated and are electrically independent from the die pad 11, the outer peripheral lead portions 12A, 12B, and the other second terminal portions 18. In addition, the etching solution is the same as described above (refer to FIG. 6(d)), and for example, an aqueous ferric chloride solution can be used.

接著，將蝕刻用光阻層34剝離並除去。之後，藉由對於各半導體元件21間之導線框架10以及密封樹脂23進行切割，來將導線框架10個別分離成各單位導線框架10a(參考圖1)。此時，例如係亦可一面使由鑽石砥石所成之刃(未圖示)旋轉，一面將各單位導線框架10a間之導線框架10以及密封樹脂23切斷。另外，在將蝕刻用光阻層34除去之後，係亦可設置在凹部27中填充與密封樹脂23相同或者是其他種類之絕緣性樹脂的工程。 Next, the photoresist layer 34 for etching is peeled and removed. After that, the lead frame 10 and the sealing resin 23 between the semiconductor elements 21 are cut to separate the lead frame 10 into each unit lead frame 10a (refer to FIG. 1). At this time, for example, the lead frame 10 and the sealing resin 23 between the unit lead frames 10a may be cut while rotating a blade (not shown) made of diamond whetstone. In addition, after the photoresist layer 34 for etching is removed, a process of filling the recess 27 with the same or another type of insulating resin as the sealing resin 23 may be provided.

如此這般，而能夠得到如圖4以及圖5中所示之半導體裝置20(圖7(f))。 In this way, the semiconductor device 20 shown in FIGS. 4 and 5 can be obtained (FIG. 7(f)).

如此這般，若依據本實施形態，則第1端子 部53為相對性地位置於內側之長外周導線部12A、和第1端子部53為相對性地位置於外側之短外周導線部12B，係被交互地作配置。藉由此，由於係能夠在將外周導線部12A、12B之間隔縮窄的同時亦將其之根數增加，因此係能夠將第1端子部53之數量增加。 In this way, if according to this embodiment, the first terminal The portion 53 is the long outer peripheral wire portion 12A relatively positioned inside, and the first terminal portion 53 is the short outer peripheral wire portion 12B relatively positioned outside, and they are alternately arranged. With this, since the interval between the outer peripheral lead portions 12A and 12B can be narrowed and the number of the wires can be increased, the number of the first terminal portions 53 can be increased.

又，若依據本實施形態，則在製作半導體裝置20時，藉由將連接環14除去，複數之第2端子部18係成為被相互個別地分離。因此，係除了外周導線部12A、12B之第1端子部53以外亦能夠使用內側導線部26A~26D之第2端子部18，而能夠將與外部之安裝基板作連接的端子部之數量(銷數)更進一步增加。藉由此，係能夠實現半導體裝置20之高密度化。 In addition, according to this embodiment, when the semiconductor device 20 is manufactured, by removing the connecting ring 14, the plural second terminal portions 18 are separated from each other individually. Therefore, in addition to the first terminal portions 53 of the outer peripheral lead portions 12A, 12B, the second terminal portions 18 of the inner lead portions 26A to 26D can also be used, and the number of terminal portions (pins) that can be connected to the external mounting board Number) further increase. With this, it is possible to achieve high density of the semiconductor device 20.

特別是，若依據本實施形態，則第2端子部18為相對性地位置於從連接環14而分離的部份處之長內側導線部26A、26C，和第2端子部18為相對性地位置於接近連接環14的部份處之短內側導線部26B、26D，係被交互地作配置。進而，複數之內側導線部26A~26D，係從連接環14之內側以及外側的雙方而延伸。藉由此，由於係能夠在將內側導線部26A~26D之間隔縮窄的同時亦將其之根數增加，因此係能夠將第2端子部18之數量增加。 In particular, according to the present embodiment, the second terminal portion 18 is the long inner lead portion 26A, 26C placed at the portion separated from the connecting ring 14 in a relative position, and the second terminal portion 18 is relatively ground. The short inner wire portions 26B, 26D located near the portion of the connecting ring 14 are alternately arranged. Furthermore, the plural inner lead portions 26A to 26D extend from both the inner side and the outer side of the connecting ring 14. With this, since the interval between the inner lead portions 26A to 26D can be narrowed and the number of the wires can be increased, the number of the second terminal portions 18 can be increased.

另外，在本實施形態中，雖係以將連接環14之全體藉由蝕刻來除去的情況為例來作了說明，但是，係並不被限定於此。例如，係亦可僅將連接環14之一部分 藉由蝕刻來除去，並使連接環14中之並未被除去的部份殘留於半導體裝置20內。 In addition, in this embodiment, although the case where the whole connection ring 14 is removed by etching was demonstrated as an example, it is not limited to this. For example, the system can also connect only part of the connecting ring 14 It is removed by etching, and the unremoved part of the connecting ring 14 remains in the semiconductor device 20.

又，在上述實施形態中，係針對內側導線部26A、26B之外部端子17C、17D(內側導線部26C、26D之外部端子17E、17F)為以在相鄰接之內側導線部26A、26B(內側導線部26C、26D)之間而位置於內側以及外側的方式，來在作平面性觀察時被交互地以交錯狀來配置成2列的情況為例，來作了說明。然而，係並不被限定於此，內側導線部26A、26B之外部端子17C、17D(內側導線部26C、26D之外部端子17E、17F)，係亦可沿著連接環14之各邊而並排於一直線上。 Furthermore, in the above-mentioned embodiment, the external terminals 17C, 17D of the inner lead portions 26A, 26B (the outer terminals 17E, 17F of the inner lead portions 26C, 26D) are connected to the inner lead portions 26A, 26B ( The method in which the inner lead portions 26C and 26D) are positioned on the inner side and the outer side has been described as an example of a case where they are alternately arranged in two rows in a staggered manner during planar observation. However, the system is not limited to this. The external terminals 17C, 17D of the inner lead portions 26A, 26B (the outer terminals 17E, 17F of the inner lead portions 26C, 26D) may be arranged side by side along each side of the connecting ring 14. On a straight line.

(第2實施形態) (Second Embodiment)

接著，參考圖8~圖11，對本發明之第2實施形態作說明。圖8乃至圖11，係為對於本發明之第2實施形態作展示者。圖8乃至圖11中所示之第2實施形態，係代替在連接環14處設置具有第2端子部之內側導線部26A~26D，係使連接環14之一部分個別地分離並成為第2端子部28，在此點上，係與第1實施形態相異，其他構成則係與第1實施形態相同。在圖8乃至圖11中，針對與第1實施形態相同的部份，係附加相同之元件符號，並省略詳細說明。 Next, referring to FIGS. 8 to 11, the second embodiment of the present invention will be described. Fig. 8 and Fig. 11 show the second embodiment of the present invention. The second embodiment shown in Figs. 8 and 11, instead of providing the inner lead portions 26A to 26D with second terminal portions at the connecting ring 14, separate a part of the connecting ring 14 and become the second terminal The part 28 is different from the first embodiment in this point, and the other structure is the same as the first embodiment. In FIG. 8 and FIG. 11, the same reference numerals are assigned to the same parts as in the first embodiment, and detailed descriptions are omitted.

在圖8~圖10所示之導線框架10A中，係在連接環14之表面上空出有間隔地而被形成有複數之凹部 14c。各凹部14c，係為藉由半蝕刻所形成者，而在厚度方向上並不被作貫通地來具有一定之深度。另外，各凹部14c，係被形成於連接環14之寬幅方向略中央部處。 In the lead frame 10A shown in FIGS. 8 to 10, the surface of the connecting ring 14 is formed with a plurality of recesses at intervals. 14c. Each recess 14c is formed by half-etching, and has a certain depth without being penetrated in the thickness direction. In addition, each recessed portion 14c is formed at a substantially central portion of the connecting ring 14 in the width direction.

又，在相互鄰接之凹部14c之間，係被形成有第2端子部28。亦即是，凹部14c和第2端子部28，係沿著連接環14之長邊方向而被交互作配置。於此情況，第2端子部28，係並不被作半蝕刻地而具備有與晶粒墊11以及支持導線13相同之厚度。另外，在各第2端子部28之表面上，係設置有用以提昇其與接合打線22之間的密著性之電鍍部25。 Moreover, the second terminal part 28 is formed between the recessed parts 14c adjacent to each other. That is, the recessed portion 14c and the second terminal portion 28 are alternately arranged along the longitudinal direction of the connecting ring 14. In this case, the second terminal portion 28 is not half-etched but has the same thickness as the die pad 11 and the support wire 13. In addition, on the surface of each second terminal portion 28, a plating portion 25 is provided to improve the adhesion between the second terminal portion 28 and the bonding wire 22.

在本實施形態中，於製造半導體裝置20A(參考圖11)時，係僅將連接環14之一部分藉由蝕刻來除去。具體而言，係將連接環14中之各凹部14c的周邊區域分別除去。另一方面，連接環14中之位置在各凹部14c之間的部分，係並不會被除去，而分別個別地被分離並構成第2端子部28。 In this embodiment, when manufacturing the semiconductor device 20A (refer to FIG. 11), only a part of the connecting ring 14 is removed by etching. Specifically, the peripheral regions of each recessed portion 14c in the connecting ring 14 are respectively removed. On the other hand, the portion of the connecting ring 14 located between the recesses 14c is not removed, but is separated individually to form the second terminal portion 28.

亦即是，在從導線框架10A之背面側起而將連接環14之一部分作蝕刻除去時(參考圖7(f))，係預先在與各凹部14c以及其周圍相對應的區域處設置蝕刻用光阻層34之開口部34a。之後，藉由從該開口部34a所進入之腐蝕液，而將連接環14中之各凹部14c的周邊區域選擇性地溶解並除去。於此情況，由於在連接環14之表面上係被設置有凹部14c，因此，從開口部34a所進入的腐蝕液，係並不會將第2端子部28和外周導線部 12A、12B作必要以上之溶解，而能夠適當地僅將連接環14中之各凹部14c之周邊區域除去。如此這般，在連接環中之相互鄰接之2個的凹部14c彼此之間，係分別殘留有第2端子部28。 That is, when a part of the connecting ring 14 is etched and removed from the back side of the lead frame 10A (refer to FIG. 7(f)), an etching is provided in advance in the area corresponding to each recess 14c and its periphery The opening 34a of the photoresist layer 34 is used. After that, the peripheral area of each recessed portion 14c in the connecting ring 14 is selectively dissolved and removed by the etching liquid entered from the opening 34a. In this case, since the concave portion 14c is provided on the surface of the connecting ring 14, the corrosive liquid entering from the opening 34a will not affect the second terminal portion 28 and the outer peripheral lead portion. 12A and 12B can be dissolved more than necessary, and only the peripheral area of each concave portion 14c in the connecting ring 14 can be removed appropriately. In this way, the second terminal portions 28 are left between the two adjacent recesses 14c in the connecting ring.

另外，在本實施形態中，凹部14c，雖係分別被形成於與長外周導線部12A之前端相對應的位置處，但是，係並不被限定於此，而亦可被形成於與短外周導線部12B之前端相對應的位置處。又，複數之凹部14c，雖係遍佈連接環14之周方向全區域地而被作設置，但是，係並不被限定於此，係亦可僅被設置在連接環14之一部分處。 In addition, in this embodiment, although the recesses 14c are respectively formed at positions corresponding to the front end of the long outer circumference lead portion 12A, the system is not limited to this, and may be formed on the short outer circumference. At a position corresponding to the front end of the wire portion 12B. In addition, although the plurality of recesses 14c are provided over the entire area of the connecting ring 14 in the circumferential direction, the system is not limited to this, and the system may be provided only at a part of the connecting ring 14.

圖11中所示之半導體裝置20A，係為由圖8~圖10中所示之導線框架10A所製作者。在此半導體裝置20A中，第2端子部28，係沿著晶粒墊11之周圍4邊(於圖11中，係為與X方向或Y方向相平行之4邊)的全部，而相互空出有間隔地來作配列。 The semiconductor device 20A shown in FIG. 11 is manufactured by the lead frame 10A shown in FIGS. 8-10. In this semiconductor device 20A, the second terminal portion 28 is along all of the four sides around the die pad 11 (in FIG. 11, the four sides parallel to the X direction or the Y direction), and are mutually empty. Arrange at intervals.

如同上述一般，導線框架10A的連接環14中之各凹部14c的周邊區域，係在藉由密封樹脂23而被作了樹脂密封之後，從背面側起來藉由蝕刻而除去。因此，如同圖11中所示一般，各第2端子部28，係從晶粒墊11、外周導線部12A、12B以及其他之第2端子部28而分離，並與此些之構件相互電性獨立。又，第2端子部28，係並不被作半蝕刻地而具備有與晶粒墊11相同之厚度。進而，在第2端子部28的背面，係形成有被與外部 之安裝基板(未圖示)作電性連接之外部端子17C。 As described above, the peripheral area of each recess 14c in the connecting ring 14 of the lead frame 10A is resin-sealed with the sealing resin 23, and then removed from the back side by etching. Therefore, as shown in FIG. 11, each second terminal portion 28 is separated from the die pad 11, the outer peripheral lead portions 12A, 12B, and other second terminal portions 28, and is electrically connected to these components. independent. In addition, the second terminal portion 28 is not half-etched but has the same thickness as the die pad 11. Furthermore, on the back surface of the second terminal portion 28, there are formed The mounting board (not shown) is used as an external terminal 17C for electrical connection.

又，伴隨著連接環14中之除了第2端子部28以外的部份被除去一事，在密封樹脂23之背面中的外周導線部12A、12B和晶粒墊11之間之區域處，係以包圍晶粒墊11的方式而被形成有凹部27。 In addition, along with the removal of the connecting ring 14 except for the second terminal portion 28, the area between the outer peripheral lead portions 12A, 12B and the die pad 11 on the back surface of the sealing resin 23 is marked with A recess 27 is formed to surround the die pad 11.

若依據本實施形態，則在製作半導體裝置20A時，連接環14之一部分係被除去，連接環14中之並未被除去的部份係被相互個別地分離並成為第2端子部28。如此這般，藉由形成多數之第2端子部28，係能夠將與外部之安裝基板作連接的端子部之數量(銷數)增加，而能夠實現半導體裝置20之更進一步的高密度化。 According to this embodiment, when manufacturing the semiconductor device 20A, a part of the connecting ring 14 is removed, and the unremoved part of the connecting ring 14 is separated from each other individually and becomes the second terminal portion 28. In this way, by forming a large number of second terminal portions 28, the number of terminal portions (the number of pins) connected to the external mounting substrate can be increased, and the semiconductor device 20 can be further increased in density.

在本實施形態中，係亦可藉由將一部分之第2端子部28形成為較其他之第2端子部28更大，並在此第2端子部28處連接複數之接合打線22，而作為用以進行電性訊號之調節的匯流排或接地(GND)端子來使用。藉由此，係能夠降低伴隨著端子數之增加所導致的發熱，而能夠作成信賴性更高之半導體裝置20A。 In this embodiment, it is also possible to form a part of the second terminal portion 28 to be larger than the other second terminal portions 28, and to connect a plurality of bonding wires 22 to the second terminal portion 28, as It is used for the bus bar or the ground (GND) terminal for adjusting the electrical signal. With this, it is possible to reduce heat generation due to an increase in the number of terminals, and it is possible to produce a more reliable semiconductor device 20A.

另外，由本實施形態所致之導線框架10A之製造方法以及半導體裝置20A之製造方法，係與由第1實施形態所致之導線框架10之製造方法(圖6(a)~(f))以及半導體裝置20之製造方法(圖7(a)~(f)))略相同。 In addition, the manufacturing method of the lead frame 10A and the manufacturing method of the semiconductor device 20A according to the present embodiment are the same as the manufacturing method of the lead frame 10 according to the first embodiment (FIGS. 6(a)~(f)) and The manufacturing method of the semiconductor device 20 (FIG. 7(a)~(f))) is slightly the same.

(第3實施形態) (Third Embodiment)

接著，參考圖12~圖17，對本發明之第3實施形態作說明。圖12乃至圖17，係為對於本發明之第3實施形態作展示者。圖12乃至圖17中所示之第3實施形態，其主要相異之處係在於內側導線部26A~26D之配置，以及連接導線57為從表面側起來作了薄化之點，其他構成則係與上述之第1實施形態略相同。在圖12乃至圖17中，針對與第1實施形態相同的部份，係附加相同之元件符號，並省略詳細說明。 Next, referring to Figs. 12 to 17, the third embodiment of the present invention will be described. Fig. 12 and Fig. 17 show the third embodiment of the present invention. The third embodiment shown in Fig. 12 and Fig. 17 differs mainly in the arrangement of the inner lead portions 26A to 26D and the point where the connecting lead 57 is thinned from the surface side. Other configurations are It is slightly the same as the above-mentioned first embodiment. In FIG. 12 and FIG. 17, the same reference numerals are assigned to the same parts as in the first embodiment, and detailed descriptions are omitted.

在圖12~圖14所示之導線框架10B以及圖15和圖16所示之半導體裝置20B中，複數之內側導線部26A~26D中的從連接環14之內側所延伸的長內側導線部26C、和從連接環14之外側所延伸之短內側導線部26B，係隔著連接環14而被配置在互為相反側之位置。亦即是，長內側導線部26C和相對應之短內側導線部26B，係包夾著連接環14而位置在一直線上。 In the lead frame 10B shown in FIGS. 12 to 14 and the semiconductor device 20B shown in FIGS. 15 and 16, the long inner wire portion 26C extending from the inner side of the connecting ring 14 among the plurality of inner wire portions 26A to 26D , And the short inner lead portion 26B extending from the outer side of the connecting ring 14 are arranged on opposite sides of the connecting ring 14 therebetween. That is, the long inner wire portion 26C and the corresponding short inner wire portion 26B are positioned on a straight line with the connecting ring 14 sandwiched therebetween.

又，從連接環14之內側所延伸的短內側導線部26D、和從連接環14之外側所延伸之長內側導線部26A，係隔著連接環14而被配置在互為相反側之位置。亦即是，短內側導線部26D和相對應之長內側導線部26A，係包夾著連接環14而位置在一直線上。藉由此，係能夠確保外部端子17D和外部端子17F之間的端子間距離，而能夠對於此些之端子彼此相互接觸的問題作防止。 In addition, the short inner wire portion 26D extending from the inner side of the connecting ring 14 and the long inner wire portion 26A extending from the outer side of the connecting ring 14 are arranged on opposite sides of the connecting ring 14. That is, the short inner wire portion 26D and the corresponding long inner wire portion 26A are positioned on a straight line with the connecting ring 14 sandwiched therebetween. By this, the distance between the external terminals 17D and the external terminals 17F can be ensured, and the problem of contact between these terminals can be prevented.

進而，從連接環14之外側而延伸之短內側導線部26B、和長外周導線部12A，係相互對向，從連接環 14之外側而延伸之長內側導線部26A、和短外周導線部12B，係相互對向。 Furthermore, the short inner wire portion 26B extending from the outer side of the connecting ring 14 and the long outer circumferential wire portion 12A are opposed to each other, from the connecting ring The long inner wire portion 26A and the short outer circumferential wire portion 12B extending from the outer side of 14 are opposed to each other.

又，在本實施形態中，內側導線部26A~26D之各連接導線57，係從表面側起來作了薄化。於此情況，由於連接導線57係於背面側而露出，因此係能夠容易地進行將連接環14和連接導線57除去的作業。又，在將連接環14藉由蝕刻而作除去時(參考圖7(e))，係能夠從背面側來容易地對於連接環14以及連接導線57是否有被確實地除去一事作確認。藉由此，使外部端子17C~17F相互獨立的作業係變得容易。另外，在第1實施形態中，亦同樣的，係能夠使各連接導線57從表面側起來作薄化。 Furthermore, in this embodiment, the connecting wires 57 of the inner wire portions 26A to 26D are thinned from the surface side. In this case, since the connecting lead 57 is exposed on the back side, the work of removing the connecting ring 14 and the connecting lead 57 can be easily performed. Moreover, when the connection ring 14 is removed by etching (refer to FIG. 7(e)), it is possible to easily confirm whether the connection ring 14 and the connection lead 57 are reliably removed from the back side. By this, the operation system of making the external terminals 17C-17F mutually independent becomes easy. In addition, in the first embodiment, in the same way, each connection lead 57 can be made thinner from the surface side.

在圖15以及圖16所示之半導體裝置20B中，雖然連接導線57係與連接環14一同地而被除去，但是，係並不被限定於此，亦可在半導體裝置20B處而使連接導線57之一部分殘留，或者是亦可使連接導線57之全體殘留。 In the semiconductor device 20B shown in FIGS. 15 and 16, although the connecting wire 57 is removed together with the connecting ring 14, it is not limited to this, and the connecting wire may be used at the semiconductor device 20B. A part of 57 remains, or the entire connecting wire 57 may remain.

圖17，係對於由本實施形態之變形例所致之導線框架10C作展示。在圖17中，從連接環14之內側係僅延伸有短內側導線部26D，長內側導線部26C則並未作延伸。故而，外部端子17A~17D、17F，係在晶粒墊11之周圍而被配置為5列。於此情況，係能夠相對於半導體裝置20B之大小而確保有廣大的晶粒墊11之面積。另外，在第1實施形態中，亦同樣的，係可並不在連接環 14之內側設置長內側導線部26C。 Fig. 17 shows a lead frame 10C resulting from a modification of this embodiment. In FIG. 17, only the short inner wire portion 26D extends from the inner side of the connecting ring 14, and the long inner wire portion 26C does not extend. Therefore, the external terminals 17A to 17D, 17F are arranged in five rows around the die pad 11. In this case, it is possible to ensure a large area of the die pad 11 relative to the size of the semiconductor device 20B. In addition, in the first embodiment, the same is true, the system may not be connected to the ring A long inner wire part 26C is provided inside 14.

另外，由本實施形態所致之導線框架10B、10C之製造方法以及半導體裝置20B之製造方法，係與由第1實施形態所致之導線框架10之製造方法(圖6(a)~(f))以及半導體裝置20之製造方法(圖7(a)~(f)))略相同。 In addition, the manufacturing method of the lead frames 10B, 10C and the manufacturing method of the semiconductor device 20B according to the present embodiment are the same as the manufacturing method of the lead frame 10 according to the first embodiment (FIG. 6(a)~(f)) ) And the manufacturing method of the semiconductor device 20 (FIG. 7(a)~(f))) are slightly the same.

在本實施形態中，在圖12(外部端子17A~17F為6列)中所示之導線框架10B以及在圖17(外部端子17A~17D、17F為5列)中所示之導線框架10C的情況時，均同樣的，係能夠將所有的外部端子17A~17F，配置為外部端子17A~17F彼此之間隔為相等之交錯狀。藉由此，係能夠對於在基板安裝時之焊錫架橋的發生作抑制，而成為能夠使安裝信賴性提昇。 In this embodiment, the lead frame 10B shown in FIG. 12 (external terminals 17A-17F are 6 columns) and the lead frame 10C shown in FIG. 17 (external terminals 17A-17D, 17F are 5 columns) In the case, it is the same, and it is possible to arrange all the external terminals 17A to 17F in a staggered pattern with equal intervals between the external terminals 17A to 17F. By this, it is possible to suppress the occurrence of solder bridging during board mounting, and it is possible to improve mounting reliability.

若依據本實施形態，則例如當12mm□之封裝的情況時，若是使用圖12中所示之導線框架10B(外部端子17A~17F為6列)，則係能夠將端子部之數量(銷數)增加至308銷。又，例如當12mm□之封裝的情況時，若是使用圖17中所示之導線框架10B(外部端子17A~17D、17F為5列)，則係能夠將端子部之數量(銷數)增加至280銷。如此這般，若依據本實施形態，則係成為能夠低價地製造可搭載高功能之LSI的半導體裝置。進而，例如當10mm□之封裝的情況時，若是使用圖17中所示之導線框架10B(外部端子17A~17D、17F為5列)，則係能夠將端子部之數量(銷數)增加至208銷~ 216銷。此一銷數(208銷~216銷)，係相當於與先前技術之28mm□之QFP(Quad Flat Package)同等之銷數。 According to this embodiment, for example, in the case of a 12mm□ package, if the lead frame 10B shown in Fig. 12 is used (external terminals 17A-17F are 6 rows), the number of terminal parts (pin number ) Increase to 308 pins. Also, for example, in the case of a 12mm□ package, if the lead frame 10B shown in Fig. 17 is used (external terminals 17A-17D, 17F are 5 rows), the number of terminal parts (number of pins) can be increased to 280 pins. In this way, according to this embodiment, a semiconductor device capable of mounting a high-function LSI can be manufactured at low cost. Furthermore, for example, in the case of a 10mm□ package, if the lead frame 10B shown in FIG. 17 is used (the external terminals 17A to 17D and 17F are in 5 rows), the number of terminal parts (the number of pins) can be increased to Pin 208~ 216 pins. This number of pins (208 pins to 216 pins) is equivalent to the same number of pins as the 28mm□ QFP (Quad Flat Package) of the prior art.

(第4實施形態) (Fourth Embodiment)

接著，參考圖18~圖21，對本發明之第4實施形態作說明。圖18乃至圖21，係為對於本發明之第4實施形態作展示者。圖18~圖21中所示之第4實施形態，其主要相異之處係在於代替連接環14而設置有導線連接部(連接條)64之點，其他構成則係與上述之第1實施形態略相同。在圖18~圖21中，針對與第1實施形態相同的部份，係附加相同之元件符號，並省略詳細說明。 Next, referring to FIGS. 18 to 21, the fourth embodiment of the present invention will be described. Figures 18 to 21 show the fourth embodiment of the present invention. The fourth embodiment shown in FIGS. 18 to 21 is mainly different in that a wire connection portion (connection bar) 64 is provided in place of the connection ring 14, and the other configuration is the same as the above-mentioned first embodiment The shape is slightly the same. In FIGS. 18 to 21, the same reference numerals are assigned to the same parts as in the first embodiment, and detailed descriptions are omitted.

在圖18以及圖19所示之導線框架10D中，在晶粒墊11和外周導線部12A、12B之間，係被配置有導線連接部64。藉由此導線連接部64，分別具備有第2端子部18之複數之內側導線部26A~26D係被作支持。導線連接部64，係並不被作半蝕刻地而具備有與晶粒墊11相同之厚度。然而，係並不被限定於此，亦可從導線連接部64之表面側來藉由半蝕刻而作薄化。又，導線連接部64，係以直線狀而延伸，其之兩端係分別被與懸吊導線16作連結。懸吊導線16，係從背面側起來藉由半蝕刻而作薄化。另外，導線連接部64，係並非絕對需要被與懸吊導線16作連結，而例如亦可被與晶粒墊11作連結。 In the lead frame 10D shown in FIG. 18 and FIG. 19, a wire connection portion 64 is arranged between the die pad 11 and the outer peripheral wire portions 12A and 12B. With this lead connection part 64, the plural inner lead parts 26A to 26D respectively provided with the second terminal part 18 are supported. The wire connection portion 64 is not half-etched but has the same thickness as the die pad 11. However, the system is not limited to this, and it may be thinned by half etching from the surface side of the wire connection portion 64. In addition, the wire connecting portion 64 extends linearly, and both ends of the wire connecting portion 64 are connected to the suspension wires 16 respectively. The suspension wire 16 is thinned by half etching from the back side. In addition, the wire connection portion 64 does not absolutely need to be connected to the suspension wire 16, but may also be connected to the die pad 11, for example.

於此情況，晶粒墊11係為平面略長方形狀，其之長邊係與X方向相平行，其之短邊係與Y方向相平行。在本實施形態中，導線連接部64，係在1個的單位導線框架10a處設置有2根，並分別與晶粒墊11之長邊相平行地而延伸。然而，係並不被限定於此，導線連接部64，係亦可在1個的單位導線框架10a處設置有1根或者是3根以上。又，導線連接部64之形狀，係並不被限定於直線狀，而亦可設為略圓弧等之曲線狀、略V字形狀、略L字形狀、略U字形狀等。 In this case, the die pad 11 has a flat rectangular shape, and its long side is parallel to the X direction, and its short side is parallel to the Y direction. In the present embodiment, two wire connection portions 64 are provided in one unit wire frame 10a, and each extends parallel to the long side of the die pad 11. However, the system is not limited to this, and the lead connection portion 64 may be provided with one or more than three in one unit lead frame 10a. In addition, the shape of the lead wire connecting portion 64 is not limited to a linear shape, and may be a curved shape such as a substantially circular arc, a substantially V-shape, a substantially L-shape, and a substantially U-shape.

又，在本實施形態中，相連續之一部分(例如4個)的外部端子17A，係藉由連結部65而被作連結，相連續之一部分(例如3個)的外部端子17E，係藉由連結部66而被作連結。連結部65、66，係亦可分別例如作為匯流排或接地(GND)端子來作使用。 In addition, in this embodiment, a continuous part (for example, four) of the external terminals 17A are connected by the connecting portion 65, and a continuous part (for example, three) of the external terminals 17E are connected by The connecting portion 66 is connected. The connecting portions 65 and 66 can also be used as bus bars or ground (GND) terminals, respectively.

圖20中所示之半導體裝置20D，係為由圖18以及圖19中所示之導線框架10D所製作者。在此半導體裝置20D處，導線連接部64係被除去，伴隨於此，在密封樹脂23之背面中的外周導線部12A、12B和晶粒墊11之間之內側導線部26A、26B與內側導線部26C、26D之間的區域處，係被形成有凹部67。此凹部67，係在1個的半導體裝置20D中而設置有2根，並分別概略對應於導線連接部64之形狀而相對於晶粒墊11之長邊來相平行地延伸為一直線狀。 The semiconductor device 20D shown in FIG. 20 is manufactured by the lead frame 10D shown in FIGS. 18 and 19. In this semiconductor device 20D, the wire connection portion 64 is removed. Accompanying this, the inner wire portions 26A, 26B between the outer peripheral wire portions 12A, 12B and the die pad 11 on the back of the sealing resin 23 and the inner wire A recessed portion 67 is formed in the area between the portions 26C and 26D. Two of the recesses 67 are provided in one semiconductor device 20D, and each roughly corresponds to the shape of the wire connection portion 64 and extends in a straight line parallel to the long side of the die pad 11.

若依據本實施形態，則由於導線連接部64係 僅沿著晶粒墊11之2邊而延伸，因此，藉由在並未被設置有導線連接部64之方向上而使晶粒墊11延伸，係能夠將晶粒墊11之面積增廣。藉由此，係成為易於在晶粒墊11上搭載大型之半導體元件21或複數之半導體元件21。 According to this embodiment, since the wire connecting portion 64 is It extends only along the two sides of the die pad 11, and therefore, by extending the die pad 11 in the direction where the wire connection portion 64 is not provided, the area of the die pad 11 can be enlarged. By this, it becomes easy to mount a large-sized semiconductor element 21 or a plurality of semiconductor elements 21 on the die pad 11.

圖21，係對於由本實施形態之變形例所致之導線框架10E作展示。在圖21中，從各導線連接部64內側係僅延伸有短內側導線部26D，長內側導線部26C則並未作延伸。於此情況，係能夠將晶粒墊11之面積擴廣至各導線連接部64側。 Fig. 21 shows a lead frame 10E resulting from a modification of this embodiment. In FIG. 21, only the short inner wire portion 26D extends from the inner side of each wire connecting portion 64, and the long inner wire portion 26C does not extend. In this case, the area of the die pad 11 can be expanded to the side of each wire connection portion 64.

另外，由本實施形態所致之導線框架10D、10E之製造方法以及半導體裝置20D之製造方法，係與由第1實施形態所致之導線框架10之製造方法(圖6(a)~(f))以及半導體裝置20之製造方法(圖7(a)~(f)))略相同。 In addition, the manufacturing method of the lead frames 10D and 10E and the manufacturing method of the semiconductor device 20D according to the present embodiment are the same as the manufacturing method of the lead frame 10 according to the first embodiment (FIG. 6(a)~(f)) ) And the manufacturing method of the semiconductor device 20 (FIG. 7(a)~(f))) are slightly the same.

(第5實施形態) (Fifth Embodiment)

接著，參考圖22~圖30，對本發明之第5實施形態作說明。圖22~圖30，係為對於本發明之第5實施形態作展示者。在圖22~圖30中，針對相同的部份，係附加相同之元件符號，並會有省略一部分之詳細說明的情形。 Next, referring to FIGS. 22 to 30, the fifth embodiment of the present invention will be described. Figures 22 to 30 show the fifth embodiment of the present invention. In FIGS. 22 to 30, for the same parts, the same component symbols are added, and some detailed descriptions may be omitted.

導線框架之構成 The composition of the lead frame

首先，根據圖22~圖26，對由本實施形態所致之導線框架的概略內容作說明。圖22~圖26，係為對於由本 實施形態所致之導線框架作展示之圖。 First, based on FIGS. 22 to 26, the outline of the lead frame by this embodiment will be described. Figure 22~Figure 26 are The lead frame caused by the implementation is shown as a diagram.

如圖22以及圖23中所示一般，導線框架10F，係包含有複數之單位導線框架10a。各單位導線框架10a，係具備有：平面矩形狀之晶粒墊11，係搭載有半導體元件21(於後再述)；和複數之細長的導線部12A、12B，係被設置於晶粒墊11之周圍，並分別與半導體元件21以及外部電路(未圖示)作連接。另外，單位導線框架10a，係為分別與半導體裝置20F(於後再述)相對應之區域，而為在圖22中位置在假想線之內側處的區域。 As shown in FIGS. 22 and 23, generally, the lead frame 10F includes a plurality of unit lead frames 10a. Each unit lead frame 10a is provided with: a flat rectangular die pad 11 on which a semiconductor element 21 (described later) is mounted; and a plurality of elongated lead portions 12A and 12B are provided on the die pad Around 11, they are connected to the semiconductor element 21 and external circuits (not shown). In addition, the unit lead frames 10a are regions respectively corresponding to the semiconductor devices 20F (described later), and are regions located inside the imaginary line in FIG. 22.

複數之單位導線框架10a，係經由支持導線(支持構件)13而被相互作連結。此支持導線13，係為支持晶粒墊11和導線部12A、12B者，並分別沿著X方向以及垂直於X方向之Y方向而延伸。又，在晶粒墊11之四角隅處，係被連接有懸吊導線16，晶粒墊11，係經由此4根的懸吊導線16而被連結支持於支持導線13處。 The plural unit lead frames 10a are connected to each other via supporting wires (supporting members) 13. The supporting wire 13 is for supporting the die pad 11 and the wire portions 12A, 12B, and respectively extends along the X direction and the Y direction perpendicular to the X direction. In addition, at the four corners of the die pad 11, suspension wires 16 are connected, and the die pad 11 is connected and supported to the supporting wires 13 via the four suspension wires 16.

相鄰接之導線部12A、12B彼此，係在半導體裝置20F(於後再述)之製造後，成為被相互電性絕緣之形狀。又，各導線部12A、12B，在半導體裝置20F之製造後，係成為被與晶粒墊11電性絕緣之形狀。在此導線部12A、12B之背面，係分別形成有被與外部之安裝基板(未圖示)作電性連接之外部端子17A、17B。各外部端子17A、17B，係在半導體裝置20F(於後再述)之製造後，分別成為從半導體裝置20F而露出於外部。 The adjacent lead portions 12A and 12B are formed into a shape electrically insulated from each other after the semiconductor device 20F (described later) is manufactured. In addition, the respective lead portions 12A and 12B have a shape that is electrically insulated from the die pad 11 after the semiconductor device 20F is manufactured. On the back surfaces of the lead portions 12A and 12B, external terminals 17A and 17B are respectively formed to be electrically connected to an external mounting substrate (not shown). The external terminals 17A and 17B are respectively exposed to the outside from the semiconductor device 20F after the semiconductor device 20F (described later) is manufactured.

於此情況，複數之導線部12A、12B之外部端 子17A、17B，係以在相鄰接之導線部12A、12B之間而位置於內側以及外側的方式，來在作平面性觀察時被交互地配置為交錯狀。亦即是，在晶粒墊11之周圍，具有相對性地位置於內側(晶粒墊11側)之外部端子17A的導線部12A，和具有相對性地位置於外側(支持導線13側)之外部端子17B的導線部12B，係遍佈全周地而被交互作配置。藉由此，係能夠對於導線部12A、12B之外部端子17A、17B和相鄰接之導線部12B、12A相互接觸的問題作防止。另外，在本實施形態中，係將位置在內側之外部端子17A亦稱作內側外部端子17A，並將位置在外側之外部端子17B亦稱作外側外部端子17B。於此情況，內側外部端子17A以及外側外部端子17B，係全部具備有相同之平面形狀。 In this case, the outer ends of the plural lead parts 12A and 12B The subs 17A and 17B are alternately arranged in a staggered shape during planar observation so that they are positioned on the inside and outside between the adjacent lead portions 12A and 12B. That is, around the die pad 11, the lead portion 12A of the external terminal 17A that has a relative position on the inner side (the die pad 11 side), and the lead portion 12A that has a relative position on the outer side (the support wire 13 side) The lead portions 12B of the external terminal 17B are alternately arranged all over the circumference. By this, it is possible to prevent the problem that the external terminals 17A, 17B of the lead portions 12A, 12B and the adjacent lead portions 12B, 12A contact each other. In addition, in this embodiment, the external terminal 17A positioned on the inside is also referred to as the internal external terminal 17A, and the external terminal 17B positioned on the outside is also referred to as the external external terminal 17B. In this case, the inner external terminal 17A and the outer external terminal 17B all have the same planar shape.

如圖22中所示一般，複數之內側外部端子17A，係當作平面性觀察時，均為沿著與晶粒墊11之一邊相平行的直線而被配列。又，複數之外側外部端子17B，係當作平面性觀察時，均為沿著與晶粒墊11之一邊相平行的直線而被配列。亦即是，複數之內側外部端子17A以及複數之外側外部端子17B，係沿著與X方向或者是Y方向之其中一者相平行的直線而被配列成2列。然而，係並不被限定於此，例如，複數之內側外部端子17A以及/或者是複數之外側外部端子17B，係亦可當作平面性觀察時而分別被配列在圓弧上。 As shown in FIG. 22, generally, the plural inner and outer terminals 17A are arranged along a straight line parallel to one side of the die pad 11 when viewed as a planar view. In addition, the plurality of outer external terminals 17B are all arranged along a straight line parallel to one side of the die pad 11 when viewed as a planar view. That is, the plural inner external terminals 17A and the plural outer outer terminals 17B are arranged in two rows along a straight line parallel to either the X direction or the Y direction. However, the system is not limited to this. For example, the plurality of inner external terminals 17A and/or the plurality of outer external terminals 17B may be arranged on an arc as a planar view.

接著，參考圖24以及圖25(a)~(b)，針 對各導線部12A、12B之構成更進一步作說明。 Next, referring to Figure 24 and Figure 25 (a) ~ (b), the needle The structure of each lead part 12A, 12B is further demonstrated.

如圖24中所示一般，導線部12A、12B中之具有內側外部端子17A的導線部12A，係具備有內導線51、和連接導線52、以及端子部(第1端子部)53。其中，內導線51，係較端子部53而更朝向內側(晶粒墊11側)延伸，在其之內側端部表面上，係被形成有內部端子15。此內部端子15，係如同後述一般，成為經由接合打線22而被與半導體元件21作電性連接之區域。因此，在內部端子15上，係設置有用以提昇其與接合打線22之間的密著性之電鍍部25。於此情況，內導線51，係相對於支持導線13而傾斜地延伸。 As shown in FIG. 24, generally, the lead part 12A having the inner external terminal 17A among the lead parts 12A and 12B includes an inner lead 51, a connecting lead 52, and a terminal part (first terminal part) 53. Among them, the inner lead 51 extends toward the inner side (die pad 11 side) than the terminal portion 53, and the inner terminal 15 is formed on the inner end surface thereof. This internal terminal 15 is a region which is electrically connected to the semiconductor element 21 via the bonding wire 22 as described later. Therefore, the internal terminal 15 is provided with a plating part 25 to improve the adhesion between the internal terminal 15 and the bonding wire 22. In this case, the inner wire 51 extends obliquely with respect to the supporting wire 13.

連接導線52，係位置在較端子部53而更外側(支持導線13側)處，其之外端部係被連結於支持導線13處。連接導線52，係相對於該連接導線52所被作連結之支持導線13而垂直地延伸。進而，在端子部53的背面，係形成有內側外部端子17A。 The connecting wire 52 is located outside the terminal portion 53 (on the side of the supporting wire 13), and its outer end is connected to the supporting wire 13. The connecting wire 52 extends vertically relative to the supporting wire 13 to which the connecting wire 52 is connected. Furthermore, an inner external terminal 17A is formed on the back surface of the terminal part 53.

如圖25(a)中所示一般，導線部12A之內導線51以及連接導線52，係分別從背面側(與搭載半導體元件21之面相反側)而藉由半蝕刻來形成為厚度較薄。另一方面，端子部53，係並不被作半蝕刻地而具備有與晶粒墊11以及支持導線13相同之厚度。如此這般，藉由使內導線51以及連接導線52之厚度成為較端子部53之厚度更薄，係能夠以良好精確度來形成寬幅為窄之導線部12A，而能夠得到小型且銷數為多之半導體裝置 20F。另外，所謂半蝕刻，係指對於被蝕刻材料而一直蝕刻至直到其之厚度方向的途中為止。 As shown in FIG. 25(a), generally, the inner wire 51 and the connecting wire 52 of the wire portion 12A are formed to be thinner by half-etching from the back side (the side opposite to the surface where the semiconductor element 21 is mounted). . On the other hand, the terminal portion 53 is not half-etched but has the same thickness as the die pad 11 and the support wire 13. In this way, by making the thickness of the inner lead 51 and the connecting lead 52 thinner than the thickness of the terminal part 53, the lead part 12A with a narrow width and a width can be formed with good accuracy, and a small size and pin count can be obtained. For many semiconductor devices 20F. In addition, the term "half etching" means that the material to be etched is etched until it is halfway in the thickness direction.

另一方面，如圖24中所示一般，導線部12A、12B中之具有外側外部端子17B的導線部12B，係具備有內導線61、和連接導線62、以及端子部63。其中，內導線61，係位置在較端子部63而內側(晶粒墊11側)，在其之內側端部表面上，係被形成有內部端子15。於此情況，內導線61，係具備有相對於支持導線13而垂直地延伸之直線部分61b、和從該直線部分61b起而傾斜地延伸之傾斜部分61a。 On the other hand, generally as shown in FIG. 24, the lead part 12B having the outer external terminal 17B among the lead parts 12A and 12B is provided with an inner lead 61, a connecting lead 62, and a terminal 63. Among them, the inner lead 61 is positioned inside the terminal portion 63 (on the side of the die pad 11), and the inner terminal 15 is formed on the inner end surface thereof. In this case, the inner wire 61 is provided with a straight portion 61b extending perpendicularly to the supporting wire 13, and an inclined portion 61a extending obliquely from the straight portion 61b.

又，連接導線62，係位置在較端子部63而更外側(支持導線13側)處，其之外端部係被連結於支持導線13處。連接導線62，係相對於該連接導線62所被作連結之支持導線13而垂直地延伸。進而，在端子部63的背面，係形成有外側外部端子17B。 In addition, the connecting lead 62 is located outside the terminal portion 63 (on the side of the support lead 13), and its outer end is connected to the support lead 13. The connecting wire 62 extends vertically relative to the supporting wire 13 to which the connecting wire 62 is connected. Furthermore, on the back surface of the terminal portion 63, an outer external terminal 17B is formed.

如圖25(b)中所示一般，導線部12B之內導線61以及連接導線62，係分別從背面側(與搭載半導體元件21之面相反側)而藉由半蝕刻來形成為厚度較薄。又，端子部63，係並不被作半蝕刻地而具備有與晶粒墊11以及支持導線13相同之厚度。如此這般，藉由使內導線61以及連接導線62之厚度成為較端子部63之厚度更薄，係能夠以良好精確度來形成寬幅為窄之導線部12B，而能夠得到小型且銷數為多之半導體裝置20F。 As shown in FIG. 25(b), generally, the inner wire 61 and the connecting wire 62 of the wire portion 12B are formed to be thinner by half etching from the back side (the side opposite to the surface where the semiconductor element 21 is mounted). . In addition, the terminal portion 63 has the same thickness as the die pad 11 and the support wire 13 without being half-etched. In this way, by making the thickness of the inner lead 61 and the connecting lead 62 thinner than the thickness of the terminal part 63, the lead part 12B with a narrow width and a width can be formed with good accuracy, and a small size and pin count can be obtained. It is the most semiconductor device 20F.

接著，參考圖26(a)~(c)，針對各導線 部12A、12B之剖面形狀(沿著與支持各導線部12A、12B之支持導線13相平行的方向之剖面形狀)更進一步作說明。 Next, referring to Figure 26 (a) ~ (c), for each wire The cross-sectional shape of the portions 12A, 12B (the cross-sectional shape along the direction parallel to the support wire 13 supporting the respective wire portions 12A, 12B) is further explained.

如圖26(a)~(c)中所示一般，導線部12A之內導線51以及連接導線52，係藉由從背面側來施加半蝕刻，而分別具備有略四角形狀、略梯形狀或者是略半圓弧狀之剖面。又，關於導線部12B之內導線61以及連接導線62，亦同樣的，係藉由從背面側來施加半蝕刻，而分別具備有略四角形狀、略梯形狀或者是略半圓弧狀之剖面。 As shown in Fig. 26(a)~(c), generally, the wires 51 and the connecting wires 52 in the wire portion 12A are half-etched from the back side, and they have a slightly rectangular shape, a slightly trapezoidal shape, or It is a cross-section of a slightly semicircular arc. In the same way, the wires 61 and the connecting wires 62 in the wire portion 12B are half-etched from the back side, and each have a quadrangular, trapezoidal, or semicircular cross-section. .

又，如圖26(a)中所示一般，導線部12A之端子部53，係具備有使其之兩側面朝向內側而作了彎曲的形狀。於此情況，內側外部端子17A(端子部53之背面)之寬幅wA2，係成為較端子部53之表面之寬幅wA1而更廣。藉由此，就算是在將相互鄰接之導線部12A和導線部12B之間的間隔作了縮窄的情況時，亦能夠將內側外部端子17A之面積確保為廣，而能夠將內側外部端子17A和外部之安裝基板(未圖示)確實地作連接。另外，如圖26(c)中所示一般，關於導線部12B之端子部63，亦同樣的，係具備有使其之兩側面朝向內側而作了彎曲的形狀，並且外側外部端子17B(端子部63之背面)之寬幅wB2，係成為較端子部63之表面之寬幅wB1而更廣。 In addition, as shown in FIG. 26(a), generally, the terminal portion 53 of the lead portion 12A has a shape in which both side surfaces are turned toward the inside and bent. In this case, the width w A2 of the inner external terminal 17A (the back surface of the terminal portion 53) becomes wider than the width w A1 of the surface of the terminal portion 53. As a result, even when the distance between the lead portion 12A and the lead portion 12B adjacent to each other is narrowed, the area of the inner external terminal 17A can be ensured to be wide, and the inner external terminal 17A can be secured. Make sure to connect with the external mounting board (not shown). In addition, as shown in FIG. 26(c), generally, the terminal portion 63 of the lead portion 12B is similarly provided with a shape in which both side faces are directed inwardly and bent, and the outer external terminal 17B (terminal The width w B2 of the back surface of the part 63 is wider than the width w B1 of the surface of the terminal part 63.

另外，如圖24中所示一般，導線部12A、12B之連接導線52、62中的支持導線13之近旁部分55， 其之寬幅wC係成為60μm~90μm或者是75μm~90μm。又，在圖25(a)~(b)中，該近旁部分55之厚度tC，係成為50μm~75μm或者是60μm~75μm。 In addition, generally, as shown in FIG. 24, the width w C of the vicinity of the supporting wire 13 of the connecting wires 52 and 62 of the wire portions 12A and 12B is 60 μm to 90 μm or 75 μm to 90 μm. In addition, in FIGS. 25(a) to (b), the thickness t C of the vicinity portion 55 is 50 μm to 75 μm or 60 μm to 75 μm.

如此這般，係藉由將近旁部分55之寬幅wC設為60μm或者是75μm以上，並將厚度tC設為50μm或者是60μm以上，來保持導線部12A、12B之相當於根部的部份(近旁部分55)之強度。因此，就算是在將導線部12A、12B之間的間隔作了縮窄的情況時，也能夠對於導線部12A、12B之強度降低的情形作抑制，而能夠防止在導線部12A、12B處產生變形的情況。又，藉由將上述近旁部分55之寬幅wC設為90μm以下，並將厚度tC設為75μm以下，係能夠將導線部12A、12B間之間隔縮窄，而能夠將各半導體裝置20F之外部端子17A、17B的數量(銷數)增加。 In this way, by setting the width w C of the vicinity portion 55 to 60 μm or more than 75 μm, and setting the thickness t C to 50 μm or more than 60 μm, the portion corresponding to the root of the lead portions 12A and 12B is maintained The strength of the part (near part 55). Therefore, even when the distance between the lead parts 12A and 12B is narrowed, the decrease in the strength of the lead parts 12A and 12B can be suppressed, and the occurrence of occurrence at the lead parts 12A and 12B can be prevented. Deformed situation. In addition, by setting the width w C of the vicinity portion 55 to be 90 μm or less and the thickness t C to be 75 μm or less, the interval between the lead portions 12A and 12B can be narrowed, and each semiconductor device 20F can be reduced The number of external terminals 17A, 17B (number of pins) increases.

又，在圖24中，導線部12A、12B之內導線51、61中的端子部53、63之近旁部分56，其之寬幅wd係成為60μm~90μm或者是75μm~90μm。進而，在圖25(a)~(b)中，該近旁部分56之厚度td，係成為50μm~75μm或者是60μm~75μm。 Furthermore, in FIG. 24, the width w d of the portion 56 near the terminal portions 53, 63 of the wires 51, 61 within the wire portions 12A, 12B is 60 μm to 90 μm or 75 μm to 90 μm. Furthermore, in FIGS. 25(a) to (b), the thickness t d of the vicinity portion 56 is 50 μm to 75 μm or 60 μm to 75 μm.

如此這般，係藉由將近旁部分56之寬幅wd設為60μm或者是75μm以上，並將厚度td設為50μm或者是60μm以上，來保持內導線51、61之相當於根部的部份(近旁部分56)之強度，而對於內導線51、61之強度降低的情況作抑制，並能夠防止在內導線51、61處產 生變形的情形。又，藉由將上述近旁部分56之寬幅wd設為90μm以下，並將厚度td設為75μm以下，由於係能夠將導線部12A、12B間之間隔縮窄，因此係能夠將各半導體裝置20F之外部端子17A、17B的數量(銷數)增加。 In this way, by setting the width w d of the nearby part 56 to 60 μm or more than 75 μm, and the thickness t d to 50 μm or more than 60 μm, the root-equivalent part of the inner leads 51 and 61 is maintained. The strength of the inner wires 51, 61 is reduced, and the inner wires 51, 61 can be prevented from being deformed. In addition, by setting the width w d of the vicinity portion 56 to 90 μm or less, and the thickness t d to 75 μm or less, since the interval between the lead portions 12A and 12B can be narrowed, each semiconductor The number of external terminals 17A, 17B (number of pins) of the device 20F is increased.

另外，在圖24中，相互鄰接之外周導線部12A、12B之間的間隔d，係以設為90μm~150μm為理想。如此這般，藉由將間隔d設為90μm以上，係能夠藉由蝕刻而確實地形成相互鄰接之導線部12A、12B之間的貫通部分。又，藉由將上述間隔d設為150μm以下，係能夠將各半導體裝置20F之外部端子17A、17B的數量(銷數)確保有一定數量以上。具體而言，外部端子17A、17B之數量(銷數)，例如係可設為80銷~250銷。 In addition, in FIG. 24, the interval d between the outer peripheral lead portions 12A and 12B adjacent to each other is preferably set to 90 μm to 150 μm. In this way, by setting the interval d to be 90 μm or more, it is possible to surely form the penetration portion between the lead portions 12A and 12B adjacent to each other by etching. In addition, by setting the interval d to 150 μm or less, the number of external terminals 17A and 17B (the number of pins) of each semiconductor device 20F can be secured to a certain number or more. Specifically, the number (number of pins) of the external terminals 17A and 17B can be set to 80 pins to 250 pins, for example.

以上所作了說明的導線框架10F，係由具備有750Mpa~1100Mpa或者是850Mpa~1100Mpa之拉張強度的金屬材料所構成，較理想，係由具備有920Mpa~1010Mpa之拉張強度的金屬材料所構成。藉由將導線框架10F藉由具有750MPa或者是850MPa以上之拉張強度的金屬材料來構成，由於係能夠對於導線部12A、12B之強度降低並產生變形的情形作抑制，因此係能夠將導線部12A、12B之間的間隔縮窄。又，一般而言，拉張強度為高之金屬材料，其導電性係會有降低的傾向。因此，藉由將導線框架10F藉由具有1100MPa以下之拉張強度的金屬材料來構成，係能夠對於導線部12A、12B之導電性降 低的情形作防止。 The lead frame 10F described above is composed of a metal material with a tensile strength of 750Mpa~1100Mpa or 850Mpa~1100Mpa. Ideally, it is composed of a metal material with a tensile strength of 920Mpa~1010Mpa . By forming the lead frame 10F with a metal material having a tensile strength of 750 MPa or more than 850 MPa, it is possible to suppress the reduction in the strength of the lead parts 12A and 12B and the occurrence of deformation. The gap between 12A and 12B is narrowed. Moreover, generally speaking, a metal material with a high tensile strength tends to decrease its conductivity. Therefore, by forming the lead frame 10F with a metal material having a tensile strength of 1100 MPa or less, the conductivity of the lead parts 12A and 12B can be reduced. Prevent low situations.

作為此種金屬材料，係可列舉出銅合金等，具體而言，例如係可列舉出卡遜系合金(Cu-Ni-Si)、鎳錫銅合金(Cu-Ni-Sn)、鈦銅合金(Cu-Ti)等。 Examples of such metal materials include copper alloys, and specific examples include Carson alloys (Cu-Ni-Si), nickel-tin-copper alloys (Cu-Ni-Sn), and titanium-copper alloys. (Cu-Ti) and so on.

又，導線框架10F之厚度，雖亦係依存於所製造之半導體裝置20F的構成，但是係可設為80μm~250μm。 In addition, the thickness of the lead frame 10F also depends on the structure of the semiconductor device 20F to be manufactured, but it can be set to 80 μm to 250 μm.

另外，在圖22中，導線部12A、12B，雖係沿著晶粒墊11之4邊的全部而被作配置，但是，係並不被限定於此，例如，係亦可僅沿著晶粒墊11之相對向的2邊來作配置。 In addition, in FIG. 22, although the lead portions 12A and 12B are arranged along all the four sides of the die pad 11, they are not limited to this. For example, they may be arranged only along the crystal The two opposite sides of the pad 11 are arranged.

半導體裝置之構成 Structure of semiconductor device

接著，根據圖27以及圖28，對由本實施形態所致之半導體裝置作說明。圖27以及圖28係為對於由本實施形態所致之半導體裝置(DR-QFN(Dual Row QFN)型態)作展示之圖。 Next, the semiconductor device according to this embodiment will be described based on FIGS. 27 and 28. 27 and 28 are diagrams showing the semiconductor device (DR-QFN (Dual Row QFN) type) caused by this embodiment.

如圖27以及圖28中所示一般，半導體裝置(半導體封裝)20F，係具備有：晶粒墊11、和被配置在晶粒墊11之周圍的複數之導線部12A、12B、和被搭載在晶粒墊11上之半導體元件21、以及將導線部12A、12B和半導體元件21作電性連接之複數之接合打線(連接構件)22。又，晶粒墊11、導線部12A、12B、半導體元件21以及接合打線22，係藉由密封樹脂23而被作樹脂密 封。 As shown in FIGS. 27 and 28, generally, a semiconductor device (semiconductor package) 20F includes a die pad 11, and a plurality of lead portions 12A, 12B arranged around the die pad 11, and mounted The semiconductor element 21 on the die pad 11 and a plurality of bonding wires (connection members) 22 that electrically connect the lead portions 12A, 12B and the semiconductor element 21. In addition, the die pad 11, the lead portions 12A, 12B, the semiconductor element 21, and the bonding wire 22 are sealed by the sealing resin 23. seal.

其中，晶粒墊11以及導線部12A、12B，係為從上述之導線框架10F所製作者。此晶粒墊11以及導線部12A、12B之構成，除了並不被包含於單位導線框架10a中的區域以外，係為與上述之圖22~圖26中所示者略相同，於此係省略詳細之說明。又，關於半導體元件21、接合打線22、密封樹脂23、接著劑24以及電鍍部25之構成，由於係與第1實施形態略相同，因此係省略詳細之說明。 Among them, the die pad 11 and the lead parts 12A, 12B are manufactured from the lead frame 10F described above. The structure of the die pad 11 and the lead portions 12A, 12B, except for the area not included in the unit lead frame 10a, is slightly the same as that shown in FIGS. 22 to 26, and is omitted here. Detailed description. In addition, since the configuration of the semiconductor element 21, the bonding wire 22, the sealing resin 23, the adhesive 24, and the plating portion 25 is a little the same as that of the first embodiment, a detailed description is omitted.

導線框架之製造方法 Manufacturing method of lead frame

接下來，針對圖22~圖26中所示之導線框架10F之製造方法，使用圖29(a)~(f)來作說明。另外，圖29(a)~(f)，係為對於導線框架10F之製造方法作展示的剖面圖(與圖23相對應之圖)。 Next, the manufacturing method of the lead frame 10F shown in FIGS. 22 to 26 will be described using FIGS. 29(a) to (f). In addition, FIGS. 29(a) to (f) are cross-sectional views showing the manufacturing method of the lead frame 10F (a diagram corresponding to FIG. 23).

首先，係如同圖29(a)中所示一般，準備平板狀之金屬基板31。作為此金屬基板31，係使用具有750MPa~1100MPa或者是850MPa~1100MPa之拉張強度者，例如，係可使用由卡遜系合金(Cu-Ni-Si)、鎳錫銅合金(Cu-Ni-Sn)、鈦銅合金(Cu-Ti)等之銅合金所成的基板。另外，金屬基板31，較理想，係使用對於其之兩面而進行脫脂等並施加了洗淨處理者。 First, as shown in FIG. 29(a), a flat metal substrate 31 is prepared. As the metal substrate 31, a tensile strength of 750 MPa to 1100 MPa or 850 MPa to 1100 MPa is used. For example, a Cu-Ni-Si alloy or nickel-tin-copper alloy (Cu-Ni- Sn), titanium copper alloy (Cu-Ti) and other copper alloy substrates. In addition, the metal substrate 31 is preferably one that has been degreasing or the like applied to both surfaces of the metal substrate 31 and subjected to cleaning treatment.

接著，在金屬基板31之表背面全體，分別塗布感光性光阻32a、33a，並使其乾燥(圖29(b))。另 外，作為感光性光阻32a、33a，係可使用先前技術所公知之物。 Next, photosensitive photoresists 32a and 33a are respectively coated on the entire front and back surfaces of the metal substrate 31 and dried (FIG. 29(b)). another In addition, as the photosensitive photoresist 32a, 33a, what is known in the prior art can be used.

接著，隔著光罩來對此金屬基板31進行曝光並進行顯像，藉由此，來形成具備有所期望之開口部32b、33b之蝕刻用光阻層32、33(圖29(c))。 Next, this metal substrate 31 is exposed and developed via a photomask, thereby forming etching resist layers 32, 33 having desired openings 32b, 33b (FIG. 29(c) ).

接著，將蝕刻用光阻層32、33作為耐腐蝕膜，而藉由腐蝕液來對於金屬基板31施加蝕刻(圖29(d))。藉由此，係形成晶粒墊11以及複數之導線部12A、12B的外形。腐蝕液，係可因應於所使用之金屬基板31的材質來適宜作選擇，例如，當作為金屬基板31而使用銅合金的情況時，通常，係可使用氯化鐵水溶液，並從金屬基板31之兩面起來藉由噴霧蝕刻而進行之。例如，與第1實施形態之情況相同的，係亦可對於金屬基板31而一次一面地來進行2個階段之噴霧蝕刻。 Next, the photoresist layers 32 and 33 for etching are used as corrosion-resistant films, and the metal substrate 31 is etched with an etching solution (FIG. 29(d)). By this, the outer shape of the die pad 11 and the plurality of wire portions 12A, 12B is formed. The etching solution can be appropriately selected according to the material of the metal substrate 31 used. For example, when a copper alloy is used as the metal substrate 31, usually an aqueous solution of ferric chloride can be used and the metal substrate 31 The two sides are raised by spray etching. For example, as in the case of the first embodiment, the metal substrate 31 may be spray-etched in two stages one surface at a time.

之後，將蝕刻用光阻層32、33剝離並除去(圖29(e))。 After that, the photoresist layers 32 and 33 for etching are peeled off and removed (FIG. 29(e)).

接著，為了將接合打線22和內部端子15之間的密著性提昇，而對於內部端子15施加電鍍處理，並形成電鍍部25(圖29(f))。於此情況，所選擇之電鍍種，只要是能夠確保有與接合打線22之間的密著性者，則係並不對其之種類作限定，但是，例如，係可為Ag或Au等之單層電鍍，亦可為將Ni/Pd或者是Ni/Pd/Au依此順序來作了層積的複數層電鍍。又，電鍍部25，係可僅對於導線部12A、12B中之與接合打線22之間的連 接部作施加，亦可對於導線框架10F之全面作施加。 Next, in order to improve the adhesion between the bonding wire 22 and the internal terminal 15, a plating process is applied to the internal terminal 15 to form a plating portion 25 (FIG. 29(f)). In this case, as long as the selected plating type is one that can ensure adhesion to the bonding wire 22, the type is not limited. However, for example, it may be a single type such as Ag or Au. The layer electroplating may also be a multiple layer electroplating in which Ni/Pd or Ni/Pd/Au is laminated in this order. In addition, the plating part 25 can only be used for the connection between the wire parts 12A and 12B and the bonding wire 22. The connection part can also be applied to the entire lead frame 10F.

如此這般，而能夠得到如圖22~圖26中所示之導線框架10F。 In this way, the lead frame 10F as shown in FIGS. 22 to 26 can be obtained.

半導體裝置之製造方法 Manufacturing method of semiconductor device

接下來，針對圖27以及圖28中所示之半導體裝置20F之製造方法，使用圖30(a)~(e)來作說明。 Next, the manufacturing method of the semiconductor device 20F shown in FIGS. 27 and 28 will be described using FIGS. 30(a) to (e).

首先，如同上述一般，藉由圖29(a)~(f)中所示之方法，來製作導線框架10F。 First, as described above, the lead frame 10F is made by the method shown in Figs. 29(a) to (f).

接著，在導線框架10F之晶粒墊11上，搭載半導體元件21。於此情況，例如係使用黏晶糊等之接著劑24，而將半導體元件21載置在晶粒墊11上並作固定(黏晶工程)(圖30(b))。 Next, the semiconductor element 21 is mounted on the die pad 11 of the lead frame 10F. In this case, for example, an adhesive 24 such as a die bonding paste is used, and the semiconductor element 21 is placed on the die pad 11 and fixed (die bonding process) (FIG. 30(b)).

接著，將半導體元件21之各電極21a和各導線部12A、12B之電鍍部25(內部端子15)分別藉由接合打線(連接構件)22而相互作電性連接(打線接合工程)(圖30(c))。 Next, each electrode 21a of the semiconductor element 21 and the plating portion 25 (internal terminal 15) of each lead portion 12A, 12B are electrically connected to each other by bonding wires (connection members) 22 (wire bonding process) (FIG. 30 (c)).

此時，係將導線框架10F載置在打線接合裝置之加熱塊36上。接著，藉由加熱塊36，來從導線部12A之內導線51以及導線部12B之內導線61之背面側來進行加熱。與此同時地，一面經由打線接合裝置之毛細管(未圖示)來施加超音波，一面將半導體元件21之各電極21a和各外周導線部12A、12B之電鍍部25分別使用接合打線22而作電性連接。 At this time, the lead frame 10F is placed on the heating block 36 of the wire bonding device. Then, by the heating block 36, heating is performed from the back side of the inner lead wire 51 of the lead part 12A and the inner lead 61 of the lead part 12B. At the same time, while ultrasonic waves are applied through the capillary (not shown) of the wire bonding device, each electrode 21a of the semiconductor element 21 and the plating portion 25 of each outer peripheral lead portion 12A, 12B are made using bonding wires 22, respectively. Electrical connection.

於此情況，導線部12A之內導線51以及導線部12B之內導線61，係分別具備有平坦之背面，藉由此，係能夠將導線部12A、12B對於加熱塊36而安定地作載置。藉由此，係成為能夠將接合打線22對於電鍍部25而安定地作連接。 In this case, the inner wire 51 of the wire portion 12A and the inner wire 61 of the wire portion 12B are each provided with a flat back surface, whereby the wire portions 12A, 12B can be stably placed on the heating block 36 . By this, it becomes possible to stably connect the bonding wire 22 to the plating part 25.

接著，藉由對於導線框架10F而將熱硬化性樹脂或熱可塑性樹脂作射出成形或者是轉移成形，來形成密封樹脂23(圖30(d))。如此這般，來將導線框架10F、半導體元件21、導線部12A、12B以及接合打線22作密封。 Next, by injection molding or transfer molding a thermosetting resin or a thermoplastic resin to the lead frame 10F, the sealing resin 23 is formed (FIG. 30(d)). In this way, the lead frame 10F, the semiconductor element 21, the lead portions 12A, 12B, and the bonding wire 22 are sealed.

之後，藉由對於各半導體元件21間之密封樹脂23進行切割，來將導線框架10F個別分離成各單位導線框架10a(參考圖22)。此時，例如係亦可一面使由鑽石砥石所成之刃(未圖示)旋轉，一面將各單位導線框架10a間之導線框架10F以及密封樹脂23切斷。 After that, the sealing resin 23 between the semiconductor elements 21 is cut to separate the lead frame 10F into each unit lead frame 10a (refer to FIG. 22). At this time, for example, the lead frame 10F and the sealing resin 23 between the unit lead frames 10a may be cut while rotating a blade (not shown) made of diamond whetstone.

如此這般，而能夠得到如圖27以及圖28中所示之半導體裝置20f(圖30(e))。 In this way, the semiconductor device 20f shown in FIGS. 27 and 28 can be obtained (FIG. 30(e)).

另外，在本實施形態中，導線框架10F，係由具有750MPa~1100MPa或者是850MPa~1100MPa之拉張強度的金屬材料所構成，各單位導線框架10a之導線部12A、12B中的支持導線13之近旁部分55的寬幅，係成為60μm~90μm或者是75μm~90μm，並且該近旁部分55之厚度，係成為50μm~75μm或者是60μm~75μm。藉由此，由於導線部12A、12B之強度降低的情形係被作抑 制，因此，例如在上述之半導體裝置20F的製造工程中，係能夠防止在導線部12A、12B處產生歪斜或彎曲等之變形的情況。其結果，係能夠將相鄰接之導線部12A和導線部12B間之間隔d(節距)縮窄，而能夠將半導體裝置20F之外部端子17A、17B的數量(銷數)增加。具體而言，相較於先前技術之半導體裝置，係成為能夠將導線部12A、12B之節距作10%以上之縮窄。例如，當半導體裝置20F之尺寸為14mm×14mm的情況時，係可將外部端子17A、17B之數量(銷數)增加至200銷以上。 In addition, in this embodiment, the lead frame 10F is made of a metal material having a tensile strength of 750 MPa to 1100 MPa or 850 MPa to 1100 MPa, and one of the support wires 13 in the lead portions 12A, 12B of each unit lead frame 10a The width of the nearby portion 55 is 60 μm to 90 μm or 75 μm to 90 μm, and the thickness of the nearby portion 55 is 50 μm to 75 μm or 60 μm to 75 μm. By this, the decrease in the strength of the lead portions 12A and 12B is suppressed Therefore, for example, in the above-mentioned manufacturing process of the semiconductor device 20F, it is possible to prevent deformation such as distortion or bending at the lead portions 12A and 12B. As a result, the interval d (pitch) between the adjacent lead portion 12A and lead portion 12B can be narrowed, and the number of external terminals 17A, 17B (pin number) of the semiconductor device 20F can be increased. Specifically, compared with the semiconductor device of the prior art, the pitch of the lead portions 12A, 12B can be narrowed by more than 10%. For example, when the size of the semiconductor device 20F is 14 mm×14 mm, the number of external terminals 17A and 17B (the number of pins) can be increased to 200 pins or more.

又，就算是在將相鄰接之導線部12A、12B之間的間隔作了縮窄的情況時，也能夠對於導線部12A、12B之強度降低的情形作抑制，而能夠防止導線部12A、12B產生變形並在外部端子17A、17B處發生位置偏移的問題。藉由此，係能夠將導線框架10F之良率提高。 In addition, even when the interval between the adjacent lead portions 12A, 12B is narrowed, the decrease in the strength of the lead portions 12A, 12B can be suppressed, and the lead portions 12A, 12A can be prevented from being reduced in strength. 12B is deformed and the external terminals 17A and 17B are displaced. By this, the yield rate of the lead frame 10F can be improved.

進而，藉由將導線部12A、12B之強度提高，由於係能夠將導線部12A、12B之長度增長，因此係能夠使內部端子15對於晶粒墊11而更為接近。藉由此，係能夠減少高價之接合打線22的使用量，而能夠將導線框架10F之製造成本降低。 Furthermore, by increasing the strength of the lead parts 12A and 12B, the length of the lead parts 12A and 12B can be increased, so that the internal terminal 15 can be brought closer to the die pad 11. As a result, the amount of expensive bonding wires 22 used can be reduced, and the manufacturing cost of the lead frame 10F can be reduced.

另外，在上述實施形態中，係以將導線部12A和導線部12B交互地作配置的情況為例來作了說明。然而，係並不被限定於此，導線框架10F，係亦可具備相互具有相同之長度的複數之導線部(QFN型態)。 In addition, in the above-mentioned embodiment, the case where the lead portion 12A and the lead portion 12B are alternately arranged has been described as an example. However, the system is not limited to this, and the lead frame 10F may have a plurality of lead parts (QFN type) having the same length.

進而，在上述實施形態中，係以將內側外部 端子17A以及外側外部端子17B以交錯狀來配列成2列的情況為例來作了說明，但是，係並不被限定於此，亦可將外部端子配置為3列以上。 Furthermore, in the above embodiment, the inside and outside The case where the terminals 17A and the outer external terminals 17B are arranged in a staggered pattern in two rows has been described as an example, but the system is not limited to this, and the external terminals may be arranged in three or more rows.

〔實施例〕 [Example]

接著，針對在本實施形態中之具體性實施例作說明。 Next, specific examples in the present embodiment will be described.

(實施例1) (Example 1)

製作了以由本實施形態所致之構成而成的導線框架10F(實施例1)。於此情況，係準備了含有3.75質量%之Ni、0.9質量%之Si、0.5質量%之Zn、0.15質量%之Sn並且殘餘部分為由銅以及不可避免之雜質所成的銅合金(古河電工股份有限公司製，商品名稱EFTEC-98S)之金屬基板31。此金屬基板31之厚度係為200μm，金屬基板31之拉張強度係為860MPa。另外，金屬基板31之拉張強度，係藉由將金屬基板31裁斷成寬幅20mm，並基於JIS Z2201來製作試驗片，再使用拉張試驗機，來作了測定。藉由將此金屬基板31切斷成300mm×100mm之大小並進行蝕刻加工，而得到了250mm×70mm之大小的導線框架10F(實施例1)。在前述蝕刻加工中，係從金屬基板之兩面來進行噴霧蝕刻(蝕刻工程)，之後，藉由鹼性水溶液來將光阻藉由噴霧方式而剝離(光阻剝離工程)，再以噴霧方式來進行了最終洗淨(最終水洗工程)。在上 述3個的工程中之噴霧時間，係設為總計10分鐘，噴霧壓力係設為0.2MPa。所得到的導線框架，係設為能夠配置56個的晶片之形狀(56面分割)，每一面的導線部之根數，係設為156根。又，將各導線部12A、12B中之支持導線13之近旁部分55的寬幅分別設為75μm，並將近旁部分55之厚度分別設為60μm。 The lead frame 10F (Example 1) having the structure according to this embodiment was produced. In this case, a copper alloy containing 3.75% by mass of Ni, 0.9% by mass of Si, 0.5% by mass of Zn, and 0.15% by mass of Sn was prepared, and the remaining part is made of copper and inevitable impurities (Furukawa Electric Manufactured by a company limited by shares, trade name EFTEC-98S) metal substrate 31. The thickness of the metal substrate 31 is 200 μm, and the tensile strength of the metal substrate 31 is 860 MPa. In addition, the tensile strength of the metal substrate 31 was measured by cutting the metal substrate 31 into a width of 20 mm, making a test piece based on JIS Z2201, and then using a tensile tester. By cutting this metal substrate 31 into a size of 300 mm×100 mm and performing etching processing, a lead frame 10F of a size of 250 mm×70 mm was obtained (Example 1). In the aforementioned etching process, spray etching is performed from both sides of the metal substrate (etching process), then the photoresist is stripped by spraying with an alkaline aqueous solution (photoresist stripping process), and then sprayed The final washing (final washing process) was performed. above The spray time in the three processes was set to 10 minutes in total, and the spray pressure was set to 0.2 MPa. The resultant lead frame was set to a shape (56-face division) capable of arranging 56 chips, and the number of lead parts per face was set to 156. In addition, the width of the vicinity part 55 of the support wire 13 in each of the lead portions 12A and 12B is set to 75 μm, and the thickness of the vicinity part 55 is set to 60 μm.

(實施例2) (Example 2)

金屬基板31之拉張強度係為780MPa，將各導線部12A、12B中之支持導線13之近旁部分55的寬幅分別設為60μm，並將近旁部分55之厚度分別設為50μml，除此之外，係與實施例1相同的，而製作了與實施例1相同形狀之導線框架。 The tensile strength of the metal substrate 31 is 780 MPa. The width of the nearby portion 55 of the supporting wire 13 in each of the wire portions 12A and 12B is set to 60 μm, and the thickness of the nearby portion 55 is set to 50 μml, except for Otherwise, the same as in Example 1, and a lead frame with the same shape as in Example 1 was produced.

〔比較例1〕 [Comparative Example 1]

作為金屬基板之材料，係使用了含有3.0質量%之Ni、0.65質量%之Si、0.15質量%之Mg並且殘餘部分為由銅以及不可避免之雜質所成的銅合金(JX日礦日石金屬股份有限公司製，商品名稱C70251/2H)，除此之外，與實施例1相同的，而製作了與實施例1相同形狀之導線框架。在對於該金屬基板之拉張強度作了測定後，其結果，係為726MPa。 As the material of the metal substrate, a copper alloy containing 3.0% by mass of Ni, 0.65% by mass of Si, and 0.15% by mass of Mg is used, and the remainder is a copper alloy (JX Nippon Steel Co., Ltd. Co., Ltd., trade name C70251/2H), except that it was the same as in Example 1, and a lead frame with the same shape as in Example 1 was produced. After measuring the tensile strength of the metal substrate, the result was 726 MPa.

針對上述3種類之導線框架(實施例1、實施例2以及比較例1)，分別實施了是否會在導線部處產生 變形之試驗。 Regarding the above three types of lead frames (Example 1, Example 2 and Comparative Example 1), it was implemented whether there would be any occurrence at the lead part. Deformation test.

此試驗方法，係藉由判定在製作各導線框架的期間中是否於導線部處產生有變形一事，來實施之。亦即是，係藉由在前述蝕刻工程、光阻剝離工程、最終水洗工程中而使其受到由噴霧所致之衝擊，來確認了在受到衝擊的部位處是否具備有所期望之強度。 This test method is implemented by judging whether there is deformation in the lead part during the production of each lead frame. That is, it was confirmed whether the impacted part has the desired strength by subjecting it to the impact caused by the spray in the aforementioned etching process, photoresist stripping process, and final washing process.

針對各導線框架，係對於在內導線處所具備之外部端子近旁以及支持導線的變形作了計測。作為此計測方法，係使用由金屬顯微鏡所進行之焦點深度計測，並對相對於導線框架之板厚方向的產生變形之高度作了計測。另外，當前述產生變形之高度係為就算是以目視來對於外觀作檢查也難以判定出來的30μm以下的情況時，係判斷為並未產生變形。 For each lead frame, the deformation of the vicinity of the external terminal and the supporting lead of the inner lead is measured. As this measurement method, a focal depth measurement performed by a metal microscope was used, and the height of the deformation relative to the thickness direction of the lead frame was measured. In addition, when the height at which the deformation occurs is 30 μm or less that is difficult to determine even by visual inspection of the appearance, it is determined that the deformation does not occur.

另外，在實施例1、實施例2以及比較例1之任一者中，均係製作了10枚的導線框架。針對所製作出之各個的導線框架，而對於產生有變形之導線部的根數作測定，並算出了在每一枚之導線框架之平均的產生了變形之根數。進而，根據所算出了在每一枚之導線框架之平均的產生了變形之根數，來算出了在每一晶片(每一分割面)之平均的產生了變形之導線部之根數。將此結果展示於表1中。 In addition, in any of Example 1, Example 2, and Comparative Example 1, 10 lead frames were produced. For each wire frame produced, the number of deformed wire portions was measured, and the average number of deformed wires in each wire frame was calculated. Furthermore, based on the calculated average number of deformed wires in each lead frame, the average number of deformed wire portions per chip (each dividing surface) is calculated. This result is shown in Table 1.

Figure 109118480-A0101-12-0059-1
Figure 109118480-A0101-12-0059-1

其結果，針對實施例1以及實施例2之導線框架10F，在導線部12A、12B處係並未發生有變形。相對於此，針對比較例1之導線框架，係於其之一部分處發生了變形。 As a result, in the lead frame 10F of Example 1 and Example 2, no deformation occurred at the lead portions 12A and 12B. In contrast, the lead frame of Comparative Example 1 was deformed in a part of it.

(第6實施形態) (The sixth embodiment)

接著，參考圖31~圖34，對本發明之第6實施形態作說明。圖31~圖34，係為對於本發明之第6實施形態作展示者。在圖31~圖34中，連接環14之半蝕刻部(凹部)，係並非為遍佈連接環14之全周地來設置，而是沿著連接環14而規則性地設置，在各半蝕刻部之間，係被形成有厚壁部28a。在圖31~圖34中，針對與第1~第5實施形態相同的部份，係附加相同之元件符號，並省略詳細說明。 Next, referring to Fig. 31 to Fig. 34, the sixth embodiment of the present invention will be described. Figures 31 to 34 show the sixth embodiment of the present invention. In FIGS. 31 to 34, the half-etched portions (recesses) of the connecting ring 14 are not provided all over the entire circumference of the connecting ring 14, but are arranged regularly along the connecting ring 14, and each half-etched Between the sections, thick sections 28a are formed. In FIGS. 31 to 34, the same reference numerals are assigned to the same parts as the first to fifth embodiments, and detailed descriptions are omitted.

在圖31以及圖32(a)、(b)所示之導線框架10G中，連接環14，係被設置在導線部12A、12B之內導線51的前端側處，並以包圍晶粒墊11的方式而被作 配置。在連接環14之外側周緣部(支持導線13側周緣部)處，係被連結有導線部12A、12B之內導線51。又，係從連接環14起朝向內側(晶粒墊11側)地而延伸出有連結條19。於此情況，連接環14，雖係被與全部的內導線51作連結而被作支持，但是，係並不被限定於此，連接環14係亦可僅被與一部分之內導線51作連結並被作支持。 In the lead frame 10G shown in FIGS. 31 and 32(a), (b), the connecting ring 14 is provided at the front end side of the wire 51 within the wire portions 12A, 12B to surround the die pad 11 To be made Configuration. At the outer peripheral edge portion of the connecting ring 14 (the peripheral edge portion on the side of the support wire 13), the inner wire 51 to which the wire portions 12A and 12B are connected is connected. In addition, a connecting bar 19 extends from the connecting ring 14 toward the inner side (die pad 11 side). In this case, although the connecting ring 14 is connected to all the inner wires 51 to be supported, the system is not limited to this, and the connecting ring 14 may be connected to only a part of the inner wires 51 And was made support.

在連接環14之表面的各內導線51之前端近旁處，係分別被形成有凹部14c。各凹部14c，係為藉由半蝕刻所形成者，而在厚度方向上並不被作貫通地來具有一定之深度。另外，各凹部14c，係被形成於連接環14之寬幅方向略中央部處。 In the vicinity of the front end of each inner lead 51 on the surface of the connection ring 14, recesses 14c are respectively formed. Each recess 14c is formed by half-etching, and has a certain depth without being penetrated in the thickness direction. In addition, each recessed portion 14c is formed at a substantially central portion of the connecting ring 14 in the width direction.

又，在相互鄰接之凹部14c之間，係被形成有厚壁部28a。亦即是，凹部14c和厚壁部28a，係沿著連接環14之長邊方向而被交互作配置。於此情況，厚壁部28a，係並不被作半蝕刻地而具備有與晶粒墊11以及支持導線13相同之厚度。又，連結條19，係在晶粒墊11之4邊的全部處，分別各被連結有2根。晶粒墊11，係藉由連接環14以及連結條19而被作支持。另一方面，在晶粒墊11之四角隅處，由於係並未被設置有懸吊導線，因此，在晶粒墊11之四角隅近旁處，係亦可配置導線部12A、12B。因此，相較於將晶粒墊11藉由懸吊導線來作支持的情況，係能夠增加導線部12A、12B之根數。 In addition, thick portions 28a are formed between the recesses 14c adjacent to each other. That is, the concave portion 14c and the thick portion 28a are alternately arranged along the longitudinal direction of the connecting ring 14. In this case, the thick portion 28a is not half-etched but has the same thickness as the die pad 11 and the support wire 13. In addition, the connecting bars 19 are connected to all the four sides of the die pad 11, and two are connected respectively. The die pad 11 is supported by the connecting ring 14 and the connecting bar 19. On the other hand, at the four corners of the die pad 11, since the system is not provided with suspended wires, the wire portions 12A and 12B can also be arranged near the four corners of the die pad 11. Therefore, compared with the case where the die pad 11 is supported by suspended wires, the number of the wire portions 12A and 12B can be increased.

在本實施形態中，於製作半導體裝置20G (參考圖33)時，連接環14中之各凹部14c之周邊的堤部、和連接環14中之位置在各凹部14c之間的厚壁部28a，係同時地被開始蝕刻，但是，在厚壁部28a之除去中，係相較於被設置有各凹部14c之區域而更耗費時間，藉由此，係能夠對於連接環14自身之蝕刻的進行作調整。 In this embodiment, the semiconductor device 20G is manufactured (Refer to FIG. 33), the embankment around each recess 14c in the connecting ring 14 and the thick portion 28a located between the recesses 14c in the connecting ring 14 are simultaneously etched, but in The removal of the thick portion 28a takes more time than the area provided with the recesses 14c, and by this, the etching of the connecting ring 14 itself can be adjusted.

亦即是，在從導線框架10G之背面側起而將連接環14作蝕刻除去時(參考圖7(e))，係預先在導線框架10以及密封樹脂23之背面的蝕刻用光阻層34之與連接環14相對應的位置處，設置開口部34a。之後，藉由從該開口部34a所進入之腐蝕液，而將連接環14中之各凹部14c和厚壁部28a適度地溶解並除去。於此情況，由於在連接環14之表面上係被設置有凹部14c，因此，從開口部34a所進入的腐蝕液，係並不會將導線部12A、12B作必要以上之溶解，而能夠適當地將連接環14之全體除去。 That is, when the connection ring 14 is etched and removed from the back side of the lead frame 10G (refer to FIG. 7(e)), the photoresist layer 34 for etching is preliminarily placed on the back surface of the lead frame 10 and the sealing resin 23 At a position corresponding to the connecting ring 14, an opening 34a is provided. After that, the recessed portion 14c and the thick portion 28a in the connecting ring 14 are appropriately dissolved and removed by the etching liquid entering from the opening 34a. In this case, since the concave portion 14c is provided on the surface of the connecting ring 14, the corrosive liquid entering from the opening 34a does not dissolve the lead portions 12A, 12B more than necessary, and can be appropriately Ground all of the connecting ring 14 is removed.

另外，在本實施形態中，凹部14c，雖係被設置在全部的內導線51之前端近旁處，但是，係並不被限定於此，而亦可僅被設置在一部分之內導線51之前端近旁處。 In addition, in this embodiment, although the recess 14c is provided near the front end of all the inner wires 51, the system is not limited to this, and it may be provided only at a part of the front end of the inner wires 51. Nearby.

如此這般，藉由沿著連接環14而將凹部14c以一定之間隔來設置為點狀，並於各凹部14c之間形成有厚壁部28a，在將連接環14作蝕刻除去時，係能夠對於腐蝕液之進入和溶解作適宜的調整。 In this way, the recesses 14c are provided in dots at regular intervals along the connecting ring 14, and thick portions 28a are formed between the recesses 14c. When the connecting ring 14 is removed by etching, The entry and dissolution of the corrosive liquid can be adjusted appropriately.

圖34中所示之半導體裝置20H，係對於本實施形態之變形例作展示，並對於並未將厚壁部28a完全除去而殘留於半導體裝置20H內部的形態作展示。此半導體裝置20H，係為由圖31以及圖32(a)、(b)中所示之導線框架10G所製作者，厚壁部28a，係並未被完全除去地而殘留，並構成第2端子部。此厚壁部28a，係沿著晶粒墊11之周圍4邊(於圖34中，係為與X方向或Y方向相平行之4邊)的全部，而相互空出有間隔地來作配列。 The semiconductor device 20H shown in FIG. 34 shows a modification of this embodiment, and shows a form in which the thick portion 28a is not completely removed but remains inside the semiconductor device 20H. This semiconductor device 20H is manufactured by the lead frame 10G shown in FIGS. 31 and 32(a) and (b). The thick portion 28a remains without being completely removed, and constitutes the second Terminal part. The thick portion 28a is arranged along all the four sides (in FIG. 34, the four sides parallel to the X direction or the Y direction) of the die pad 11, and is arranged at intervals. .

於圖34中，厚壁部28a，由於係由連接環14之一部分所形成，因此係沿著將各內導線51之前端近旁作連結的直線而被作配置。在圖34中，複數之厚壁部28a，係在晶粒墊11和內導線51之前端之間的區域中，而被配置為矩形狀。 In FIG. 34, since the thick portion 28a is formed by a part of the connecting ring 14, it is arranged along a straight line connecting the vicinity of the front end of each inner lead 51. In FIG. 34, the plural thick portions 28a are located in the area between the die pad 11 and the front end of the inner wire 51, and are arranged in a rectangular shape.

於此情況，導線框架10G的連接環14中之各凹部14c的周邊區域，係在藉由密封樹脂23而被作了樹脂密封之後，從背面側起來藉由蝕刻而除去。另一方面，各厚壁部28a，係從晶粒墊11、導線部12A、12B以及其他之厚壁部28a而分離，並與此些之構件相互電性獨立，而構成第2端子部。此厚壁部28a，係並不被作半蝕刻地而具備有與晶粒墊11相同之厚度。進而，在厚壁部28a的背面，係形成有被與外部之安裝基板(未圖示)作電性連接之外部端子17C。又，在厚壁部28a之表面上，係設置有用以提昇其與接合打線22之間的密著性之電鍍部 25，並分別被連接有接合打線22。 In this case, the peripheral area of each recess 14c in the connecting ring 14 of the lead frame 10G is resin-sealed by the sealing resin 23, and then removed from the back side by etching. On the other hand, each thick portion 28a is separated from the die pad 11, the lead portions 12A, 12B, and other thick portions 28a, and is electrically independent of these members to form a second terminal portion. The thick portion 28a is not half-etched but has the same thickness as the die pad 11. Furthermore, on the back surface of the thick portion 28a, external terminals 17C electrically connected to an external mounting substrate (not shown) are formed. In addition, on the surface of the thick portion 28a, a plating portion is provided to improve the adhesion between it and the bonding wire 22 25, and are respectively connected with bonding wires 22.

又，伴隨著連接環14中之除了厚壁部28a以外的部份被除去一事，在密封樹脂23之背面中的導線部12A、12B和晶粒墊11之間之區域處，係被形成有凹部27。 Also, with the removal of the connecting ring 14 except for the thick portion 28a, the area between the lead portions 12A, 12B and the die pad 11 on the back surface of the sealing resin 23 is formed with Recess 27.

若依據圖34中所示之形態，則在製作半導體裝置20H時，連接環14之一部分係被除去，連接環14中之並未被除去的部份係被相互個別地分離並被形成為構成第2端子部之厚壁部28a。如此這般，藉由被形成有多數之厚壁部28a，係能夠將與外部之安裝基板作連接的端子部之數量(銷數)增加，而能夠實現半導體裝置20之更進一步的高密度化。 According to the form shown in FIG. 34, when manufacturing the semiconductor device 20H, a part of the connecting ring 14 is removed, and the unremoved part of the connecting ring 14 is separated from each other individually and formed into a structure The thick portion 28a of the second terminal portion. In this way, by forming a large number of thick portions 28a, it is possible to increase the number of terminal portions (the number of pins) connected to an external mounting substrate, and it is possible to further increase the density of the semiconductor device 20 .

於圖34中，被殘留於半導體裝置20H內之厚壁部28a，係並非絕對需要作為外部端子(第2端子部)來使用。例如，殘留於半導體裝置20H內之厚壁部28a，係亦可發揮當對於半導體裝置20H施加有衝擊時而防止晶粒墊11周邊之變形的作用。或者是，厚壁部28a，係亦可藉由將露出於半導體裝置20H之背面的金屬部分增加，來發揮將半導體裝置20H之散熱性提昇的作用。 In FIG. 34, the thick portion 28a remaining in the semiconductor device 20H is not absolutely necessary to be used as an external terminal (second terminal portion). For example, the thick portion 28a remaining in the semiconductor device 20H can also play a role in preventing deformation of the periphery of the die pad 11 when an impact is applied to the semiconductor device 20H. Alternatively, the thick portion 28a may play a role of improving the heat dissipation of the semiconductor device 20H by increasing the metal portion exposed on the back surface of the semiconductor device 20H.

另外，由本實施形態所致之導線框架10G之製造方法以及半導體裝置20G、20C之製造方法，係與由第1實施形態所致之導線框架10之製造方法(圖6(a)~(f))以及半導體裝置20之製造方法(圖7(a)~(f)))略相同。 In addition, the manufacturing method of the lead frame 10G and the manufacturing methods of the semiconductor devices 20G, 20C according to this embodiment are the same as the manufacturing method of the lead frame 10 according to the first embodiment (FIG. 6(a)~(f)) ) And the manufacturing method of the semiconductor device 20 (FIG. 7(a)~(f))) are slightly the same.

10:導線框架 10: Wire frame

10a:單位導線框架 10a: unit lead frame

11:晶粒墊 11: Die pad

12A:長外周導線部 12A: Long outer peripheral wire part

12B:短外周導線部 12B: Short outer peripheral wire part

13:支持導線 13: Support wire

14:連接環 14: connecting ring

14a:凹溝 14a: groove

14b:堤部 14b: Embankment

15A:內部端子 15A: Internal terminal

15B:內部端子 15B: Internal terminal

16:懸吊導線 16: suspension wire

17A:內側外部端子 17A: Internal external terminal

17B:外側外部端子 17B: Outer external terminal

17C:外部端子 17C: External terminal

17D:外部端子 17D: External terminal

17E:外部端子 17E: External terminal

17F:外部端子 17F: External terminal

18:第2端子部 18: The second terminal part

25:電鍍部 25: Electroplating Department

26A:長內側導線部 26A: Long inner lead part

26B:短內側導線部 26B: Short inner wire part

26C:長內側導線部 26C: Long inner lead part

26D:短內側導線部 26D: Short inner lead part

27:凹部 27: recess

52:連接導線 52: Connect the wires

53:第1端子部 53: The first terminal

57:連接導線 57: Connect the wires

Claims (4)

一種導線框架，係為半導體裝置用之導線框架，其特徵為，係具備有： A lead frame, which is a lead frame for semiconductor devices, is characterized in that it has: 矩形狀之晶粒墊，係搭載有半導體元件；和 Rectangular die pads are equipped with semiconductor components; and 複數之外周導線部，係被設置於前述晶粒墊之周圍，並分別包含有第1端子部；和 The plurality of outer peripheral lead parts are arranged around the aforementioned die pads and respectively include first terminal parts; and 導線連接部，係被配置在前述晶粒墊和前述外周導線部之間；和 The wire connection part is arranged between the die pad and the outer peripheral wire part; and 複數之內側導線部，係藉由前述導線連接部而被支持，並分別包含有第2端子部， The plurality of inner lead parts are supported by the aforementioned lead connection parts, and each includes a second terminal part, 前述複數之內側導線部，係包含有長內側導線部和短內側導線部，前述長內側導線部和前述短內側導線部，係沿著前述導線連接部而被交互作配置， The plurality of inner wire portions includes a long inner wire portion and a short inner wire portion, and the long inner wire portion and the short inner wire portion are alternately arranged along the wire connecting portion, 前述導線連接部，係僅沿著前述晶粒墊之相互平行之2邊而延伸，而並未設置有沿著其他之相互平行之2邊而延伸的導線連接部。 The wire connection portion only extends along two parallel sides of the die pad, and there is no wire connection portion extending along the other two parallel sides. 一種半導體裝置，其特徵為，係具備有： A semiconductor device, characterized in that it has: 矩形狀之晶粒墊；和 Rectangular die pads; and 複數之外周導線部，係被設置在前述晶粒墊之周圍，並分別包含有第1端子部；和 The plurality of outer peripheral lead portions are arranged around the aforementioned die pads, and each includes a first terminal portion; and 複數之第2端子部，係被配置在前述晶粒墊和前述外周導線部之間，並從前述晶粒墊以及前述外周導線部而作了分離；和 A plurality of second terminal portions are arranged between the die pad and the outer peripheral lead portion, and are separated from the die pad and the outer peripheral lead portion; and 半導體元件，係被搭載於前述晶粒墊上；和 The semiconductor element is mounted on the aforementioned die pad; and 連接構件，係將前述半導體元件和各外周導線部作電性連接，並且將前述半導體元件和各第2端子部作電性連接；和 The connecting member electrically connects the aforementioned semiconductor element and each outer peripheral lead portion, and electrically connects the aforementioned semiconductor element and each second terminal portion; and 密封樹脂，係將前述晶粒墊和前述複數之外周導線部和前述複數之第2端子部和前述半導體元件以及前述連接構件作密封， The sealing resin seals the die pad, the plurality of outer peripheral lead portions, the plurality of second terminal portions, the semiconductor element, and the connecting member, 前述複數之外周導線部，係包含有使前述第1端子部相對性地位置於內側之長外周導線部、和使前述第1端子部相對性地位置於外側之短外周導線部，前述長外周導線部和前述短外周導線部係被交互作配置， The plurality of outer peripheral lead parts includes a long outer peripheral lead part where the relative position of the first terminal part is placed inside, and a short peripheral lead part where the relative position of the first terminal part is placed outside, and the long outer circumference The lead part and the aforementioned short outer peripheral lead part are alternately arranged, 在前述密封樹脂的背面中之前述外周導線部與前述晶粒墊之間的區域處，係被形成有凹部， A recessed portion is formed in the area between the outer peripheral lead portion and the die pad on the back surface of the sealing resin, 前述凹部，係僅沿著前述晶粒墊之相互平行之2邊而延伸，而並未設置有沿著其他之相互平行之2邊而延伸的凹部。 The recesses extend only along the two parallel sides of the die pad, and are not provided with recesses extending along the other two parallel sides. 一種導線框架之製造方法，係為如申請專利範圍第1項所記載之導線框架之製造方法，其特徵為，係具備有： A method for manufacturing a lead frame is the method for manufacturing a lead frame as described in item 1 of the scope of patent application, characterized in that it has: 準備金屬基板之工程；和 The process of preparing the metal substrate; and 藉由對於前述金屬基板進行蝕刻加工，而在前述金屬基板上形成前述晶粒墊、前述外周導線部、前述導線連接部以及前述內側導線部之工程。 The process of forming the die pad, the outer peripheral wire portion, the wire connection portion, and the inner wire portion on the metal substrate by etching the metal substrate. 一種半導體裝置之製造方法，其特徵 為，係具備有： A method of manufacturing a semiconductor device, its characteristics For, the department has: 準備如請求項1所記載之導線框架之工程；和 Prepare the wire frame project as described in claim 1; and 在前述導線框架之前述晶粒墊上搭載前述半導體元件之工程；和將前述半導體元件和各外周導線部藉由連接構件來作電性連接之工程；和 The process of mounting the aforementioned semiconductor element on the aforementioned die pad of the aforementioned lead frame; and the process of electrically connecting the aforementioned semiconductor element and each peripheral lead part through a connecting member; and 將前述晶粒墊和前述複數之外周導線部和前述半導體元件以及前述連接構件藉由密封樹脂來作密封之工程；和 The process of sealing the die pad, the plurality of outer peripheral lead portions, the semiconductor element, and the connecting member with a sealing resin; and 藉由從前述導線框架之背面側來將前述導線連接部之至少一部分除去，而將前述複數之第2端子部分別個別地作分離之工程。 By removing at least a part of the wire connection part from the back side of the lead frame, the plurality of second terminal parts are individually separated.
TW109118480A 2014-01-22 2015-01-22 Lead frame and its manufacturing method, and semiconductor device and its manufacturing method TWI719905B (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2014-009332 2014-01-22
JP2014009332 2014-01-22
JP2014031975 2014-02-21
JP2014-031975 2014-02-21
JP2014-158121 2014-08-01
JP2014158121 2014-08-01

Publications (2)

Publication Number Publication Date
TW202038408A true TW202038408A (en) 2020-10-16
TWI719905B TWI719905B (en) 2021-02-21

Family

ID=53681424

Family Applications (3)

Application Number Title Priority Date Filing Date
TW109118480A TWI719905B (en) 2014-01-22 2015-01-22 Lead frame and its manufacturing method, and semiconductor device and its manufacturing method
TW104102106A TWI662673B (en) 2014-01-22 2015-01-22 Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof
TW108110126A TWI712137B (en) 2014-01-22 2015-01-22 Lead frame and its manufacturing method, and semiconductor device and its manufacturing method

Family Applications After (2)

Application Number Title Priority Date Filing Date
TW104102106A TWI662673B (en) 2014-01-22 2015-01-22 Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof
TW108110126A TWI712137B (en) 2014-01-22 2015-01-22 Lead frame and its manufacturing method, and semiconductor device and its manufacturing method

Country Status (2)

Country Link
TW (3) TWI719905B (en)
WO (1) WO2015111623A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10177081B2 (en) * 2017-01-13 2019-01-08 Littlefuse, Inc. Thyristor and thermal switch device and assembly techniques therefor

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2937032B2 (en) * 1993-09-20 1999-08-23 住友電気工業株式会社 Lead frame manufacturing method
JP3046024B1 (en) * 1999-04-23 2000-05-29 松下電子工業株式会社 Lead frame and method of manufacturing resin-encapsulated semiconductor device using the same
JP2002261193A (en) * 2001-03-06 2002-09-13 Hitachi Ltd Method for manufacturing semiconductor device
JP2003017645A (en) * 2001-07-03 2003-01-17 Shinko Electric Ind Co Ltd Lead frame and method of fabricating the same
JP4173346B2 (en) * 2001-12-14 2008-10-29 株式会社ルネサステクノロジ Semiconductor device
JP3804534B2 (en) * 2002-01-08 2006-08-02 凸版印刷株式会社 Lead frame manufacturing method
US8278148B2 (en) * 2007-09-13 2012-10-02 Stats Chippac Ltd. Integrated circuit package system with leads separated from a die paddle
US9202777B2 (en) * 2008-05-30 2015-12-01 Stats Chippac Ltd. Semiconductor package system with cut multiple lead pads
US8072050B1 (en) * 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
JP4563480B2 (en) * 2008-11-28 2010-10-13 Ｄｏｗａメタルテック株式会社 Copper alloy sheet and manufacturing method thereof
US8404524B2 (en) * 2010-09-16 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system with paddle molding and method of manufacture thereof

Also Published As

Publication number Publication date
TW201535648A (en) 2015-09-16
TW201929173A (en) 2019-07-16
WO2015111623A1 (en) 2015-07-30
TWI662673B (en) 2019-06-11
TWI712137B (en) 2020-12-01
TWI719905B (en) 2021-02-21

Similar Documents

Publication Publication Date Title
TWI587457B (en) Resin-encapsulated semiconductor device and method of manufacturing the same
JP2005057067A (en) Semiconductor device and manufacturing method thereof
JP6319644B2 (en) Lead frame, manufacturing method thereof, and manufacturing method of semiconductor device
JP6205816B2 (en) Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof
JP7044142B2 (en) Lead frame and its manufacturing method
JP7174363B2 (en) Lead frames and semiconductor equipment
JP6936963B2 (en) Lead frame
JP6379448B2 (en) Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof
TWI712137B (en) Lead frame and its manufacturing method, and semiconductor device and its manufacturing method
JP6573157B2 (en) Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof
JP6607429B2 (en) Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof
JP6946870B2 (en) Lead frames, semiconductor devices, and methods for manufacturing semiconductor devices
JP6788825B2 (en) Lead frames and semiconductor devices
JP6807050B2 (en) Lead frames and semiconductor devices
JP6465394B2 (en) Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof
JP7380750B2 (en) Lead frames and semiconductor devices
JP7223347B2 (en) Manufacturing method of lead frame and semiconductor device
JP6436202B2 (en) Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof
JP7081702B2 (en) Lead frames and semiconductor devices
JP6842649B2 (en) Lead frames and semiconductor devices
JP2015154042A (en) Lead frame and manufacturing method therefor, and semiconductor device and manufacturing method therefor
JP6807043B2 (en) Lead frames and semiconductor devices
JP2021036626A (en) Lead frame and semiconductor device
JPH0290662A (en) Inner lead of lead frame
JP2001077273A (en) Lead frame and manufacture of resin-sealed semiconductor device using the same