TWI662673B - Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof - Google Patents

Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof Download PDF

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TWI662673B
TWI662673B TW104102106A TW104102106A TWI662673B TW I662673 B TWI662673 B TW I662673B TW 104102106 A TW104102106 A TW 104102106A TW 104102106 A TW104102106 A TW 104102106A TW I662673 B TWI662673 B TW I662673B
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lead
portions
die pad
outer peripheral
lead frame
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TW104102106A
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Chinese (zh)
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TW201535648A (en
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永田昌博
矢崎雅樹
冨田幸治
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日商大日本印刷股份有限公司
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    • H—ELECTRICITY
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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Abstract

導線框架(10)，係具備有：晶粒墊(11)，係搭載有半導體元件(21)；和複數之長外周導線部(12A)以及短外周導線部(12B)，係被設置於晶粒墊(11)之周圍，並分別包含有第1端子部(53)；和連接環(14)，係被配置在晶粒墊(11)和長外周導線部(12A)以及短外周導線部(12B)之間，並包圍晶粒墊(11)。複數之內側導線部(26A~26D)，係包含有長內側導線部(26A、26C)，和短內側導線部(26B、26D)。長內側導線部(26A、26C)和短內側導線部(26B、26D)，係沿著連接環(14)而被交互作配置。 The lead frame (10) is provided with a die pad (11) on which a semiconductor element (21) is mounted, and a plurality of long outer lead portions (12A) and short outer lead portions (12B) provided on a crystal. The periphery of the grain pad (11) includes a first terminal portion (53); and a connecting ring (14), which are arranged on the die pad (11), the long outer conductor portion (12A), and the short outer conductor portion. (12B) and surround the die pad (11). The plurality of inner lead portions (26A to 26D) include long inner lead portions (26A, 26C) and short inner lead portions (26B, 26D). The long inner lead portions (26A, 26C) and the short inner lead portions (26B, 26D) are alternately arranged along the connecting ring (14).

Description

導線框架及其製造方法、以及半導體裝置及其製造方法 Lead frame and manufacturing method thereof, and semiconductor device and manufacturing method thereof

本發明，係有關於導線框架及其製造方法、以及半導體裝置及其製造方法 The present invention relates to a lead frame and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof.

近年來，係對於被安裝在基板上之半導體裝置的小型化以及薄型化有所要求。為了對應於此種要求，於先前技術中，係對於使用導線框架，並將搭載於其之搭載面上的半導體元件藉由密封樹脂來作密封，且在背面側使導線的一部分露出，而構成的所謂QFN(Quad Flat Non-lead)形態之半導體裝置作了各種的提案。 In recent years, there has been a demand for miniaturization and thinning of semiconductor devices mounted on a substrate. In order to meet such a requirement, in the prior art, a lead frame is used, and a semiconductor element mounted on the mounting surface is sealed with a sealing resin, and a part of the lead is exposed on the back side. Various proposals have been made for semiconductor devices of the so-called QFN (Quad Flat Non-lead) type.

然而，在由先前技術之一般構造所成之QFN的情況時，伴隨著端子數量的增加，由於封裝係會變大，因此係有著會變得難以確保安裝信賴性的課題。相對於此，作為用以實現作了多銷化之QFN的技術，對於將外部端子配列成2列的封裝之開發係有所進展(例如專利文獻1)。此種封裝，係亦被稱作DR-QFN(Dual Row QFN)封裝。 However, in the case of a QFN formed by a general structure of the prior art, as the number of terminals increases, the package system becomes larger, and therefore, it is difficult to ensure mounting reliability. On the other hand, as a technology for realizing multi-pin QFN, there has been progress in the development of a package in which external terminals are arranged in two rows (for example, Patent Document 1). This package is also called DR-QFN (Dual Row QFN) package.

〔先前技術文獻〕 [Previous Technical Literature] 〔專利文獻〕 [Patent Literature]

〔專利文獻1〕日本特開2006-19767號公報 [Patent Document 1] Japanese Patent Laid-Open No. 2006-19767

近年來，在生產DR-QFN封裝時，係要求能夠並不對於晶片尺寸作變更地而增加導線部之數量(銷數)。針對此，於先前技術中，為了增加銷數，係採用有將封裝尺寸增大的手法。然而，由於係存在有需要將封裝搭載於電子機器上一事所導致的限制，因此在將封裝尺寸增大一事上係存在有極限。又，伴隨著封裝尺寸之增大，由於內導線的長度也會變長，因此係亦存在著會變成易於在內導線處產生變形的問題。 In recent years, when producing a DR-QFN package, it is required to increase the number of lead portions (number of pins) without changing the size of the wafer. In view of this, in the prior art, in order to increase the number of pins, a method of increasing the package size is used. However, there is a limit in increasing the size of the package due to limitations due to the need to mount the package on an electronic device. In addition, as the package size increases, the length of the inner lead also becomes longer, so there is a problem that the inner lead is liable to be deformed.

本發明，係為對於此種問題作考慮所進行者，其目的，係在於提供一種能夠將與外部作連接之端子部的數量(銷數)增加之導線框架及其製造方法、以及半導體裝置及其製造方法。 The present invention has been made in consideration of such problems, and an object thereof is to provide a lead frame capable of increasing the number (pin number) of terminal portions connected to the outside, a method for manufacturing the same, a semiconductor device, and a semiconductor device. Its manufacturing method.

本發明，係為一種導線框架，其係為半導體裝置用之導線框架，其特徵為，係具備有：晶粒墊，係搭載有半導體元件；和複數之外周導線部，係被設置於前述晶粒墊之周圍，並分別包含有第1端子部；和連接環，係被配置在前述晶粒墊和前述外周導線部之間，並包圍前述晶粒墊；和複數之內側導線部，係藉由前述連接環而被支持，並分別包含有第2端子部，前述複數之內側導線部，係包含有長內側導線部和短內側導線部，前述長內側導線 部和前述短內側導線部，係沿著前述連接環而被交互作配置。 The present invention is a lead frame, which is a lead frame for a semiconductor device, and is characterized in that it is provided with: a die pad, on which a semiconductor element is mounted; and a plurality of outer peripheral lead portions, which are provided on the aforementioned crystal Around the grain pad, each includes a first terminal portion; and a connecting ring is disposed between the die pad and the outer peripheral wire portion and surrounds the die pad; and a plurality of inner lead portions are borrowed Supported by the connection ring, and each includes a second terminal portion, and the plurality of inner conductor portions includes a long inner conductor portion and a short inner conductor portion, and the long inner conductor portion. The portion and the short inner lead portion are arranged alternately along the connecting ring.

本發明，係為一種導線框架，其中，前述複數之內側導線部，係從前述連接環之內側以及外側的雙方而延伸。 The present invention is a lead frame in which the plurality of inner lead portions extend from both the inner side and the outer side of the connection ring.

本發明，係為一種導線框架，其中，前述複數之內側導線部中的從前述連接環之內側所延伸之前述短內側導線部、和從前述連接環之外側所延伸之前述長內側導線部，係隔著前述連接環而被配置在互為相反側之位置。 The present invention is a lead frame in which the short inner lead portion extending from the inner side of the connecting ring and the long inner lead portion extending from the outer side of the connecting ring among the plurality of inner lead portions, It is arrange | positioned on the opposite side to each other via the said connection ring.

本發明，係為一種導線框架，其中，在前述連接環之表面上，係沿著前述連接環而被形成有凹溝。 The present invention is a lead frame in which a groove is formed along a surface of the connection ring along the connection ring.

本發明，係為一種導線框架，其中，前述內側導線部，係具備有被與前述連接環作連結之連接導線，前述連接導線，係從背面側起而作了厚度薄化。 The present invention is a lead frame in which the inner lead portion is provided with a connecting lead connected to the connecting ring, and the connecting lead is reduced in thickness from the back side.

本發明，係為一種導線框架，其中，前述內側導線部，係具備有被與前述連接環作連結之連接導線，前述連接導線，係從表面側起而作了厚度薄化。 The present invention is a lead frame in which the inner lead portion is provided with a connecting lead connected to the connecting ring, and the connecting lead is reduced in thickness from the surface side.

本發明，係為一種導線框架，其中，前述複數之外周導線部，係包含有長外周導線部和短外周導線部，前述長外周導線部和前述短外周導線部係被交互配置，前述複數之內側導線部，係從前述連接環之至少外側而延伸，前述長外周導線部和前述短內側導線部係相互對向，前述短外周導線部和前述長內側導線部係相互對向。 The present invention is a lead frame, wherein the plurality of outer peripheral lead portions includes a long outer peripheral lead portion and a short outer peripheral lead portion, and the long outer peripheral lead portion and the short outer peripheral lead portion are alternately arranged. The inner lead portion extends from at least the outer side of the connection ring, the long outer lead portion and the short inner lead portion face each other, and the short outer lead portion and the long inner lead portion face each other.

本發明，係為一種導線框架，其中，係由具備有750Mpa~1100Mpa之拉張強度的金屬材料所構成。 The present invention is a lead frame, which is made of a metal material having a tensile strength of 750Mpa ~ 1100Mpa.

本發明，係為一種導線框架，其係為半導體裝置用之導線框架，其特徵為，係具備有：晶粒墊，係搭載有半導體元件；和複數之外周導線部，係被設置於前述晶粒墊之周圍，並分別包含有第1端子部；和導線連接部，係被配置在前述晶粒墊和前述外周導線部之間；和複數之內側導線部，係藉由前述導線連接部而被支持，並分別包含有第2端子部，前述複數之內側導線部，係包含有長內側導線部和短內側導線部，前述長內側導線部和前述短內側導線部，係沿著前述導線連接部而被交互作配置。 The present invention is a lead frame, which is a lead frame for a semiconductor device, and is characterized in that it is provided with: a die pad, on which a semiconductor element is mounted; and a plurality of outer peripheral lead portions, which are provided on the aforementioned crystal Around the pad, each includes a first terminal portion; and a lead connection portion disposed between the die pad and the outer peripheral lead portion; and a plurality of inner lead portions by the lead connection portion. It is supported and includes a second terminal portion, and the plurality of inner lead portions include a long inner lead portion and a short inner lead portion. The long inner lead portion and the short inner lead portion are connected along the lead. It is configured interactively.

本發明，係為一種半導體裝置，其特徵為，係具備有：晶粒墊；和複數之外周導線部，係被設置在前述晶粒墊之周圍，並分別包含有第1端子部；和複數之第2端子部，係被配置在前述晶粒墊和前述外周導線部之間，並從前述晶粒墊以及前述外周導線部而作了分離；和半導體元件，係被搭載於前述晶粒墊上；和連接構件，係將前述半導體元件和各外周導線部作電性連接，並且將前述半導體元件和各第2端子部作電性連接；和密封樹脂，係將前述晶粒墊和前述複數之外周導線部和前述複數之第2端子部和前述半導體元件以及前述連接構件作密封，前述複數之外周導線部，係包含有使前述第1端子部相對性地位置於內側之長外周導線部、和使前述第1端子部相對性地位置於外側之短外周導線部，前述長外周導線部和前 述短外周導線部係被交互作配置，在前述密封樹脂的背面中之前述外周導線部與前述晶粒墊之間的區域處，係以包圍前述晶粒墊的方式而被形成有凹部。 The present invention relates to a semiconductor device, comprising: a die pad; and a plurality of peripheral lead portions provided around the die pad and each including a first terminal portion; and The second terminal portion is disposed between the die pad and the outer peripheral lead portion, and is separated from the die pad and the outer peripheral lead portion; and a semiconductor element is mounted on the die pad. ; And a connecting member, which electrically connects the semiconductor element and each peripheral lead portion, and electrically connects the semiconductor element and each second terminal portion; and a sealing resin, which connects the die pad and the plurality of The outer peripheral lead portion and the plurality of second terminal portions are sealed with the semiconductor element and the connection member. The plurality of outer peripheral lead portions include a long outer peripheral lead portion in which the first terminal portion is positioned inside. And the short outer peripheral lead portion which places the first terminal portion on the outside in a relative position, and the long outer lead portion and the front portion The short outer peripheral lead portions are alternately arranged, and a recess is formed at a region between the outer peripheral lead portion and the die pad in the back surface of the sealing resin so as to surround the die pad.

本發明，係為一種半導體裝置，其特徵為，係具備有：晶粒墊；和複數之外周導線部，係被設置在前述晶粒墊之周圍，並分別包含有第1端子部；和複數之第2端子部，係被配置在前述晶粒墊和前述外周導線部之間，並從前述晶粒墊以及前述外周導線部而作了分離；和半導體元件，係被搭載於前述晶粒墊上；和連接構件，係將前述半導體元件和各外周導線部作電性連接，並且將前述半導體元件和各第2端子部作電性連接；和密封樹脂，係將前述晶粒墊和前述複數之外周導線部和前述複數之第2端子部和前述半導體元件以及前述連接構件作密封，前述複數之外周導線部，係包含有使前述第1端子部相對性地位置於內側之長外周導線部、和使前述第1端子部相對性地位置於外側之短外周導線部，前述長外周導線部和前述短外周導線部係被交互作配置，在前述密封樹脂的背面中之前述外周導線部與前述晶粒墊之間的區域處，係被形成有凹部。 The present invention relates to a semiconductor device, comprising: a die pad; and a plurality of peripheral lead portions provided around the die pad and each including a first terminal portion; and The second terminal portion is disposed between the die pad and the outer peripheral lead portion, and is separated from the die pad and the outer peripheral lead portion; and a semiconductor element is mounted on the die pad. ; And a connecting member, which electrically connects the semiconductor element and each peripheral lead portion, and electrically connects the semiconductor element and each second terminal portion; and a sealing resin, which connects the die pad and the plurality of The outer peripheral lead portion and the plurality of second terminal portions are sealed with the semiconductor element and the connection member. The plurality of outer peripheral lead portions include a long outer peripheral lead portion in which the first terminal portion is positioned inside. And the short outer peripheral lead portion that places the first terminal portion on the outside in a relative position, and the long outer peripheral lead portion and the short outer peripheral lead portion are arranged alternately in the dense At a region between the periphery of the die pad and the lead portion of the outer back surface of the resin, it is formed with a recessed based portion.

本發明，係為一種導線框架之製造方法，其特徵為，係具備有：準備金屬基板之工程；和藉由對於前述金屬基板進行蝕刻加工，而在前述金屬基板上形成前述晶粒墊、前述外周導線部、前述連接環以及前述內側導線部之工程。 The present invention is a method for manufacturing a lead frame, and is characterized by comprising: a process of preparing a metal substrate; and forming the aforementioned die pad on the aforementioned metal substrate by the etching process of the aforementioned metallic substrate, and the aforementioned Engineering of the outer conductor portion, the connection ring, and the inner conductor portion.

本發明，係為一種半導體裝置之製造方法，其特徵為，係具備有：準備導線框架之工程；和在前述導線框架之前述晶粒墊上搭載前述半導體元件之工程；和將前述半導體元件和各外周導線部藉由連接構件來作電性連接之工程；和將前述晶粒墊和前述複數之外周導線部和前述半導體元件以及前述連接構件藉由密封樹脂來作密封之工程；和藉由從前述導線框架之背面側來將前述連接環之至少一部分除去，而將前述複數之第2端子部分別個別地作分離之工程。 The present invention is a method for manufacturing a semiconductor device, comprising: a process of preparing a lead frame; and a process of mounting the semiconductor element on the die pad of the lead frame; and combining the semiconductor element and each A process of electrically connecting the outer peripheral wire portion by a connecting member; and a process of sealing the die pad and the plurality of outer peripheral wire portions with the semiconductor element and the connecting member by a sealing resin; At least a part of the connection ring is removed from the back side of the lead frame, and the plurality of second terminal portions are individually separated.

本發明，係為一種導線框架之製造方法，其特徵為，係具備有：準備金屬基板之工程；和藉由對於前述金屬基板進行蝕刻加工，而在前述金屬基板上形成前述晶粒墊、前述外周導線部、前述導線連接部以及前述內側導線部之工程。 The present invention is a method for manufacturing a lead frame, and is characterized by comprising: a process of preparing a metal substrate; and forming the aforementioned die pad on the aforementioned metal substrate by the etching process of the aforementioned metallic substrate, and the aforementioned Engineering of the outer lead portion, the lead connection portion, and the inner lead portion.

本發明，係為一種半導體裝置之製造方法，其特徵為，係具備有：準備導線框架之工程；和在前述導線框架之前述晶粒墊上搭載前述半導體元件之工程；和將前述半導體元件和各外周導線部藉由連接構件來作電性連接之工程；和將前述晶粒墊和前述複數之外周導線部和前述半導體元件以及前述連接構件藉由密封樹脂來作密封之工程；和藉由從前述導線框架之背面側來將前述導線連接部之至少一部分除去，而將前述複數之第2端子部分別個別地作分離之工程。 The present invention is a method for manufacturing a semiconductor device, comprising: a process of preparing a lead frame; and a process of mounting the semiconductor element on the die pad of the lead frame; and combining the semiconductor element and each A process of electrically connecting the outer peripheral wire portion by a connecting member; and a process of sealing the die pad and the plurality of outer peripheral wire portions with the semiconductor element and the connecting member by a sealing resin; and At least a part of the lead connection portion is removed from the back side of the lead frame, and the plurality of second terminal portions are individually separated.

若依據本發明，則係能夠將與外部作連接之 端子部的數量(銷數)增加。 According to the present invention, it is possible to connect with the outside The number of terminal portions (number of pins) increases.

本發明，係為一種導線框架，係包含有相互經由支持構件來作了連結的複數之單位導線框架，其特徵為：各單位導線框架，係具備有：晶粒墊，係搭載有半導體元件；和複數之導線部，係被設置於前述晶粒墊之周圍，並分別包含有端子部和從前述端子部起而朝向內側延伸之內導線，前述導線部，係藉由被設置在相鄰接之前述單位導線框架間之前述支持構件而被作支持，前述導線框架，係由具有850MPa~1100MPa之拉張強度的金屬材料所構成，各單位導線框架之前述導線部中的前述支持構件之近旁部分，其寬幅係為75μm~90μm，其厚度係為60μm~75μm。 The present invention is a lead frame, which includes a plurality of unit lead frames connected to each other via a supporting member, and is characterized in that each unit lead frame is provided with: a die pad and a semiconductor element; And a plurality of lead portions are provided around the die pad, and each includes a terminal portion and an inner lead extending from the terminal portion toward the inside, and the lead portion is provided adjacently The support members between the unit lead frames are supported. The lead frames are made of a metal material having a tensile strength of 850 MPa to 1100 MPa. The support members in the lead portions of the unit lead frames are adjacent to the support members. In part, the width is 75 μm to 90 μm, and the thickness is 60 μm to 75 μm.

本發明，係為一種導線框架，其中，前述複數之導線部的前述端子部，係以在相鄰接之前述導線部間而位置在內側以及外側處的方式，來在作平面觀察時而被交互地配置為交錯狀。 The present invention is a lead frame in which the terminal portions of the plurality of lead portions are positioned inside and outside of the lead portions adjacent to each other when viewed in a plane. Interactively arranged in a staggered pattern.

本發明，係為一種導線框架，其中，前述內導線，其厚度係較前述端子部而更薄。 The present invention is a lead frame in which the thickness of the inner lead is thinner than the terminal portion.

本發明，係為一種導線框架，其中，前述導線部，係包含有從前述端子部起而朝向外側延伸之連接導線，前述連接導線，其厚度係較前述端子部而更薄。 The present invention is a lead frame, wherein the lead portion includes a connecting lead extending outward from the terminal portion, and a thickness of the connecting lead is thinner than the terminal portion.

本發明，係為一種導線框架，其中，前述導線部之前述內導線中的前述端子部之近旁部分，其寬幅係為75μm~90μm，其厚度係為60μm~75μm。 The present invention is a lead frame in which the width of the vicinity of the terminal portion of the inner lead of the lead portion is 75 μm to 90 μm, and the thickness is 60 μm to 75 μm.

本發明，係為一種導線框架，其中，前述金屬材料，係身為卡遜系合金(Cu-Ni-Si)、鎳錫銅合金(Cu-Ni-Sn)或者是鈦銅合金(Cu-Ti)。 The present invention relates to a lead frame, in which the aforementioned metal material is a Carson-based alloy (Cu-Ni-Si), a nickel-tin-copper alloy (Cu-Ni-Sn), or a titanium-copper alloy (Cu-Ti ).

本發明，係為一種導線框架，係包含有相互經由支持構件來作了連結的複數之單位導線框架，其特徵為：各單位導線框架，係具備有：晶粒墊，係搭載有半導體元件；和複數之導線部，係被設置於前述晶粒墊之周圍，並分別包含有端子部和從前述端子部起而朝向內側延伸之內導線，前述導線部，係藉由被設置在相鄰接之前述單位導線框架間之前述支持構件而被作支持，前述導線框架，係由具有750MPa~1100MPa之拉張強度的金屬材料所構成，各單位導線框架之前述導線部中的前述支持構件之近旁部分，其寬幅係為60μm~90μm，其厚度係為50μm~75μm。 The present invention is a lead frame, which includes a plurality of unit lead frames connected to each other via a supporting member, and is characterized in that each unit lead frame is provided with: a die pad and a semiconductor element; And a plurality of lead portions are provided around the die pad, and each includes a terminal portion and an inner lead extending from the terminal portion toward the inside, and the lead portion is provided adjacently The support members between the aforementioned unit lead frames are supported. The lead frames are made of a metal material having a tensile strength of 750 MPa to 1100 MPa. The support members in the lead portions of the unit lead frames are near the support members. In part, the width is 60 μm to 90 μm, and the thickness is 50 μm to 75 μm.

本發明，係為一種使用導線框架而製作的半導體裝置，其特徵為，係具備有：前述晶粒墊；和複數之前述導線部，係被設置在前述晶粒墊之周圍，並分別包含有前述端子部和從前述端子部起而朝向內側延伸之前述內導線；和半導體元件，係被搭載於前述晶粒墊上；和連接構件，係將前述半導體元件和各導線部之前述內導線作電性連接；和密封樹脂，係將前述晶粒墊和前述複數之導線部和前述半導體元件以及前述連接構件作密封。 The present invention is a semiconductor device manufactured using a lead frame, and is characterized by comprising: the die pad; and a plurality of the lead portions, which are provided around the die pad and each include The terminal portion and the inner lead extending from the terminal portion to the inside; and a semiconductor element mounted on the die pad; and a connection member for electrically connecting the semiconductor element and the inner lead of each lead portion. And a sealing resin that seals the die pad and the plurality of lead portions, the semiconductor element, and the connection member.

本發明，係為一種導線框架之製造方法，其特徵為：該導線框架，係包含有相互經由支持構件來作了 連結的複數之單位導線框架，各單位導線框架，係具備有：晶粒墊，係搭載有半導體元件；和複數之導線部，係被設置於前述晶粒墊之周圍，並分別包含有端子部和從前述端子部起而朝向內側延伸之內導線，該導線框架之製造方法，係具備有：準備藉由具備850MPa~1100MPa之拉張強度之金屬材料所構成之金屬基板之工程；和藉由對於前述金屬基板進行蝕刻加工，而在前述金屬基板上形成前述晶粒墊以及前述導線部之工程，當在前述金屬基板上形成前述晶粒墊以及前述導線部時，各單位導線框架之前述導線部中的前述支持構件之近旁部分，其寬幅係為75μm~90μm，其厚度係為60μm~75μm。 The present invention is a method for manufacturing a lead frame, which is characterized in that: the lead frame includes A plurality of connected unit lead frames, each unit lead frame, include: a die pad, on which a semiconductor element is mounted; and a plurality of lead portions, which are provided around the die pad and each include a terminal portion And an inner lead extending from the terminal portion to the inside, the method for manufacturing the lead frame includes: preparing a metal substrate made of a metal material having a tensile strength of 850 MPa to 1100 MPa; and In the process of etching the metal substrate and forming the die pad and the lead portion on the metal substrate, when the die pad and the lead portion are formed on the metal substrate, the leads of each unit lead frame are formed. The width of the near part of the support member in the section is 75 μm to 90 μm, and the thickness is 60 μm to 75 μm.

本發明，係為一種導線框架之製造方法，其特徵為：該導線框架，係包含有相互經由支持構件來作了連結的複數之單位導線框架，各單位導線框架，係具備有：晶粒墊，係搭載有半導體元件；和複數之導線部，係被設置於前述晶粒墊之周圍，並分別包含有端子部和從前述端子部起而朝向內側延伸之內導線，該導線框架之製造方法，係具備有：準備藉由具備750MPa~1100MPa之拉張強度之金屬材料所構成之金屬基板之工程；和藉由對於前述金屬基板進行蝕刻加工，而在前述金屬基板上形成前述晶粒墊以及前述導線部之工程，當在前述金屬基板上形成前述晶粒墊以及前述導線部時，各單位導線框架之前述導線部中的前述支持構件之近旁部分，其寬幅係為60μm~90μm，其厚度係為50μm~75μm。 The invention is a method for manufacturing a lead frame, which is characterized in that the lead frame includes a plurality of unit lead frames connected to each other via a supporting member, and each unit lead frame is provided with: a die pad A semiconductor device is mounted; and a plurality of lead portions are provided around the die pad, and each includes a terminal portion and an inner lead extending from the terminal portion toward the inside, and a method for manufacturing the lead frame. It is provided with: a process of preparing a metal substrate made of a metal material having a tensile strength of 750 MPa to 1100 MPa; and forming the aforementioned die pad on the aforementioned metal substrate by performing an etching process on the aforementioned metallic substrate, and In the process of the lead portion, when the die pad and the lead portion are formed on the metal substrate, a width of the support member in the lead portion of each unit lead frame is 60 μm to 90 μm. The thickness is 50 μm to 75 μm.

本發明，係為一種半導體裝置之製造方法，其特徵為，係具備有：藉由導線框架之製造方法來製造導線框架之工程；和在前述導線框架之前述晶粒墊上搭載前述半導體元件之工程；和將前述半導體元件和各導線部之前述內導線藉由連接構件來作電性連接之工程；和將前述晶粒墊和前述複數之導線部和前述半導體元件以及前述連接構件藉由密封樹脂來作密封之工程。 The present invention is a method for manufacturing a semiconductor device, and is characterized by comprising: a process of manufacturing a lead frame by a method of manufacturing a lead frame; and a process of mounting the semiconductor element on the die pad of the lead frame. ; And a process of electrically connecting the semiconductor element and the inner lead of each lead portion by a connecting member; and the die pad and the plurality of lead portions and the semiconductor element and the connecting member by a sealing resin For sealing work.

若依據本發明，則由於係能夠對於導線部之強度降低的情形作抑制，因此係能夠防止在導線部處產生變形的情況，且能夠將相鄰接之導線部彼此的間隔縮窄。 According to the present invention, since the reduction in the strength of the lead portions can be suppressed, deformation of the lead portions can be prevented, and the interval between adjacent lead portions can be narrowed.

本發明，係為一種半導體裝置用之導線框架，其特徵為，係具備有：晶粒墊，係搭載有半導體元件；和複數之導線部，係被設置於前述晶粒墊之周圍，並分別包含有第1端子部和從前述第1端子部起而朝向內側延伸之內導線；和連接環，係被設置在前述內導線之前端側處，並包圍前述晶粒墊，前述連接環，係藉由至少1個的前述內導線而被作支持，沿著前述連接環，而規則性地設置凹部，在各凹部之間，形成有厚壁部。 The present invention is a lead frame for a semiconductor device, which is provided with: a die pad, on which a semiconductor element is mounted; and a plurality of lead portions, which are provided around the die pad and are respectively A first terminal portion and an inner lead extending from the first terminal portion toward the inside are included; and a connection ring is provided at the front end side of the inner lead and surrounds the die pad, the connection ring, and Recesses are supported by at least one of the inner wires, and recesses are regularly provided along the connection ring, and thick-walled portions are formed between the recesses.

若依據本發明，則係能夠防止內導線之變形，並且能夠將與外部作連接之端子部的數量(銷數)增加。 According to the present invention, it is possible to prevent deformation of the inner conductor and increase the number of terminal portions (pins) to be connected to the outside.

10‧‧‧導線框架 10‧‧‧ lead frame

10a‧‧‧單位導線框架 10a‧‧‧Unit lead frame

10A‧‧‧導線框架 10A‧‧‧ lead frame

10B‧‧‧導線框架 10B‧‧‧ lead frame

10C‧‧‧導線框架 10C‧‧‧ lead frame

10D‧‧‧導線框架 10D‧‧‧ lead frame

10E‧‧‧導線框架 10E‧‧‧ lead frame

10F‧‧‧導線框架 10F‧‧‧ lead frame

10G‧‧‧導線框架 10G‧‧‧ lead frame

11‧‧‧晶粒墊 11‧‧‧ die pad

12A‧‧‧長外周導線部 12A‧‧‧Long peripheral wire section

12B‧‧‧短外周導線部 12B‧‧‧Short peripheral wire section

13‧‧‧支持導線 13‧‧‧ Support wire

14‧‧‧連接環 14‧‧‧ connecting ring

14a‧‧‧凹溝 14a‧‧‧Ditch

14b‧‧‧堤部 14b‧‧‧ Embankment

14c‧‧‧凹部 14c‧‧‧Concave

15A‧‧‧內部端子 15A‧‧‧Internal Terminal

15B‧‧‧內部端子 15B‧‧‧Internal Terminal

16‧‧‧懸吊導線 16‧‧‧ Suspended wire

17A‧‧‧內側外部端子 17A‧‧‧Inside external terminal

17B‧‧‧外側外部端子 17B‧‧‧Outside External Terminal

17C‧‧‧外部端子 17C‧‧‧External Terminal

17D‧‧‧外部端子 17D‧‧‧External Terminal

17E‧‧‧外部端子 17E‧‧‧External Terminal

17F‧‧‧外部端子 17F‧‧‧External Terminal

18‧‧‧第2端子部 18‧‧‧ 2nd terminal section

19‧‧‧連結條 19‧‧‧ Link Article

20‧‧‧半導體裝置 20‧‧‧Semiconductor device

20A‧‧‧半導體裝置 20A‧‧‧Semiconductor device

20B‧‧‧半導體裝置 20B‧‧‧Semiconductor device

20D‧‧‧半導體裝置 20D‧‧‧Semiconductor device

20F‧‧‧半導體裝置 20F‧‧‧Semiconductor device

20G‧‧‧半導體裝置 20G‧‧‧Semiconductor device

20H‧‧‧半導體裝置 20H‧‧‧Semiconductor device

21‧‧‧半導體元件 21‧‧‧Semiconductor element

21a‧‧‧電極 21a‧‧‧electrode

22‧‧‧接合打線 22‧‧‧Joint Wire

23‧‧‧密封樹脂 23‧‧‧sealing resin

24‧‧‧接著劑 24‧‧‧ Adhesive

25‧‧‧電鍍部 25‧‧‧Plating Department

26A‧‧‧長內側導線部 26A‧‧‧Long inner wire section

26B‧‧‧短內側導線部 26B‧‧‧Short inner wire section

26C‧‧‧長內側導線部 26C‧‧‧Long inner wire section

26D‧‧‧短內側導線部 26D‧‧‧Short inner wire section

27‧‧‧凹部 27‧‧‧ recess

27a‧‧‧突起部 27a‧‧‧ protrusion

28‧‧‧第2端子部 28‧‧‧ 2nd terminal section

28a‧‧‧厚壁部 28a‧‧‧thick wall

31‧‧‧金屬基板 31‧‧‧ metal substrate

32‧‧‧蝕刻用光阻層 32‧‧‧Photoresist for etching

32a‧‧‧感光性光阻 32a‧‧‧Photoresist

32b‧‧‧開口部 32b‧‧‧ opening

33‧‧‧蝕刻用光阻層 33‧‧‧Photoresist for etching

33a‧‧‧感光性光阻 33a‧‧‧Photoresist

33b‧‧‧開口部 33b‧‧‧ opening

34‧‧‧蝕刻用光阻層 34‧‧‧Photoresist for etching

34a‧‧‧開口部 34a‧‧‧ opening

36‧‧‧加熱塊 36‧‧‧Heating block

51‧‧‧內導線 51‧‧‧Inner wire

52‧‧‧連接導線 52‧‧‧Connecting wire

53‧‧‧第1端子部 53‧‧‧The first terminal

55‧‧‧近旁部分 55‧‧‧ Nearby

56‧‧‧近旁部分 56‧‧‧ Nearby

57‧‧‧連接導線 57‧‧‧ connecting lead

61‧‧‧內導線 61‧‧‧Inner wire

61a‧‧‧傾斜部分 61a‧‧‧inclined

61b‧‧‧直線部分 61b‧‧‧Straight part

62‧‧‧連接導線 62‧‧‧Connecting wire

63‧‧‧端子部 63‧‧‧Terminal

64‧‧‧導線連接部 64‧‧‧Wire connection

65‧‧‧連結部 65‧‧‧Link Department

66‧‧‧連結部 66‧‧‧Connection Department

67‧‧‧凹部 67‧‧‧ Recess

〔圖1〕圖1，係為對於由本發明之第1實施形態所致之導線框架作展示的平面圖。 [Fig. 1] Fig. 1 is a plan view showing a lead frame according to the first embodiment of the present invention.

〔圖2〕圖2，係為對於由本發明之第1實施形態所致之導線框架作展示的底面圖。 [Fig. 2] Fig. 2 is a bottom view showing a lead frame according to the first embodiment of the present invention.

〔圖3〕圖3(a)，係為對於由本發明之第1實施形態所致之導線框架作展示的剖面圖(圖1之IIIA-IIIA線剖面圖)，圖3(b)，係為對於由本發明之第1實施形態所致之導線框架作展示的剖面圖(圖1之IIIB-IIIB線剖面圖)。 [Fig. 3] Fig. 3 (a) is a sectional view showing a lead frame caused by the first embodiment of the present invention (a sectional view taken along the line IIIA-IIIA in Fig. 1), and Fig. 3 (b) is A cross-sectional view showing a lead frame according to the first embodiment of the present invention (a cross-sectional view taken along the line IIIB-IIIB in FIG. 1).

〔圖4〕圖4，係為對於由本發明之第1實施形態所致之半導體裝置作展示的平面圖。 [FIG. 4] FIG. 4 is a plan view showing a semiconductor device according to the first embodiment of the present invention.

〔圖5〕圖5，係為對於由本發明之第1實施形態所致之半導體裝置作展示的剖面圖(圖4之V-V線剖面圖)。 [FIG. 5] FIG. 5 is a sectional view showing a semiconductor device according to the first embodiment of the present invention (a sectional view taken along the line V-V in FIG. 4).

〔圖6〕圖6(a)~(f)，係為對於由本發明之第1實施形態所致之導線框架之製造方法作展示的剖面圖。 [Fig. 6] Figs. 6 (a) to (f) are sectional views showing a method for manufacturing a lead frame according to the first embodiment of the present invention.

〔圖7〕圖7(a)~(f)，係為對於由本發明之第1實施形態所致之半導體裝置之製造方法作展示的剖面圖。 [Fig. 7] Figs. 7 (a) to (f) are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

〔圖8〕圖8，係為對於由本發明之第2實施形態所致之導線框架作展示的平面圖。 [Fig. 8] Fig. 8 is a plan view showing a lead frame according to a second embodiment of the present invention.

〔圖9〕圖9，係為對於由本發明之第2實施形態所致之導線框架作展示的底面圖。 [Fig. 9] Fig. 9 is a bottom view showing a lead frame according to a second embodiment of the present invention.

〔圖10〕圖10(a)，係為對於由本發明之第2實施形態所致之導線框架作展示的剖面圖(圖8之XA-XA線 剖面圖)，圖10(b)，係為對於由本發明之第2實施形態所致之導線框架作展示的剖面圖(圖8之XB-XB線剖面圖)。 [Fig. 10] Fig. 10 (a) is a sectional view showing a lead frame caused by the second embodiment of the present invention (XA-XA line of Fig. 8) (Sectional view), and FIG. 10 (b) are cross-sectional views showing a lead frame according to the second embodiment of the present invention (XB-XB line sectional view of FIG. 8).

〔圖11〕圖11，係為對於由本發明之第2實施形態所致之半導體裝置作展示的平面圖。 [FIG. 11] FIG. 11 is a plan view showing a semiconductor device according to a second embodiment of the present invention.

〔圖12〕圖12，係為對於由本發明之第3實施形態所致之導線框架作展示的平面圖。 [Fig. 12] Fig. 12 is a plan view showing a lead frame according to a third embodiment of the present invention.

〔圖13〕圖13，係為對於由本發明之第3實施形態所致之導線框架作展示的底面圖。 [Fig. 13] Fig. 13 is a bottom view showing a lead frame according to a third embodiment of the present invention.

〔圖14〕圖14(a)，係為對於由本發明之第3實施形態所致之導線框架作展示的剖面圖(圖12之XIVA-XIVA線剖面圖)，圖14(b)，係為對於由本發明之第3實施形態所致之導線框架作展示的剖面圖(圖12之XIVB-XIVB線剖面圖)。 [Fig. 14] Fig. 14 (a) is a cross-sectional view showing a lead frame caused by the third embodiment of the present invention (sectional view taken along the line XIVA-XIVA in Fig. 12), and Fig. 14 (b) is A cross-sectional view showing a lead frame according to the third embodiment of the present invention (XIVB-XIVB line cross-sectional view in FIG. 12).

〔圖15〕圖15，係為對於由本發明之第3實施形態所致之半導體裝置作展示的平面圖。 [FIG. 15] FIG. 15 is a plan view showing a semiconductor device according to a third embodiment of the present invention.

〔圖16〕圖16，係為對於由本發明之第3實施形態所致之半導體裝置作展示的剖面圖(圖15之XVI-XVI線剖面圖)。 [FIG. 16] FIG. 16 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention (XVI-XVI cross-sectional view of FIG. 15).

〔圖17〕圖17，係為對於由本發明之第3實施形態之變形例所致之導線框架作展示的平面圖。 [Fig. 17] Fig. 17 is a plan view showing a lead frame according to a modification of the third embodiment of the present invention.

〔圖18〕圖18，係為對於由本發明之第4實施形態所致之導線框架作展示的平面圖。 [FIG. 18] FIG. 18 is a plan view showing a lead frame according to a fourth embodiment of the present invention.

〔圖19〕圖19，係為對於由本發明之第4實施形態 所致之導線框架作展示的底面圖。 [Fig. 19] Fig. 19 shows a fourth embodiment of the present invention. The resulting bottom view of the lead frame is shown.

〔圖20〕圖20，係為對於由本發明之第4實施形態所致之半導體裝置作展示的平面圖。 [FIG. 20] FIG. 20 is a plan view showing a semiconductor device according to a fourth embodiment of the present invention.

〔圖21〕圖21，係為對於由本發明之第4實施形態之變形例所致之導線框架作展示的平面圖。 [Fig. 21] Fig. 21 is a plan view showing a lead frame according to a modification of the fourth embodiment of the present invention.

〔圖22〕圖22，係為對於由本發明之第5實施形態所致之導線框架作展示的平面圖。 [Fig. 22] Fig. 22 is a plan view showing a lead frame according to a fifth embodiment of the present invention.

〔圖23〕圖23，係為對於由本發明之第5實施形態所致之導線框架作展示的剖面圖(圖22之XXIII-XXIII線剖面圖)。 [FIG. 23] FIG. 23 is a cross-sectional view showing a lead frame according to a fifth embodiment of the present invention (a cross-sectional view taken along line XXIII-XXIII in FIG. 22).

〔圖24〕圖24，係為對於由本發明之第5實施形態所致之導線框架作展示的擴大平面圖(圖22之部分擴大圖)。 [Fig. 24] Fig. 24 is an enlarged plan view showing a lead frame according to a fifth embodiment of the present invention (partial enlarged view of Fig. 22).

〔圖25〕圖25(a)~(b)，係為導線部之剖面圖(分別為圖24之XXVA-XXVA線剖面圖、XXVB-XXVB線剖面圖)。 [Fig. 25] Figs. 25 (a) to (b) are cross-sectional views of the lead portion (the cross-sectional views along the line XXVA-XXVA and the cross-sectional views along the line XXVB-XXVB in Fig. 24).

〔圖26〕圖26(a)~(c)，係為導線部之剖面圖(分別為圖24之XXVIA-XXVIA線剖面圖、XXVIB-XXVIB線剖面圖、XXVIC-XXVIC線剖面圖)。 [Fig. 26] Figs. 26 (a) to (c) are cross-sectional views of the lead wire section (XXVIA-XXVIA line cross-sectional view, XXVIB-XXVIB line cross-sectional view, and XXVIC-XXVIC line cross-sectional view of Fig. 24).

〔圖27〕圖27，係為對於由本發明之第5實施形態所致之半導體裝置作展示的平面圖。 [FIG. 27] FIG. 27 is a plan view showing a semiconductor device according to a fifth embodiment of the present invention.

〔圖28〕圖28，係為對於由本發明之第5實施形態所致之半導體裝置作展示的剖面圖(圖27之XXVIII-XXVIII線剖面圖)。 [FIG. 28] FIG. 28 is a cross-sectional view showing a semiconductor device according to a fifth embodiment of the present invention (cross-sectional view taken along line XXVIII-XXVIII in FIG. 27).

〔圖29〕圖29(a)~(f)，係為對於由本發明之第5實施形態所致之導線框架之製造方法作展示的剖面圖。 [Fig. 29] Figs. 29 (a) to (f) are sectional views showing a method for manufacturing a lead frame according to a fifth embodiment of the present invention.

〔圖30〕圖30(a)~(e)，係為對於由本發明之第5實施形態所致之半導體裝置之製造方法作展示的剖面圖。 [Fig. 30] Figs. 30 (a) to (e) are cross-sectional views showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

〔圖31〕圖31，係為對於由本發明之第6實施形態所致之導線框架作展示的平面圖。 [FIG. 31] FIG. 31 is a plan view showing a lead frame according to a sixth embodiment of the present invention.

〔圖32〕圖32(a)，係為對於由本發明之第5實施形態所致之導線框架作展示的剖面圖(圖31之XXXIIA-XXXIIA線剖面圖)，圖32(b)，係為對於由本發明之第6實施形態所致之導線框架作展示的剖面圖(圖31之XXXIIB-XXXIIB線剖面圖)。 [Fig. 32] Fig. 32 (a) is a cross-sectional view showing a lead frame caused by the fifth embodiment of the present invention (cross-sectional view taken along line XXXIIA-XXXIIA in Fig. 31), and Fig. 32 (b) is A cross-sectional view showing a lead frame according to the sixth embodiment of the present invention (a cross-sectional view taken along line XXXIIB-XXXIIB in FIG. 31).

〔圖33〕圖33，係為對於由本發明之第6實施形態所致之半導體裝置作展示的平面圖。 [Fig. 33] Fig. 33 is a plan view showing a semiconductor device according to a sixth embodiment of the present invention.

〔圖34〕圖34，係為對於由本發明之第6實施形態之變形例所致之半導體裝置作展示的平面圖。 [Fig. 34] Fig. 34 is a plan view showing a semiconductor device according to a modification of the sixth embodiment of the present invention.

〔第1實施形態〕 [First Embodiment]

以下，參考圖1~圖7，對本發明之第1實施形態作說明。另外，在以下之各圖中，針對相同的部份，係附加相同之元件符號，並會有省略一部分之詳細說明的情形。 Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 to 7. In addition, in the following drawings, the same components are denoted by the same reference numerals, and some detailed descriptions may be omitted.

導線框架之構成 The composition of the lead frame

首先，根據圖1~圖3，對由本實施形態所致之導線框架的概略內容作說明。圖1，係為對於由本實施形態所致之導線框架作展示的平面圖，圖2，係為對於由本實施形態所致之導線框架作展示的底面圖。圖3(a)、(b)，係分別為對於由本實施形態所致之導線框架作展示的剖面圖。 First, the outline of the lead frame according to this embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 is a plan view showing a lead frame according to this embodiment, and FIG. 2 is a bottom view showing a lead frame according to this embodiment. 3 (a) and 3 (b) are cross-sectional views showing a lead frame according to this embodiment, respectively.

如圖1~圖3中所示一般，導線框架10，係具備有：晶粒墊11，係搭載有半導體元件21(於後再述)；和複數之細長的外周導線部12A、12B，係被設置於晶粒墊11之周圍，並分別與半導體元件21以及外部電路(未圖示)作連接；和連接環14，係被設置在晶粒墊11和外周導線部12A、12B之間。又，分別具備有第2端子部18之複數之內側導線部26A~26D，係藉由連接環14而被作支持。 As shown in FIG. 1 to FIG. 3, the lead frame 10 generally includes a die pad 11 on which a semiconductor element 21 is mounted (to be described later), and a plurality of elongated outer peripheral lead portions 12A and 12B. It is provided around the die pad 11 and is connected to the semiconductor element 21 and an external circuit (not shown), respectively; and a connection ring 14 is provided between the die pad 11 and the peripheral lead portions 12A and 12B. In addition, a plurality of inner lead portions 26A to 26D each having a second terminal portion 18 are supported by the connection ring 14.

此導線框架10，係包含有分別身為與半導體裝置20(於後再述)相對應之區域的複數之單位導線框架10a。單位導線框架10a，在圖1中係身為位置在假想線之內側處的區域。此些之複數之單位導線框架10a，係經由支持導線(支持構件)13而被相互作連結。此支持導線13，係為支持晶粒墊11和外周導線部12A、12B以及連接環14者，並分別沿著X方向以及垂直於X方向之Y方向而延伸。 The lead frame 10 includes a plurality of unit lead frames 10 a each including an area corresponding to a semiconductor device 20 (to be described later). The unit lead frame 10a is a region located inside the imaginary line in FIG. 1. These plural unit lead frames 10 a are connected to each other via a support lead (support member) 13. The supporting wire 13 is for supporting the die pad 11, the peripheral wire portions 12A and 12B, and the connection ring 14, and extends along the X direction and the Y direction perpendicular to the X direction, respectively.

晶粒墊11，係為平面略矩形狀，其之4邊係沿著X方向或Y方向之其中一者而延伸。又，在晶粒墊11之四角隅處，係被連結有懸吊導線16。而，晶粒墊11，係經由此4根的懸吊導線16而被連結支持於支持導線13處。 The die pad 11 has a substantially rectangular shape in a plane, and four sides thereof extend along one of the X direction and the Y direction. Suspended wires 16 are connected to the four corners of the die pad 11. The die pad 11 is connected to and supported by the support wires 13 through the four suspension wires 16.

又，複數之外周導線部12A、12B，係沿著各單位導線框架10a之外周而設置，並包含有相對性而言為較長之長外周導線部12A、和相對性而言為較短之短外周導線部12B。在本說明書中，係亦將長外周導線部12A和短外周導線部12B總稱為外周導線部12A、12B。以下，針對此種外周導線部12A、12B之構成更進一步作說明。 The plurality of outer peripheral lead portions 12A and 12B are provided along the outer periphery of each unit lead frame 10a, and include a long outer peripheral lead portion 12A which is relatively long and a relatively short one. Short outer periphery lead portion 12B. In this specification, the long outer peripheral lead portion 12A and the short outer peripheral lead portion 12B are collectively referred to as the outer peripheral lead portions 12A and 12B. Hereinafter, the configuration of such outer peripheral lead portions 12A and 12B will be further described.

如圖1~圖3中所示一般，各外周導線部12A、12B，係分別具備有連接導線52和第1端子部53。其中，第1端子部53係於其之表面上具備有內部端子15A。此內部端子15A，係如同後述一般，成為經由接合打線22而被與半導體元件21作電性連接之區域。因此，在內部端子15A上，係設置有用以提昇其與接合打線22之間的密著性之電鍍部25。又，連接導線52，係位置在較第1端子部53而更外側(支持導線13側)處，其之基端部係被連結於支持導線13處。此連接導線52，係相對於該連接導線52所被作連結之支持導線13而垂直地延伸。 As shown in FIGS. 1 to 3, each of the outer peripheral lead portions 12A and 12B is provided with a connection lead 52 and a first terminal portion 53, respectively. The first terminal portion 53 includes an internal terminal 15A on its surface. This internal terminal 15A is a region electrically connected to the semiconductor element 21 via a bonding wire 22 as described later. Therefore, the internal terminal 15A is provided with a plating portion 25 for improving the adhesion between the internal terminal 15A and the bonding wire 22. The connecting lead 52 is positioned further outside (the supporting lead 13 side) than the first terminal portion 53, and the base end portion thereof is connected to the supporting lead 13. The connecting wire 52 extends perpendicularly to the supporting wire 13 to which the connecting wire 52 is connected.

又，如圖3(a)、(b)中所示一般，外周導線部12A、12B之連接導線52，係分別從背面側(與搭載 半導體元件21之面相反側)而藉由半蝕刻來形成為厚度較薄。另一方面，第1端子部53，係並不被作半蝕刻地而具備有與晶粒墊11以及支持導線13相同之厚度。如此這般，藉由使連接導線52之厚度成為較第1端子部53之厚度更薄，係能夠以良好精確度來形成寬幅為窄之外周導線部12A、12B，而能夠得到小型且銷數為多之半導體裝置20。另外，所謂半蝕刻，係指對於被蝕刻材料而一直蝕刻至直到其之厚度方向的途中為止。 As shown in FIGS. 3 (a) and 3 (b), generally, the connecting wires 52 of the outer peripheral wire portions 12A and 12B are respectively connected from the rear side (and The semiconductor element 21 is formed on the side opposite to the surface) and is formed to be thinner by half-etching. On the other hand, the first terminal portion 53 is provided with the same thickness as that of the die pad 11 and the support wire 13 without being semi-etched. In this way, by making the thickness of the connection lead 52 thinner than the thickness of the first terminal portion 53, it is possible to form the outer peripheral lead portions 12A and 12B with a narrow width with good accuracy, and it is possible to obtain a small and pin The number of semiconductor devices 20 is large. In addition, the term "half etching" means that the material to be etched is etched to the middle of its thickness direction.

在各外周導線部12A、12B之第1端子部53的背面，係分別形成有被與外部之安裝基板(未圖示)作電性連接之外部端子17A、17B。各外部端子17A、17B，係在半導體裝置20(於後再述)之製造後，分別成為從半導體裝置20而露出於外部。 External terminals 17A and 17B electrically connected to an external mounting substrate (not shown) are formed on the back surface of the first terminal portion 53 of each of the outer peripheral lead portions 12A and 12B. Each of the external terminals 17A and 17B is exposed from the semiconductor device 20 after being manufactured after the semiconductor device 20 (to be described later).

此些之第1端子部53中的長外周導線部12A之第1端子部53，係相對性地位置於內側(晶粒墊11側)，短外周導線部12B之第1端子部53，係相對性地位置於外側(支持導線13側)。 Among these first terminal portions 53, the first terminal portion 53 of the long outer peripheral lead portion 12A is positioned inside (the die pad 11 side), and the first terminal portion 53 of the short outer peripheral lead portion 12B is The relative position is placed on the outer side (side of the support wire 13).

又，外周導線部12A、12B之外部端子17A、17B，係以在相鄰接之外周導線部12A、12B之間而位置於內側以及外側的方式，來在作平面性觀察時被交互地配置為交錯狀。亦即是，在晶粒墊11之周圍，具有相對性地位置於內側(晶粒墊11側)之外部端子(內側外部端子)17A的長外周導線部12A，和具有相對性地位置於外側(支持導線13側)之外部端子(外側外部端子)17B 的短外周導線部12B，係沿著支持導線13之各邊而被交互作配置。藉由此，就算是在將外周導線部12A和12B作近接設置的情況時，也能夠對於外部端子17A和17B相互接觸的問題作防止。於此情況，外部端子17A以及外部端子17B，係全部具備有相同之平面形狀。 In addition, the external terminals 17A and 17B of the outer peripheral lead portions 12A and 12B are alternately disposed during planar observation when the outer terminals 17A and 17B are adjacently located between the outer peripheral lead portions 12A and 12B. Staggered. That is, around the die pad 11, a long outer peripheral wire portion 12A having an external terminal (inside external terminal) 17A having a relative position on the inside (side of the die pad 11) and a relative position on the outside (Support wire 13 side) external terminal (outside external terminal) 17B The short outer peripheral lead portions 12B are alternately arranged along each side of the support lead 13. With this, even when the outer peripheral lead portions 12A and 12B are provided in close proximity, the problem that the external terminals 17A and 17B contact each other can be prevented. In this case, all of the external terminals 17A and 17B have the same planar shape.

進而，如圖2中所示一般，複數之外部端子17A，係當作平面性觀察時，均為沿著與晶粒墊11之一邊相平行的直線而被配列。同樣的，複數之外部端子17B，係當作平面性觀察時，均為沿著與晶粒墊11之一邊相平行的直線而被配列。亦即是，複數之外部端子17A、17B，係沿著與X方向或者是Y方向之其中一者相平行的直線而被配列成2列。 Further, as shown in FIG. 2, generally, the plurality of external terminals 17A are arranged along a straight line parallel to one side of the die pad 11 when viewed as a flatness. Similarly, the plurality of external terminals 17B are arranged along a straight line parallel to one side of the die pad 11 when viewed as planarity. That is, the plurality of external terminals 17A and 17B are arranged in two rows along a straight line parallel to one of the X direction and the Y direction.

於此情況，相互鄰接之外周導線部12A、12B之間的間隔，係以設為90μm~150μm為理想。如此這般，藉由將外周導線部12A、12B之間的間隔設為90μm以上，係能夠藉由蝕刻而確實地形成相互鄰接之外周導線部12A、12B之間的貫通部分。又，藉由將上述間隔設為150μm以下，係能夠將各半導體裝置20之外部端子17A、17B的數量(銷數)確保有一定數量以上。 In this case, the interval between the outer peripheral lead portions 12A and 12B adjacent to each other is preferably set to 90 μm to 150 μm. As described above, by setting the interval between the outer peripheral lead portions 12A and 12B to 90 μm or more, it is possible to reliably form a through portion between the outer peripheral lead portions 12A and 12B adjacent to each other by etching. In addition, by setting the interval to 150 μm or less, the number (pin number) of the external terminals 17A and 17B of each semiconductor device 20 can be secured to a certain number or more.

接著，針對連接環14以及內側導線部26A~26D之構成作說明。 Next, the configuration of the connection ring 14 and the inner lead portions 26A to 26D will be described.

如圖1以及圖2中所示一般，連接環14，係在外周導線部12A、12B之前端側處，以包圍晶粒墊11的方式而被作配置。此連接環14，係作為全體而具備有 略矩形形狀，其之各邊係沿著X方向或Y方向而延伸。在連接環14之四角隅處，係分別被連接有懸吊導線16，連接環14，係經由4根的懸吊導線16而被支持於支持導線13處。 As shown in FIG. 1 and FIG. 2, the connection ring 14 is generally arranged at the front end side of the outer peripheral lead portions 12A and 12B so as to surround the die pad 11. The connecting ring 14 is provided as a whole. Slightly rectangular shape, each side of which extends along the X or Y direction. Suspension wires 16 are connected to the four corners of the connection ring 14 respectively, and the connection ring 14 is supported by the support wires 13 via the four suspension wires 16.

在連接環14之表面上，係沿著連接環14之長邊方向而被形成有凹溝14a。此凹溝14a，係為藉由半蝕刻所形成者，而在厚度方向上並不被作貫通地來具有一定之深度。又，凹溝14a，係被形成於連接環14之寬幅方向略中央部處，在凹溝14a之寬幅方向兩側處，係被形成有並未被作半蝕刻之堤部14b。於此情況，連接環14之與長邊方向相垂直的剖面，係成為略凹字形狀或略U字形狀。另外，在本實施形態中，凹溝14a，係被形成於連接環14之全周的除了四角隅以外之處，但是，係並不被限定於此，例如，亦可包含有連接環14之四角隅地而涵蓋全周來作設置。又，係亦可構成為：在連接環14處係並未被設置有凹溝14a，而使連接環14之全體維持為金屬基板之板厚的狀態。 A groove 14 a is formed on the surface of the connection ring 14 along the longitudinal direction of the connection ring 14. The groove 14a is formed by half-etching, and has a certain depth without being penetrated in the thickness direction. Further, the groove 14a is formed at a slightly central portion in the width direction of the connection ring 14, and at both sides in the width direction of the groove 14a, a bank portion 14b which is not semi-etched is formed. In this case, the cross-section of the connecting ring 14 perpendicular to the long-side direction is formed into a slightly concave shape or a slightly U-shape. In addition, in the present embodiment, the grooves 14a are formed on the entire circumference of the connecting ring 14 except for the four corners. However, the system is not limited to this. For example, the grooves 14a may be included in the connecting ring 14. Set around the corners and cover the whole week. In addition, the system may be configured such that the groove 14 a is not provided at the connection ring 14, and the entire connection ring 14 is maintained in a state of a plate thickness of the metal substrate.

藉由如此這般而設置凹溝14a，由於連接環14之體積係減少，因此，如同後述一般，在將複數之第2端子部18個別地分離時，係成為易於將連接環14藉由蝕刻來除去。 By providing the grooves 14a in this way, the volume of the connection ring 14 is reduced. Therefore, as described later, when the plurality of second terminal portions 18 are individually separated, it becomes easy to etch the connection ring 14 by etching. To remove.

另一方面，從連接環14，係分別延伸出複數之內側導線部26A~26D。此些之複數之內側導線部26A~26D，係包含有相對性而言為較長之長內側導線部 26A、26C，和相對性而言為較短之短內側導線部26B、26D。在本說明書中，係亦將長內側導線部26A、26C和短內側導線部26B、26D總稱為內側導線部26A~26D。 On the other hand, a plurality of inner lead portions 26A to 26D are respectively extended from the connection ring 14. These plural inner lead portions 26A to 26D include relatively long inner lead portions. 26A and 26C are relatively short short inner lead portions 26B and 26D. In this specification, the long inner lead portions 26A and 26C and the short inner lead portions 26B and 26D are collectively referred to as inner lead portions 26A to 26D.

各內側導線部26A~26D，係分別於其前端處具備有第2端子部18。第2端子部18，係如同後述一般，為經由接合打線22而被與半導體元件21作電性連接者。 Each of the inner lead portions 26A to 26D is provided with a second terminal portion 18 at a front end thereof. The second terminal portion 18 is, as described later, electrically connected to the semiconductor element 21 via the bonding wire 22.

又，複數之第2端子部18，係沿著連接環14而相互空出有間隔地被作配列，並分別被連結支持於連接環14處。此第2端子部18，係如同後述一般，在製作半導體裝置20時，於將連接環14除去之後，被相互個別地分離。亦即是，各第2端子部18，於將連接環14除去之後，係成為會與晶粒墊11、連接環14以及其他之第2端子部18之全部均相互分離。 In addition, the plurality of second terminal portions 18 are arranged along the connection ring 14 with a gap therebetween, and are respectively supported and supported at the connection ring 14. The second terminal portions 18 are separated from each other individually after the connection ring 14 is removed when the semiconductor device 20 is manufactured, as described later. That is, each of the second terminal portions 18 is separated from all of the die pad 11, the connection ring 14, and the other second terminal portions 18 after the connection ring 14 is removed.

此些之複數之第2端子部18中的長內側導線部26A、26C之第2端子部18，係相對性地位置於從連接環14而分離了的部份處，短內側導線部26B、26D之第2端子部18，係相對性地位置於與連接環14相接近之部分處。 Among the plurality of second inner terminal portions 18, the second inner terminal portions 18 of the long inner lead portions 26A and 26C are relatively positioned at portions separated from the connection ring 14, and the short inner lead portions 26B, The second terminal portion 18 of 26D is positioned relative to the connecting ring 14 at a relative position.

又，複數之內側導線部26A~26D中的長內側導線部26A和短內側導線部26B，係分別從連接環14之外側(支持導線13側)而延伸。此些之長內側導線部26A和短內側導線部26B，係在連接環14之外側處而被交互作配置。 The long inner wire portion 26A and the short inner wire portion 26B of the plurality of inner wire portions 26A to 26D extend from the outer side of the connection ring 14 (the supporting wire 13 side), respectively. These long inner lead portions 26A and short inner lead portions 26B are arranged alternately at the outer side of the connection ring 14.

另一方面，長內側導線部26C和短內側導線部26D，係分別從連接環14之內側(晶粒墊11側)而延伸。此些之長內側導線部26C和短內側導線部26D，係在連接環14之內側處而被交互作配置。 On the other hand, the long inner lead portion 26C and the short inner lead portion 26D are respectively extended from the inner side (the die pad 11 side) of the connection ring 14. These long inner lead portions 26C and short inner lead portions 26D are alternately arranged at the inner side of the connection ring 14.

如圖3(a)中所示一般，各內側導線部26A~26D，係分別具備有被與連接環14作連結之連接導線57，各連接導線57，係從背面側起而作了厚度薄化。如此這般，藉由將各內側導線部26A~26D之連接導線57作了厚度薄化，在藉由密封樹脂23而作了樹脂密封之後，密封樹脂23係從背面側起而朝向連接導線57作進入(參考圖5)。藉由此，在將連接環14藉由蝕刻而作了除去之後，係能夠對於第2端子部18脫落至背面側之問題作防止。 As shown in FIG. 3 (a), generally, each of the inner lead portions 26A to 26D is provided with a connecting lead 57 connected to the connecting ring 14, and each connecting lead 57 is thin from the back side. Into. In this way, the connecting lead 57 of each of the inner lead portions 26A to 26D is reduced in thickness, and after the resin is sealed by the sealing resin 23, the sealing resin 23 is directed from the back side toward the connecting lead 57. Enter (refer to Figure 5). Accordingly, after the connection ring 14 is removed by etching, the problem that the second terminal portion 18 falls off to the back side can be prevented.

又，各第2端子部18，係具備有被設置在表面側之內部端子15B、和被設置在背面側之外部端子17C~17F。其中，內部端子15B，係為經由接合打線22而被與半導體元件21作電性連接者。另外，在內部端子15B上，係與內部端子15A相同的，設置有用以提昇其與接合打線22之間的密著性之電鍍部25。又，外部端子17C~17F，係為被與外部之安裝基板(未圖示)作電性連接者，並分別被設置在內側導線部26A~26D之前端處。 Each second terminal portion 18 includes an internal terminal 15B provided on the front side and external terminals 17C to 17F provided on the back side. Among them, the internal terminal 15B is a person who is electrically connected to the semiconductor element 21 via a bonding wire 22. In addition, the internal terminal 15B is the same as the internal terminal 15A, and a plating portion 25 is provided to improve the adhesion between the internal terminal 15B and the bonding wire 22. The external terminals 17C to 17F are electrically connected to an external mounting substrate (not shown), and are provided at the front ends of the inner lead portions 26A to 26D, respectively.

如圖2中所示一般，位置在連接環14之外側(支持導線13側)處的內側導線部26A、26B之外部端子17C、17D，係以在相鄰接之內側導線部26A、26B之 間而位置於內側以及外側的方式，來在作平面性觀察時被交互地配置為交錯狀。亦即是，在晶粒墊11之周圍，相對性地位置於內側(晶粒墊11側)之外部端子17D，和相對性地位置於外側(支持導線13側)之外部端子17C，係沿著連接環14之各邊而被交互作配置。藉由此，就算是在將內側導線部26A和26B作近接設置的情況時，也能夠對於外部端子17C和17D相互接觸的問題作防止。 As shown in FIG. 2, generally, the external terminals 17C, 17D of the inner lead portions 26A, 26B located at the outer side of the connection ring 14 (side of the support lead 13) are connected to the inner lead portions 26A, 26B adjacent to each other. The method of locating on the inside and outside is alternately arranged in a staggered pattern when viewed in a plane. That is, around the die pad 11, the external terminal 17D with the relative position on the inside (the die pad 11 side) and the external terminal 17C with the relative position on the outside (the support wire 13 side) are along the Configurations are interactively directed towards each side of the connection ring 14. With this, even when the inner lead portions 26A and 26B are provided in close proximity, the problem that the external terminals 17C and 17D contact each other can be prevented.

同樣的，位置在連接環14之內側(晶粒墊11側)處的內側導線部26C、26D之外部端子17E、17F，係以在相鄰接之內側導線部26C、26D之間而位置於內側以及外側的方式，來在作平面性觀察時被交互地配置為交錯狀。亦即是，在晶粒墊11之周圍，相對性地位置於內側(晶粒墊11側)之外部端子17E，和相對性地位置於外側(支持導線13側)之外部端子17F，係沿著連接環14之各邊而被交互作配置。藉由此，就算是在將內側導線部26C和26D作近接設置的情況時，也能夠對於外部端子17E和17F相互接觸的問題作防止。 Similarly, the external terminals 17E and 17F of the inner lead portions 26C and 26D at the inner side of the connection ring 14 (on the die pad 11 side) are positioned between the adjacent inner lead portions 26C and 26D. The inner and outer modes are alternately arranged in a staggered pattern during planar observation. That is, around the die pad 11, the external terminal 17E with the relative position on the inside (the die pad 11 side) and the external terminal 17F with the relative position on the outside (the support wire 13 side) are along Configurations are interactively directed towards each side of the connection ring 14. With this, even when the inner lead portions 26C and 26D are provided in close proximity, the problem that the external terminals 17E and 17F contact each other can be prevented.

上述之複數之外部端子17C~17F，係當作平面性觀察時，均為沿著與晶粒墊11之一邊相平行的直線而被配列。亦即是，複數之外部端子17C~17F，係沿著與X方向或者是Y方向之其中一者相平行的直線而被配列成4列。 The plurality of external terminals 17C to 17F described above are arranged along a straight line parallel to one side of the die pad 11 when viewed as a flatness. That is, the plurality of external terminals 17C to 17F are arranged in four rows along a straight line parallel to one of the X direction or the Y direction.

又，從連接環14之外側而延伸之短內側導線 部26B、和長外周導線部12A，係相互對向，從連接環14之外側而延伸之長內側導線部26A、和短外周導線部12B，係相互對向。藉由此，係能夠確保外部端子17A和外部端子17D之間的端子間距離、以及外部端子17B和外部端子17C之間的端子間距離，而能夠對於此些之端子彼此相互接觸的問題作防止。 Also, a short inner wire extending from the outside of the connection ring 14 The portion 26B and the long outer peripheral lead portion 12A face each other, and the long inner lead portion 26A and the short outer lead portion 12B extending from the outside of the connection ring 14 face each other. As a result, the distance between the terminals between the external terminals 17A and 17D and the distance between the terminals between the external terminals 17B and 17C can be ensured, and the problem that these terminals contact each other can be prevented. .

以上所說明了的導線框架10，作為全體，係由銅、銅合金、42合金(Ni42%之Fe合金)等的金屬所構成。又，導線框架10之厚度，雖亦係依存於所製造之半導體裝置20的構成，但是係可設為80μm~250μm。又，導線框架10，較理想，係由具備有750Mpa~1100Mpa之拉張強度的金屬材料所構成。在如同本實施形態一般之多銷構造之導線框架10中，係有必要將導線部12A、12B、26A~26D設為較先前技術者而更細，但是，藉由以上述一般之金屬來製作導線框架，係能夠得到具備有就算是細也難以變形之導線部12A、12B、26A~26D之導線框架10。 The lead frame 10 described above is composed of metals such as copper, copper alloy, and 42 alloy (Fe alloy of 42% Ni) as a whole. The thickness of the lead frame 10 depends on the structure of the semiconductor device 20 to be manufactured, but it can be set to 80 μm to 250 μm. The lead frame 10 is preferably made of a metal material having a tensile strength of 750 MPa to 1100 MPa. In the lead frame 10 having a multi-pin structure as in this embodiment, it is necessary to make the lead portions 12A, 12B, 26A to 26D thinner than those of the prior art. However, the lead frame 10 is made of the general metal described above. The lead frame is a lead frame 10 having lead portions 12A, 12B, 26A to 26D that are difficult to deform even if thin.

另外，在圖1中，外周導線部12A、12B以及內側導線部26A~26D，雖係分別沿著晶粒墊11之4邊的全部而被作配置，但是，係並不被限定於此，例如，係亦可僅沿著晶粒墊11之相對向的2邊來作配置。又，內側導線部26A~26D，雖係從連接環14之外側(支持導線13側)以及內側(晶粒墊11側)的雙方而延伸，但是，係並不被限定於此，亦可僅從連接環14之外側或內側的 其中一方來延伸。 In addition, in FIG. 1, the outer peripheral lead portions 12A and 12B and the inner lead portions 26A to 26D are arranged along all four sides of the die pad 11, but the system is not limited to this. For example, it may be arranged only along two opposite sides of the die pad 11. The inner lead portions 26A to 26D extend from both the outer side of the connection ring 14 (supporting the lead 13 side) and the inner side (the die pad 11 side). However, the inner lead portions 26A to 26D are not limited to this, and may be only From outside or inside of the connecting ring 14 One of them to extend.

半導體裝置之構成 Structure of a semiconductor device

接著，根據圖4以及圖5，對由本實施形態所致之半導體裝置作說明。圖4以及圖5係為對於由本實施形態所致之半導體裝置(DR-QFN(Dual Row QFN)型態)作展示之圖。 Next, a semiconductor device according to this embodiment will be described with reference to FIGS. 4 and 5. 4 and 5 are diagrams showing a semiconductor device (DR-QFN (Dual Row QFN) type) according to this embodiment.

如圖4以及圖5中所示一般，半導體裝置(半導體封裝)20，係具備有：晶粒墊11、和被配置在晶粒墊11之周圍的複數之外周導線部12A、12B、和被配置在晶粒墊11與外周導線部12A、12B之間之複數之第2端子部18。其中，在晶粒墊11上，係搭載有半導體元件21，半導體元件21和各外周導線部12A、12B之第1端子部53以及各內側導線部26A~26D之第2端子部18，係分別藉由接合打線(連接構件)22而被作電性連接。又，晶粒墊11、外周導線部12A、12B、第2端子部18、半導體元件21以及接合打線22，係藉由密封樹脂23而被作樹脂密封。 As shown in FIGS. 4 and 5, generally, a semiconductor device (semiconductor package) 20 includes a die pad 11, a plurality of outer peripheral lead portions 12A, 12B, and a die pad 11 arranged around the die pad 11. A plurality of second terminal portions 18 are arranged between the die pad 11 and the outer peripheral lead portions 12A and 12B. Among them, the die pad 11 is mounted with the semiconductor element 21, the semiconductor element 21, the first terminal portion 53 of each of the outer peripheral lead portions 12A and 12B, and the second terminal portion 18 of each of the inner lead portions 26A to 26D, respectively. It is electrically connected by bonding wires (connecting members) 22. The die pad 11, the peripheral lead portions 12A and 12B, the second terminal portion 18, the semiconductor element 21, and the bonding wire 22 are resin-sealed by a sealing resin 23.

其中，晶粒墊11、外周導線部12A、12B以及內側導線部26A~26D，係為從上述之導線框架10所製作者。此晶粒墊11、外周導線部12A、12B以及內側導線部26A~26D之構成，除了並不被包含於單位導線框架10a中的區域以外，係為與上述之圖1~圖3中所示者略相同，於此係省略詳細之說明。 Among them, the die pad 11, the outer lead portions 12A, 12B, and the inner lead portions 26A to 26D are made from the lead frame 10 described above. The structure of the die pad 11, the peripheral lead portions 12A, 12B, and the inner lead portions 26A to 26D is the same as that shown in Figs. 1 to 3 except that the areas are not included in the unit lead frame 10a. They are slightly the same, and detailed descriptions are omitted here.

另一方面，上述之連接環14，係在藉由密封樹脂23而被作了樹脂密封之後，從背面側起來藉由蝕刻而除去。因此，如同圖4以及圖5中所示一般，各內側導線部26A~26D之第2端子部18，係從晶粒墊11、外周導線部12A、12B以及其他之第2端子部18而分離，並與此些之構件相互電性獨立。 On the other hand, the above-mentioned connection ring 14 is removed from the back side by etching after being resin-sealed by the sealing resin 23. Therefore, as shown in FIGS. 4 and 5, the second terminal portion 18 of each of the inner lead portions 26A to 26D is separated from the die pad 11, the peripheral lead portions 12A and 12B, and the other second terminal portions 18. , And these components are electrically independent of each other.

如此這般，伴隨著連接環14被除去一事，在密封樹脂23之背面中的外周導線部12A、12B和晶粒墊11之間之內側導線部26A、26B與內側導線部26C、26D之間的區域處，係被形成有凹部27。此凹部27，係概略與連接環14之形狀相對應，並以包圍晶粒墊11的方式而具備有平面矩形形狀。另外，在凹部27內，係突出有由密封樹脂23之一部分所成的突起部27a(參考圖5)。此突起部27a，係具備有與上述之連接環14之凹溝14a相對應的形狀。另外，在凹部27中，係亦可填充有與密封樹脂23相同或者是相異種類之絕緣性樹脂。 As such, with the connection ring 14 removed, the inner lead portions 26A and 26B and the inner lead portions 26C and 26D between the outer lead portions 12A and 12B and the die pad 11 in the back surface of the sealing resin 23 In the region, a recess 27 is formed. The recessed portion 27 roughly corresponds to the shape of the connection ring 14 and has a planar rectangular shape so as to surround the die pad 11. In addition, in the recessed portion 27, a protruding portion 27a made of a part of the sealing resin 23 is projected (see FIG. 5). The protruding portion 27a has a shape corresponding to the groove 14a of the connection ring 14 described above. The recess 27 may be filled with an insulating resin that is the same as or different from the sealing resin 23.

另一方面，作為半導體元件21，係可使用在先前技術中所一般使用之各種半導體元件，而並未特別限定，但是，例如係可使用積體電路、大規模積體電路、電晶體、閘流體、二極體等。此半導體元件21，係具備分別被安裝有接合打線22之複數之電極21a。又，半導體元件21，例如係藉由黏晶糊等之接著劑24而被固定在晶粒墊11之表面上。 On the other hand, as the semiconductor element 21, various semiconductor elements generally used in the prior art can be used without particular limitation, but, for example, integrated circuits, large-scale integrated circuits, transistors, and gates can be used. Fluids, diodes, etc. This semiconductor element 21 is provided with a plurality of electrodes 21 a to which bonding wires 22 are respectively mounted. The semiconductor element 21 is fixed to the surface of the die pad 11 by an adhesive 24 such as a paste.

各接合打線22，例如係由金、銅等之導電性 為佳的材料所成。各接合打線22，係分別使其之其中一端與半導體元件21之電極21a相連接，並且使其之另外一端分別與各外周導線部12A、12B之內部端子15A或者是第2端子部18之內部端子15B作連接。另外，在內部端子15A、15B處，係分別設置有用以提昇其與接合打線22之間的密著性之電鍍部25。 Each bonding wire 22 is made of, for example, a conductive material such as gold or copper. Made of better materials. Each bonding wire 22 has its one end connected to the electrode 21a of the semiconductor element 21, and the other end thereof is respectively connected to the internal terminal 15A or the second terminal portion 18 of each of the outer peripheral lead portions 12A and 12B. Terminal 15B is connected. In addition, at the internal terminals 15A and 15B, plating portions 25 are provided to improve the adhesion between the internal terminals 15A and 15B, respectively.

作為密封樹脂23，係可使用矽酮樹脂或環氧樹脂等之熱硬化性樹脂，或者是使用PPS樹脂等之熱可塑性樹脂。密封樹脂23全體之厚度，係可設為500μm~1000μm程度。另外，在圖4中，係將位置在較晶粒墊11、外周導線部12A、12B以及內側導線部26A~26D而更表面側的密封樹脂23之標示作省略。 As the sealing resin 23, a thermosetting resin such as a silicone resin or an epoxy resin, or a thermoplastic resin using a PPS resin or the like can be used. The thickness of the entire sealing resin 23 can be set to approximately 500 μm to 1000 μm. In addition, in FIG. 4, the indication of the sealing resin 23 on the surface side of the die pad 11, the outer peripheral lead portions 12A and 12B, and the inner lead portions 26A to 26D is omitted.

另外，半導體裝置20之一邊，例如係可設為8mm~16mm。 In addition, one side of the semiconductor device 20 may be, for example, 8 mm to 16 mm.

導線框架之製造方法 Method for manufacturing lead frame

接下來，針對圖1乃至圖3中所示之導線框架10之製造方法，使用圖6(a)~(f)來作說明。另外，圖6(a)~(f)，係為對於導線框架10之製造方法作展示的剖面圖(與圖3(b)相對應之圖)。 Next, the manufacturing method of the lead frame 10 shown in FIGS. 1 to 3 will be described using FIGS. 6 (a) to (f). 6 (a) to (f) are cross-sectional views showing a method for manufacturing the lead frame 10 (a view corresponding to FIG. 3 (b)).

首先，係如同圖6(a)中所示一般，準備平板狀之金屬基板31。作為此金屬基板31，係可使用由銅、銅合金、42合金(Ni42%之Fe合金)等的金屬所成之基板。另外，金屬基板31，較理想，係使用對於其之 兩面而進行脫脂等並施加了洗淨處理者。 First, as shown in FIG. 6 (a), a flat metal substrate 31 is prepared. As the metal substrate 31, a substrate made of a metal such as copper, a copper alloy, or a 42 alloy (Ni42% Fe alloy) can be used. In addition, the metal substrate 31 is preferably used for the purpose. A person who performs degreasing and the like on both sides and applies a washing treatment.

接著，在金屬基板31之表背面全體，分別塗布感光性光阻32a、33a，並使其乾燥(圖6(b))。另外，作為感光性光阻32a、33a，係可使用先前技術所公知之物。 Next, the entire surface of the metal substrate 31 is coated with photosensitive resists 32a and 33a and dried (FIG. 6 (b)). In addition, as the photosensitive resists 32a and 33a, those known in the prior art can be used.

接著，隔著光罩來對此金屬基板31進行曝光並進行顯像，藉由此，來形成具備有所期望之開口部32b、33b之蝕刻用光阻層32、33(圖6(c))。 Next, the metal substrate 31 is exposed and developed through a photomask, thereby forming photoresist layers 32 and 33 for etching having desired openings 32b and 33b (FIG. 6 (c)). ).

接著，將蝕刻用光阻層32、33作為耐腐蝕膜，而藉由腐蝕液來對於金屬基板31施加蝕刻(圖6(d))。藉由此，係形成晶粒墊11、複數之外周導線部12A、12B、連接環14以及複數之內側導線部26A~26D的外形。腐蝕液，係可因應於所使用之金屬基板31的材質來適宜作選擇，例如，當作為金屬基板31而使用銅合金的情況時，通常，係可使用氯化鐵水溶液，並從金屬基板31之兩面起來藉由噴霧蝕刻而進行之。 Next, the photoresist layers 32 and 33 for etching are used as corrosion-resistant films, and the metal substrate 31 is etched with an etching solution (FIG. 6 (d)). As a result, the outer shape of the die pad 11, the plurality of outer peripheral lead portions 12A, 12B, the connection ring 14, and the plurality of inner lead portions 26A to 26D are formed. The etchant can be appropriately selected according to the material of the metal substrate 31 to be used. For example, when a copper alloy is used as the metal substrate 31, in general, an aqueous ferric chloride solution can be used. Both sides are made by spray etching.

之後，將蝕刻用光阻層32、33剝離並除去(圖6(e))。 Thereafter, the photoresist layers 32 and 33 for etching are peeled and removed (FIG. 6 (e)).

另外，在上述內容中，雖係以從金屬基板31之兩面側來進行噴霧蝕刻的情況為例來作了說明，但是，係並不被限定於此。例如，係亦可對於金屬基板31而一次一面地來進行2個階段之噴霧蝕刻。具體而言，首先，係形成具有特定之圖案的蝕刻用光阻層32、33(參考圖6(c))，之後，在金屬基板31之背面側，設置具有耐蝕 刻性之密封層(未圖示)，並在此狀態下而僅對於金屬基板31之表面側實施蝕刻。接著，將該背面側之密封層剝離，並在金屬基板31之表面上設置密封層(未圖示)。此時，表面側之密封層，係亦會進入至被作了蝕刻加工的金屬基板31之表面側的凹部內。接著，僅對於金屬基板31之作了露出的背面進行蝕刻，之後，將表面側之密封層剝離，藉由此，而形成晶粒墊11、複數之外周導線部12A、12B、連接環14以及複數之內側導線部26A~26D的外形。藉由如此這般地對於金屬基板31而一次一面地進行噴霧蝕刻，係可得到下述之效果：亦即是，係容易避免發生外周導線部12A、12B以及內側導線部26A~26D之變形。 In the above description, the case where spray etching is performed from both sides of the metal substrate 31 has been described as an example, but the system is not limited to this. For example, the metal substrate 31 may be spray-etched in two stages one at a time. Specifically, first, photoresist layers 32 and 33 for etching having a specific pattern are formed (refer to FIG. 6 (c)), and then, a corrosion resistance is provided on the back surface side of the metal substrate 31. A etched sealing layer (not shown) is etched only in the surface side of the metal substrate 31 in this state. Next, the sealing layer on the back side is peeled off, and a sealing layer (not shown) is provided on the surface of the metal substrate 31. At this time, the sealing layer on the surface side also enters the recessed portion on the surface side of the metal substrate 31 subjected to the etching process. Next, only the exposed back surface of the metal substrate 31 is etched, and then the sealing layer on the front side is peeled off, thereby forming the die pad 11, the plurality of outer peripheral lead portions 12A, 12B, the connection ring 14, and The outer shape of the plurality of inner lead portions 26A to 26D. By performing spray etching on the metal substrate 31 one at a time as described above, the following effects can be obtained: that is, it is easy to avoid deformation of the outer peripheral lead portions 12A and 12B and the inner lead portions 26A to 26D.

接著，為了將接合打線22和各內部端子15A、15B之間的密著性提昇，而對於各內部端子15A、15B分別施加電鍍處理，並形成電鍍部25(圖6(f))。於此情況，所選擇之電鍍種，只要是能夠確保有與接合打線22之間的密著性者，則係並不對其之種類作限定，但是，例如，係可為Ag或Au等之單層電鍍，亦可為將Ni/Pd或者是Ni/Pd/Au依此順序來作了層積的複數層電鍍。又，電鍍部25，係可僅對於外周導線部12A、12B以及內側導線部26A~26D中之與接合打線22之間的連接部作施加，亦可對於導線框架10之全面作施加。 Next, in order to improve the adhesion between the bonding wire 22 and each of the internal terminals 15A and 15B, a plating process is applied to each of the internal terminals 15A and 15B to form a plating portion 25 (FIG. 6 (f)). In this case, as long as the selected plating type can ensure the adhesion with the bonding wire 22, the type is not limited, but, for example, it can be Ag or Au, etc. The layer plating may be a plurality of layers of Ni / Pd or Ni / Pd / Au laminated in this order. The plating portion 25 may be applied only to the connection portions between the outer lead portions 12A and 12B and the inner lead portions 26A to 26D and the bonding wires 22, and may be applied to the entire lead frame 10.

如此這般，而能夠得到如圖1~圖3中所示之 導線框架10。 In this way, we can get as shown in Figure 1 ~ 3 Lead frame 10.

半導體裝置之製造方法 Manufacturing method of semiconductor device

接下來，針對圖4以及圖5中所示之半導體裝置20之製造方法，使用圖7(a)~(f)來作說明。圖7(a)~(f)，係為對於半導體裝置20之製造方法作展示的剖面圖(與圖5相對應之圖)。 Next, the manufacturing method of the semiconductor device 20 shown in FIGS. 4 and 5 will be described using FIGS. 7 (a) to (f). FIGS. 7 (a) to (f) are cross-sectional views showing a method of manufacturing the semiconductor device 20 (views corresponding to FIG. 5).

首先，例如藉由圖6(a)~(f)中所示之方法(如上所述)，來製作導線框架10。 First, for example, the lead frame 10 is manufactured by the method shown in FIGS. 6 (a) to (f) (as described above).

接著，在導線框架10之晶粒墊11上，搭載半導體元件21。於此情況，例如係使用黏晶糊等之接著劑24，而將半導體元件21載置在晶粒墊11上並作固定(黏晶工程)(圖7(a))。 Next, a semiconductor element 21 is mounted on the die pad 11 of the lead frame 10. In this case, for example, an adhesive 24 such as a sticky paste is used, and the semiconductor element 21 is placed on the die pad 11 and fixed (sticky process) (FIG. 7 (a)).

接著，將半導體元件21之各電極21a和各外周導線部12A、12B之電鍍部25(內部端子15A)分別藉由接合打線(連接構件)22而相互作電性連接。同樣的，將半導體元件21之各電極21a和各內側導線部26A~26D之電鍍部25(內部端子15B)分別藉由接合打線(連接構件)22而相互作電性連接(打線接合工程)(圖7(b))。 Next, the electrodes 21a of the semiconductor element 21 and the plating portions 25 (internal terminals 15A) of the outer peripheral lead portions 12A and 12B are electrically connected to each other by bonding wires (connecting members) 22, respectively. Similarly, the electrodes 21a of the semiconductor element 21 and the plating portions 25 (internal terminals 15B) of the inner lead portions 26A to 26D are electrically connected to each other by bonding wires (connecting members) 22 (wire bonding process) ( Figure 7 (b)).

此時，係將導線框架10載置在打線接合裝置之加熱塊36上。接著，藉由加熱塊36，來對於各外周導線部12A、12B以及各內側導線部26A~26D而從該些之背面側來進行加熱。與此同時地，一面經由打線接合裝置之毛細管(未圖示)來施加超音波，一面將半導體元件 21之各電極21a和各外周導線部12A、12B以及各內側導線部26A~26D之電鍍部25分別使用接合打線22而作電性連接。 At this time, the lead frame 10 is placed on the heating block 36 of the wire bonding device. Next, each of the outer peripheral lead portions 12A and 12B and each of the inner lead portions 26A to 26D are heated by the heating block 36 from the back side. At the same time, a semiconductor element was applied while applying an ultrasonic wave through a capillary (not shown) of a wire bonding device. The electrodes 21a of 21 and the plating portions 25 of the outer peripheral lead portions 12A and 12B and the inner lead portions 26A to 26D are electrically connected using bonding wires 22, respectively.

接著，藉由對於導線框架10而將熱硬化性樹脂或熱可塑性樹脂作射出成形或者是轉移成形，來形成密封樹脂23(圖7(c))。如此這般，晶粒墊11、複數之外周導線部12A、12B、複數之內側導線部26A~26D、半導體元件21以及接合打線22，係被作樹脂密封。 Next, the lead frame 10 is formed by injection molding or transfer molding of a thermosetting resin or a thermoplastic resin to form a sealing resin 23 (FIG. 7 (c)). As such, the die pad 11, the plurality of outer peripheral lead portions 12A, 12B, the plurality of inner lead portions 26A to 26D, the semiconductor element 21, and the bonding wire 22 are sealed with resin.

接著，在導線框架10以及密封樹脂23之背面，設置具備有特定之開口部34a的蝕刻用光阻層34((圖7(d))。 Next, on the back surface of the lead frame 10 and the sealing resin 23, an etching photoresist layer 34 including a specific opening 34a is provided ((FIG. 7 (d)).

於此期間中，首先係在導線框架10以及密封樹脂23之背面全體，分別塗布感光性光阻。接著，隔著光罩來對該感光性光阻進行曝光並進行顯像，藉由此，來形成具備有所期望之開口部34a之蝕刻用光阻層34。 During this period, first, a photoresist is applied to the entire back surface of the lead frame 10 and the sealing resin 23. Next, the photosensitive photoresist is exposed and developed through a photomask, thereby forming a photoresist layer 34 for etching having a desired opening portion 34a.

於此情況，蝕刻用光阻層34，係將除了開口部34a以外的導線框架10以及密封樹脂23之背面全體作覆蓋。又，開口部34a，係具備有與連接環14之位置略對應的平面略矩形的帶形狀，連接環14之背面(金屬部分)係從開口部34a而露出。另外，作為蝕刻用光阻層34，例如係可使用周知之乾薄膜光阻。 In this case, the photoresist layer 34 for etching covers the entire back surface of the lead frame 10 and the sealing resin 23 except for the opening 34a. In addition, the opening portion 34 a has a strip shape having a substantially rectangular plane corresponding to the position of the connection ring 14, and the back surface (metal portion) of the connection ring 14 is exposed from the opening portion 34 a. As the photoresist layer 34 for etching, a well-known dry film photoresist can be used, for example.

接著，將蝕刻用光阻層34作為耐腐蝕膜，而藉由腐蝕液來對於導線框架10施加蝕刻(圖7(e))。此時，從開口部34a所進入之腐蝕液，係將連接環14之 全體溶解並除去。此時，內側導線部26A~26D之連接導線57的一部分，係亦可被與連接環14一同地被除去。於此情況，由於在連接環14之表面上係被設置有凹溝14a，因此，從開口部34a所進入的腐蝕液，係並不會將第2端子部18和外周導線部12A、12B作必要以上之溶解，而能夠適當地將連接環14除去。 Next, using the photoresist layer 34 for etching as a corrosion-resistant film, the lead frame 10 is etched with an etching solution (FIG. 7 (e)). At this time, the etching solution entering from the opening portion 34a The whole was dissolved and removed. At this time, a part of the connecting lead 57 of the inner lead portions 26A to 26D may be removed together with the connecting ring 14. In this case, since the groove 14a is provided on the surface of the connection ring 14, the second terminal portion 18 and the outer peripheral lead portions 12A and 12B are not used as the etching solution entering from the opening portion 34a. If the above dissolution is necessary, the connecting ring 14 can be removed appropriately.

如此這般，連接環14係被除去，內側導線部26A~26D係被相互分離。其結果，各第2端子部18係被個別地分離，並與晶粒墊11、外周導線部12A、12B以及其他之第2端子部18相互電性獨立。另外，腐蝕液，係與上述相同的(參考圖6(d))，例如可使用氯化鐵水溶液。 In this manner, the connecting ring 14 is removed, and the inner lead portions 26A to 26D are separated from each other. As a result, each of the second terminal portions 18 is separately separated from each other, and is electrically independent of the die pad 11, the peripheral lead portions 12A and 12B, and the other second terminal portions 18. The etchant is the same as described above (see FIG. 6 (d)), and for example, an aqueous ferric chloride solution can be used.

接著，將蝕刻用光阻層34剝離並除去。之後，藉由對於各半導體元件21間之導線框架10以及密封樹脂23進行切割，來將導線框架10個別分離成各單位導線框架10a(參考圖1)。此時，例如係亦可一面使由鑽石砥石所成之刃(未圖示)旋轉，一面將各單位導線框架10a間之導線框架10以及密封樹脂23切斷。另外，在將蝕刻用光阻層34除去之後，係亦可設置在凹部27中填充與密封樹脂23相同或者是其他種類之絕緣性樹脂的工程。 Next, the photoresist layer 34 for etching is peeled and removed. Thereafter, the lead frame 10 and the sealing resin 23 between the semiconductor elements 21 are cut to individually separate the lead frame 10 into the unit lead frames 10 a (see FIG. 1). At this time, for example, the lead frame 10 and the sealing resin 23 between the unit lead frames 10a may be cut while rotating a blade (not shown) made of diamond vermiculite. In addition, after the photoresist layer 34 for etching is removed, it is also possible to provide a process for filling the recess 27 with the same or other type of insulating resin as the sealing resin 23.

如此這般，而能夠得到如圖4以及圖5中所示之半導體裝置20(圖7(f))。 In this way, a semiconductor device 20 as shown in FIGS. 4 and 5 can be obtained (FIG. 7 (f)).

如此這般，若依據本實施形態，則第1端子 部53為相對性地位置於內側之長外周導線部12A、和第1端子部53為相對性地位置於外側之短外周導線部12B，係被交互地作配置。藉由此，由於係能夠在將外周導線部12A、12B之間隔縮窄的同時亦將其之根數增加，因此係能夠將第1端子部53之數量增加。 As such, according to this embodiment, the first terminal The portion 53 is a long peripheral lead portion 12A with a relative position inside, and the first terminal portion 53 is a short peripheral lead portion 12B with a relative position outside, and are arranged alternately. As a result, the number of the first terminal portions 53 can be increased because the distance between the outer peripheral lead portions 12A and 12B can be narrowed and the number of the lead portions can be increased.

又，若依據本實施形態，則在製作半導體裝置20時，藉由將連接環14除去，複數之第2端子部18係成為被相互個別地分離。因此，係除了外周導線部12A、12B之第1端子部53以外亦能夠使用內側導線部26A~26D之第2端子部18，而能夠將與外部之安裝基板作連接的端子部之數量(銷數)更進一步增加。藉由此，係能夠實現半導體裝置20之高密度化。 Furthermore, according to this embodiment, when the semiconductor device 20 is manufactured, the plurality of second terminal portions 18 are separated from each other by removing the connection ring 14. Therefore, in addition to the first terminal portions 53 of the outer lead portions 12A and 12B, the second terminal portions 18 of the inner lead portions 26A to 26D can be used, and the number of terminal portions that can be connected to an external mounting substrate Number) increased even further. This makes it possible to increase the density of the semiconductor device 20.

特別是，若依據本實施形態，則第2端子部18為相對性地位置於從連接環14而分離的部份處之長內側導線部26A、26C，和第2端子部18為相對性地位置於接近連接環14的部份處之短內側導線部26B、26D，係被交互地作配置。進而，複數之內側導線部26A~26D，係從連接環14之內側以及外側的雙方而延伸。藉由此，由於係能夠在將內側導線部26A~26D之間隔縮窄的同時亦將其之根數增加，因此係能夠將第2端子部18之數量增加。 In particular, according to this embodiment, the second terminal portion 18 is a long inner lead portion 26A, 26C which is positioned opposite to the portion separated from the connection ring 14, and the second terminal portion 18 is a relative ground. The short inner wire portions 26B, 26D located at the portion close to the connection ring 14 are arranged alternately. Furthermore, the plurality of inner lead portions 26A to 26D extend from both the inner side and the outer side of the connection ring 14. As a result, the number of the second terminal portions 18 can be increased because the distance between the inner lead portions 26A to 26D can be reduced while the number of the inner lead portions 26A to 26D can be increased.

另外，在本實施形態中，雖係以將連接環14之全體藉由蝕刻來除去的情況為例來作了說明，但是，係並不被限定於此。例如，係亦可僅將連接環14之一部分 藉由蝕刻來除去，並使連接環14中之並未被除去的部份殘留於半導體裝置20內。 In this embodiment, the case where the entire connecting ring 14 is removed by etching has been described as an example, but the system is not limited to this. For example, it is also possible to connect only a part of the connecting ring 14 It is removed by etching, and a portion of the connection ring 14 that has not been removed remains in the semiconductor device 20.

又，在上述實施形態中，係針對內側導線部26A、26B之外部端子17C、17D(內側導線部26C、26D之外部端子17E、17F)為以在相鄰接之內側導線部26A、26B(內側導線部26C、26D)之間而位置於內側以及外側的方式，來在作平面性觀察時被交互地以交錯狀來配置成2列的情況為例，來作了說明。然而，係並不被限定於此，內側導線部26A、26B之外部端子17C、17D(內側導線部26C、26D之外部端子17E、17F)，係亦可沿著連接環14之各邊而並排於一直線上。 In the above-mentioned embodiment, the external terminals 17C and 17D of the inner lead portions 26A and 26B (the outer terminals 17E and 17F of the inner lead portions 26C and 26D) are such that the inner lead portions 26A and 26B adjacent to each other The method in which the inner lead portions 26C and 26D) are positioned inside and outside is alternately arranged in two rows in a staggered pattern during planar observation as an example. However, the system is not limited to this, and the external terminals 17C and 17D of the inner lead portions 26A and 26B (the external terminals 17E and 17F of the inner lead portions 26C and 26D) may be arranged side by side along each side of the connection ring 14 On the line.

(第2實施形態) (Second Embodiment)

接著，參考圖8~圖11，對本發明之第2實施形態作說明。圖8乃至圖11，係為對於本發明之第2實施形態作展示者。圖8乃至圖11中所示之第2實施形態，係代替在連接環14處設置具有第2端子部之內側導線部26A~26D，係使連接環14之一部分個別地分離並成為第2端子部28，在此點上，係與第1實施形態相異，其他構成則係與第1實施形態相同。在圖8乃至圖11中，針對與第1實施形態相同的部份，係附加相同之元件符號，並省略詳細說明。 Next, a second embodiment of the present invention will be described with reference to FIGS. 8 to 11. FIG. 8 to FIG. 11 show the second embodiment of the present invention. The second embodiment shown in FIG. 8 to FIG. 11 replaces the inner lead portions 26A to 26D having the second terminal portion at the connection ring 14, and separates a part of the connection ring 14 and becomes the second terminal. The unit 28 is different from the first embodiment in this point, and the other structures are the same as those of the first embodiment. In FIGS. 8 to 11, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed descriptions are omitted.

在圖8~圖10所示之導線框架10A中，係在連接環14之表面上空出有間隔地而被形成有複數之凹部 14c。各凹部14c，係為藉由半蝕刻所形成者，而在厚度方向上並不被作貫通地來具有一定之深度。另外，各凹部14c，係被形成於連接環14之寬幅方向略中央部處。 In the lead frame 10A shown in FIG. 8 to FIG. 10, a plurality of recesses are formed on the surface of the connection ring 14 at intervals. 14c. Each of the recesses 14c is formed by half-etching and has a certain depth without being penetrated in the thickness direction. In addition, each recessed portion 14 c is formed at a substantially central portion in the width direction of the connection ring 14.

又，在相互鄰接之凹部14c之間，係被形成有第2端子部28。亦即是，凹部14c和第2端子部28，係沿著連接環14之長邊方向而被交互作配置。於此情況，第2端子部28，係並不被作半蝕刻地而具備有與晶粒墊11以及支持導線13相同之厚度。另外，在各第2端子部28之表面上，係設置有用以提昇其與接合打線22之間的密著性之電鍍部25。 A second terminal portion 28 is formed between the adjacent recessed portions 14c. That is, the recessed portion 14 c and the second terminal portion 28 are alternately arranged along the longitudinal direction of the connection ring 14. In this case, the second terminal portion 28 is provided with the same thickness as that of the die pad 11 and the support wire 13 without being semi-etched. A plating portion 25 is provided on the surface of each second terminal portion 28 to improve the adhesion between the second terminal portion 28 and the bonding wire 22.

在本實施形態中，於製造半導體裝置20A(參考圖11)時，係僅將連接環14之一部分藉由蝕刻來除去。具體而言，係將連接環14中之各凹部14c的周邊區域分別除去。另一方面，連接環14中之位置在各凹部14c之間的部分，係並不會被除去，而分別個別地被分離並構成第2端子部28。 In this embodiment, when manufacturing the semiconductor device 20A (refer to FIG. 11), only a part of the connection ring 14 is removed by etching. Specifically, the peripheral area of each recessed part 14c in the connection ring 14 is removed separately. On the other hand, the portions of the connection ring 14 between the recessed portions 14 c are not removed, but are separately separated to form the second terminal portions 28.

亦即是，在從導線框架10A之背面側起而將連接環14之一部分作蝕刻除去時(參考圖7(f))，係預先在與各凹部14c以及其周圍相對應的區域處設置蝕刻用光阻層34之開口部34a。之後，藉由從該開口部34a所進入之腐蝕液，而將連接環14中之各凹部14c的周邊區域選擇性地溶解並除去。於此情況，由於在連接環14之表面上係被設置有凹部14c，因此，從開口部34a所進入的腐蝕液，係並不會將第2端子部28和外周導線部 12A、12B作必要以上之溶解，而能夠適當地僅將連接環14中之各凹部14c之周邊區域除去。如此這般，在連接環中之相互鄰接之2個的凹部14c彼此之間，係分別殘留有第2端子部28。 That is, when a portion of the connection ring 14 is etched away from the back surface side of the lead frame 10A (refer to FIG. 7 (f)), etching is provided in advance in a region corresponding to each of the recesses 14c and its surroundings. An opening portion 34a of the photoresist layer 34 is used. Thereafter, the peripheral region of each recessed portion 14c in the connection ring 14 is selectively dissolved and removed by the etching solution entering from the opening portion 34a. In this case, since the recessed portion 14c is provided on the surface of the connection ring 14, the second terminal portion 28 and the outer peripheral lead portion are not corroded by the etchant entering from the opening portion 34a. 12A and 12B are dissolved as necessary, and only the peripheral region of each recessed portion 14c in the connection ring 14 can be appropriately removed. In this manner, the second terminal portions 28 are left between the two adjacent recessed portions 14c in the connection ring.

另外，在本實施形態中，凹部14c，雖係分別被形成於與長外周導線部12A之前端相對應的位置處，但是，係並不被限定於此，而亦可被形成於與短外周導線部12B之前端相對應的位置處。又，複數之凹部14c，雖係遍佈連接環14之周方向全區域地而被作設置，但是，係並不被限定於此，係亦可僅被設置在連接環14之一部分處。 In addition, in the present embodiment, the recessed portions 14c are formed at positions corresponding to the front ends of the long outer peripheral lead portions 12A, respectively. However, the recesses 14c are not limited to this, and may be formed at a short outer periphery. The lead portion 12B is at a position corresponding to the front end. The plurality of recessed portions 14c are provided throughout the entire area in the circumferential direction of the connection ring 14, but the system is not limited to this, and may be provided only at a part of the connection ring 14.

圖11中所示之半導體裝置20A，係為由圖8~圖10中所示之導線框架10A所製作者。在此半導體裝置20A中，第2端子部28，係沿著晶粒墊11之周圍4邊(於圖11中，係為與X方向或Y方向相平行之4邊)的全部，而相互空出有間隔地來作配列。 The semiconductor device 20A shown in FIG. 11 is manufactured by the lead frame 10A shown in FIGS. 8 to 10. In this semiconductor device 20A, the second terminal portions 28 are spaced apart from each other along all four sides of the die pad 11 (four sides parallel to the X direction or the Y direction in FIG. 11). Arranged at intervals.

如同上述一般，導線框架10A的連接環14中之各凹部14c的周邊區域，係在藉由密封樹脂23而被作了樹脂密封之後，從背面側起來藉由蝕刻而除去。因此，如同圖11中所示一般，各第2端子部28，係從晶粒墊11、外周導線部12A、12B以及其他之第2端子部28而分離，並與此些之構件相互電性獨立。又，第2端子部28，係並不被作半蝕刻地而具備有與晶粒墊11相同之厚度。進而，在第2端子部28的背面，係形成有被與外部 之安裝基板(未圖示)作電性連接之外部端子17C。 As described above, the peripheral area of each recessed portion 14c in the connection ring 14 of the lead frame 10A is sealed with resin by the sealing resin 23 and then removed by etching from the back side. Therefore, as shown in FIG. 11, each of the second terminal portions 28 is separated from the die pad 11, the peripheral lead portions 12A and 12B, and the other second terminal portions 28, and these members are electrically conductive with each other. independent. The second terminal portion 28 has the same thickness as that of the die pad 11 without being semi-etched. Furthermore, a back surface is formed on the back surface of the second terminal portion 28. The mounting substrate (not shown) is used as an external terminal 17C for electrical connection.

又，伴隨著連接環14中之除了第2端子部28以外的部份被除去一事，在密封樹脂23之背面中的外周導線部12A、12B和晶粒墊11之間之區域處，係以包圍晶粒墊11的方式而被形成有凹部27。 In addition, with the removal of the portion of the connection ring 14 other than the second terminal portion 28, the area between the outer peripheral lead portions 12A, 12B and the die pad 11 in the back surface of the sealing resin 23 is marked with A recess 27 is formed so as to surround the die pad 11.

若依據本實施形態，則在製作半導體裝置20A時，連接環14之一部分係被除去，連接環14中之並未被除去的部份係被相互個別地分離並成為第2端子部28。如此這般，藉由形成多數之第2端子部28，係能夠將與外部之安裝基板作連接的端子部之數量(銷數)增加，而能夠實現半導體裝置20之更進一步的高密度化。 According to this embodiment, when the semiconductor device 20A is manufactured, a part of the connection ring 14 is removed, and the parts of the connection ring 14 that have not been removed are separated from each other and become the second terminal portion 28. As described above, by forming a large number of second terminal portions 28, the number (pin number) of terminal portions that can be connected to an external mounting substrate can be increased, and the semiconductor device 20 can be further increased in density.

在本實施形態中，係亦可藉由將一部分之第2端子部28形成為較其他之第2端子部28更大，並在此第2端子部28處連接複數之接合打線22，而作為用以進行電性訊號之調節的匯流排或接地(GND)端子來使用。藉由此，係能夠降低伴隨著端子數之增加所導致的發熱，而能夠作成信賴性更高之半導體裝置20A。 In this embodiment, a part of the second terminal portion 28 may be formed larger than the other second terminal portions 28, and a plurality of bonding wires 22 may be connected to the second terminal portion 28 as The bus or ground (GND) terminal is used to adjust the electrical signal. As a result, it is possible to reduce the heat generation caused by an increase in the number of terminals, and it is possible to produce a more reliable semiconductor device 20A.

另外，由本實施形態所致之導線框架10A之製造方法以及半導體裝置20A之製造方法，係與由第1實施形態所致之導線框架10之製造方法(圖6(a)~(f))以及半導體裝置20之製造方法(圖7(a)~(f)))略相同。 The manufacturing method of the lead frame 10A according to this embodiment and the manufacturing method of the semiconductor device 20A are the same as the manufacturing method of the lead frame 10 according to the first embodiment (Figs. 6 (a) to (f)) and The manufacturing method of the semiconductor device 20 (FIGS. 7 (a) to (f)) is slightly the same.

(第3實施形態) (Third Embodiment)

接著，參考圖12~圖17，對本發明之第3實施形態作說明。圖12乃至圖17，係為對於本發明之第3實施形態作展示者。圖12乃至圖17中所示之第3實施形態，其主要相異之處係在於內側導線部26A~26D之配置，以及連接導線57為從表面側起來作了薄化之點，其他構成則係與上述之第1實施形態略相同。在圖12乃至圖17中，針對與第1實施形態相同的部份，係附加相同之元件符號，並省略詳細說明。 Next, a third embodiment of the present invention will be described with reference to FIGS. 12 to 17. FIG. 12 to FIG. 17 show the third embodiment of the present invention. The third embodiment shown in FIG. 12 to FIG. 17 is mainly different in the arrangement of the inner lead portions 26A to 26D and the point where the connecting lead 57 is thinned from the surface side. The other components are This is slightly the same as the first embodiment described above. In FIGS. 12 to 17, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed descriptions are omitted.

在圖12~圖14所示之導線框架10B以及圖15和圖16所示之半導體裝置20B中，複數之內側導線部26A~26D中的從連接環14之內側所延伸的長內側導線部26C、和從連接環14之外側所延伸之短內側導線部26B，係隔著連接環14而被配置在互為相反側之位置。亦即是，長內側導線部26C和相對應之短內側導線部26B，係包夾著連接環14而位置在一直線上。 In the lead frame 10B shown in FIG. 12 to FIG. 14 and the semiconductor device 20B shown in FIG. 15 and FIG. 16, among the plurality of inner lead portions 26A to 26D, the long inner lead portion 26C extends from the inner side of the connection ring 14. And the short inner lead portion 26B extending from the outer side of the connection ring 14 are disposed at positions opposite to each other across the connection ring 14. That is, the long inner lead portion 26C and the corresponding short inner lead portion 26B are positioned on a straight line with the connection ring 14 sandwiched therebetween.

又，從連接環14之內側所延伸的短內側導線部26D、和從連接環14之外側所延伸之長內側導線部26A，係隔著連接環14而被配置在互為相反側之位置。亦即是，短內側導線部26D和相對應之長內側導線部26A，係包夾著連接環14而位置在一直線上。藉由此，係能夠確保外部端子17D和外部端子17F之間的端子間距離，而能夠對於此些之端子彼此相互接觸的問題作防止。 The short inner wire portion 26D extending from the inner side of the connection ring 14 and the long inner wire portion 26A extending from the outer side of the connection ring 14 are disposed at positions opposite to each other across the connection ring 14. That is, the short inner lead portion 26D and the corresponding long inner lead portion 26A are positioned on a straight line with the connection ring 14 sandwiched therebetween. Thereby, the distance between terminals of the external terminal 17D and the external terminal 17F can be ensured, and the problem that these terminals contact each other can be prevented.

進而，從連接環14之外側而延伸之短內側導線部26B、和長外周導線部12A，係相互對向，從連接環 14之外側而延伸之長內側導線部26A、和短外周導線部12B，係相互對向。 Furthermore, the short inner lead wire portion 26B and the long outer lead wire portion 12A extending from the outer side of the connection ring 14 face each other, and from the connection ring 14 The long inner lead wire portion 26A and the short outer lead wire portion 12B extending outwardly face each other.

又，在本實施形態中，內側導線部26A~26D之各連接導線57，係從表面側起來作了薄化。於此情況，由於連接導線57係於背面側而露出，因此係能夠容易地進行將連接環14和連接導線57除去的作業。又，在將連接環14藉由蝕刻而作除去時(參考圖7(e))，係能夠從背面側來容易地對於連接環14以及連接導線57是否有被確實地除去一事作確認。藉由此，使外部端子17C~17F相互獨立的作業係變得容易。另外，在第1實施形態中，亦同樣的，係能夠使各連接導線57從表面側起來作薄化。 In this embodiment, each of the connection wires 57 of the inner wire portions 26A to 26D is thinned from the surface side. In this case, since the connection lead 57 is exposed on the back side, the operation of removing the connection ring 14 and the connection lead 57 can be easily performed. When the connection ring 14 is removed by etching (see FIG. 7 (e)), it is possible to easily confirm whether the connection ring 14 and the connection lead 57 have been reliably removed from the back side. This makes it easier to operate the external terminals 17C to 17F independently of each other. In the first embodiment, similarly, each connection lead 57 can be made thinner from the surface side.

在圖15以及圖16所示之半導體裝置20B中，雖然連接導線57係與連接環14一同地而被除去，但是，係並不被限定於此，亦可在半導體裝置20B處而使連接導線57之一部分殘留，或者是亦可使連接導線57之全體殘留。 In the semiconductor device 20B shown in FIGS. 15 and 16, although the connection lead 57 is removed together with the connection ring 14, the system is not limited to this, and the connection lead may be used at the semiconductor device 20B. A part of 57 remains, or the entire connection lead 57 may remain.

圖17，係對於由本實施形態之變形例所致之導線框架10C作展示。在圖17中，從連接環14之內側係僅延伸有短內側導線部26D，長內側導線部26C則並未作延伸。故而，外部端子17A~17D、17F，係在晶粒墊11之周圍而被配置為5列。於此情況，係能夠相對於半導體裝置20B之大小而確保有廣大的晶粒墊11之面積。另外，在第1實施形態中，亦同樣的，係可並不在連接環 14之內側設置長內側導線部26C。 FIG. 17 shows a lead frame 10C according to a modification of this embodiment. In FIG. 17, only the short inner lead portion 26D is extended from the inner side of the connection ring 14, and the long inner lead portion 26C is not extended. Therefore, the external terminals 17A to 17D and 17F are arranged in five rows around the die pad 11. In this case, it is possible to secure a large area of the die pad 11 with respect to the size of the semiconductor device 20B. In addition, in the first embodiment, it is the same as in the first embodiment. A long inner wire portion 26C is provided inside 14.

另外，由本實施形態所致之導線框架10B、10C之製造方法以及半導體裝置20B之製造方法，係與由第1實施形態所致之導線框架10之製造方法(圖6(a)~(f))以及半導體裝置20之製造方法(圖7(a)~(f)))略相同。 The manufacturing method of the lead frames 10B and 10C according to this embodiment and the manufacturing method of the semiconductor device 20B are the same as the manufacturing method of the lead frame 10 according to the first embodiment (FIG. 6 (a) to (f) ) And the manufacturing method of the semiconductor device 20 (FIGS. 7 (a) to (f))) are slightly the same.

在本實施形態中，在圖12(外部端子17A~17F為6列)中所示之導線框架10B以及在圖17(外部端子17A~17D、17F為5列)中所示之導線框架10C的情況時，均同樣的，係能夠將所有的外部端子17A~17F，配置為外部端子17A~17F彼此之間隔為相等之交錯狀。藉由此，係能夠對於在基板安裝時之焊錫架橋的發生作抑制，而成為能夠使安裝信賴性提昇。 In this embodiment, the lead frames 10B shown in FIG. 12 (6 rows of external terminals 17A to 17F) and the lead frames 10C shown in FIG. 17 (5 rows of external terminals 17A to 17D and 17F) In this case, all the external terminals 17A to 17F can be arranged in a staggered manner in which the intervals between the external terminals 17A to 17F are equal to each other. This makes it possible to suppress the occurrence of solder bridges during board mounting, and to improve the reliability of mounting.

若依據本實施形態，則例如當12mm□之封裝的情況時，若是使用圖12中所示之導線框架10B(外部端子17A~17F為6列)，則係能夠將端子部之數量(銷數)增加至308銷。又，例如當12mm□之封裝的情況時，若是使用圖17中所示之導線框架10B(外部端子17A~17D、17F為5列)，則係能夠將端子部之數量(銷數)增加至280銷。如此這般，若依據本實施形態，則係成為能夠低價地製造可搭載高功能之LSI的半導體裝置。進而，例如當10mm□之封裝的情況時，若是使用圖17中所示之導線框架10B(外部端子17A~17D、17F為5列)，則係能夠將端子部之數量(銷數)增加至208銷~ 216銷。此一銷數(208銷~216銷)，係相當於與先前技術之28mm□之QFP(Quad Flat Package)同等之銷數。 According to this embodiment, for example, in the case of a 12 mm □ package, if the lead frame 10B shown in FIG. 12 is used (the external terminals 17A to 17F are 6 rows), the number of terminal portions (number of pins) ) To 308 pins. In the case of a 12mm □ package, for example, if the lead frame 10B shown in FIG. 17 is used (the external terminals 17A to 17D and 17F are in 5 rows), the number of terminal portions (number of pins) can be increased to 280 pins. As described above, according to this embodiment, a semiconductor device capable of mounting a high-performance LSI can be manufactured at a low cost. Furthermore, for example, in the case of a 10 mm □ package, if the lead frame 10B shown in FIG. 17 is used (the external terminals 17A to 17D and 17F are in 5 rows), the number of terminal portions (number of pins) can be increased to 208 pins ~ 216 pins. This number of pins (208 pins to 216 pins) is equivalent to the QFP (Quad Flat Package) of 28mm □ in the prior art.

(第4實施形態) (Fourth Embodiment)

接著，參考圖18~圖21，對本發明之第4實施形態作說明。圖18乃至圖21，係為對於本發明之第4實施形態作展示者。圖18~圖21中所示之第4實施形態，其主要相異之處係在於代替連接環14而設置有導線連接部(連接條)64之點，其他構成則係與上述之第1實施形態略相同。在圖18~圖21中，針對與第1實施形態相同的部份，係附加相同之元件符號，並省略詳細說明。 Next, a fourth embodiment of the present invention will be described with reference to FIGS. 18 to 21. FIG. 18 to FIG. 21 show the fourth embodiment of the present invention. The fourth embodiment shown in FIGS. 18 to 21 is mainly different from the point in which a wire connection portion (connection bar) 64 is provided instead of the connection ring 14. The other structure is the same as the first embodiment described above. The shape is slightly the same. In FIGS. 18 to 21, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed descriptions are omitted.

在圖18以及圖19所示之導線框架10D中，在晶粒墊11和外周導線部12A、12B之間，係被配置有導線連接部64。藉由此導線連接部64，分別具備有第2端子部18之複數之內側導線部26A~26D係被作支持。導線連接部64，係並不被作半蝕刻地而具備有與晶粒墊11相同之厚度。然而，係並不被限定於此，亦可從導線連接部64之表面側來藉由半蝕刻而作薄化。又，導線連接部64，係以直線狀而延伸，其之兩端係分別被與懸吊導線16作連結。懸吊導線16，係從背面側起來藉由半蝕刻而作薄化。另外，導線連接部64，係並非絕對需要被與懸吊導線16作連結，而例如亦可被與晶粒墊11作連結。 In the lead frame 10D shown in FIGS. 18 and 19, a lead connection portion 64 is arranged between the die pad 11 and the outer lead portions 12A and 12B. By this wire connection portion 64, a plurality of inner wire portions 26A to 26D each including the second terminal portion 18 are supported. The lead connecting portion 64 is provided with the same thickness as the die pad 11 without being semi-etched. However, the system is not limited to this, and may be thinned by half-etching from the surface side of the lead connection portion 64. In addition, the lead connecting portion 64 extends linearly, and both ends of the lead connecting portion 64 are connected to the hanging lead 16, respectively. The suspension wire 16 is thinned from the back side by half-etching. In addition, the wire connecting portion 64 does not absolutely need to be connected to the suspension wire 16, but may be connected to the die pad 11, for example.

於此情況，晶粒墊11係為平面略長方形狀，其之長邊係與X方向相平行，其之短邊係與Y方向相平行。在本實施形態中，導線連接部64，係在1個的單位導線框架10a處設置有2根，並分別與晶粒墊11之長邊相平行地而延伸。然而，係並不被限定於此，導線連接部64，係亦可在1個的單位導線框架10a處設置有1根或者是3根以上。又，導線連接部64之形狀，係並不被限定於直線狀，而亦可設為略圓弧等之曲線狀、略V字形狀、略L字形狀、略U字形狀等。 In this case, the die pad 11 has a substantially rectangular shape in a plane, and a long side thereof is parallel to the X direction, and a short side thereof is parallel to the Y direction. In this embodiment, two lead connection portions 64 are provided at one unit lead frame 10a, and each of the lead connection portions 64 extends parallel to the long side of the die pad 11. However, the system is not limited to this, and one or three or more lead connection portions 64 may be provided in one unit lead frame 10a. The shape of the lead connecting portion 64 is not limited to a straight line, but may be a curved shape such as a slightly circular arc, a slightly V-shape, a slightly L-shape, a slightly U-shape, or the like.

又，在本實施形態中，相連續之一部分(例如4個)的外部端子17A，係藉由連結部65而被作連結，相連續之一部分(例如3個)的外部端子17E，係藉由連結部66而被作連結。連結部65、66，係亦可分別例如作為匯流排或接地(GND)端子來作使用。 In this embodiment, a continuous portion (for example, four) of the external terminals 17A is connected by the connecting portion 65, and a continuous portion (for example, three) of the external terminals 17E is connected by The connection portion 66 is connected. The connection portions 65 and 66 can also be used as, for example, bus bars or ground (GND) terminals, respectively.

圖20中所示之半導體裝置20D，係為由圖18以及圖19中所示之導線框架10D所製作者。在此半導體裝置20D處，導線連接部64係被除去，伴隨於此，在密封樹脂23之背面中的外周導線部12A、12B和晶粒墊11之間之內側導線部26A、26B與內側導線部26C、26D之間的區域處，係被形成有凹部67。此凹部67，係在1個的半導體裝置20D中而設置有2根，並分別概略對應於導線連接部64之形狀而相對於晶粒墊11之長邊來相平行地延伸為一直線狀。 The semiconductor device 20D shown in FIG. 20 is manufactured by the lead frame 10D shown in FIGS. 18 and 19. In this semiconductor device 20D, the lead connecting portion 64 is removed, and the inner lead portions 26A and 26B and the inner lead between the outer lead portions 12A and 12B and the die pad 11 in the back surface of the sealing resin 23 are removed. A recessed portion 67 is formed in a region between the portions 26C and 26D. Two recesses 67 are provided in one semiconductor device 20D, and each of the recesses 67 roughly corresponds to the shape of the wire connection portion 64 and extends in a straight line parallel to the long side of the die pad 11.

若依據本實施形態，則由於導線連接部64係 僅沿著晶粒墊11之2邊而延伸，因此，藉由在並未被設置有導線連接部64之方向上而使晶粒墊11延伸，係能夠將晶粒墊11之面積增廣。藉由此，係成為易於在晶粒墊11上搭載大型之半導體元件21或複數之半導體元件21。 According to this embodiment, since the lead connecting portion 64 is The die pad 11 extends along only two sides of the die pad 11. Therefore, by extending the die pad 11 in a direction in which the wire connection portion 64 is not provided, the area of the die pad 11 can be enlarged. This makes it easy to mount a large-sized semiconductor element 21 or a plurality of semiconductor elements 21 on the die pad 11.

圖21，係對於由本實施形態之變形例所致之導線框架10E作展示。在圖21中，從各導線連接部64內側係僅延伸有短內側導線部26D，長內側導線部26C則並未作延伸。於此情況，係能夠將晶粒墊11之面積擴廣至各導線連接部64側。 FIG. 21 shows a lead frame 10E caused by a modification of this embodiment. In FIG. 21, only the short inner lead portion 26D is extended from the inner side of each lead connecting portion 64, and the long inner lead portion 26C is not extended. In this case, it is possible to widen the area of the die pad 11 to each lead connection portion 64 side.

另外，由本實施形態所致之導線框架10D、10E之製造方法以及半導體裝置20D之製造方法，係與由第1實施形態所致之導線框架10之製造方法(圖6(a)~(f))以及半導體裝置20之製造方法(圖7(a)~(f)))略相同。 The method for manufacturing the lead frames 10D and 10E according to this embodiment and the method for manufacturing the semiconductor device 20D are the same as those for manufacturing the lead frame 10 according to the first embodiment (FIG. 6 (a) to (f) ) And the manufacturing method of the semiconductor device 20 (FIGS. 7 (a) to (f))) are slightly the same.

(第5實施形態) (Fifth Embodiment)

接著，參考圖22~圖30，對本發明之第5實施形態作說明。圖22~圖30，係為對於本發明之第5實施形態作展示者。在圖22~圖30中，針對相同的部份，係附加相同之元件符號，並會有省略一部分之詳細說明的情形。 Next, a fifth embodiment of the present invention will be described with reference to FIGS. 22 to 30. 22 to 30 are illustrations showing a fifth embodiment of the present invention. In FIG. 22 to FIG. 30, the same component symbols are attached to the same parts, and a detailed description of some parts may be omitted.

導線框架之構成 The composition of the lead frame

首先，根據圖22~圖26，對由本實施形態所致之導線框架的概略內容作說明。圖22~圖26，係為對於由本 實施形態所致之導線框架作展示之圖。 First, the outline of the lead frame according to this embodiment will be described with reference to FIGS. 22 to 26. Figure 22 to Figure 26 are for The lead frame caused by the implementation is shown in the figure.

如圖22以及圖23中所示一般，導線框架10F，係包含有複數之單位導線框架10a。各單位導線框架10a，係具備有：平面矩形狀之晶粒墊11，係搭載有半導體元件21(於後再述)；和複數之細長的導線部12A、12B，係被設置於晶粒墊11之周圍，並分別與半導體元件21以及外部電路(未圖示)作連接。另外，單位導線框架10a，係為分別與半導體裝置20F(於後再述)相對應之區域，而為在圖22中位置在假想線之內側處的區域。 As shown in FIG. 22 and FIG. 23, the lead frame 10F generally includes a plurality of unit lead frames 10a. Each unit lead frame 10a includes a flat rectangular die pad 11 on which a semiconductor element 21 is mounted (to be described later), and a plurality of elongated lead portions 12A and 12B provided on the die pad. 11 is connected to the semiconductor element 21 and an external circuit (not shown), respectively. The unit lead frame 10 a is a region corresponding to each of the semiconductor devices 20F (to be described later), and is a region located inside the virtual line in FIG. 22.

複數之單位導線框架10a，係經由支持導線(支持構件)13而被相互作連結。此支持導線13，係為支持晶粒墊11和導線部12A、12B者，並分別沿著X方向以及垂直於X方向之Y方向而延伸。又，在晶粒墊11之四角隅處，係被連接有懸吊導線16，晶粒墊11，係經由此4根的懸吊導線16而被連結支持於支持導線13處。 The plurality of unit lead frames 10 a are connected to each other via a support lead (support member) 13. This supporting wire 13 is for supporting the die pad 11 and the wire portions 12A and 12B, and extends along the X direction and the Y direction perpendicular to the X direction, respectively. Suspended wires 16 are connected to the four corners of the die pad 11, and the die pad 11 is connected to and supported by the support wires 13 through the four suspended wires 16.

相鄰接之導線部12A、12B彼此，係在半導體裝置20F(於後再述)之製造後，成為被相互電性絕緣之形狀。又，各導線部12A、12B，在半導體裝置20F之製造後，係成為被與晶粒墊11電性絕緣之形狀。在此導線部12A、12B之背面，係分別形成有被與外部之安裝基板(未圖示)作電性連接之外部端子17A、17B。各外部端子17A、17B，係在半導體裝置20F(於後再述)之製造後，分別成為從半導體裝置20F而露出於外部。 The adjacent lead portions 12A and 12B are formed in a shape that is electrically insulated from each other after the semiconductor device 20F (described later) is manufactured. In addition, each of the lead portions 12A and 12B has a shape that is electrically insulated from the die pad 11 after the semiconductor device 20F is manufactured. On the back surfaces of the lead portions 12A and 12B, external terminals 17A and 17B electrically connected to an external mounting substrate (not shown) are formed. Each of the external terminals 17A and 17B is exposed from the semiconductor device 20F after being manufactured after the semiconductor device 20F (to be described later).

於此情況，複數之導線部12A、12B之外部端 子17A、17B，係以在相鄰接之導線部12A、12B之間而位置於內側以及外側的方式，來在作平面性觀察時被交互地配置為交錯狀。亦即是，在晶粒墊11之周圍，具有相對性地位置於內側(晶粒墊11側)之外部端子17A的導線部12A，和具有相對性地位置於外側(支持導線13側)之外部端子17B的導線部12B，係遍佈全周地而被交互作配置。藉由此，係能夠對於導線部12A、12B之外部端子17A、17B和相鄰接之導線部12B、12A相互接觸的問題作防止。另外，在本實施形態中，係將位置在內側之外部端子17A亦稱作內側外部端子17A，並將位置在外側之外部端子17B亦稱作外側外部端子17B。於此情況，內側外部端子17A以及外側外部端子17B，係全部具備有相同之平面形狀。 In this case, the outer ends of the plurality of lead portions 12A, 12B The subs 17A and 17B are alternately arranged in a staggered manner during planar observation when the subs 17A and 17B are positioned inside and outside between the adjacent lead portions 12A and 12B. That is, around the die pad 11, the lead portion 12A of the external terminal 17A having a relative position on the inside (the die pad 11 side), and the outside of the die pad 11 (on the supporting lead 13 side) have a relative position. The lead portions 12B of the external terminals 17B are alternately arranged throughout the entire circumference. Accordingly, the problem that the external terminals 17A and 17B of the lead portions 12A and 12B and the adjacent lead portions 12B and 12A contact each other can be prevented. In this embodiment, the external terminal 17A positioned on the inside is also referred to as an internal external terminal 17A, and the external terminal 17B positioned on the outside is also referred to as an external external terminal 17B. In this case, all of the inner external terminal 17A and the outer external terminal 17B have the same planar shape.

如圖22中所示一般，複數之內側外部端子17A，係當作平面性觀察時，均為沿著與晶粒墊11之一邊相平行的直線而被配列。又，複數之外側外部端子17B，係當作平面性觀察時，均為沿著與晶粒墊11之一邊相平行的直線而被配列。亦即是，複數之內側外部端子17A以及複數之外側外部端子17B，係沿著與X方向或者是Y方向之其中一者相平行的直線而被配列成2列。然而，係並不被限定於此，例如，複數之內側外部端子17A以及/或者是複數之外側外部端子17B，係亦可當作平面性觀察時而分別被配列在圓弧上。 As shown in FIG. 22, generally, the plurality of inner external terminals 17A are arranged along a straight line parallel to one side of the die pad 11 when viewed as a flatness. The plurality of external terminals 17B are arranged along a straight line parallel to one side of the die pad 11 when viewed as a flatness. That is, the plural inner external terminals 17A and the plural outer external terminals 17B are arranged in two rows along a straight line parallel to one of the X direction and the Y direction. However, the system is not limited to this. For example, the plurality of inner external terminals 17A and / or the plurality of outer external terminals 17B may be arranged on an arc respectively when viewed as planarity.

接著，參考圖24以及圖25(a)~(b)，針 對各導線部12A、12B之構成更進一步作說明。 Next, referring to FIGS. 24 and 25 (a) to (b), the needle The configuration of each of the lead portions 12A and 12B will be further described.

如圖24中所示一般，導線部12A、12B中之具有內側外部端子17A的導線部12A，係具備有內導線51、和連接導線52、以及端子部(第1端子部)53。其中，內導線51，係較端子部53而更朝向內側(晶粒墊11側)延伸，在其之內側端部表面上，係被形成有內部端子15。此內部端子15，係如同後述一般，成為經由接合打線22而被與半導體元件21作電性連接之區域。因此，在內部端子15上，係設置有用以提昇其與接合打線22之間的密著性之電鍍部25。於此情況，內導線51，係相對於支持導線13而傾斜地延伸。 As shown in FIG. 24, the lead portion 12A having the inner external terminal 17A among the lead portions 12A and 12B is generally provided with an inner lead 51, a connection lead 52, and a terminal portion (first terminal portion) 53. Among them, the inner lead 51 extends further toward the inner side (the die pad 11 side) than the terminal portion 53, and an inner terminal 15 is formed on the inner end surface of the inner lead 51. The internal terminal 15 is a region electrically connected to the semiconductor element 21 via a bonding wire 22 as described later. Therefore, the internal terminal 15 is provided with a plating portion 25 for improving the adhesion between the internal terminal 15 and the bonding wire 22. In this case, the inner lead 51 extends obliquely with respect to the support lead 13.

連接導線52，係位置在較端子部53而更外側(支持導線13側)處，其之外端部係被連結於支持導線13處。連接導線52，係相對於該連接導線52所被作連結之支持導線13而垂直地延伸。進而，在端子部53的背面，係形成有內側外部端子17A。 The connecting lead 52 is positioned further outside (the supporting lead 13 side) than the terminal portion 53, and the outer end portion thereof is connected to the supporting lead 13. The connecting wire 52 extends perpendicularly to the supporting wire 13 to which the connecting wire 52 is connected. Further, an inner external terminal 17A is formed on the back surface of the terminal portion 53.

如圖25(a)中所示一般，導線部12A之內導線51以及連接導線52，係分別從背面側(與搭載半導體元件21之面相反側)而藉由半蝕刻來形成為厚度較薄。另一方面，端子部53，係並不被作半蝕刻地而具備有與晶粒墊11以及支持導線13相同之厚度。如此這般，藉由使內導線51以及連接導線52之厚度成為較端子部53之厚度更薄，係能夠以良好精確度來形成寬幅為窄之導線部12A，而能夠得到小型且銷數為多之半導體裝置 20F。另外，所謂半蝕刻，係指對於被蝕刻材料而一直蝕刻至直到其之厚度方向的途中為止。 As shown in FIG. 25 (a), generally, the lead 51 and the connecting lead 52 in the lead portion 12A are formed from the back side (the side opposite to the surface on which the semiconductor element 21 is mounted) by semi-etching to be thinner. . On the other hand, the terminal portion 53 is provided with the same thickness as that of the die pad 11 and the support wire 13 without being semi-etched. In this way, by making the thickness of the inner lead 51 and the connecting lead 52 thinner than the thickness of the terminal portion 53, it is possible to form the lead portion 12A having a narrow width with good accuracy, and a small number of pins can be obtained Semiconductor device 20F. In addition, the term "half etching" means that the material to be etched is etched to the middle of its thickness direction.

另一方面，如圖24中所示一般，導線部12A、12B中之具有外側外部端子17B的導線部12B，係具備有內導線61、和連接導線62、以及端子部63。其中，內導線61，係位置在較端子部63而內側(晶粒墊11側)，在其之內側端部表面上，係被形成有內部端子15。於此情況，內導線61，係具備有相對於支持導線13而垂直地延伸之直線部分61b、和從該直線部分61b起而傾斜地延伸之傾斜部分61a。 On the other hand, as shown in FIG. 24, the lead portion 12B having the outer external terminal 17B of the lead portions 12A and 12B is generally provided with an inner lead 61, a connection lead 62, and a terminal portion 63. Among them, the inner lead 61 is located on the inner side (the die pad 11 side) from the terminal portion 63, and the inner terminal 15 is formed on the inner end surface of the inner lead 61. In this case, the inner lead 61 includes a straight portion 61b extending perpendicularly to the support lead 13 and an inclined portion 61a extending obliquely from the straight portion 61b.

又，連接導線62，係位置在較端子部63而更外側(支持導線13側)處，其之外端部係被連結於支持導線13處。連接導線62，係相對於該連接導線62所被作連結之支持導線13而垂直地延伸。進而，在端子部63的背面，係形成有外側外部端子17B。 The connection lead 62 is positioned further outside (the support lead 13 side) than the terminal portion 63, and the outer end portion thereof is connected to the support lead 13. The connecting wire 62 extends perpendicularly to the supporting wire 13 to which the connecting wire 62 is connected. Further, an outer external terminal 17B is formed on the back surface of the terminal portion 63.

如圖25(b)中所示一般，導線部12B之內導線61以及連接導線62，係分別從背面側(與搭載半導體元件21之面相反側)而藉由半蝕刻來形成為厚度較薄。又，端子部63，係並不被作半蝕刻地而具備有與晶粒墊11以及支持導線13相同之厚度。如此這般，藉由使內導線61以及連接導線62之厚度成為較端子部63之厚度更薄，係能夠以良好精確度來形成寬幅為窄之導線部12B，而能夠得到小型且銷數為多之半導體裝置20F。 As shown in FIG. 25 (b), in general, the inner lead 61 and the connecting lead 62 in the lead portion 12B are formed from the back side (the side opposite to the side on which the semiconductor element 21 is mounted) by thin etching to be thinner. . The terminal portion 63 is provided with the same thickness as that of the die pad 11 and the support lead 13 without being semi-etched. As such, by making the thickness of the inner lead 61 and the connecting lead 62 thinner than the thickness of the terminal portion 63, it is possible to form the lead portion 12B with a narrow width and a good width with good accuracy, and it is possible to obtain a small and pin number There are many semiconductor devices 20F.

接著，參考圖26(a)~(c)，針對各導線 部12A、12B之剖面形狀(沿著與支持各導線部12A、12B之支持導線13相平行的方向之剖面形狀)更進一步作說明。 Next, referring to FIGS. 26 (a) to (c), for each lead The cross-sectional shape of the portions 12A and 12B (the cross-sectional shape in a direction parallel to the support wire 13 supporting each of the lead portions 12A and 12B) will be further described.

如圖26(a)~(c)中所示一般，導線部12A之內導線51以及連接導線52，係藉由從背面側來施加半蝕刻，而分別具備有略四角形狀、略梯形狀或者是略半圓弧狀之剖面。又，關於導線部12B之內導線61以及連接導線62，亦同樣的，係藉由從背面側來施加半蝕刻，而分別具備有略四角形狀、略梯形狀或者是略半圓弧狀之剖面。 As shown in FIGS. 26 (a) to (c), generally, the lead 51 and the connecting lead 52 in the lead portion 12A are provided with a slightly quadrangular shape, a ladder shape or It is a slightly semi-circular section. In addition, the inner lead 61 and the connecting lead 62 in the lead portion 12B are similarly provided with a slightly quadrangular shape, a ladder shape, or a substantially semi-circular cross section by applying a half-etching from the back side. .

又，如圖26(a)中所示一般，導線部12A之端子部53，係具備有使其之兩側面朝向內側而作了彎曲的形狀。於此情況，內側外部端子17A(端子部53之背面)之寬幅wA2，係成為較端子部53之表面之寬幅wA1而更廣。藉由此，就算是在將相互鄰接之導線部12A和導線部12B之間的間隔作了縮窄的情況時，亦能夠將內側外部端子17A之面積確保為廣，而能夠將內側外部端子17A和外部之安裝基板(未圖示)確實地作連接。另外，如圖26(c)中所示一般，關於導線部12B之端子部63，亦同樣的，係具備有使其之兩側面朝向內側而作了彎曲的形狀，並且外側外部端子17B(端子部63之背面)之寬幅wB2，係成為較端子部63之表面之寬幅wB1而更廣。 Further, as shown in FIG. 26 (a), the terminal portion 53 of the lead portion 12A is generally provided with a shape in which both side surfaces are bent inward. In this case, the width w A2 of the inner external terminal 17A (the back surface of the terminal portion 53) is wider than the width w A1 of the surface of the terminal portion 53. Accordingly, even when the interval between the adjacent lead portions 12A and 12B is narrowed, the area of the inner external terminal 17A can be ensured to be wide, and the inner external terminal 17A can be secured. It is securely connected to an external mounting substrate (not shown). In general, as shown in FIG. 26 (c), the terminal portion 63 of the lead portion 12B is also provided with a shape in which both sides are bent toward the inside, and the outer external terminal 17B (terminal The width w B2 of the back surface of the portion 63 is wider than the width w B1 of the surface of the terminal portion 63.

另外，如圖24中所示一般，導線部12A、12B之連接導線52、62中的支持導線13之近旁部分55， 其之寬幅wC係成為60μm~90μm或者是75μm~90μm。又，在圖25(a)~(b)中，該近旁部分55之厚度tC，係成為50μm~75μm或者是60μm~75μm。 In addition, as shown in FIG. 24, generally, the width w C of the support portion 13 of the connection leads 52 and 62 of the lead portions 12A and 12B is 60 μm to 90 μm or 75 μm to 90 μm. In addition, in FIGS. 25 (a) to (b), the thickness t C of the adjacent portion 55 is 50 μm to 75 μm or 60 μm to 75 μm.

如此這般，係藉由將近旁部分55之寬幅wC設為60μm或者是75μm以上，並將厚度tC設為50μm或者是60μm以上，來保持導線部12A、12B之相當於根部的部份(近旁部分55)之強度。因此，就算是在將導線部12A、12B之間的間隔作了縮窄的情況時，也能夠對於導線部12A、12B之強度降低的情形作抑制，而能夠防止在導線部12A、12B處產生變形的情況。又，藉由將上述近旁部分55之寬幅wC設為90μm以下，並將厚度tC設為75μm以下，係能夠將導線部12A、12B間之間隔縮窄，而能夠將各半導體裝置20F之外部端子17A、17B的數量(銷數)增加。 He goes, by the Department of the vicinity of the wide portion w C of 55 to 60μm or 75μm or more, and a thickness t C is 60μm or more to 50 m, to the wire holding portions 12A, 12B corresponding to the root portion (Proximity 55). Therefore, even when the interval between the lead portions 12A and 12B is narrowed, it is possible to suppress the decrease in the strength of the lead portions 12A and 12B and prevent the occurrence of the lead portions 12A and 12B. Deformation. In addition, by setting the width w C of the near portion 55 to 90 μm or less and the thickness t C to 75 μm or less, the interval between the lead portions 12A and 12B can be narrowed, and each semiconductor device 20F can be narrowed. The number of external terminals 17A and 17B (number of pins) increases.

又，在圖24中，導線部12A、12B之內導線51、61中的端子部53、63之近旁部分56，其之寬幅wd係成為60μm~90μm或者是75μm~90μm。進而，在圖25(a)~(b)中，該近旁部分56之厚度td，係成為50μm~75μm或者是60μm~75μm。 Further, in FIG. 24, the widths w d of the adjacent portions 56 of the terminal portions 53 and 63 of the lead wires 51 and 61 within the lead portions 12A and 12B are 60 μm to 90 μm or 75 μm to 90 μm. Further, in FIGS. 25 (a) to (b), the thickness t d of the near portion 56 is 50 μm to 75 μm or 60 μm to 75 μm.

如此這般，係藉由將近旁部分56之寬幅wd設為60μm或者是75μm以上，並將厚度td設為50μm或者是60μm以上，來保持內導線51、61之相當於根部的部份(近旁部分56)之強度，而對於內導線51、61之強度降低的情況作抑制，並能夠防止在內導線51、61處產 生變形的情形。又，藉由將上述近旁部分56之寬幅wd設為90μm以下，並將厚度td設為75μm以下，由於係能夠將導線部12A、12B間之間隔縮窄，因此係能夠將各半導體裝置20F之外部端子17A、17B的數量(銷數)增加。 It goes, by the Department of width w d vicinity of portion 56 is 75μm to 60μm or more, and a thickness t d is 60μm or more to 50 m, inner leads 51, 61 to keep the portion corresponding to the root It is possible to suppress the decrease in the strength of the inner conductors 51 and 61 and prevent the deformation of the inner conductors 51 and 61. Furthermore, by setting the width w d of the near portion 56 to 90 μm or less and the thickness t d to 75 μm or less, the interval between the lead portions 12A and 12B can be narrowed, so that each semiconductor can be narrowed. The number (pin number) of the external terminals 17A and 17B of the device 20F is increased.

另外，在圖24中，相互鄰接之外周導線部12A、12B之間的間隔d，係以設為90μm~150μm為理想。如此這般，藉由將間隔d設為90μm以上，係能夠藉由蝕刻而確實地形成相互鄰接之導線部12A、12B之間的貫通部分。又，藉由將上述間隔d設為150μm以下，係能夠將各半導體裝置20F之外部端子17A、17B的數量(銷數)確保有一定數量以上。具體而言，外部端子17A、17B之數量(銷數)，例如係可設為80銷~250銷。 In addition, in FIG. 24, the interval d between the outer peripheral lead portions 12A and 12B adjacent to each other is preferably set to 90 μm to 150 μm. As described above, by setting the interval d to 90 μm or more, it is possible to reliably form a through portion between the lead portions 12A and 12B adjacent to each other by etching. In addition, by setting the interval d to 150 μm or less, the number (pin number) of the external terminals 17A and 17B of each semiconductor device 20F can be secured to a certain number or more. Specifically, the number (pin number) of the external terminals 17A and 17B can be set to, for example, 80 to 250 pins.

以上所作了說明的導線框架10F，係由具備有750Mpa~1100Mpa或者是850Mpa~1100Mpa之拉張強度的金屬材料所構成，較理想，係由具備有920Mpa~1010Mpa之拉張強度的金屬材料所構成。藉由將導線框架10F藉由具有750MPa或者是850MPa以上之拉張強度的金屬材料來構成，由於係能夠對於導線部12A、12B之強度降低並產生變形的情形作抑制，因此係能夠將導線部12A、12B之間的間隔縮窄。又，一般而言，拉張強度為高之金屬材料，其導電性係會有降低的傾向。因此，藉由將導線框架10F藉由具有1100MPa以下之拉張強度的金屬材料來構成，係能夠對於導線部12A、12B之導電性降 低的情形作防止。 The lead frame 10F described above is made of a metal material having a tensile strength of 750Mpa ~ 1100Mpa or 850Mpa ~ 1100Mpa, and is more preferably made of a metal material having a tensile strength of 920Mpa ~ 1010Mpa. . By constructing the lead frame 10F with a metallic material having a tensile strength of 750 MPa or above 850 MPa, it is possible to suppress the reduction and deformation of the lead portions 12A and 12B, so the lead portion can be reduced. The interval between 12A and 12B is narrowed. In addition, generally, a metal material having a high tensile strength tends to have a reduced conductivity. Therefore, by constructing the lead frame 10F from a metal material having a tensile strength of 1100 MPa or less, the electrical conductivity of the lead portions 12A and 12B can be reduced. Prevent low situations.

作為此種金屬材料，係可列舉出銅合金等，具體而言，例如係可列舉出卡遜系合金(Cu-Ni-Si)、鎳錫銅合金(Cu-Ni-Sn)、鈦銅合金(Cu-Ti)等。 Examples of such metal materials include copper alloys, and specifically, examples thereof include Carson-based alloys (Cu-Ni-Si), nickel-tin-copper alloys (Cu-Ni-Sn), and titanium-copper alloys. (Cu-Ti) and the like.

又，導線框架10F之厚度，雖亦係依存於所製造之半導體裝置20F的構成，但是係可設為80μm~250μm。 The thickness of the lead frame 10F depends on the structure of the manufactured semiconductor device 20F, but it can be set to 80 μm to 250 μm.

另外，在圖22中，導線部12A、12B，雖係沿著晶粒墊11之4邊的全部而被作配置，但是，係並不被限定於此，例如，係亦可僅沿著晶粒墊11之相對向的2邊來作配置。 In addition, in FIG. 22, the lead portions 12A and 12B are arranged along all four sides of the die pad 11, but the system is not limited to this. For example, the lead portions 12A and 12B may be arranged only along the die. The opposite sides of the grain pad 11 are arranged.

半導體裝置之構成 Structure of a semiconductor device

接著，根據圖27以及圖28，對由本實施形態所致之半導體裝置作說明。圖27以及圖28係為對於由本實施形態所致之半導體裝置(DR-QFN(Dual Row QFN)型態)作展示之圖。 Next, a semiconductor device according to this embodiment will be described with reference to FIGS. 27 and 28. 27 and 28 are diagrams showing a semiconductor device (DR-QFN (Dual Row QFN) type) according to this embodiment.

如圖27以及圖28中所示一般，半導體裝置(半導體封裝)20F，係具備有：晶粒墊11、和被配置在晶粒墊11之周圍的複數之導線部12A、12B、和被搭載在晶粒墊11上之半導體元件21、以及將導線部12A、12B和半導體元件21作電性連接之複數之接合打線(連接構件)22。又，晶粒墊11、導線部12A、12B、半導體元件21以及接合打線22，係藉由密封樹脂23而被作樹脂密 封。 As shown in FIGS. 27 and 28, a semiconductor device (semiconductor package) 20F generally includes a die pad 11 and a plurality of lead portions 12A and 12B arranged around the die pad 11 and mounted thereon. The semiconductor element 21 on the die pad 11 and a plurality of bonding wires (connecting members) 22 for electrically connecting the lead portions 12A and 12B and the semiconductor element 21. In addition, the die pad 11, the lead portions 12A, 12B, the semiconductor element 21, and the bonding wire 22 are made resin-tight by a sealing resin 23. seal.

其中，晶粒墊11以及導線部12A、12B，係為從上述之導線框架10F所製作者。此晶粒墊11以及導線部12A、12B之構成，除了並不被包含於單位導線框架10a中的區域以外，係為與上述之圖22~圖26中所示者略相同，於此係省略詳細之說明。又，關於半導體元件21、接合打線22、密封樹脂23、接著劑24以及電鍍部25之構成，由於係與第1實施形態略相同，因此係省略詳細之說明。 The die pad 11 and the lead portions 12A and 12B are manufactured from the lead frame 10F described above. The structures of the die pad 11 and the lead portions 12A and 12B are the same as those shown in FIG. 22 to FIG. 26 except that they are not included in the unit lead frame 10a, and are omitted here. Detailed explanation. The configurations of the semiconductor element 21, the bonding wire 22, the sealing resin 23, the adhesive 24, and the plating portion 25 are slightly the same as those of the first embodiment, and detailed descriptions are omitted.

導線框架之製造方法 Method for manufacturing lead frame

接下來，針對圖22~圖26中所示之導線框架10F之製造方法，使用圖29(a)~(f)來作說明。另外，圖29(a)~(f)，係為對於導線框架10F之製造方法作展示的剖面圖(與圖23相對應之圖)。 Next, a method for manufacturing the lead frame 10F shown in FIGS. 22 to 26 will be described using FIGS. 29 (a) to (f). In addition, FIGS. 29 (a) to (f) are cross-sectional views showing the method for manufacturing the lead frame 10F (corresponding to FIG. 23).

首先，係如同圖29(a)中所示一般，準備平板狀之金屬基板31。作為此金屬基板31，係使用具有750MPa~1100MPa或者是850MPa~1100MPa之拉張強度者，例如，係可使用由卡遜系合金(Cu-Ni-Si)、鎳錫銅合金(Cu-Ni-Sn)、鈦銅合金(Cu-Ti)等之銅合金所成的基板。另外，金屬基板31，較理想，係使用對於其之兩面而進行脫脂等並施加了洗淨處理者。 First, as shown in FIG. 29 (a), a flat metal substrate 31 is prepared. As the metal substrate 31, those having a tensile strength of 750 MPa to 1100 MPa or 850 MPa to 1100 MPa are used, and for example, a Carson-based alloy (Cu-Ni-Si), a nickel-tin-copper alloy (Cu-Ni- A substrate made of a copper alloy such as Sn) and a titanium-copper alloy (Cu-Ti). The metal substrate 31 is preferably one that has been subjected to degreasing or the like on both sides thereof and subjected to a cleaning treatment.

接著，在金屬基板31之表背面全體，分別塗布感光性光阻32a、33a，並使其乾燥(圖29(b))。另 外，作為感光性光阻32a、33a，係可使用先前技術所公知之物。 Next, the entire surface of the metal substrate 31 is coated with photosensitive resists 32a and 33a and dried (FIG. 29 (b)). another In addition, as the photosensitive resists 32a and 33a, those known in the prior art can be used.

接著，隔著光罩來對此金屬基板31進行曝光並進行顯像，藉由此，來形成具備有所期望之開口部32b、33b之蝕刻用光阻層32、33(圖29(c))。 Next, this metal substrate 31 is exposed and developed through a photomask, thereby forming photoresist layers 32 and 33 for etching having desired openings 32b and 33b (FIG. 29 (c)). ).

接著，將蝕刻用光阻層32、33作為耐腐蝕膜，而藉由腐蝕液來對於金屬基板31施加蝕刻(圖29(d))。藉由此，係形成晶粒墊11以及複數之導線部12A、12B的外形。腐蝕液，係可因應於所使用之金屬基板31的材質來適宜作選擇，例如，當作為金屬基板31而使用銅合金的情況時，通常，係可使用氯化鐵水溶液，並從金屬基板31之兩面起來藉由噴霧蝕刻而進行之。例如，與第1實施形態之情況相同的，係亦可對於金屬基板31而一次一面地來進行2個階段之噴霧蝕刻。 Next, using the photoresist layers 32 and 33 for etching as corrosion-resistant films, the metal substrate 31 is etched with an etching solution (FIG. 29 (d)). As a result, the outer shape of the die pad 11 and the plurality of lead portions 12A and 12B is formed. The etchant can be appropriately selected according to the material of the metal substrate 31 to be used. For example, when a copper alloy is used as the metal substrate 31, in general, an aqueous ferric chloride solution can be used. Both sides are made by spray etching. For example, as in the case of the first embodiment, the metal substrate 31 may be spray-etched in two stages one at a time.

之後，將蝕刻用光阻層32、33剝離並除去(圖29(e))。 Thereafter, the photoresist layers 32 and 33 for etching are peeled and removed (FIG. 29 (e)).

接著，為了將接合打線22和內部端子15之間的密著性提昇，而對於內部端子15施加電鍍處理，並形成電鍍部25(圖29(f))。於此情況，所選擇之電鍍種，只要是能夠確保有與接合打線22之間的密著性者，則係並不對其之種類作限定，但是，例如，係可為Ag或Au等之單層電鍍，亦可為將Ni/Pd或者是Ni/Pd/Au依此順序來作了層積的複數層電鍍。又，電鍍部25，係可僅對於導線部12A、12B中之與接合打線22之間的連 接部作施加，亦可對於導線框架10F之全面作施加。 Next, in order to improve the adhesion between the bonding wire 22 and the internal terminal 15, a plating process is applied to the internal terminal 15 and a plating portion 25 is formed (FIG. 29 (f)). In this case, as long as the selected plating type can ensure the adhesion with the bonding wire 22, the type is not limited, but, for example, it can be Ag or Au, etc. The layer plating may be a plurality of layers of Ni / Pd or Ni / Pd / Au laminated in this order. In addition, the plating portion 25 is only applicable to the connection between the lead portions 12A and 12B and the bonding wire 22. The connection portion is applied, and the entire lead frame 10F can also be applied.

如此這般，而能夠得到如圖22~圖26中所示之導線框架10F。 In this way, a lead frame 10F as shown in FIGS. 22 to 26 can be obtained.

半導體裝置之製造方法 Manufacturing method of semiconductor device

接下來，針對圖27以及圖28中所示之半導體裝置20F之製造方法，使用圖30(a)~(e)來作說明。 Next, the manufacturing method of the semiconductor device 20F shown in FIGS. 27 and 28 will be described using FIGS. 30 (a) to (e).

首先，如同上述一般，藉由圖29(a)~(f)中所示之方法，來製作導線框架10F。 First, as described above, the lead frame 10F is manufactured by the method shown in FIGS. 29 (a) to (f).

接著，在導線框架10F之晶粒墊11上，搭載半導體元件21。於此情況，例如係使用黏晶糊等之接著劑24，而將半導體元件21載置在晶粒墊11上並作固定(黏晶工程)(圖30(b))。 Next, a semiconductor element 21 is mounted on the die pad 11 of the lead frame 10F. In this case, for example, an adhesive 24 such as a sticky paste is used, and the semiconductor element 21 is placed on the die pad 11 and fixed (sticky process) (FIG. 30 (b)).

接著，將半導體元件21之各電極21a和各導線部12A、12B之電鍍部25(內部端子15)分別藉由接合打線(連接構件)22而相互作電性連接(打線接合工程)(圖30(c))。 Next, the electrodes 21a of the semiconductor element 21 and the plating portions 25 (internal terminals 15) of the lead portions 12A and 12B are electrically connected to each other by bonding wires (connecting members) 22 (wire bonding process) (FIG. 30) (c)).

此時，係將導線框架10F載置在打線接合裝置之加熱塊36上。接著，藉由加熱塊36，來從導線部12A之內導線51以及導線部12B之內導線61之背面側來進行加熱。與此同時地，一面經由打線接合裝置之毛細管(未圖示)來施加超音波，一面將半導體元件21之各電極21a和各外周導線部12A、12B之電鍍部25分別使用接合打線22而作電性連接。 At this time, the lead frame 10F is placed on the heating block 36 of the wire bonding device. Next, the heating block 36 is used to heat from the back side of the lead 51 in the lead portion 12A and the lead 61 in the lead portion 12B. At the same time, while applying an ultrasonic wave through a capillary (not shown) of the wire bonding device, each electrode 21a of the semiconductor element 21 and the plating portion 25 of each of the outer peripheral lead portions 12A and 12B were each made by bonding wire 22 Electrical connection.

於此情況，導線部12A之內導線51以及導線部12B之內導線61，係分別具備有平坦之背面，藉由此，係能夠將導線部12A、12B對於加熱塊36而安定地作載置。藉由此，係成為能夠將接合打線22對於電鍍部25而安定地作連接。 In this case, the lead 51 in the lead portion 12A and the lead 61 in the lead portion 12B are each provided with a flat back surface, so that the lead portions 12A and 12B can be stably placed on the heating block 36. . Thereby, the bonding wire 22 can be connected to the plating part 25 stably.

接著，藉由對於導線框架10F而將熱硬化性樹脂或熱可塑性樹脂作射出成形或者是轉移成形，來形成密封樹脂23(圖30(d))。如此這般，來將導線框架10F、半導體元件21、導線部12A、12B以及接合打線22作密封。 Next, the lead frame 10F is formed by injection molding or transfer molding of a thermosetting resin or a thermoplastic resin to form the sealing resin 23 (FIG. 30 (d)). In this way, the lead frame 10F, the semiconductor element 21, the lead portions 12A, 12B, and the bonding wire 22 are sealed.

之後，藉由對於各半導體元件21間之密封樹脂23進行切割，來將導線框架10F個別分離成各單位導線框架10a(參考圖22)。此時，例如係亦可一面使由鑽石砥石所成之刃(未圖示)旋轉，一面將各單位導線框架10a間之導線框架10F以及密封樹脂23切斷。 Thereafter, the sealing resin 23 between the semiconductor elements 21 is cut to individually separate the lead frame 10F into each unit lead frame 10a (see FIG. 22). At this time, for example, the lead frame 10F and the sealing resin 23 between the unit lead frames 10a may be cut while rotating a blade (not shown) made of diamond vermiculite.

如此這般，而能夠得到如圖27以及圖28中所示之半導體裝置20f(圖30(e))。 In this way, a semiconductor device 20f as shown in FIG. 27 and FIG. 28 can be obtained (FIG. 30 (e)).

另外，在本實施形態中，導線框架10F，係由具有750MPa~1100MPa或者是850MPa~1100MPa之拉張強度的金屬材料所構成，各單位導線框架10a之導線部12A、12B中的支持導線13之近旁部分55的寬幅，係成為60μm~90μm或者是75μm~90μm，並且該近旁部分55之厚度，係成為50μm~75μm或者是60μm~75μm。藉由此，由於導線部12A、12B之強度降低的情形係被作抑 制，因此，例如在上述之半導體裝置20F的製造工程中，係能夠防止在導線部12A、12B處產生歪斜或彎曲等之變形的情況。其結果，係能夠將相鄰接之導線部12A和導線部12B間之間隔d(節距)縮窄，而能夠將半導體裝置20F之外部端子17A、17B的數量(銷數)增加。具體而言，相較於先前技術之半導體裝置，係成為能夠將導線部12A、12B之節距作10%以上之縮窄。例如，當半導體裝置20F之尺寸為14mm×14mm的情況時，係可將外部端子17A、17B之數量(銷數)增加至200銷以上。 In addition, in this embodiment, the lead frame 10F is made of a metal material having a tensile strength of 750 MPa to 1100 MPa or 850 MPa to 1100 MPa. Among the lead portions 12A and 12B of each unit lead frame 10a, the support lead 13 is formed. The width of the near portion 55 is 60 μm to 90 μm or 75 μm to 90 μm, and the thickness of the near portion 55 is 50 μm to 75 μm or 60 μm to 75 μm. As a result, the situation where the strength of the lead portions 12A and 12B is reduced is suppressed. Therefore, for example, in the manufacturing process of the semiconductor device 20F described above, it is possible to prevent deformation such as distortion or bending at the lead portions 12A and 12B. As a result, the distance d (pitch) between the adjacent lead portions 12A and 12B can be reduced, and the number (pins) of the external terminals 17A and 17B of the semiconductor device 20F can be increased. Specifically, compared with the semiconductor device of the prior art, the pitch of the lead portions 12A and 12B can be reduced by more than 10%. For example, when the size of the semiconductor device 20F is 14 mm × 14 mm, the number (pin number) of the external terminals 17A and 17B can be increased to 200 pins or more.

又，就算是在將相鄰接之導線部12A、12B之間的間隔作了縮窄的情況時，也能夠對於導線部12A、12B之強度降低的情形作抑制，而能夠防止導線部12A、12B產生變形並在外部端子17A、17B處發生位置偏移的問題。藉由此，係能夠將導線框架10F之良率提高。 In addition, even when the interval between the adjacent lead portions 12A and 12B is narrowed, it is possible to suppress the decrease in the strength of the lead portions 12A and 12B and prevent the lead portions 12A and 12A. 12B has a problem that a deformation occurs and a position shift occurs at the external terminals 17A and 17B. Thereby, the yield of the lead frame 10F can be improved.

進而，藉由將導線部12A、12B之強度提高，由於係能夠將導線部12A、12B之長度增長，因此係能夠使內部端子15對於晶粒墊11而更為接近。藉由此，係能夠減少高價之接合打線22的使用量，而能夠將導線框架10F之製造成本降低。 Furthermore, by increasing the strength of the lead portions 12A and 12B, since the length of the lead portions 12A and 12B can be increased, the internal terminal 15 can be made closer to the die pad 11. As a result, the amount of expensive bonding wires 22 to be used can be reduced, and the manufacturing cost of the lead frame 10F can be reduced.

另外，在上述實施形態中，係以將導線部12A和導線部12B交互地作配置的情況為例來作了說明。然而，係並不被限定於此，導線框架10F，係亦可具備相互具有相同之長度的複數之導線部(QFN型態)。 Moreover, in the said embodiment, the case where the lead wire part 12A and the lead wire part 12B are arrange | positioned alternately was demonstrated as an example. However, the system is not limited to this, and the lead frame 10F may include a plurality of lead portions (QFN type) having the same length.

進而，在上述實施形態中，係以將內側外部 端子17A以及外側外部端子17B以交錯狀來配列成2列的情況為例來作了說明，但是，係並不被限定於此，亦可將外部端子配置為3列以上。 Furthermore, in the above-mentioned embodiment, the inside and outside The terminal 17A and the outer external terminal 17B are described as an example in which two terminals are arranged in a staggered pattern, but the system is not limited to this, and the external terminals may be arranged in three or more columns.

〔實施例〕 [Example]

接著，針對在本實施形態中之具體性實施例作說明。 Next, specific examples in this embodiment will be described.

(實施例1) (Example 1)

製作了以由本實施形態所致之構成而成的導線框架10F(實施例1)。於此情況，係準備了含有3.75質量%之Ni、0.9質量%之Si、0.5質量%之Zn、0.15質量%之Sn並且殘餘部分為由銅以及不可避免之雜質所成的銅合金(古河電工股份有限公司製，商品名稱EFTEC-98S)之金屬基板31。此金屬基板31之厚度係為200μm，金屬基板31之拉張強度係為860MPa。另外，金屬基板31之拉張強度，係藉由將金屬基板31裁斷成寬幅20mm，並基於JIS Z2201來製作試驗片，再使用拉張試驗機，來作了測定。藉由將此金屬基板31切斷成300mm×100mm之大小並進行蝕刻加工，而得到了250mm×70mm之大小的導線框架10F(實施例1)。在前述蝕刻加工中，係從金屬基板之兩面來進行噴霧蝕刻(蝕刻工程)，之後，藉由鹼性水溶液來將光阻藉由噴霧方式而剝離(光阻剝離工程)，再以噴霧方式來進行了最終洗淨(最終水洗工程)。在上 述3個的工程中之噴霧時間，係設為總計10分鐘，噴霧壓力係設為0.2MPa。所得到的導線框架，係設為能夠配置56個的晶片之形狀(56面分割)，每一面的導線部之根數，係設為156根。又，將各導線部12A、12B中之支持導線13之近旁部分55的寬幅分別設為75μm，並將近旁部分55之厚度分別設為60μm。 A lead frame 10F having a structure according to this embodiment (Example 1) was produced. In this case, a copper alloy (Furukawa Electric) containing 3.75% by mass of Ni, 0.9% by mass of Si, 0.5% by mass of Zn, and 0.15% by mass of Sn was prepared and the remainder was made of copper and unavoidable impurities. Co., Ltd., trade name EFTEC-98S). The thickness of the metal substrate 31 is 200 μm, and the tensile strength of the metal substrate 31 is 860 MPa. The tensile strength of the metal substrate 31 was measured by cutting the metal substrate 31 to a width of 20 mm and preparing a test piece based on JIS Z2201, and then using a tensile tester. By cutting this metal substrate 31 to a size of 300 mm × 100 mm and performing an etching process, a lead frame 10F having a size of 250 mm × 70 mm was obtained (Example 1). In the aforementioned etching process, spray etching (etching process) is performed from both sides of the metal substrate, and thereafter, the photoresist is peeled off by a spray method using an alkaline aqueous solution (photoresist peeling process), and then sprayed. Final washing was performed (final water washing process). above The spraying time in the three processes described above was set to a total of 10 minutes, and the spraying pressure was set to 0.2 MPa. The obtained lead frame was shaped so that 56 chips could be arranged (56 plane divisions), and the number of lead portions per side was set to 156. The width of the near portion 55 of the supporting lead 13 in each of the lead portions 12A and 12B is set to 75 μm, and the thickness of the near portion 55 is set to 60 μm.

(實施例2) (Example 2)

金屬基板31之拉張強度係為780MPa，將各導線部12A、12B中之支持導線13之近旁部分55的寬幅分別設為60μm，並將近旁部分55之厚度分別設為50μml，除此之外，係與實施例1相同的，而製作了與實施例1相同形狀之導線框架。 The tensile strength of the metal substrate 31 is 780 MPa. The width of the near portion 55 of the support wire 13 in each of the lead portions 12A and 12B is set to 60 μm, and the thickness of the near portion 55 is set to 50 μml. In addition, a lead frame having the same shape as that of Example 1 was produced in the same manner as in Example 1.

〔比較例1〕 [Comparative Example 1]

作為金屬基板之材料，係使用了含有3.0質量%之Ni、0.65質量%之Si、0.15質量%之Mg並且殘餘部分為由銅以及不可避免之雜質所成的銅合金(JX日礦日石金屬股份有限公司製，商品名稱C7025 1/2H)，除此之外，與實施例1相同的，而製作了與實施例1相同形狀之導線框架。在對於該金屬基板之拉張強度作了測定後，其結果，係為726MPa。 As the material of the metal substrate, a copper alloy (JX Nippon Nissei Metal) containing 3.0% by mass of Ni, 0.65% by mass of Si, and 0.15% by mass of Mg was used, and the remainder was made of copper and inevitable impurities. Co., Ltd., product name: C7025 1 / 2H), except that the lead frame was the same as in Example 1, and a lead frame with the same shape as in Example 1 was produced. The tensile strength of this metal substrate was measured. As a result, it was 726 MPa.

針對上述3種類之導線框架(實施例1、實施例2以及比較例1)，分別實施了是否會在導線部處產生 變形之試驗。 Regarding the three types of lead frames (Example 1, Example 2, and Comparative Example 1), whether or not the lead frames are generated at the lead portions are implemented. Deformation test.

此試驗方法，係藉由判定在製作各導線框架的期間中是否於導線部處產生有變形一事，來實施之。亦即是，係藉由在前述蝕刻工程、光阻剝離工程、最終水洗工程中而使其受到由噴霧所致之衝擊，來確認了在受到衝擊的部位處是否具備有所期望之強度。 This test method is implemented by determining whether or not a deformation occurs at the lead portion during the production of each lead frame. In other words, it was confirmed whether the desired strength was obtained at the impacted part by subjecting it to an impact caused by spray in the aforementioned etching process, photoresist peeling process, and final water washing process.

針對各導線框架，係對於在內導線處所具備之外部端子近旁以及支持導線的變形作了計測。作為此計測方法，係使用由金屬顯微鏡所進行之焦點深度計測，並對相對於導線框架之板厚方向的產生變形之高度作了計測。另外，當前述產生變形之高度係為就算是以目視來對於外觀作檢查也難以判定出來的30μm以下的情況時，係判斷為並未產生變形。 For each lead frame, the deformations of the outer terminals near the inner lead and the supporting lead were measured. As this measurement method, a focal depth measurement by a metal microscope was used, and the height of deformation in the thickness direction of the lead frame was measured. In addition, when the height at which the deformation occurs is 30 μm or less, which is difficult to determine even by visual inspection of the appearance, it is determined that no deformation has occurred.

另外，在實施例1、實施例2以及比較例1之任一者中，均係製作了10枚的導線框架。針對所製作出之各個的導線框架，而對於產生有變形之導線部的根數作測定，並算出了在每一枚之導線框架之平均的產生了變形之根數。進而，根據所算出了在每一枚之導線框架之平均的產生了變形之根數，來算出了在每一晶片(每一分割面)之平均的產生了變形之導線部之根數。將此結果展示於表1中。 In addition, in any of Example 1, Example 2, and Comparative Example 1, 10 lead frames were produced. For each of the produced lead frames, the number of deformed lead portions was measured, and the average number of deformed roots was calculated for each lead frame. Furthermore, based on the calculated number of deformed lead frames in each lead frame, the average number of deformed lead portions per wafer (each divided surface) was calculated. The results are shown in Table 1.

其結果，針對實施例1以及實施例2之導線框架10F，在導線部12A、12B處係並未發生有變形。相對於此，針對比較例1之導線框架，係於其之一部分處發生了變形。 As a result, the lead frames 10F of Examples 1 and 2 were not deformed at the lead portions 12A and 12B. In contrast, the lead frame of Comparative Example 1 was deformed at a portion thereof.

(第6實施形態) (Sixth embodiment)

接著，參考圖31~圖34，對本發明之第6實施形態作說明。圖31~圖34，係為對於本發明之第6實施形態作展示者。在圖31~圖34中，連接環14之半蝕刻部(凹部)，係並非為遍佈連接環14之全周地來設置，而是沿著連接環14而規則性地設置，在各半蝕刻部之間，係被形成有厚壁部28a。在圖31~圖34中，針對與第1~第5實施形態相同的部份，係附加相同之元件符號，並省略詳細說明。 Next, a sixth embodiment of the present invention will be described with reference to FIGS. 31 to 34. Figures 31 to 34 show the sixth embodiment of the present invention. In FIGS. 31 to 34, the half-etched portions (concave portions) of the connection ring 14 are not provided throughout the entire circumference of the connection ring 14, but are provided regularly along the connection ring 14 and etched in each half. Between the parts, a thick-walled part 28a is formed. In FIGS. 31 to 34, the same components as those in the first to fifth embodiments are denoted by the same reference numerals, and detailed descriptions are omitted.

在圖31以及圖32(a)、(b)所示之導線框架10G中，連接環14，係被設置在導線部12A、12B之內導線51的前端側處，並以包圍晶粒墊11的方式而被作 配置。在連接環14之外側周緣部(支持導線13側周緣部)處，係被連結有導線部12A、12B之內導線51。又，係從連接環14起朝向內側(晶粒墊11側)地而延伸出有連結條19。於此情況，連接環14，雖係被與全部的內導線51作連結而被作支持，但是，係並不被限定於此，連接環14係亦可僅被與一部分之內導線51作連結並被作支持。 In the lead frame 10G shown in FIGS. 31 and 32 (a) and (b), the connection ring 14 is provided at the front end side of the lead 51 within the lead portions 12A and 12B to surround the die pad 11. By the way Configuration. The inner lead 51 of the lead portions 12A and 12B is connected to the outer peripheral edge portion of the connection ring 14 (the peripheral peripheral edge portion supporting the lead 13). A connecting bar 19 extends from the connecting ring 14 toward the inside (the die pad 11 side). In this case, although the connection ring 14 is supported by being connected to all the inner conductors 51, the connection ring 14 is not limited to this, and the connection ring 14 may be connected to only some of the inner conductors 51. And was supported.

在連接環14之表面的各內導線51之前端近旁處，係分別被形成有凹部14c。各凹部14c，係為藉由半蝕刻所形成者，而在厚度方向上並不被作貫通地來具有一定之深度。另外，各凹部14c，係被形成於連接環14之寬幅方向略中央部處。 In the vicinity of the front end of each inner lead 51 on the surface of the connection ring 14, recesses 14c are formed respectively. Each of the recesses 14c is formed by half-etching and has a certain depth without being penetrated in the thickness direction. In addition, each recessed portion 14 c is formed at a substantially central portion in the width direction of the connection ring 14.

又，在相互鄰接之凹部14c之間，係被形成有厚壁部28a。亦即是，凹部14c和厚壁部28a，係沿著連接環14之長邊方向而被交互作配置。於此情況，厚壁部28a，係並不被作半蝕刻地而具備有與晶粒墊11以及支持導線13相同之厚度。又，連結條19，係在晶粒墊11之4邊的全部處，分別各被連結有2根。晶粒墊11，係藉由連接環14以及連結條19而被作支持。另一方面，在晶粒墊11之四角隅處，由於係並未被設置有懸吊導線，因此，在晶粒墊11之四角隅近旁處，係亦可配置導線部12A、12B。因此，相較於將晶粒墊11藉由懸吊導線來作支持的情況，係能夠增加導線部12A、12B之根數。 A thick-walled portion 28a is formed between the adjacent concave portions 14c. That is, the recessed portion 14 c and the thick-walled portion 28 a are alternately arranged along the longitudinal direction of the connection ring 14. In this case, the thick portion 28 a is provided with the same thickness as that of the die pad 11 and the support wire 13 without being semi-etched. Further, two connecting strips 19 are connected to each of the four sides of the die pad 11, and two are connected. The die pad 11 is supported by a connecting ring 14 and a connecting bar 19. On the other hand, since the lead wires of the die pad 11 are not provided with hanging wires, the lead wires 12A and 12B may be arranged near the corner of the die pad 11. Therefore, the number of lead portions 12A and 12B can be increased compared to a case where the die pad 11 is supported by a hanging wire.

在本實施形態中，於製作半導體裝置20G (參考圖33)時，連接環14中之各凹部14c之周邊的堤部、和連接環14中之位置在各凹部14c之間的厚壁部28a，係同時地被開始蝕刻，但是，在厚壁部28a之除去中，係相較於被設置有各凹部14c之區域而更耗費時間，藉由此，係能夠對於連接環14自身之蝕刻的進行作調整。 In this embodiment, a semiconductor device 20G is manufactured. (Refer to FIG. 33) At the same time, the bank portion around each recessed portion 14c in the connection ring 14 and the thick portion 28a in the connection ring 14 between the recessed portions 14c were simultaneously etched. Removal of the thick-walled portion 28a takes more time than the area in which each recessed portion 14c is provided, so that the etching of the connection ring 14 itself can be adjusted.

亦即是，在從導線框架10G之背面側起而將連接環14作蝕刻除去時(參考圖7(e))，係預先在導線框架10以及密封樹脂23之背面的蝕刻用光阻層34之與連接環14相對應的位置處，設置開口部34a。之後，藉由從該開口部34a所進入之腐蝕液，而將連接環14中之各凹部14c和厚壁部28a適度地溶解並除去。於此情況，由於在連接環14之表面上係被設置有凹部14c，因此，從開口部34a所進入的腐蝕液，係並不會將導線部12A、12B作必要以上之溶解，而能夠適當地將連接環14之全體除去。 That is, when the connection ring 14 is etched away from the back surface side of the lead frame 10G (refer to FIG. 7 (e)), the photoresist layer 34 for etching is formed on the back surface of the lead frame 10 and the sealing resin 23 in advance. An opening portion 34 a is provided at a position corresponding to the connection ring 14. Thereafter, each of the recessed portions 14c and the thick-walled portions 28a in the connection ring 14 are appropriately dissolved and removed by the etching solution entering through the opening portion 34a. In this case, since the recessed portion 14c is provided on the surface of the connection ring 14, the etching solution entering from the opening portion 34a does not dissolve the lead portions 12A and 12B more than necessary, and can be appropriately performed. Remove the entire connecting ring 14 from the ground.

另外，在本實施形態中，凹部14c，雖係被設置在全部的內導線51之前端近旁處，但是，係並不被限定於此，而亦可僅被設置在一部分之內導線51之前端近旁處。 In addition, in the present embodiment, although the recessed portion 14c is provided near the front ends of all the inner leads 51, it is not limited to this, but may be provided only at the front ends of some of the inner leads 51. Nearby.

如此這般，藉由沿著連接環14而將凹部14c以一定之間隔來設置為點狀，並於各凹部14c之間形成有厚壁部28a，在將連接環14作蝕刻除去時，係能夠對於腐蝕液之進入和溶解作適宜的調整。 In this way, the recessed portions 14c are arranged in a dot shape at a certain interval along the connection ring 14, and a thick wall portion 28a is formed between each recessed portion 14c. When the connection ring 14 is removed by etching, Can make appropriate adjustments for the entry and dissolution of corrosive liquid.

圖34中所示之半導體裝置20H，係對於本實施形態之變形例作展示，並對於並未將厚壁部28a完全除去而殘留於半導體裝置20H內部的形態作展示。此半導體裝置20H，係為由圖31以及圖32(a)、(b)中所示之導線框架10G所製作者，厚壁部28a，係並未被完全除去地而殘留，並構成第2端子部。此厚壁部28a，係沿著晶粒墊11之周圍4邊(於圖34中，係為與X方向或Y方向相平行之4邊)的全部，而相互空出有間隔地來作配列。 The semiconductor device 20H shown in FIG. 34 shows a modification of the present embodiment, and shows a form that remains inside the semiconductor device 20H without completely removing the thick portion 28a. This semiconductor device 20H is produced by the lead frame 10G shown in FIGS. 31 and 32 (a) and (b), and the thick portion 28a is left without being completely removed, and constitutes the second Terminal section. This thick-walled portion 28a is arranged along all four sides of the die pad 11 (in FIG. 34, it is four sides parallel to the X direction or the Y direction), and is arranged to be spaced apart from each other. .

於圖34中，厚壁部28a，由於係由連接環14之一部分所形成，因此係沿著將各內導線51之前端近旁作連結的直線而被作配置。在圖34中，複數之厚壁部28a，係在晶粒墊11和內導線51之前端之間的區域中，而被配置為矩形狀。 In FIG. 34, since the thick-walled portion 28a is formed by a part of the connecting ring 14, the thick-walled portion 28a is arranged along a straight line connecting the front ends of the inner conductors 51. In FIG. 34, a plurality of thick-walled portions 28a are arranged in a rectangular shape in a region between the die pad 11 and the front end of the inner lead 51.

於此情況，導線框架10G的連接環14中之各凹部14c的周邊區域，係在藉由密封樹脂23而被作了樹脂密封之後，從背面側起來藉由蝕刻而除去。另一方面，各厚壁部28a，係從晶粒墊11、導線部12A、12B以及其他之厚壁部28a而分離，並與此些之構件相互電性獨立，而構成第2端子部。此厚壁部28a，係並不被作半蝕刻地而具備有與晶粒墊11相同之厚度。進而，在厚壁部28a的背面，係形成有被與外部之安裝基板(未圖示)作電性連接之外部端子17C。又，在厚壁部28a之表面上，係設置有用以提昇其與接合打線22之間的密著性之電鍍部 25，並分別被連接有接合打線22。 In this case, the peripheral region of each recessed portion 14c in the connection ring 14 of the lead frame 10G is resin-sealed by the sealing resin 23 and then removed by etching from the back side. On the other hand, each thick-walled portion 28a is separated from the die pad 11, the lead portions 12A, 12B, and other thick-walled portions 28a, and these members are electrically independent from each other to constitute a second terminal portion. The thick portion 28a is provided with the same thickness as that of the die pad 11 without being semi-etched. Furthermore, an external terminal 17C electrically connected to an external mounting substrate (not shown) is formed on the back surface of the thick portion 28a. In addition, a plating portion is provided on the surface of the thick-walled portion 28a to improve the adhesion between the thick-walled portion 28a and the bonding wire 22. 25, and the bonding wires 22 are connected respectively.

又，伴隨著連接環14中之除了厚壁部28a以外的部份被除去一事，在密封樹脂23之背面中的導線部12A、12B和晶粒墊11之間之區域處，係被形成有凹部27。 In addition, with the removal of portions other than the thick portion 28 a in the connection ring 14, a region between the lead portions 12A, 12B and the die pad 11 in the back surface of the sealing resin 23 is formed. Concave portion 27.

若依據圖34中所示之形態，則在製作半導體裝置20H時，連接環14之一部分係被除去，連接環14中之並未被除去的部份係被相互個別地分離並被形成為構成第2端子部之厚壁部28a。如此這般，藉由被形成有多數之厚壁部28a，係能夠將與外部之安裝基板作連接的端子部之數量(銷數)增加，而能夠實現半導體裝置20之更進一步的高密度化。 According to the form shown in FIG. 34, when the semiconductor device 20H is manufactured, a part of the connection ring 14 is removed, and parts of the connection ring 14 that have not been removed are separated from each other and formed into a structure. The thick portion 28a of the second terminal portion. In this way, by forming a large number of thick-walled portions 28a, the number of terminal portions (pin numbers) that can be connected to an external mounting substrate is increased, and the semiconductor device 20 can be further densified. .

於圖34中，被殘留於半導體裝置20H內之厚壁部28a，係並非絕對需要作為外部端子(第2端子部)來使用。例如，殘留於半導體裝置20H內之厚壁部28a，係亦可發揮當對於半導體裝置20H施加有衝擊時而防止晶粒墊11周邊之變形的作用。或者是，厚壁部28a，係亦可藉由將露出於半導體裝置20H之背面的金屬部分增加，來發揮將半導體裝置20H之散熱性提昇的作用。 In FIG. 34, the thick-walled portion 28a remaining in the semiconductor device 20H is not absolutely required to be used as an external terminal (second terminal portion). For example, the thick-walled portion 28 a remaining in the semiconductor device 20H can also play a role in preventing deformation of the periphery of the die pad 11 when an impact is applied to the semiconductor device 20H. Alternatively, the thick-walled portion 28a can also increase the metal portion exposed on the back surface of the semiconductor device 20H, thereby improving the heat dissipation of the semiconductor device 20H.

另外，由本實施形態所致之導線框架10G之製造方法以及半導體裝置20G、20C之製造方法，係與由第1實施形態所致之導線框架10之製造方法(圖6(a)~(f))以及半導體裝置20之製造方法(圖7(a)~(f)))略相同。 In addition, the manufacturing method of the lead frame 10G according to this embodiment and the manufacturing methods of the semiconductor devices 20G and 20C are the same as the manufacturing method of the lead frame 10 according to the first embodiment (FIG. 6 (a) to (f) ) And the manufacturing method of the semiconductor device 20 (FIGS. 7 (a) to (f))) are slightly the same.

Claims (12)

一種導線框架，係為半導體裝置用之導線框架，其特徵為，係具備有：晶粒墊，係搭載有半導體元件；和複數之外周導線部，係被設置於前述晶粒墊之周圍，並分別包含有第1端子部；和連接環，係被配置在前述晶粒墊和前述外周導線部之間，並包圍前述晶粒墊；和複數之內側導線部，係藉由前述連接環而被支持，並分別包含有第2端子部，前述複數之內側導線部，係包含有長內側導線部和短內側導線部，前述長內側導線部和前述短內側導線部，係沿著前述連接環而被交互作配置，前述連接環，係具備有身為前述半導體元件所被搭載之側之面的表面、和身為前述表面之相反側之面的背面，在前述連接環之前述表面處，係被形成有凹溝或複數之凹部。A lead frame is a lead frame for a semiconductor device, and is characterized in that it is provided with: a die pad, on which a semiconductor element is mounted; and a plurality of outer peripheral lead portions, which are provided around the die pad, and Each includes a first terminal portion; and a connection ring, which is disposed between the die pad and the outer peripheral wire portion, and surrounds the die pad; and a plurality of inner lead portions, which are covered by the connection ring. Supported, and each includes a second terminal portion, the plurality of inner conductor portions includes a long inner conductor portion and a short inner conductor portion, and the long inner conductor portion and the short inner conductor portion are along the connecting ring. The connection ring is arranged alternately. The connection ring includes a surface that is a surface on the side on which the semiconductor element is mounted, and a back surface that is a surface on the opposite side of the surface. A groove or a plurality of recesses are formed. 如申請專利範圍第1項所記載之導線框架，其中，前述複數之內側導線部，係從前述連接環之內側以及外側的雙方而延伸。The lead frame as described in the scope of claim 1, wherein the plurality of inner lead portions extend from both the inner side and the outer side of the connection ring. 如申請專利範圍第2項所記載之導線框架，其中，前述複數之內側導線部中的從前述連接環之內側所延伸之前述短內側導線部、和從前述連接環之外側所延伸之前述長內側導線部，係隔著前述連接環而被配置在互為相反側之位置。The lead frame according to item 2 of the scope of patent application, wherein among the plurality of inner lead portions, the short inner lead portion extending from the inner side of the connecting ring and the long lead extending from the outer side of the connecting ring The inner lead portion is disposed at positions opposite to each other via the connection ring. 如申請專利範圍第1項所記載之導線框架，其中，前述內側導線部，係具備有被與前述連接環作連結之連接導線，前述連接導線，係從背面側起而作了厚度薄化。According to the lead frame described in the scope of claim 1, the inner lead portion is provided with a connecting lead connected to the connecting ring, and the connecting lead is thinned from the back side. 如申請專利範圍第1項所記載之導線框架，其中，前述內側導線部，係具備有被與前述連接環作連結之連接導線，前述連接導線，係從表面側起而作了厚度薄化。The lead frame as described in the scope of claim 1, wherein the inner lead portion is provided with a connecting lead connected to the connecting ring, and the connecting lead is reduced in thickness from the surface side. 如申請專利範圍第1項所記載之導線框架，其中，前述複數之外周導線部，係包含有長外周導線部和短外周導線部，前述長外周導線部和前述短外周導線部係被交互配置，前述複數之內側導線部，係從前述連接環之至少外側而延伸，前述長外周導線部和前述短內側導線部係相互對向，前述短外周導線部和前述長內側導線部係相互對向。According to the lead frame described in the first scope of the patent application, the plurality of outer peripheral lead portions include a long outer lead portion and a short outer lead portion, and the long outer lead portion and the short outer lead portion are alternately arranged. The plurality of inner conductor portions extend from at least the outer side of the connection ring, the long outer conductor portion and the short inner conductor portion face each other, and the short outer conductor portion and the long inner conductor portion face each other. . 如申請專利範圍第1項所記載之導線框架，其中，係由具備有750Mpa~1100Mpa之拉張強度的金屬材料所構成。The lead frame according to item 1 of the scope of patent application, wherein the lead frame is made of a metal material having a tensile strength of 750Mpa to 1100Mpa. 一種半導體裝置，其特徵為，係具備有：晶粒墊；和複數之外周導線部，係被設置在前述晶粒墊之周圍，並分別包含有第1端子部；和複數之第2端子部，係被配置在前述晶粒墊和前述外周導線部之間，並從前述晶粒墊以及前述外周導線部而作了分離；和半導體元件，係被搭載於前述晶粒墊上；和連接構件，係將前述半導體元件和各外周導線部作電性連接，並且將前述半導體元件和各第2端子部作電性連接；和密封樹脂，係將前述晶粒墊和前述複數之外周導線部和前述複數之第2端子部和前述半導體元件以及前述連接構件作密封，前述複數之外周導線部，係包含有使前述第1端子部相對性地位置於內側之長外周導線部、和使前述第1端子部相對性地位置於外側之短外周導線部，前述長外周導線部和前述短外周導線部係被交互作配置，在前述密封樹脂的背面中之前述外周導線部與前述晶粒墊之間的區域處，係以包圍前述晶粒墊的方式而被形成有凹部，在前述凹部內，由前述密封樹脂之一部分所形成的突起部係突出。A semiconductor device comprising: a die pad; and a plurality of outer peripheral lead portions provided around the die pad and each including a first terminal portion; and a plurality of second terminal portions Is disposed between the die pad and the outer peripheral lead portion, and is separated from the die pad and the outer peripheral lead portion; and a semiconductor element is mounted on the die pad; and a connection member, The semiconductor element is electrically connected to each of the outer peripheral lead portions, and the semiconductor element is electrically connected to each of the second terminal portions; and a sealing resin is used to connect the die pad and the plurality of outer peripheral lead portions to the foregoing. The plurality of second terminal portions are sealed with the semiconductor element and the connection member, and the plurality of outer peripheral lead portions include a long outer peripheral lead portion in which the relative position of the first terminal portion is placed inside, and the first peripheral portion The terminal portion is a short outer peripheral wire portion which is positioned on the outside. The long outer peripheral wire portion and the short outer peripheral wire portion are alternately arranged, and are arranged on the back of the sealing resin. At a region between the sum of the outer circumferential conductor portion and the die pad, lines to surround the die pad is formed with a recess in the concave portion, the protrusion lines by a portion of the sealing resin is formed projecting. 一種半導體裝置，其特徵為，係具備有：晶粒墊；和複數之外周導線部，係被設置在前述晶粒墊之周圍，並分別包含有第1端子部；和複數之第2端子部，係被配置在前述晶粒墊和前述外周導線部之間，並從前述晶粒墊以及前述外周導線部而作了分離；和半導體元件，係被搭載於前述晶粒墊上；和連接構件，係將前述半導體元件和各外周導線部作電性連接，並且將前述半導體元件和各第2端子部作電性連接；和密封樹脂，係將前述晶粒墊和前述複數之外周導線部和前述複數之第2端子部和前述半導體元件以及前述連接構件作密封，前述複數之外周導線部，係包含有使前述第1端子部相對性地位置於內側之長外周導線部、和使前述第1端子部相對性地位置於外側之短外周導線部，前述長外周導線部和前述短外周導線部係被交互作配置，在前述密封樹脂的背面中之前述外周導線部與前述晶粒墊之間的區域處，係以包圍前述晶粒墊的方式而被形成有凹部，前述複數之第2端子部，係位置於前述凹部內。A semiconductor device comprising: a die pad; and a plurality of outer peripheral lead portions provided around the die pad and each including a first terminal portion; and a plurality of second terminal portions Is disposed between the die pad and the outer peripheral lead portion, and is separated from the die pad and the outer peripheral lead portion; and a semiconductor element is mounted on the die pad; and a connection member, The semiconductor element is electrically connected to each of the outer peripheral lead portions, and the semiconductor element is electrically connected to each of the second terminal portions; and a sealing resin is used to connect the die pad and the plurality of outer peripheral lead portions to the foregoing. The plurality of second terminal portions are sealed with the semiconductor element and the connection member, and the plurality of outer peripheral lead portions include a long outer peripheral lead portion in which the relative position of the first terminal portion is placed inside, and the first peripheral portion The terminal portion is a short outer peripheral wire portion which is positioned on the outside. The long outer peripheral wire portion and the short outer peripheral wire portion are alternately arranged, and are arranged on the back of the sealing resin. At a region between the periphery of the die pad and the lead portion of the outside, so as to surround the die pad based manner is formed with recessed portions, the second portion of the plurality of terminals, based on the position of the concave portion. 一種導線框架之製造方法，係為如申請專利範圍第1項所記載之導線框架之製造方法，其特徵為，係具備有：準備金屬基板之工程；和藉由對於前述金屬基板進行蝕刻加工，而在前述金屬基板上形成前述晶粒墊、前述外周導線部、前述連接環以及前述內側導線部之工程。A method for manufacturing a lead frame is the method for manufacturing a lead frame as described in item 1 of the scope of patent application, which is characterized by having: a process of preparing a metal substrate; and performing an etching process on the metal substrate, The process of forming the die pad, the outer peripheral wire portion, the connection ring, and the inner wire portion on the metal substrate. 一種半導體裝置之製造方法，其特徵為，係具備有：準備如申請專利範圍第1項所記載之導線框架之工程；和在前述導線框架之前述晶粒墊上搭載前述半導體元件之工程；和將前述半導體元件和各外周導線部藉由連接構件來作電性連接之工程；和將前述晶粒墊和前述複數之外周導線部和前述半導體元件以及前述連接構件藉由密封樹脂來作密封之工程；和藉由從前述導線框架之背面側來將前述連接環之至少一部分除去，而將前述複數之第2端子部分別個別地作分離之工程。A method of manufacturing a semiconductor device, comprising: a process of preparing a lead frame as described in item 1 of the scope of patent application; and a process of mounting the semiconductor element on the die pad of the lead frame; and A process for electrically connecting the semiconductor element and each peripheral wire portion with a connection member; and a process for sealing the die pad and the plurality of outer peripheral wire portions with the semiconductor element and the connection member with a sealing resin And removing at least a part of the connection ring from the back side of the lead frame, and separately separating the plurality of second terminal portions. 一種導線框架，係為半導體裝置用之導線框架，其特徵為，係具備有：晶粒墊，係搭載有半導體元件；和複數之導線部，係被設置於前述晶粒墊之周圍，並分別包含有第1端子部和從前述第1端子部起而朝向內側延伸之內導線；和連接環，係被設置在前述內導線之前端側處，並包圍前述晶粒墊，前述連接環，係藉由至少1個的前述內導線而被作支持，沿著前述連接環，而規則性地設置凹部，在各凹部之間，形成有厚壁部。A lead frame is a lead frame for a semiconductor device, and is characterized by comprising: a die pad, on which a semiconductor element is mounted; and a plurality of lead portions, which are provided around the die pad and are respectively A first terminal portion and an inner lead extending from the first terminal portion toward the inside are included; and a connection ring is provided at the front end side of the inner lead and surrounds the die pad, the connection ring, and Recesses are supported by at least one of the inner wires, and recesses are regularly provided along the connection ring, and thick-walled portions are formed between the recesses.
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