TW202006944A - 積體晶片 - Google Patents

積體晶片 Download PDF

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TW202006944A
TW202006944A TW107129328A TW107129328A TW202006944A TW 202006944 A TW202006944 A TW 202006944A TW 107129328 A TW107129328 A TW 107129328A TW 107129328 A TW107129328 A TW 107129328A TW 202006944 A TW202006944 A TW 202006944A
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Taiwan
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mesa
layer
bump
metal
etch stop
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TW107129328A
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TWI788404B (zh
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陳志彬
蔡嘉雄
劉銘棋
逸群 陳
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台灣積體電路製造股份有限公司
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Abstract

本申請的各種實施例涉及一種形成將III-V族元件結合到基底的積體晶片的方法以及所得積體晶片。在一些實施例中，所述方法包括：形成包括磊晶堆疊的晶片、位於所述磊晶堆疊上的金屬結構、及位於所述金屬結構與所述磊晶堆疊之間的擴散層；將晶片結合到基底，以使金屬結構位於所述基底與磊晶堆疊之間；以及向磊晶堆疊執行蝕刻以形成檯面結構，所述檯面結構具有與擴散層的側壁間隔開的側壁。金屬結構可例如為在進行結合之前圖案化的金屬凸塊，或者可例如為位於蝕刻停止層上的金屬層且穿過所述蝕刻停止層突出到擴散層的金屬層。

Description

積體晶片
本發明的實施例是有關於一種積體晶片。
在過去的幾十年中，以矽為基礎的半導體元件一直被當做標準。然而，以替代性材料為基礎的半導體元件由於與以矽為基礎的半導體元件相比具有優勢而受到越來越多的關注。舉例來說，以III-V族半導體材料為基礎的半導體元件由於與以矽為基礎的半導體元件相比具有高的電子遷移率（electron mobility）及直接帶隙（direct bandgap）而受到越來越多的關注。
儘管以替代性材料為基礎的半導體元件受到越來越多的關注，然而在技術上並不像以矽為基礎的半導體元件的技術那樣成熟。這樣一來，以替代性材料為基礎的半導體元件的應用受到的限制更大且成本更高。因此，可採用包括以矽與替代性材料二者為基礎的半導體元件的積體晶片來減輕以上擔憂。
在一些實施例中，本申請提供一種積體晶片，所述積體晶片包括：基底；檯面結構，位於所述基底上且包含半導體材料；凸塊結構，位於所述基底與所述檯面結構之間，其中所述凸塊結構包含導電材料；以及擴散層，凹陷到所述檯面結構中，位於所述凸塊結構與所述檯面結構之間，其中所述擴散層包含分別來自所述檯面結構及所述凸塊結構的半導體材料及導電材料，且所述擴散層的側壁從所述檯面結構的側壁間隔開。
在一些實施例中，本申請提供一種形成積體晶片的方法，所述方法包括：形成包括磊晶堆疊及位於所述磊晶堆疊上的第一金屬凸塊的晶片，其中所述第一金屬凸塊被定位到所述磊晶堆疊的檯面區域；在基底上形成第二金屬凸塊；在所述第一金屬凸塊與所述第二金屬凸塊相互接觸的介面處將所述晶片結合到所述基底；以及向所述晶片執行蝕刻，以在所述磊晶堆疊的所述檯面區域處界定檯面結構，其中所述檯面結構的側壁相對於所述第一金屬凸塊的側壁在側向上偏置。
在一些實施例中，本申請提供另一種形成積體晶片的方法，所述方法包括：形成包括磊晶堆疊、蝕刻停止層及金屬層的晶片，其中所述蝕刻停止層位於所述磊晶堆疊與所述金屬層之間；在基底上形成第一金屬凸塊；將所述晶片結合到所述基底，使得所述金屬層位於所述第一金屬凸塊與所述磊晶堆疊之間；向所述磊晶堆疊執行蝕刻，以界定檯面結構，其中所述蝕刻在所述蝕刻停止層上停止；將所述蝕刻停止層圖案化，以將所述檯面結構的圖案轉移到所述蝕刻停止層；以及將所述金屬層圖案化，以在所述第一金屬凸塊與所述檯面結構之間形成第二金屬凸塊。
本發明提供用於實作本發明的不同特徵的許多不同實施例或實例。以下闡述元件及排列的具體實例以簡化本公開內容。當然，這些僅為實例且不旨在進行限制。舉例來說，以下說明中將第一特徵形成在第二特徵“之上”或第二特徵“上”可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“之下（beneath）”、“下面（below）”、“下部的（lower）”、“上方（above）”、“上部的（upper）”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括元件在使用或操作中的不同取向。裝置可具有其他取向（旋轉90度或其他取向），且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
根據形成具有矽半導體元件及III-V族半導體元件二者的積體電路（integratd circuit，IC）晶片的方法，形成包括III-V族磊晶堆疊及金屬層的晶片。在晶片上形成矽基(silicon-based)互補金屬氧化物半導體（complementary metal-oxide-semiconductor，CMOS）元件，形成覆蓋矽基互補金屬氧化物半導體元件及所述晶片的內連線結構，且在所述內連線結構上形成晶片金屬凸塊。晶片被定位成使金屬層位於晶片金屬凸塊與III-V族磊晶堆疊之間且隨後經由所述晶片金屬凸塊結合到晶片的晶粒區(die region)。向晶片中執行乾式蝕刻（dry etch）以界定檯面結構（mesa structure），並進一步界定晶片金屬凸塊。檯面結構至少部分地界定個別III-V族半導體元件，所述個別III-V族半導體元件可例如為垂直空腔表面發射雷射器（vertical-cavity surface-emitting laser，VCSEL）或一些其他適合的元件。各晶片金屬凸塊分別用於各III-V族半導體元件，且將各所述III-V族半導體元件分別電耦合到鄰接的晶片金屬凸塊。執行濕式蝕刻（wet etch）以使晶片金屬凸塊縮小，且隨後將晶片分離成多個個別積體電路晶片。
所述方法的挑戰是來自金屬層的金屬擴散到磊晶堆疊中並形成難以被化學蝕刻的擴散層。舉例來說，擴散層可包括鎳、鍺、金、鎵、及砷的組合。因此，利用離子轟擊（ion bombardment）執行乾式蝕刻。然而，離子轟擊是髒亂的且造成所蝕刻的材料重新沉積(redeposition)在蝕刻製程室的側壁上及晶片凸塊的側壁上。所述重新沉積可能造成晶片凸塊的電短路，這可能造成低的製造良率（manufacturing yield）。此外，所述重新沉積可能降低蝕刻速率及/或可能對在蝕刻製程室中使用的其他晶片造成污染。另一挑戰是濕式蝕刻可能使晶片凸塊顯著縮小。通常，晶片凸塊包括個別的鎳/金區段(segment)及與所述鎳/金區段鄰接的個別的金區段。相對上，用於濕式蝕刻的蝕刻劑對金區段的蝕刻速率可比對鎳/金區段的蝕刻速率高，由此金區段的大小可能顯著減小。這反過來會造成高的電阻並對III-V族半導體元件的效能及功率效率（power efficiency）造成負面影響。
本申請的各種實施例涉及一種形成將III-V族元件結合到基底的積體晶片的方法、以及通過所述方法得到的所述積體晶片。在一些實施例中，所述方法包括：形成包括磊晶堆疊的晶片，在所述磊晶堆疊上形成金屬結構，並在所述金屬結構與所述磊晶堆疊之間形成擴散層；將晶片結合到基底，以使金屬結構在結合期間位於所述基底與磊晶堆疊之間；以及向磊晶堆疊的檯面區域中執行蝕刻，以形成側壁從擴散層間隔開的檯面結構。擴散層包含來自金屬結構的金屬，且還包含來自磊晶堆疊的半導體材料。
在一些實施例中，金屬結構是金屬凸塊，且所述形成晶片包括在進行結合之前通過金屬剝除製程（metal liftoff process）形成金屬結構。在一些實施例中，所述形成晶片包括在磊晶堆疊上沉積蝕刻停止層且將所述蝕刻停止層圖案化以形成被定位到檯面區域且從檯面區域的側邊界間隔開的開口。可例如採用蝕刻停止層作為所述蝕刻的蝕刻停止件。在其他實施例中，不形成蝕刻停止層。在金屬結構為金屬凸塊的一些實施例中，在進行結合之前通過在開口中進行金屬剝除製程來形成金屬結構。在一些實施例中，金屬結構為金屬層，且所述形成晶片包括在進行結合之前形成覆蓋蝕刻停止層且填充所述開口的金屬結構。在此種實施例中，在蝕刻之後，將金屬結構圖案化成金屬凸塊。
擴散層是通過來自金屬結構的金屬擴散到磊晶堆疊中而形成。通過使用金屬剝除製程形成金屬結構來作為金屬凸塊，所述金屬結構可僅限於在被定位到檯面區域且從所述檯面區域的側邊界間隔開的接觸介面處接觸磊晶堆疊。因此，金屬向磊晶堆疊中的擴散可僅限於接觸介面。此外，擴散層可定位形成到接觸介面且因此從檯面區域的側邊界間隔開。通過在蝕刻停止層上形成金屬結構來作為金屬層，所述蝕刻停止層可將金屬結構從磊晶堆疊部分地間隔開，以使所述金屬結構僅限於在所述蝕刻停止層的開口中的接觸介面處接觸磊晶堆疊。由於蝕刻停止層的開口被定位到檯面區域且從檯面區域的側邊界間隔開，因此接觸介面也被定位到檯面區域且從檯面區域的側邊界間隔開。因此，如上所述，金屬向磊晶堆疊中的擴散可僅限於接觸介面。此外，擴散層可定位形成到接觸介面且因此從檯面區域的側邊界間隔開。
通過形成從檯面區域的側邊界間隔開的擴散層，可在不蝕刻穿過擴散層的情況下執行所述蝕刻。這樣一來，檯面結構的側壁可形成為從擴散層間隔開。在一些實施例中，來自磊晶堆疊的半導體材料與來自金屬結構的金屬以使得擴散層難以通過濕蝕刻劑及/或化學蝕刻劑來蝕刻及/或移除的方式進行組合。通過形成從檯面區域的側邊界間隔開的擴散層，可通過濕蝕刻劑及/或化學蝕刻劑執行所述蝕刻。否則，可通過離子轟擊執行所述蝕刻。然而，由於來自離子的動能被轉移到所蝕刻的材料，因此離子轟擊比濕式蝕刻及/或化學蝕刻髒亂。舉例來說，所蝕刻的材料可能重新沉積且造成接墊及/或接觸件之間的電短路。作為另一實例，所蝕刻的材料可能重新沉積在蝕刻製程室的側壁上，在所述側壁上所蝕刻的材料可能降低蝕刻速率及/或可能對在蝕刻製程室中進行加工的其他結構造成污染。因此，通過濕式蝕刻及/或化學蝕刻執行蝕刻避免了與離子轟擊相關的挑戰。
如上所述，在一些實施例中，金屬結構是在結合之前形成的金屬凸塊。通過照這樣形成金屬結構，基底上的其他凸塊及/或結構不會因為在蝕刻之後執行將金屬結構圖案化成金屬凸塊的蝕刻製程而遭受損壞及/或縮小。
參照圖1，提供將III-V族元件102結合到基底104的積體晶片的一些實施例的剖視圖100。基底104包括沿著基底104的頂表面的第一接墊106a及第二接墊106b。在一些實施例中，基底104包括半導體基底（未示出）、位於所述半導體基底（未示出）上的半導體元件、及覆蓋所述半導體基底及所述半導體元件的內連線結構。內連線結構可例如將第一接墊106a及第二接墊106b電耦合到半導體元件。
III-V族元件102上覆在第一接墊106a上且包括檯面結構108及凸塊結構110。檯面結構108上覆在凸塊結構110上且可為或包含例如砷化鎵銦（indium gallium arsenide）、砷化鎵鋁（aluminum gallium arsenide）、一些其他III-V族材料、或它們的任意組合。凸塊結構110包括在結合介面116處結合在一起的檯面側凸塊112與基底側凸塊114。檯面側凸塊112及基底側凸塊114是導電性的且可為或包含例如金、鎳、鈦、一些其他適合的金屬、一些其他適合的導電材料、或它們的任意組合。
在一些實施例中，檯面側凸塊112包括第一凸塊區段112a，且還包括上覆在第一凸塊區段112a上的第二凸塊區段112b。第一凸塊區段112a可為或包含例如金、鈦、一些其他適合的金屬、或它們的任意組合，及/或可例如包括金層及上覆在所述金層上的鈦層。在一些實施例中，基底側凸塊114與第一凸塊區段112a為或包含相同的材料。此外，第一凸塊區段112a可例如具有約50納米到800納米的厚度或一些其他適合的厚度。第二凸塊區段112b可為或含有例如鎳、金、一些其他適合的金屬、或它們的任意組合，及/或可例如包括金層、上覆在所述金層上的第一鎳層、上覆在所述第一鎳層上的鍺金層、及上覆在所述鍺金層上的第二鎳層。此外，第二凸塊區段112b可例如具有約50納米到500納米的厚度或一些其他適合的厚度。在一些實施例中，基底側凸塊114為或包含金及/或一些其他適合的金屬，及/或具有介於約0.5微米到5.0微米之間的厚度或一些其他適合的厚度。
如在下文中看出，檯面側凸塊112可例如在形成檯面結構108之前通過金屬剝除製程來形成。通過如此製程形成檯面側凸塊112，檯面側凸塊112及基底側凸塊114可不遭受蝕刻損壞。舉例來說，如果檯面側凸塊112未在形成檯面結構108之前通過金屬剝除製程形成，則可能在形成檯面結構108之後執行濕式蝕刻製程以從金屬層形成檯面側凸塊。然而，相對上，濕蝕刻劑對基底側凸塊114及第一凸塊區段112a的選擇性可比對第二凸塊區段112b的選擇性高，由此濕蝕刻劑可能使基底側凸塊114縮小及/或形成實質上小於第二凸塊區段112b的第一凸塊區段112a。這反過來可能造成在結合介面116處的接觸面積較小。此外，檯面側凸塊112與基底側凸塊114之間的電阻可能為高的且功率效率可能為低的。因此，在形成檯面結構108之前通過金屬剝除製程形成檯面側凸塊112可在檯面側凸塊112與基底側凸塊114之間造成低的電阻且可造成高的功率效率。
擴散層118在檯面結構108與凸塊結構110之間凹陷到檯面結構108的下側中。此外，擴散層118在側向上從檯面結構108的外側壁間隔開距離D。如在下文中看出，擴散層118是通過來自檯面側凸塊112的金屬向檯面結構108的鄰接的部分擴散而形成。因此，擴散層118包含來自檯面結構108的III-V族材料，且更包含來自檯面側凸塊112的金屬。舉例來說，擴散層118可包含來自檯面結構108的鍺、鎵、砷化物、或它們的任意組合，且還可包含來自檯面側凸塊112的鎳、金、或它們的任意組合。
如在下文中看出，可向一個或多個III-V族層形成的堆疊執行蝕刻製程以從所述III-V族堆疊的檯面區域形成檯面結構108。此外，如在下文中看出，可在蝕刻製程之前通過金屬剝除製程在III-V族堆疊上形成檯面側凸塊112。通過在蝕刻製程之前利用金屬剝除製程形成檯面側凸塊112，擴散層118可局部形成到檯面側凸塊112且從檯面區域的側邊界間隔開。這反過來使得能夠在不蝕刻穿過擴散層118的情況下執行所述蝕刻製程。
在一些實施例中，來自檯面結構108的III-V族材料與來自檯面側凸塊112的金屬以使得擴散層118難以通過濕蝕刻劑來蝕刻及/或移除的方式進行組合。因此，在可在不蝕刻穿過擴散層118的情況下執行蝕刻製程的情形中，可通過濕蝕刻劑執行所述蝕刻製程。否則，可使用離子轟擊執行所述蝕刻製程。然而，由於來自離子的動能被轉移到所蝕刻的材料，因此離子轟擊比濕式蝕刻髒亂。舉例來說，所蝕刻的材料可能重新沉積並使第一接墊106a與第二接墊106b電短路。作為另一實例，所蝕刻的材料可能重新沉積在蝕刻製程室的側壁上，在所述側壁上所蝕刻的材料可能降低蝕刻速率及/或可能對在蝕刻製程室中進行加工的其他結構造成污染。因此，通過在蝕刻製程之前利用金屬剝除製程形成檯面側凸塊112，可避免與離子轟擊相關的挑戰。
背側接觸件120位於III-V族元件102的背側上、第一接墊106a與凸塊結構110之間，且電耦合到第一接墊106a。前側接觸件122位於III-V族元件102的前側上，與III-V族元件102的背側相對，且電耦合到第二接墊106b。舉例來說，前側接觸件122可通過從第二接墊106b延伸到前側接觸件122的導電結構124電耦合到第二接墊106b。在一些實施例中，前側接觸件122的俯視佈局是方環形、圓環形、或一些其他適合的形狀。前側接觸件122及背側接觸件120可為或包含例如鈦、鎢、銅、一些其他適合的導電材料、或它們的任意組合。在一些實施例中，背側接觸件120包括鈦層、上覆在所述鈦層上的銅層、及上覆在所述銅層上的鈦鎢層。在一些實施例中，背側接觸件120具有約2000埃到5000埃、約3200埃的厚度、或一些其他適合的厚度。
介電結構126環繞III-V族元件102且在一些實施例中在III-V族元件102的前側上界定接觸開口128。如在下文中看出，III-V族元件102可例如從III-V族元件102的前側發射輻射（例如，可見光或一些其他適合的輻射），使得接觸開口128容許所述輻射無阻礙地穿過介電結構126。介電結構126可為或包含例如模塑化合物、一些其他適合的導電材料、或它們的任意組合。
在一些實施例中，III-V族元件102為垂直空腔表面發射雷射器且包括第一布拉格(Bragg)反射器130、第二布拉格反射器132、及主動層134。主動層134位於第一布拉格反射器130與第二布拉格反射器132之間且可例如包括一個或多個量子阱（quantum well）。主動層134可例如具有約1納米到20納米的厚度或一些其他適合的厚度。主動層134可為或含有例如砷化鎵銦及/或一些其他適合的III-V族材料。在一些實施例中，主動層134為或包含[InxGaAs]y，其中x為約0.1到0.9且y為約1到5。
第一布拉格反射器130及第二布拉格反射器132分別位於III-V族元件102的背側上及III-V族元件102的前側上。此外，第一布拉格反射器130及第二布拉格反射器132是由多個第一反射器層136及多個第二反射器層138界定。為易於示出，僅將第一反射器層136中的一者標記為136，且僅將第二反射器層138中的一者標記為138。第一反射器層136與第二反射器層138交錯堆疊，且第一反射器層136可具有例如與第二反射器層138不同的性質（例如，折射率或一些其他適合的性質）。第一反射器層136及第二反射器層138可為或包含例如砷化鎵鋁、一些其他適合的III-V族材料、或它們的任意組合。
在一些實施例中，第一反射器層136各自為AlxGaAs，其中x為約0到0.9。此外，在一些實施例中，第一反射器層136各自具有介於4納米到100納米之間的厚度或一些其他適合的厚度。在一些實施例中，第二反射器層138各自為AlxGaAs，其中x為約0.1到1.0。此外，在一些實施例中，第二反射器層138各自具有介於4納米到100納米之間的厚度或一些其他適合的厚度。在一些實施例中，界定第二布拉格反射器132的第一反射器層136及第二反射器層138為P型，而界定第一布拉格反射器130的第一反射器層136及第二反射器層138為N型，反之亦然。在一些實施例中，III-V族元件102的前側上的反射器層對140重複出現0到100次以增大第二布拉格反射器132，及/或III-V族元件102的背側上的反射器層對（未標記）重複出現0到100次以增大第一布拉格反射器130。
參照圖2，提供前側接觸件122的一些實施例的俯視圖200。前側接觸件122具有環形佈局且位於檯面結構108上。然而，在其他實施例中替代性佈局也是可接受的。在一些實施例中，前側接觸件122的內徑ID為約8微米到10微米、約9微米、或一些其他適合的值。在一些實施例中，前側接觸件的外徑OD為約10微米到14微米、約12微米、或一些其他適合的值。當在橫截面中觀察時（參見例如圖1），前側接觸件122可例如直接接觸檯面結構108。在此種實施例中的一些實施例中，檯面結構108與前側接觸件122之間的接觸面積為約50平方微米到200平方微米、約50平方微米、或一些其他適合的面積。
參照圖3，提供檯面側凸塊112及基底側凸塊114的一些實施例的俯視圖300。檯面側凸塊112位於基底側凸塊114上且在一些實施例中，檯面側凸塊112與基底側凸塊114具有上覆位移（overlay shift）OS。上覆位移OS可例如為約0微米到6微米、約1微米到6微米、或一些其他適合的上覆位移。此外，檯面側凸塊112及基底側凸塊114具有圓形佈局。然而，在其他實施例中替代性佈局也是可接受的。在一些實施例中，檯面側凸塊112的直徑D1為約10微米到14微米、約12微米、或一些其他適合的值。在一些實施例中，基底側凸塊114的直徑D2相同於或約相同於檯面側凸塊112的直徑D1，及/或為約10微米到14微米、約12微米、或一些其他適合的值。當在橫截面中觀察時（參見例如圖1），檯面側凸塊112與基底側凸塊114可例如直接接觸。在此種實施例中的一些實施例中，檯面側凸塊112與基底側凸塊114之間的接觸面積為約44平方微米到114平方微米、約400到500平方微米、或一些其他適合的面積。
參照圖4A，提供其中檯面側凸塊112穿過蝕刻停止層402突出到擴散層118的圖1所示積體晶片的一些替代性實施例的剖視圖400A。蝕刻停止層402可為或包含例如氮化矽、氧化矽、氮氧化矽、一些其他適合的介電質、一些其他適合的蝕刻停止材料、或它們的任意組合。蝕刻停止層402可例如具有約10納米到500納米的厚度或一些其他適合的厚度。在一些實施例中，檯面側凸塊112包繞在蝕刻停止層402的隅角周圍及/或具有比基底側凸塊114大的寬度。在一些實施例中，檯面側凸塊112的第二凸塊區段112b具有比檯面側凸塊112的第一凸塊區段112a大的寬度，及/或第一凸塊區段112a具有比基底側凸塊114大的寬度。
如在下文中看出，在形成檯面結構108期間使用蝕刻停止層402作為蝕刻停止件。舉例來說，可向由一個或多個III-V族層形成的堆疊中執行蝕刻製程，且可在蝕刻停止層上停止，以從所述III-V族堆疊的檯面區域形成檯面結構108。此外，如在下文中看出，蝕刻停止層402可使擴散層118形成為從檯面區域的側邊界間隔開。這反過來使得能夠在不蝕刻穿過擴散層118的情況下執行所述蝕刻製程。因此，在來自檯面結構108的III-V族材料與來自檯面側凸塊112的金屬以使得擴散層118難以通過濕式蝕刻來蝕刻及/或移除的方式進行組合的一些實施例中，可避免與離子轟擊相關的挑戰（參照圖1所論述）。
參照圖4B，提供其中檯面側凸塊112不包繞在蝕刻停止層402的隅角(corner)周圍的圖4A所示積體晶片的一些替代性實施例的剖視圖400B。此外，在一些實施例中，凸塊結構110的寬度從頂部到底部增大，及/或基底側凸塊114具有倒T形輪廓。然而，在其他實施例中其他輪廓也是可接受的。
如在下文中看出，可在形成檯面結構108之前通過金屬剝除製程形成檯面側凸塊112。通過照這樣形成檯面側凸塊112，檯面側凸塊112及基底側凸塊114不遭受因進行蝕刻以形成檯面側凸塊112而造成的損壞。如參照圖1所論述，此種損壞可能使結合介面116處的檯面側凸塊112與基底側凸塊114之間的接觸面積較小。此外，檯面側凸塊112與基底側凸塊114之間的電阻可能為高的且功率效率可能為低的。因此，在形成檯面結構108之前通過金屬剝除製程形成檯面側凸塊112可在檯面側凸塊112與基底側凸塊114之間造成低的電阻且可造成高的功率效率。
參照圖5A，提供包括將第一III-V族元件102a及第二III-V族元件102b結合到基底104的積體晶片的一些實施例的剖視圖500A。第一III-V族元件102a上覆在第一接墊106a上且電耦合到第一接墊106a，且第二III-V族元件102b上覆在第三接墊106c上且電耦合到第三接墊106c。此外，第二接墊106b位於第一III-V族元件102a與第二III-V族元件102b之間且通過導電結構124電耦合到第一III-V族元件102a及第二III-V族元件102b。在一些實施例中，導電結構124具有T形輪廓，但在其他實施例中其他輪廓也是可接受的。
第一III-V族元件102a及第二III-V族元件102b是根據圖1所示III-V族元件102的更詳細實施例而配置且因此還包括硬罩幕502及側壁間隔件504。硬罩幕502上覆在檯面結構108上且在一些實施例中至少部分地界定接觸開口128。側壁間隔件504對檯面結構108的側壁及凸塊結構110的側壁進行襯墊。如在下文中看出，可例如採用硬罩幕502作為罩幕來界定檯面結構108，及/或側壁間隔件504可例如在界定背側接觸件120的同時保護檯面結構108及凸塊結構110。硬罩幕502及側壁間隔件504可為或包含例如氮化矽、氧化矽、氮氧化矽、一些其他適合的介電質、或它們的任意組合。在一些實施例中，硬罩幕502與側壁間隔件504為相同的材料。
基底104包括半導體基底508、位於半導體基底508之上的多個半導體元件510、及位於半導體基底508及半導體元件510之上的內連線結構512。為易於示出，僅將半導體元件510中的一些標記為510。半導體基底508可為例如塊狀單晶矽基底、絕緣體上矽（silicon-on-insulator，SOI）基底、或一些其他適合的半導體基底。半導體元件510可為或包含例如金屬氧化物半導體場效電晶體（metal-oxide-semiconductor field-effect transistor，MOSFET）、一些其他適合的金屬氧化物半導體（MOS）元件、一些其他適合的絕緣閘極場效電晶體（insulated-gate field- field-effect transistor，IGFET）、互補金屬氧化物半導體元件、一些其他適合的半導體元件、或它們的任意組合。
內連線結構512包括內連線介電層514、多個配線516、多個通孔518、及多個接墊。為易於示出，僅將配線516中的一些標記為516，且僅將通孔518中的一些標記為518。內連線介電層514可為或包含例如硼磷矽酸鹽玻璃（borophosphosilicate glass，BPSG）、磷矽酸鹽玻璃（phosphorus-silicate glass，PSG）、未經摻雜的矽玻璃（undoped silicon glass，USG）、一些其他低介電常數（k）介電質、氧化矽、碳化矽、一些其他適合的介電質、或它們的任意組合。本文中所使用的低介電常數介電質可為或包括例如具有小於約3.9、3、2、或1的介電常數的介電質。接墊包括第一接墊106a、第二接墊106b、及第三接墊106c，且配線516、通孔518、及所述接墊在內連線介電層514中交錯堆疊。配線516及通孔518界定對半導體元件510進行內連及/或將半導體元件510連接到接墊的導電路徑。配線516、通孔518、及所述接墊可為或包含例如銅、鋁銅、鋁、鈦、鎢、一些其他適合的金屬、或它們的任意組合。
參照圖5B，提供其中第一III-V族元件102a及第二III-V族元件102b根據圖4A所示III-V族元件102的更詳細實施例進行配置的圖5A所示積體晶片的一些替代性實施例的剖視圖500B。如在圖5A中一樣，硬罩幕502位於檯面結構108上且側壁間隔件504位於檯面結構108的側壁上。然而，與圖5A相反，側壁間隔件504不位於凸塊結構110的側壁上。
參照圖5C，提供其中第一III-V族元件102a及第二III-V族元件102b根據圖4B所示III-V族元件102的更詳細實施例進行配置的圖5A所示積體晶片的一些替代性實施例的剖視圖500C。如在圖5A中一樣，硬罩幕502位於檯面結構108上且側壁間隔件504位於檯面結構108的側壁及凸塊結構110的側壁上。然而，與圖5A相反，凸塊結構110具有倒T形輪廓。然而，在其他實施例中其他適合的輪廓也是可接受的。
儘管圖1、圖4A、及圖4B闡述III-V族元件102，然而應知，可使用以半導體材料而非III-V族材料為基礎的元件來取代III-V族元件102。舉例來說，可使用矽基元件來取代III-V族元件102，由此檯面結構108可為或包含矽。相似地，儘管5A到5C闡述第一III-V族元件102a及第二III-V族元件102b，然而應知，可使用以半導體材料而非III-V族材料為基礎的元件來取代第一III-V族元件102a及第二III-V族元件102b。
參照圖6A、圖6B、圖7A、圖7B、圖8、圖9A、圖9B、圖10、圖11A、圖11B、及圖12到圖25，一系列圖示出形成包括利用預圖案化檯面側凸塊結合到基底的多個III-V族元件的積體晶片的方法的一些實施例。在其他實施例中，所述方法可形成及/或使用以半導體材料而非III-V族材料為基礎的元件來取代III-V族元件。積體晶片可例如如參照圖5A所示出及闡述一樣。儘管參照一種方法來闡述圖6A、圖6B、圖7A、圖7B、圖8、圖9A、圖9B、圖10、圖11A、圖11B、及圖12到圖25，然而應知，圖6A、圖6B、圖7A、圖7B、圖8、圖9A、圖9B、圖10、圖11A、圖11B、及圖12到圖25中所示結構並非僅限於所述方法且可為獨立的。
如由圖6A及圖6B所示圖600A、600B所示，形成第一工件602。圖6A示出第一工件602的一些實施例的俯視佈局600A，且圖6B示出沿圖6A中的線A截取的第一工件602的一些實施例的剖視圖600B。
著重看圖6A，第一工件602包括多個晶粒區604。為易於示出，僅將晶粒區604中的一些標記為604。晶粒區604可例如各自具有相同的佈局及/或配置。在一些實施例中，第一工件602具有圓形俯視佈局及/或約6英寸的直徑。在其他實施例中，第一工件602具有一些其他俯視佈局及/或一些其他尺寸。
著重看圖6B，第一工件602還包括第一半導體基底606、第一蝕刻停止層608、及磊晶堆疊610。第一蝕刻停止層608上覆在第一半導體基底606上，且磊晶堆疊610上覆在第一蝕刻停止層608上。至少在所述方法的此階段處，第一半導體基底606可例如還被稱作第一半導體晶片。第一半導體基底606可例如為砷化鎵基底、一些其他適合的III-V族基底、或一些其他適合的半導體基底。此外，第一半導體基底606可例如具有約200微米的厚度，但在其他實施例中其他厚度也是可接受的。第一蝕刻停止層608可例如為或包含磷化鎵銦、一些其他適合的III-V族材料、一些其他適合的蝕刻停止材料、或它們的任意組合。磊晶堆疊610包括一個或多個磊晶層。此外，磊晶堆疊610可為或包含例如砷化鎵鋁、砷化鎵銦、一些其他適合的III-V族材料、一些其他適合的半導體材料、或它們的任意組合。
在一些實施例中，從磊晶堆疊610形成垂直空腔表面發射雷射器。在此種實施例中的一些實施例中，磊晶堆疊610包括第一布拉格反射器130、第二布拉格反射器132、及主動層134。主動層134夾置在第一布拉格反射器130與第二布拉格反射器132之間。主動層134可例如包含一個或多個量子阱及/或可例如包含砷化鎵銦及/或一些其他適合的III-V族材料。第一布拉格反射器130及第二布拉格反射器132是由多個第一反射器層136及多個第二反射器層138界定。為易於示出，僅將第一反射器層136中的一些標記為136，且僅將第二反射器層138中的一些標記為138。第一反射器層136與第二反射器層138交錯堆疊，且可具有例如與第二反射器層138不同的性質（例如，折射率或一些其他適合的性質）。第一反射器層136及第二反射器層138可為或包含例如砷化鎵鋁、一些其他適合的III-V族材料、或它們的任意組合。
如由圖7A及圖7B所示圖700A、700B所示，在第一工件602上、第一工件602的檯面區域702（參見圖7B）處形成檯面側凸塊112。圖7A示出第一工件602及檯面側凸塊112的一些實施例的俯視佈局700A，且圖7B示出沿圖7A中的線A截取的第一工件602及檯面側凸塊112的一些實施例的剖視圖700B。為易於示出，在圖7A中僅將檯面側凸塊112中的一些標記為112。檯面側凸塊112是導電性的且可為或包含例如鎳、金、一些其他適合的金屬、或它們的任意組合。在一些實施例中，檯面側凸塊112包括個別的第一凸塊區段112a及位於第一凸塊區段112a之下的個別的第二凸塊區段112b。第一凸塊區段112a可為或包含例如金及/或一些其他適合的金屬，及/或第二凸塊區段112b包含鎳、金、一些其他適合的金屬、或它們的任意組合。
在一些實施例中，在形成檯面側凸塊112時，檯面側凸塊112的材料擴散到磊晶堆疊610中且界定檯面側凸塊112各自的擴散層118。因此，擴散層118包含來自磊晶堆疊610與檯面側凸塊112二者的材料。舉例來說，擴散層118可包含來自磊晶堆疊610的鍺、鎵、砷化物、或它們的任意組合，及/或可包含來自檯面側凸塊112的鎳、金、或它們的任意組合。在一些實施例中，來自磊晶堆疊610的材料與來自檯面側凸塊112的材料以使得擴散層118難以通過濕蝕刻劑來蝕刻及/或移除的方式進行組合。
著重看圖7B，在一些實施例中通過金屬剝除製程形成檯面側凸塊112。然而，在其他實施例中用於形成檯面側凸塊112的其他方式也是可接受的。在一些實施例中，金屬剝除製程包括：在磊晶堆疊610上形成在檯面區域702處具有開口的光阻罩幕704；在光阻罩幕704置位的同時，在光阻罩幕704上及所述開口中沉積檯面側凸塊層706；以及移除光阻罩幕704。在一些實施例中，檯面側凸塊層706包括與第一凸塊區段112a及第二凸塊區段112b分別對應的第一檯面側凸塊層706a及第二檯面側凸塊層706b。通過移除光阻罩幕704，檯面側凸塊層706位於光阻罩幕704上的部分被剝除，而檯面側凸塊層706位於開口中的部分餘留下來以界定檯面側凸塊112。可例如通過濺鍍（sputtering）、電子束物理氣相沉積（electron-beam physical vapor deposition，EBPVD）、一些其他適合的沉積製程、或它們的任意組合來執行所述沉積。
通過利用金屬剝除製程形成檯面側凸塊112，金屬可僅被擴散到定位於檯面側凸塊112的磊晶堆疊610的一部分中。這樣一來，擴散層118可形成為從檯面區域702的側邊界間隔開距離D。如在下文中看出，這使得能夠在不進行髒亂且會導致大量問題的離子轟擊的情況下形成檯面結構。
如由圖8所示俯視佈局800所示，將第一工件602（以虛影示出）的晶粒區604（參見圖7A）分離成多個晶片802。可例如通過晶粒鋸（die saw）或一些其他適合的工具來執行所述分離。
如由圖9A及圖9B所示圖900A、900B所示，形成第二工件902。圖9A示出第二工件902的一些實施例的俯視佈局900A，且圖9B示出沿圖9A中的線B截取的第二工件902的一些實施例的剖視圖900B。
著重看圖9A，第二工件902包括多個晶粒區904。為易於示出，僅將晶粒區904中的一些標記為904。晶粒區904可例如各自具有相同的佈局及/或配置。在一些實施例中，第二工件902具有圓形俯視佈局及/或約12英寸的直徑。在其他實施例中，第二工件902具有一些其他俯視佈局及/或一些其他尺寸。在圖6A所示第一工件602以及第二工件902具有圓形俯視佈局的一些實施例中，第二工件902具有比第一工件602的直徑大的直徑。
著重看圖9B所示剖視圖900B，第二工件902還包括第二半導體基底508、位於第二半導體基底508之上的多個半導體元件510、及位於第二半導體基底508及半導體元件510之上的內連線結構512。為易於示出，僅將半導體元件510中的一些標記為510。至少在所述方法的此階段處，第二半導體基底508可例如還被稱作第二半導體晶片。第二半導體基底508可為例如塊狀單晶矽基底、絕緣體上矽基底、或一些其他適合的半導體基底。半導體元件510可為或包含例如互補金屬氧化物半導體元件、一些其他適合的半導體元件、或它們的任意組合。
內連線結構512包括內連線介電層514、多個配線516、多個通孔518、及多個接墊106。為易於示出，僅將配線516中的一些標記為516，且僅將通孔518中的一些標記為518。配線516、通孔518、及接墊106在內連線介電層514中交錯堆疊，且配線516及通孔518界定對半導體元件510進行內連及/或將半導體元件510連接到接墊106的導電路徑。配線516、通孔518、及接墊106可為或包含例如銅、鋁銅、鋁、鈦、鎢、一些其他適合的金屬、一些其他適合的導電材料、或它們的任意組合。
如由圖10所示剖視圖1000所示，在第二工件902之上以堆疊方式形成第一接觸層1002及晶種層1004。晶種層1004上覆在第一接觸層1002上且可為或包含例如金、一些其他適合的金屬、一些其他適合的導電材料、或它們的任意組合。第一接觸層1002可為或包含例如鈦、鎢、銅、一些其他適合的金屬、一些其他適合的導電材料、或它們的任意組合。可例如通過化學氣相沉積（chemical vapor deposition，CVD）、物理氣相沉積（physical vapor deposition，PVD）、一些其他適合的沉積製程、或它們的任意組合來形成第一接觸層1002及晶種層1004。
如由圖11A及圖11B所示圖1100A、1100B所示，在第二工件902上、第二工件902的對應接墊106（參見圖11B）處形成基底側凸塊114。圖11A示出第二工件902及基底側凸塊114的一些實施例的俯視佈局1100A，且圖11B示出沿圖11A中的線B截取的第二工件902及基底側凸塊114的一些實施例的剖視圖1100B。為易於示出，在圖11A中僅將基底側凸塊114中的一些標記為114。基底側凸塊114為導電性的且為或包含與晶種層1004（參見圖11B）相同的材料。
著重看圖11B，通過鍍覆製程形成基底側凸塊114。然而，在其他實施例中用於形成基底側凸塊114的其他方式也是可接受的。在通過鍍覆製程形成基底側凸塊114的一些實施例中，在晶種層1004上形成在與基底側凸塊114對應的接墊106處具有開口的光阻罩幕1102。接著執行鍍覆製程以在光阻罩幕1102置位的同時從晶種層1004生長基底側凸塊114，且隨後移除光阻罩幕1102。所述鍍覆製程可例如為電鍍、無電鍍覆、或一些其他適合的鍍覆製程。
如由圖12所示剖視圖1200所示，執行回蝕（etch back）以移除晶種層1004（參見圖11B），同時留下基底側凸塊114。可例如通過濕式蝕刻或修剪（trim）及/或一些其他適合的蝕刻製程來執行所述回蝕。
如由圖13所示剖視圖1300所示，在垂直方向上將第一工件602的晶片802（參見圖8）翻轉並在基底側凸塊114與檯面側凸塊112進行接觸的結合介面116處結合到第二工件902。在第二半導體基底508為晶片的實施例中，所述結合可例如被稱作晶片對晶片（chip-to-wafer，C2W）結合。可例如通過金屬對金屬結合及/或一些其他適合的結合製程來執行所述結合。
如由圖14所示剖視圖1400所示，在晶片802周圍形成保護層1402，且保護層1402的頂表面凹陷而低於晶片802的頂表面。保護層1402可例如為或包含有機抗反射塗層（anti-reflective coating，ARC）、無機抗反射塗層、一些其他適合的保護材料、或它們的任意組合。可例如通過濺鍍、化學氣相沉積、物理氣相沉積、一些其他適合的沉積製程、或它們的任意組合來形成保護層1402。
如由圖15所示剖視圖1500所示，在保護層1402置位元的情況下，向第一半導體基底606（參見圖14）及第一蝕刻停止層608（參見圖14）中執行蝕刻製程，以移除第一半導體基底606及第一蝕刻停止層608。在一些實施例中，蝕刻製程包括對第一半導體基底606執行第一蝕刻以移除第一半導體基底606，並隨後執行向第一蝕刻停止層608中的第二蝕刻以移除第一蝕刻停止層608。在此種實施例中，第一蝕刻停止層608可例如充當第一蝕刻的蝕刻停止件。在其他實施例中，所述蝕刻製程僅限於單一蝕刻或者不僅包括第一蝕刻及第二蝕刻。
如由圖16所示剖視圖1600所示，移除保護層1402（參見圖15）。可例如通過蝕刻製程及/或一些其他適合的移除製程來執行所述移除。
此外，如由圖16所示剖視圖1600所示，在磊晶堆疊610上形成硬罩幕層1602。硬罩幕層1602可為或包含例如氧化矽、氮化矽、氮氧化矽、一些其他適合的硬罩幕材料、或它們的任意組合。可例如通過化學氣相沉積、物理氣相沉積、氧化、一些其他適合的沉積製程、或它們的任意組合來形成硬罩幕層1602。在一些實施例中，將硬罩幕層1602定位到磊晶堆疊610的頂表面。在此種實施例的一些實施例中，通過等離子體增強型物理氣相沉積沉積硬罩幕層1602以實現此種定位。
如由圖17所示剖視圖1700所示，將硬罩幕層1602（參見圖16）圖案化以在磊晶堆疊610的檯面區域702上形成硬罩幕502。可例如通過微影/蝕刻製程及/或一些其他適合的圖案化製程來執行所述圖案化。微影/蝕刻製程可例如包括在硬罩幕層1602上形成光阻罩幕1702，在光阻罩幕1702置位元的情況下向硬罩幕層1602執行蝕刻，且隨後剝掉光阻罩幕1702。
如由圖18所示剖視圖1800所示，在硬罩幕502置位元的情況下向磊晶堆疊610（參見圖17）執行蝕刻製程以在檯面區域702（參見圖17）處形成檯面結構108。可例如通過濕式蝕刻及/或一些其他適合的蝕刻來執行所述蝕刻製程。如上所示，由於可通過金屬剝除製程形成檯面側凸塊112，因此金屬可僅擴散到被定位到檯面側凸塊112的磊晶堆疊610的一部分中且擴散層118可形成為從檯面區域702的側邊界間隔開。因此，可在不蝕刻擴散層118的情況下執行所述蝕刻製程。
在一些實施例中，來自磊晶堆疊610的材料與來自檯面側凸塊112的材料以使得擴散層118難以通過濕蝕刻劑來蝕刻及/或移除的方式進行組合。因此，在不蝕刻擴散層118的情況下執行蝕刻製程的情形中，可通過濕式蝕刻執行所述蝕刻製程。否則，可使用離子轟擊執行所述蝕刻製程。然而，由於來自離子的動能被轉移到所蝕刻的材料，因此離子轟擊比濕式蝕刻髒亂。舉例來說，所蝕刻的材料可能重新沉積在接墊106上並使接墊106電短路。作為另一實例，所蝕刻的材料可能重新沉積在蝕刻製程室的側壁上，在所述側壁上所蝕刻的材料可能降低蝕刻速率及/或可能對在蝕刻製程室中進行加工的其他結構造成污染。因此，通過利用金屬剝除製程形成檯面側凸塊112，可避免以上與離子轟擊相關聯挑戰。
如由圖19所示剖視圖1900所示，在檯面結構108的側壁、檯面側凸塊112的側壁、及基底側凸塊114的側壁上形成側壁間隔件504。側壁間隔件504可為或包含例如氧化矽、氮化矽、氮氧化矽、一些其他適合的介電質、或它們的任意組合。在一些實施例中，形成側壁間隔件504的製程包括沉積側壁間隔件層且隨後執行向側壁間隔件層中的回蝕。可例如通過化學氣相沉積、物理氣相沉積、一些其他適合的沉積製程、或它們的任意組合來執行所述沉積。
如由圖20所示剖視圖2000所示，向第一接觸層1002（參見圖19）中執行蝕刻製程以在各基底側凸塊114下方分別形成背側接觸件120。蝕刻製程包括對第一接觸層1002施加蝕刻劑且使用側壁間隔件504及硬罩幕502作為罩幕以形成背側接觸件120。側壁間隔件504及硬罩幕502還在蝕刻製程期間保護檯面結構108。可例如通過濕式蝕刻、乾式蝕刻、一些其他適合的蝕刻、或它們的任意組合來執行所述蝕刻製程。
同樣如由圖20所示剖視圖2000所示，形成環繞檯面結構108的介電結構126。介電結構126可為或包含例如模塑化合物、一些其他適合的導電材料、或它們的任意組合。在一些實施例中，形成介電結構126的製程包括通過化學氣相沉積、物理氣相沉積、濺鍍、一些其他沉積製程、或它們的任意組合來沉積介電結構126。在一些實施例中，所述製程還包括化學機械拋光（chemical mechanical polish，CMP）或者向介電結構126的上表面或頂表面進行的一些其他適合的平坦化製程。
如由圖21所示剖視圖2100所示，將介電結構126圖案化以形成位於相鄰的檯面結構108之間且暴露出接墊106中的一者的通孔開口2102。可例如通過微影/蝕刻製程及/或一些其他適合的圖案化製程來執行所述圖案化。微影/蝕刻製程可例如包括在介電結構126上形成光阻罩幕2104，在光阻罩幕2104置位元的情況下向介電結構126執行蝕刻，且隨後剝掉光阻罩幕2104。
如由圖22所示剖視圖2200所示，在通孔開口2102中形成通孔124v。通孔124v可為或包含例如鈦、鎢、銅、鋁銅、一些其他適合的導電材料、或它們的任意組合。在一些實施例中，通過使用接墊106中對應的一者作為晶種的鍍覆製程形成通孔124v。所述鍍覆製程可例如為電鍍、無電鍍覆、一些其他適合的鍍覆製程、或它們的任意組合。在其他實施例中，通過以下方式形成通孔124v：沉積覆蓋介電結構126且填充通孔開口2102的金屬層；以及隨後向金屬層執行向金屬層平坦化，直到所述金屬層的上表面或頂表面大約與介電結構126齊平。儘管使用上述兩種製程形成通孔124v的，然而在其他實施例中其他製程也是可接受的。
如由圖23所示剖視圖2300所示，將介電結構126及硬罩幕502圖案化以形成暴露出檯面結構108的接觸開口128。可例如通過微影/蝕刻製程及/或一些其他適合的圖案化製程來執行所述圖案化。微影/蝕刻製程可例如包括在介電結構126上形成光阻罩幕2302，在光阻罩幕2302置位元的情況下向介電結構126及硬罩幕502執行蝕刻，且隨後剝掉光阻罩幕2302。
如由圖24所示剖視圖2400所示，在檯面結構108上、接觸開口128（參見圖23）中形成前側接觸件122。在一些實施例中，前側接觸件122的俯視佈局是方環形、圓環形、或一些其他適合的形狀。前側接觸件122可為或包含例如鈦、鎢、銅、一些其他適合的導電材料、或它們的任意組合。
在一些實施例中，通過金屬剝除製程來形成前側接觸件122。然而，在其他實施例中用於形成前側接觸件122的其他方式也是可接受的。在一些實施例中，金屬剝除製程包括：形成具有與前側接觸件122對應的開口的光阻罩幕2402；在光阻罩幕2402置位的同時，在光阻罩幕2402上及所述開口中沉積第二接觸層2404；以及移除光阻罩幕2402。通過移除光阻罩幕2402，第二接觸層2404位於光阻罩幕2402上的部分被剝除，而第二接觸層2404位於開口中的部分餘留下來以界定前側接觸件122。可例如通過濺鍍、EB物理氣相沉積、一些其他適合的沉積製程、或它們的任意組合來執行所述沉積。
如由圖25所示剖視圖2500所示，形成將通孔124v電耦合到前側接觸件122的配線124w。配線124w可為或包含例如鈦、鎢、銅、鋁銅、一些其他適合的導電材料、或它們的任意組合。
在一些實施例中，通過金屬剝除製程來形成配線124w。然而，在其他實施例中用於形成配線124w的其他方式也是可接受的。在一些實施例中，金屬剝除製程包括：形成具有與配線124w對應的開口的光阻罩幕2502；在光阻罩幕2502置位的同時，在光阻罩幕2502上及所述開口中沉積導電層2504；以及移除光阻罩幕2502。通過移除光阻罩幕2502，導電層2504位於光阻罩幕2502上的部分被剝除，而導電層2504位於開口中的部分餘留下來以界定配線124w。可例如通過濺鍍、電子束物理氣相沉積、一些其他適合的沉積製程、或它們的任意組合來執行所述沉積。
在一些實施例中，在形成配線124w之後，將第二工件902的晶粒區904（參見圖11A）分離成積體電路晶片。可例如通過晶粒鋸或一些其他適合的工具來執行所述分離。
參照圖26，提供圖6A、圖6B、圖7A、圖7B、圖8、圖9A、圖9B、圖10、圖11A、圖11B、及圖12到圖25所示方法的一些實施例的方塊圖2600。
在2602處，形成包括半導體基底及位於所述半導體基底上的磊晶堆疊的第一工件。參見例如圖6A及圖6B。
在2604處，在磊晶堆疊上形成檯面側凸塊。參見例如圖7A及圖7B。
在2606處，將第一工件單體化以界定晶片。參見例如圖8。
在2608處，形成第二工件。參見例如圖9A及圖9B。
在2610處，在第二工件上形成接觸層及基底側凸塊。參見例如圖10、圖11A、圖11B、及圖12。
在2612處，在檯面側凸塊與基底側凸塊進行接觸的介面處將晶片結合到第二工件。參見例如圖13。
在2614處，移除半導體基底。參見例如圖14到圖16。
在2616處，將磊晶堆疊圖案化以界定檯面側凸塊各自的檯面結構。參見例如圖16到圖18。
在2618處，將接觸層圖案化以形成背側接觸件。參見例如圖19及圖20。
在2620處，形成將檯面結構的上表面電耦合到第二工件的導電結構。參見例如圖20到圖25。
儘管在本文中將圖26所示方塊圖2600示出並闡述為一系列動作或事件，然而應知，此類動作或事件的所示次序不應被解釋為具有限制性意義。舉例來說，一些動作可以不同的次序發生及/或與除本文中所示出及/或闡述的動作或事件以外的其他動作或事件同步地發生。此外，可能並非需要所有所示動作來實作本文中所作說明的一個或多個方面或實施例，且本文中所繪示動作中的一個或多個動作可以一個或多個單獨的動作及/或階段施行。
參照圖27到圖34，一系列剖視圖2700到3400示出形成包括結合到基底的多個III-V族元件且具有蝕刻停止層的積體晶片的方法的一些實施例。在其他實施例中，所述方法可形成及/或使用以半導體材料而非III-V族材料為基礎的元件來取代III-V族元件。積體晶片可例如如參照圖5B所示出及闡述一樣。儘管參照一種方法來闡述圖27到圖34，然而應知，圖27到圖34中所示結構並非僅限於所述方法且可為獨立的。
如由圖27所示剖視圖2700所示，形成第一工件602。第一工件602可例如參照圖6A及圖6B所示出及闡述一樣。此外，在第一工件602上形成第二蝕刻停止層402。第二蝕刻停止層402可為或包含例如氮化矽、氧化矽、氮氧化矽、一些其他適合的介電質、一些其他適合的蝕刻停止材料、或它們的任意組合。在一些實施例中，通過化學氣相沉積、物理氣相沉積、濺鍍、一些其他適合的沉積製程、或它們的任意組合來形成第二蝕刻停止層402。
如由圖28所示剖視圖2800所示，將第二蝕刻停止層402圖案化以形成暴露出磊晶堆疊610的檯面區域702的檯面開口2802。可例如通過微影/蝕刻製程及/或一些其他適合的圖案化製程來執行所述圖案化。微影/蝕刻製程可例如包括在第二蝕刻停止層402上形成光阻罩幕2804，在光阻罩幕2804置位元的情況下執行向第二蝕刻停止層402中的蝕刻，且隨後剝掉光阻罩幕2804。
如由圖29所示剖視圖2900所示，形成覆蓋第二蝕刻停止層402且對檯面開口2802（參見圖28）進行襯墊的檯面側凸塊層706。檯面側凸塊層706可為或包含例如金、鎳、鈦、一些其他適合的金屬、一些其他適合的導電材料、或它們的任意組合。在一些實施例中，檯面側凸塊層706包括第一檯面側凸塊層706a及第二檯面側凸塊層706b。可例如通過化學氣相沉積、物理氣相沉積、電鍍、無電鍍覆、一些其他適合的沉積及/或鍍覆製程、或它們的任意組合來形成檯面側凸塊層706。
在一些實施例中，在形成檯面側凸塊層706時，檯面側凸塊層706的材料擴散到磊晶堆疊610中且界定檯面區域702各自的擴散層118。因此，擴散層118包含來自磊晶堆疊610與檯面側凸塊112二者的材料。在一些實施例中，來自磊晶堆疊610的材料與來自檯面側凸塊層706的材料以使得擴散層118難以通過濕蝕刻劑來蝕刻及/或移除的方式進行組合。通過在第二蝕刻停止層402之上形成檯面側凸塊層706，第二蝕刻停止層402將檯面側凸塊層706從磊晶堆疊610的部分到檯面區域702的側邊間隔開。因此，第二蝕刻停止層402使擴散層118形成為從檯面區域702的側邊界間隔開距離D。
如由圖30所示剖視圖3000所示，如以上所示出及闡述，執行圖8、圖9A、圖9B、圖10、圖11A、圖11B、及圖13處的動作，但不執行圖12處的動作。在執行圖8處的動作的同時，將第一工件602（參見圖29）劃分成多個晶片802。在執行圖9A及圖9B處的動作的同時，形成第二工件902。在執行圖10所示動作的同時，在第二工件902上形成第一接觸層1002及晶種層1004。在執行圖11A及圖11B處的動作的同時，在第二工件902上、第二工件902的對應接墊106處形成基底側凸塊114。在執行圖13處的動作的同時，在垂直方向上將晶片802中的一者翻轉並在基底側凸塊114與檯面側凸塊層706進行接觸的結合介面116處結合到第二工件902。
如由圖31所示剖視圖3100所示，如以上所示出及闡述，執行圖14到圖18處的動作。採用圖14及圖15處的動作移除第一蝕刻停止層608及第一半導體基底606。採用圖16到圖18處的動作將磊晶堆疊610（參見圖30）圖案化以在檯面區域702（參見圖30）處界定檯面結構108。所述圖案化包括在磊晶堆疊610上形成硬罩幕502，且隨後在硬罩幕502置位元的情況下向磊晶堆疊610執行蝕刻。在蝕刻期間，使用第二蝕刻停止層402作為蝕刻停止件。可例如通過濕式蝕刻製程或化學蝕刻製程來執行所述蝕刻，及/或可通過一些其他適合的蝕刻製程來執行所述蝕刻。
在一些實施例中，來自磊晶堆疊610的材料與來自檯面側凸塊112的材料以使得擴散層118難以通過濕蝕刻劑來蝕刻及/或移除的方式進行組合。在不蝕刻穿過擴散層118的情況下執行蝕刻的情形中，可通過濕式蝕刻執行所述蝕刻。否則，可例如使用離子轟擊執行所述蝕刻。然而，由於來自離子的動能被轉移到所蝕刻的材料，因此離子轟擊比濕式蝕刻髒亂。舉例來說，所蝕刻的材料可能重新沉積在接墊106及/或基底側凸塊114上並使接墊106及/或基底側凸塊114電短路。作為另一實例，所蝕刻的材料可能重新沉積在蝕刻製程室的側壁上，在所述側壁上所蝕刻的材料可能降低蝕刻速率及/或可能對其他結構造成污染。由於第二蝕刻停止層402使擴散層118定位形成到檯面區域702（參見圖30）且因而定位形成到檯面結構108，因此可在不蝕刻穿過擴散層118的情況下執行所述蝕刻且可避免以上與離子轟擊相關的挑戰。
如由圖32所示剖視圖3200所示，根據硬罩幕502的佈局將第二蝕刻停止層402圖案化。可例如通過蝕刻製程及/或一些其他適合的圖案化製程來執行所述圖案化。蝕刻製程可例如包括對第二蝕刻停止層402施加濕蝕刻劑、幹蝕刻劑、一些其他適合的蝕刻劑、或它們的任意組合。
此外，如由圖32所示剖視圖3200所示，在檯面結構108的側壁及第二蝕刻停止層402的側壁上形成側壁間隔件504。在一些實施例中，形成側壁間隔件504的製程包括沉積側壁間隔件層且隨後向側壁間隔件層執行回蝕。可例如通過化學氣相沉積、物理氣相沉積、一些其他適合的沉積製程、或它們的任意組合來執行所述沉積。
如由圖33所示剖視圖3300所示，將檯面側凸塊層706（參見圖32）圖案化以形成檯面結構108各自的檯面側凸塊112。在一些實施例中，檯面側凸塊112包括由第一檯面側凸塊層706a形成的個別第一凸塊區段112a，且還包括位於第一凸塊區段112a之下且由第二檯面側凸塊層706b形成的個別第二凸塊區段112b。另外，移除晶種層1004（參見圖32）。可例如通過其中硬罩幕520及側壁間隔件504保護檯面結構108且充當罩幕的蝕刻製程來執行所述將檯面側凸塊層706圖案化及所述移除晶種層1004。然而，在其他實施例中用於執行所述圖案化的其他方式也是可接受的。所述蝕刻製程可例如為濕式蝕刻製程、乾式蝕刻製程、或一些其他適合的蝕刻製程。在一些實施例中，在蝕刻製程期間，基底側凸塊114的大小減小。此外，在一些實施例中，在蝕刻製程期間，第一凸塊區段112a比第二凸塊區段112b受到的蝕刻多，使得第一凸塊區段112a相對於第二凸塊區段112b具有減小的寬度。
如由圖34所示剖視圖3400所示，如以上所示出及闡述，執行圖20到圖25處的動作。在執行圖20處的動作的同時，將第一接觸層1002（參見圖33）圖案化以形成背側接觸件120。此外，形成環繞檯面結構108的介電結構126。在執行圖21處的動作的同時，將介電結構126圖案化以形成位於相鄰的檯面結構108之間且暴露出接墊106中的一者的通孔開口。在執行圖22處的動作的同時，在通孔開口中形成通孔124v。在執行圖23處的動作的同時，將介電結構126及硬罩幕502圖案化以形成暴露出檯面結構108的接觸開口。在執行圖24處的動作的同時，在檯面結構108上、接觸開口中形成前側接觸件122。在執行圖25處的動作的同時，形成將通孔124v電耦合到前側接觸件122的配線124w。
參照圖35，提供圖27到圖34所示方法的一些實施例的方塊圖3500。
在3502處，形成包括半導體基底及位於所述半導體基底上的磊晶堆疊的第一工件。參見例如圖27。
在3504處，在磊晶堆疊上形成蝕刻停止層，其中所述蝕刻停止層在所述磊晶堆疊的檯面區域處具有開口。參見例如圖27及圖28。
在3506處，在蝕刻停止層上形成對所述開口進行襯墊的檯面側凸塊層。參見例如圖29。
在3508處，將第一工件單體化以界定晶片。參見例如圖30。
在3510處，形成第二工件。參見例如圖30。
在3512處，在第二工件上形成接觸層及基底側凸塊。參見例如圖30。
在3514處，在檯面側凸塊層與基底側凸塊進行接觸的介面處將晶片結合到第二工件。參見例如圖30。
在3516處，移除半導體基底。參見例如圖31。
在3518處，向磊晶堆疊執行蝕刻以形成檯面區域各自的檯面結構，其中所述蝕刻在蝕刻停止層上停止。參見例如圖31。
在3520處，將蝕刻停止層及檯面側凸塊層圖案化，其中所述將檯面側凸塊層圖案化會形成檯面側凸塊。參見例如圖32及圖33。
在3522處，將接觸層圖案化以形成背側接觸件。參見例如圖34。
在3524處，形成將檯面結構的上表面電耦合到第二工件的導電結構。參見例如圖35。
儘管在本文中將圖35所示方塊圖3500示出並闡述為一系列動作或事件，然而應知，此類動作或事件的所示次序不應被解釋為具有限制性意義。舉例來說，一些動作可以不同的次序發生及/或與除本文中所示出及/或闡述的動作或事件以外的其他動作或事件同步地發生。此外，可能並非需要所有所示動作來實作本文中所作說明的一個或多個方面或實施例，且本文中所繪示動作中的一個或多個動作可以一個或多個單獨的動作及/或階段施行。
參照圖36到圖40，一系列剖視圖3600到4000示出形成包括利用預圖案化檯面側凸塊結合到基底的多個III-V族元件且具有蝕刻停止層的積體晶片的方法的一些實施例。在其他實施例中，所述方法可形成及/或使用以半導體材料而非III-V族材料為基礎的元件來取代III-V族元件。積體晶片可例如如參照圖5C所示出及闡述一樣。儘管參照一種方法來闡述圖36到圖40，然而應知，圖36到圖40中所示結構並非僅限於所述方法且可為獨立的。
如由圖36所示剖視圖3600所示，形成第一工件602。第一工件602可例如如參照圖6A及圖6B所示出及闡述一樣。此外，根據參照圖27及圖28所示出及闡述的動作在第一工件602上形成第二蝕刻停止層402並將第二蝕刻停止層402圖案化。在執行圖27處的動作的同時，在第一工件602上形成第二蝕刻停止層402。在執行圖28處的動作的同時，將蝕刻停止層圖案化以形成暴露出磊晶堆疊610的檯面區域702的檯面開口2802。
如由圖37所示剖視圖3700所示，在第一工件602上、檯面開口2082（參見圖36）內形成檯面側凸塊112。在一些實施例中，檯面側凸塊112包括個別的第一凸塊區段112a及位於第一凸塊區段112a之下的個別的第二凸塊區段112b。在一些實施例中，在形成檯面側凸塊112時，檯面側凸塊112的材料擴散到磊晶堆疊610中且界定檯面側凸塊112各自的擴散層118。在一些實施例中，來自磊晶堆疊610的材料與來自檯面側凸塊112的材料以使得擴散層118難以通過濕蝕刻劑來蝕刻及/或移除的方式進行組合。
在一些實施例中通過金屬剝除製程形成檯面側凸塊112。然而，在其他實施例中用於形成檯面側凸塊112的其他方式也是可接受的。在一些實施例中，金屬剝除製程包括：在磊晶堆疊610上形成在檯面區域702處具有開口的光阻罩幕704；在光阻罩幕704置位的同時，在光阻罩幕704上及所述開口中沉積檯面側凸塊層706；以及移除光阻罩幕704。在一些實施例中，檯面側凸塊層706包括與第一凸塊區段112a及第二凸塊區段112b分別對應的第一檯面側凸塊層706a及第二檯面側凸塊層706b。通過移除光阻罩幕704，檯面側凸塊層706位於光阻罩幕704上的部分被剝除，而檯面側凸塊層706位於開口中的部分餘留下來以界定檯面側凸塊112。通過在第二蝕刻停止層402之上形成檯面側凸塊層706，第二蝕刻停止層402將檯面側凸塊層706從磊晶堆疊610的部分到檯面區域702的側邊間隔開。因此，第二蝕刻停止層402使擴散層118從檯面區域702的側邊界間隔開距離D。
如由圖38所示剖視圖3800所示，如以上所示出及闡述，執行圖8、圖9A、圖9B、圖10、圖11A、圖11B、及圖13處的動作，但不執行圖12處的動作。在執行圖8處的動作的同時，將第一工件602（參見圖37）劃分成多個晶片802。在執行圖9A及圖9B處的動作的同時，形成第二工件902。在執行圖10處的動作的同時，在第二工件902上形成第一接觸層1002及晶種層1004。在執行圖11A及圖11B處的動作的同時，在第二工件902上、第二工件902的對應接墊106處形成基底側凸塊114。在執行圖13處的動作的同時，在垂直方向上將晶片802中的一者翻轉並在基底側凸塊114與檯面側凸塊112進行接觸的結合介面116處結合到第二工件902。
如由圖39所示剖視圖3900所示，如以上所示出及闡述，執行圖14到圖18處的動作。採用圖14及圖15處的動作移除第一蝕刻停止層608及第一半導體基底606。採用圖16到圖18處的動作將磊晶堆疊610（參見圖38）圖案化以在檯面區域702（參見圖38）處界定檯面結構108。所述圖案化包括在磊晶堆疊610上形成硬罩幕502，且隨後在硬罩幕502置位元的情況下向磊晶堆疊610執行蝕刻。在蝕刻期間，使用第二蝕刻停止層402作為蝕刻停止件。可例如通過濕式蝕刻製程或化學蝕刻製程來執行所述蝕刻，及/或可例如通過一些其他適合的蝕刻製程來執行所述蝕刻。
在一些實施例中，來自磊晶堆疊610的材料與來自檯面側凸塊112的材料以使得擴散層118難以通過濕蝕刻劑來蝕刻及/或移除的方式進行組合。在可在不蝕刻穿過擴散層118的情況下執行蝕刻的情形中，可通過濕式蝕刻執行所述蝕刻。否則，可例如使用離子轟擊執行所述蝕刻。然而，離子轟擊引入以上所述一定數量的挑戰。由於第二蝕刻停止層402使擴散層118局部形成到檯面區域702（參見圖39）且因而局部形成到檯面結構108，因此可在不蝕刻穿過擴散層118的情況下執行所述蝕刻且可避免與離子轟擊相關聯的挑戰。
此外，如由圖39所示剖視圖3900所示，根據硬罩幕502的佈局將第二蝕刻停止層402圖案化。可例如通過蝕刻製程及/或一些其他適合的圖案化製程來執行所述圖案化。蝕刻製程可例如包括對第二蝕刻停止層402施加濕蝕刻劑、幹蝕刻劑、一些其他適合的蝕刻劑、或它們的任意組合。
如由圖40所示剖視圖4000所示，如以上所示出及闡述，執行圖19到圖25處的動作。在執行圖19處的動作的同時，在檯面結構108的側壁、檯面側凸塊112的側壁、及基底側凸塊114的側壁上形成側壁間隔件504。在執行圖20處的動作的同時，移除晶種層1004（參見圖39）且將第一接觸層1002（參見圖39）圖案化以形成背側接觸件120。此外，形成環繞檯面結構108的介電結構126。在執行圖21處的動作的同時，將介電結構126圖案化以形成位於相鄰的檯面結構108之間且暴露出接墊106中的一者的通孔開口。在執行圖22處的動作的同時，在通孔開口中形成通孔124v。在執行圖23處的動作的同時，將介電結構126及硬罩幕502圖案化以形成暴露出檯面結構108的接觸開口。在執行圖24處的動作的同時，在檯面結構108上、接觸開口中形成前側接觸件122。在執行圖25所示動作的同時，形成將通孔124v電耦合到前側接觸件122的配線124w。
參照圖41，提供圖36到圖40所示方法的一些實施例的方塊圖4100。
在4102處，形成包括半導體基底及位於所述半導體基底上的磊晶堆疊的第一工件。參見例如圖36。
在4104處，在磊晶堆疊上形成蝕刻停止層，其中所述蝕刻停止層在所述磊晶堆疊的檯面區域處具有開口。參見例如圖36。
在4106處，在磊晶堆疊上、分別在各開口中形成檯面側凸塊。參見例如圖37。
在4108處，將第一工件單體化以界定晶片。參見例如圖38。
在4110處，形成第二工件。參見例如圖38。
在4112處，在第二工件上形成接觸層及基底側凸塊。參見例如圖38。
在4114處，在檯面側凸塊與基底側凸塊進行接觸的介面處將晶片結合到第二工件。參見例如圖38。
在4116處，移除半導體基底。參見例如圖39。
在4118處，向磊晶堆疊執行蝕刻以形成檯面區域各自的檯面結構，其中所述蝕刻在蝕刻停止層上停止。參見例如圖39。
在4120處，根據檯面結構的佈局將蝕刻停止層圖案化。參見例如圖39。
在4122處，將接觸層圖案化以形成背側接觸件。參見例如圖40。
在4124處，形成將檯面結構的上表面電耦合到第二工件的導電結構。參見例如圖40。
儘管在本文中將圖41所示方塊圖4100示出並闡述為一系列動作或事件，然而應知，此類動作或事件的所示次序不應被解釋為具有限制性意義。舉例來說，一些動作可以不同的次序發生及/或與除本文中所示出及/或闡述的動作或事件以外的其他動作或事件同步地發生。此外，可能並非需要所有所示動作來實作本文中所作說明的一個或多個方面或實施例，且本文中所繪示動作中的一個或多個動作可以一個或多個單獨的動作及/或階段施行。
在一些實施例中，本申請提供一種積體晶片，所述積體晶片包括：基底；檯面結構，位於所述基底上且包含半導體材料；凸塊結構，位於所述基底與所述檯面結構之間，其中所述凸塊結構包含導電材料；以及擴散層，凹陷到所述檯面結構中，位於所述凸塊結構與所述檯面結構之間，其中所述擴散層包含分別來自所述檯面結構及所述凸塊結構的半導體材料及導電材料，且所述擴散層的側壁從所述檯面結構的側壁間隔開。在一些實施例中，積體晶片還包括：蝕刻停止層，位於所述檯面結構上，且所述蝕刻停止層在所述檯面結構與所述基底之間，其中所述凸塊結構穿過所述蝕刻停止層突出到所述擴散層。在一些實施例中，所述凸塊結構包繞在所述蝕刻停止層的鄰接的隅角周圍。在一些實施例中，所述蝕刻停止層是介電性的，且其中所述凸塊結構包含金屬。在一些實施例中，所述擴散層包含來自所述檯面結構的鍺、鎵、砷、或它們的任意組合，且所述擴散層還包含來自所述凸塊結構的鎳、金、或它們的任意組合。在一些實施例中，所述凸塊結構的側壁相對於所述檯面結構的所述側壁在側向上偏置。在一些實施例中，所述檯面結構包括由不同的III-V族層形成的交錯堆疊。在一些實施例中，所述積體晶片還包括：導電接觸件，位於所述檯面結構上，其中所述檯面結構位於所述導電接觸件與所述凸塊結構之間；以及導電結構，從所述基底延伸到所述導電接觸件。在一些實施例中，所述基底包括：半導體基底；互補金屬氧化物半導體元件，位於所述半導體基底上；以及內連線結構，覆蓋所述半導體基底及所述互補金屬氧化物半導體元件。
在一些實施例中，本申請提供一種形成積體晶片的方法，所述方法包括：形成包括磊晶堆疊及位於所述磊晶堆疊上的第一金屬凸塊的晶片，其中所述第一金屬凸塊被定位到所述磊晶堆疊的檯面區域；在基底上形成第二金屬凸塊；在所述第一金屬凸塊與所述第二金屬凸塊相互接觸的介面處將所述晶片結合到所述基底；以及向所述晶片執行蝕刻，以在所述磊晶堆疊的所述檯面區域處界定檯面結構，其中所述檯面結構的側壁相對於所述第一金屬凸塊的側壁在側向上偏置。在一些實施例中，所述形成所述晶片包括通過金屬剝除製程在所述磊晶堆疊上形成所述第一金屬凸塊。在一些實施例中，所述形成所述第二金屬凸塊包括：在所述基底上形成金屬晶種層；在所述金屬晶種層上形成罩幕，其中所述罩幕界定開口，所述開口暴露出所述金屬晶種層；以及執行鍍覆製程以在所述開口中形成所述第二金屬凸塊，其中所述金屬晶種層在所述鍍覆製程期間成為所述第二金屬凸塊的晶種。在一些實施例中，所述形成積體晶片的方法還包括：執行向所述晶種層中的第二蝕刻，以移除所述晶種層的未被所述第二金屬凸塊覆蓋的部分，其中所述第二蝕刻是在所述結合之前執行。在一些實施例中，所述形成積體晶片的方法還包括：向所述晶種層執行第二蝕刻，以移除所述晶種層的未被所述第二金屬凸塊覆蓋的部分，其中所述第二蝕刻是在所述蝕刻之後執行。在一些實施例中，所述形成所述晶片包括：在所述磊晶堆疊上沉積蝕刻停止層；將所述蝕刻停止層圖案化，以在所述磊晶堆疊的所述檯面區域處界定開口；以及通過金屬剝除製程在所述開口中形成所述第一金屬凸塊，其中蝕刻在所述蝕刻停止層上停止。
在一些實施例中，本申請提供另一種形成積體晶片的方法，所述方法包括：形成包括磊晶堆疊、蝕刻停止層及金屬層的晶片，其中所述蝕刻停止層位於所述磊晶堆疊與所述金屬層之間；在基底上形成第一金屬凸塊；將所述晶片結合到所述基底，使得所述金屬層位於所述第一金屬凸塊與所述磊晶堆疊之間；向所述磊晶堆疊執行蝕刻，以界定檯面結構，其中所述蝕刻在所述蝕刻停止層上停止；將所述蝕刻停止層圖案化，以將所述檯面結構的圖案轉移到所述蝕刻停止層；以及將所述金屬層圖案化，以在所述第一金屬凸塊與所述檯面結構之間形成第二金屬凸塊。在一些實施例中，所述形成所述晶片包括：在所述磊晶堆疊上沉積所述蝕刻停止層；將所述蝕刻停止層圖案化，以在所述磊晶堆疊的檯面區域處界定開口；以及沉積覆蓋所述蝕刻停止層並填充所述開口的所述金屬層。在一些實施例中，所述形成所述第一金屬凸塊包括：在所述基底上形成晶種層；在所述晶種層上形成罩幕，其中所述罩幕界定開口，所述開口暴露出所述晶種層；以及執行鍍覆製程以在所述開口中形成所述第一金屬凸塊，其中所述晶種層在所述鍍覆製程期間成為所述第一金屬凸塊的晶種。在一些實施例中，所述的方法還包括：將所述晶種層圖案化以移除所述晶種層的未被所述第一金屬凸塊覆蓋的部分，其中所述晶種層的所述圖案化是在所述蝕刻之後執行。在一些實施例中，所述的方法還包括：形成環繞所述檯面結構的介電結構；形成穿過所述介電結構延伸到所述基底的通孔；在所述檯面結構上形成接觸件，其中所述接觸件具有環形佈局；以及形成將所述接觸件電耦合到所述通孔的配線。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本發明的各個方面。所屬領域中的技術人員應理解，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替及變更。
100、400A、400B、500A、500B、500C、1000、1200、1300、1400、1500、1600、1700、1800、1900、2000、2100、2200、2300、2400、2500、2700、2800、2900、3000、3100、3200、3300、3400、3600、3700、3800、3900、4000‧‧‧剖視圖102‧‧‧III-V族元件102a‧‧‧第一III-V族元件102b‧‧‧第二III-V族元件104‧‧‧基底106‧‧‧接墊106a‧‧‧第一接墊106b‧‧‧第二接墊106c‧‧‧第三接墊108‧‧‧檯面結構110‧‧‧凸塊結構112‧‧‧檯面側凸塊112a‧‧‧第一凸塊區段112b‧‧‧第二凸塊區段114‧‧‧基底側凸塊116‧‧‧結合介面118‧‧‧擴散層120‧‧‧背側接觸件122‧‧‧前側接觸件124‧‧‧導電結構124v、518‧‧‧通孔124w、516‧‧‧配線126‧‧‧介電結構128‧‧‧接觸開口130‧‧‧第一布拉格反射器132‧‧‧第二布拉格反射器134‧‧‧主動層136‧‧‧第一反射器層138‧‧‧第二反射器層140‧‧‧反射器層對200、300‧‧‧俯視圖402‧‧‧蝕刻停止層/第二蝕刻停止層502‧‧‧硬罩幕504‧‧‧側壁間隔件508‧‧‧半導體基底/第二半導體基底510‧‧‧半導體元件512‧‧‧內連線結構514‧‧‧內連線介電層600A、700A、900A、1100A‧‧‧圖/俯視佈局600B、700B、900B、1100B‧‧‧圖/剖視圖602‧‧‧第一工件604、904‧‧‧晶粒區606‧‧‧第一半導體基底608‧‧‧第一蝕刻停止層610‧‧‧磊晶堆疊702‧‧‧檯面區域704、1102、1702、2104、2302、2402、2502、2804‧‧‧光阻罩幕706‧‧‧檯面側凸塊層706a‧‧‧第一檯面側凸塊層706b‧‧‧第二檯面側凸塊層800‧‧‧俯視佈局802‧‧‧晶片902‧‧‧第二工件1002‧‧‧第一接觸層1004‧‧‧晶種層1402‧‧‧保護層1602‧‧‧硬罩幕層2102‧‧‧通孔開口2404‧‧‧第二接觸層2504‧‧‧導電層2600、3500、4100‧‧‧方塊圖2602、2604、2606、2608、2610、2612、2614、2616、2618、2620、3502、3504、3506、3508、3510、3512、3514、3516、3518、3520、3522、3524、4102、4104、4106、4108、4110、4112、4114、4116、4118、4120、4122、4124‧‧‧步驟2802‧‧‧檯面開口A、B‧‧‧線D‧‧‧距離D1、D2‧‧‧直徑ID‧‧‧內徑OD‧‧‧外徑OS‧‧‧上覆位移
包含附圖以便進一步理解本發明，且附圖併入本說明書中並構成本說明書的一部分。附圖說明本發明的實施例，並與描述一起用於解釋本發明的原理。結合附圖閱讀以下詳細說明，會最好地理解本發明的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1示出利用預圖案化檯面側（mesa-side）凸塊將III-V族元件結合到基底的積體晶片的一些實施例的剖視圖。 圖2示出圖1所示III-V族元件的前側接觸件的一些實施例的俯視圖。 圖3示出圖1所示III-V族元件的檯面側凸塊及基底側凸塊的一些實施例的俯視圖。 圖4A及圖4B示出其中III-V族元件具有蝕刻停止層的圖1所示積體晶片的各種替代性實施例的剖視圖。 圖5A到圖5C示出包括結合到基底且根據圖1、圖4A及圖4B所示III-V族元件的更詳細實施例而分別配置的多個III-V族元件的積體晶片的各種實施例的剖視圖。 圖6A、圖6B、圖7A、圖7B、圖8、圖9A、圖9B、圖10、圖11A、圖11B、及圖12到圖25示出形成包括利用預圖案化檯面側凸塊結合到基底的多個III-V族元件的積體晶片的方法的一些實施例的一系列圖。 圖26示出圖6A、圖6B、圖7A、圖7B、圖8、圖9A、圖9B、圖10、圖11A、圖11B、及圖12到圖25所示方法的一些實施例的方塊圖。 圖27到圖34示出形成包括結合到基底的多個III-V族元件且具有蝕刻停止層的積體晶片的方法的一些實施例的一系列剖視圖。 圖35示出圖27到圖34所示方法的一些實施例的方塊圖。 圖36到圖40示出形成包括利用預圖案化檯面側凸塊結合到基底的多個III-V族元件且多個III-V族元件具有蝕刻停止層的積體晶片的方法的一些實施例的一系列剖視圖。 圖41示出圖36到圖40所示方法的一些實施例的方塊圖。
100‧‧‧剖視圖
102‧‧‧III-V族元件
104‧‧‧基底
106a‧‧‧第一接墊
106b‧‧‧第二接墊
108‧‧‧檯面結構
110‧‧‧凸塊結構
112‧‧‧檯面側凸塊
112a‧‧‧第一凸塊區段
112b‧‧‧第二凸塊區段
114‧‧‧基底側凸塊
116‧‧‧結合介面
118‧‧‧擴散層
120‧‧‧背側接觸件
122‧‧‧前側接觸件
124‧‧‧導電結構
126‧‧‧介電結構
128‧‧‧接觸開口
130‧‧‧第一布拉格反射器
132‧‧‧第二布拉格反射器
134‧‧‧主動層
136‧‧‧第一反射器層
138‧‧‧第二反射器層
140‧‧‧反射器層對
D‧‧‧距離

Claims (1)

  1. 一種積體晶片，包括： 基底； 檯面結構，位於所述基底上且包含半導體材料； 凸塊結構，位於所述基底與所述檯面結構之間，其中所述凸塊結構包含導電材料；以及 擴散層，凹陷到所述檯面結構中，位於所述凸塊結構與所述檯面結構之間， 其中所述擴散層包含分別來自所述檯面結構及所述凸塊結構的所述半導體材料及所述導電材料，且 所述擴散層的側壁從所述檯面結構的側壁間隔開。
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