TW202002229A - 三維積體電路結構 - Google Patents

三維積體電路結構 Download PDF

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TW202002229A
TW202002229A TW107132238A TW107132238A TW202002229A TW 202002229 A TW202002229 A TW 202002229A TW 107132238 A TW107132238 A TW 107132238A TW 107132238 A TW107132238 A TW 107132238A TW 202002229 A TW202002229 A TW 202002229A
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Taiwan
Prior art keywords
die
alignment mark
integrated circuit
seal ring
bonding
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TW107132238A
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English (en)
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陳潔
陳憲偉
陳英儒
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台灣積體電路製造股份有限公司
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Publication of TW202002229A publication Critical patent/TW202002229A/zh

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Abstract

本發明實施例公開多種三維積體電路結構。一種三維積體電路結構包括第一晶粒以及接合到所述第一晶粒的第二晶粒。所述第一晶粒包括第一積體電路區以及圍繞所述第一積體電路區的第一密封環區，且具有位於所述第一積體電路區內的第一對準標記。所述第二晶粒包括第二積體電路區以及圍繞所述第二積體電路區的第二密封環區，且具有位於所述第二密封環區內且與所述第一對準標記對應的第二對準標記。

Description

三維積體電路結構
本發明實施例是關於三維積體電路結構。
近年來，由於各種電子元件（例如，電晶體、二極體、電阻器、電容器等）的集成密度持續提高，半導體行業已經歷了快速成長。在很大程度上來說，集成密度的這種提高歸因於最小特徵大小（minimum feature size）的連續減小，這使得在給定區域中能夠集成有更多組件。
這些較小的電子元件也需要與先前的封裝相比佔據較小面積的較小的封裝。半導體的封裝類型的實例包括方形扁平封裝（quad flat pack，QFP）、引腳柵陣列（pin grid array，PGA）封裝、球柵陣列（ball grid array，BGA）封裝、倒裝晶片（flip chip，FC）、三維積體電路（three-dimensional integrated circuit，3DIC）、晶圓級封裝（wafer level package，WLP）以及疊層封裝（package on package，PoP）裝置等。一些三維積體電路是通過將晶片放置在半導體晶圓級上的晶片之上製備而成。三維積體電路提供提高的集成密度及其他優點，例如更快的速度及更高的頻寬，這是因為堆疊的晶片之間的內連線的長度減小。然而，仍存在諸多與三維積體電路相關的挑戰。
根據本發明的一些實施例，一種三維積體電路結構包括第一晶粒及接合到所述第一晶粒的第二晶粒。所述第一晶粒包括第一積體電路區、圍繞所述第一積體電路區的第一密封環區以及位於所述第一積體電路區內的第一對準標記。所述第二晶粒包括第二積體電路區、圍繞所述第二積體電路區的第二密封環區以及位於所述第二密封環區內且與所述第一對準標記對應的第二對準標記。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例從而以簡化方式傳達本公開。當然，這些僅為實例而非旨在進行限制。舉例來說，在以下說明中，在第一特徵之上或第一特徵上形成第二特徵可包括其中第二特徵與第一特徵被形成為直接接觸的實施例，且也可包括其中第二特徵與第一特徵之間可形成附加特徵從而使得第二特徵與第一特徵可不直接接觸的實施例。另外，在本公開的各種實例中可使用相同的參考編號及/或字母來指代相同或類似的部件。參考編號的此種重複使用是為了簡明及清晰起見，且自身並不表示所討論的各個實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「在…之下」、「在…下方」、「下部」、「在…上」、「在…之上」、「位於…上方」、「在…上」、「上部」等空間相對性用語來闡述圖中所示一個元件或特徵與另一（其他）元件或特徵的關係。除了附圖中所繪示的取向以外，所述空間相對性用語更旨在涵蓋裝置在使用或操作中的不同取向。設備可具有另外的取向（旋轉90度或處於其他取向），且本文所使用的空間相對性用語可同樣相應地作出解釋。
圖1是根據一些實施例的三維積體電路結構的剖視圖。圖2是根據一些實施例的三維積體電路結構的簡化俯視圖。具體來說，圖1是沿圖2所示的線I-I截取的剖視圖。為使說明簡化及清晰，僅在圖2所示的簡化俯視圖中示出了例如第一晶粒和第二晶粒以及第一對準標記和第二對準標記等少數元件，且該些元件未必位於同一平面中。圖3是圖2所示部分A的放大俯視圖。
參照圖1，提供了第一晶粒100。第一晶粒100可例如為應用專用積體電路（application-specific integrated circuit，ASIC）晶片、類比（analog）晶片、感測器晶片、無線及射頻晶片、電壓調節器晶片或存儲晶片。在一些實施例中，第一晶粒100可為主動元件或被動元件。在一些實施例中，第一晶粒100包括第一半導體基底102、第一內連結構104、多個第一密封環圖案SP1、第一對準標記AM1以及第一接合結構BS1。
在一些實施例中，第一半導體基底102包括元素半導體（例如，矽或鍺）及/或化合物半導體（例如矽鍺、碳化矽、砷化鎵、砷化銦、氮化鎵或磷化銦）。在一些實施例中，第一半導體基底102為絕緣體上半導體（semiconductor-on-insulator，SOI）基底。在各種實施例中，第一半導體基底102可採用平面基底、具有多個鰭的基底、奈米管的形式、或所屬領域中的通常知識者已知的其他形式。取決於設計的要求，第一半導體基底102可為P型基底或N型基底且可在其中具有摻雜區。可針對N型裝置或P型裝置配置摻雜區。
在一些實施例中，第一半導體基底102包括第一積體電路區10以及位於第一積體電路區10周圍或環繞第一積體電路區10的第一密封環區12。第一積體電路區10以及第一密封環區12構成第一晶粒100的第一晶粒區或晶片區。
在一些實施例中，第一半導體基底102包括界定至少一個主動區域的隔離結構，且第一裝置層設置在所述主動區域上/中。第一裝置層包括多個裝置。在一些實施例中，所述裝置包括主動元件、被動元件或其組合。在一些實施例中，所述裝置可包括積體電路裝置。所述裝置例如為電晶體、電容器、電阻器、二極體、光電二極體、熔絲裝置或其他類似裝置。在一些實施例中，第一裝置層包括閘極結構、源極區/汲極區、間隔件等。
第一內連結構104設置在第一半導體基底102的第一側（例如，前側）之上。具體來說，第一內連結構104設置在第一積體電路區10內的第一裝置層之上且電連接到所述第一裝置層。在一些實施例中，第一內連結構104包括至少一個第一絕緣層106以及多個第一金屬特徵108。第一金屬特徵108設置在第一絕緣層106中且彼此電連接。第一金屬特徵108的一部分（例如，第一頂部金屬特徵108a及108b）被第一絕緣層106暴露出。在一些實施例中，第一絕緣層106包括位於第一半導體基底102上的層間介電（inter-layer dielectric，ILD）層、以及位於所述層間介電層之上的至少一個金屬間介電（inter-metal dielectric，IMD）層。在一些實施例中，第一絕緣層106包含氧化矽、氮氧化矽、氮化矽、低介電常數（低k）材料或其組合。第一絕緣層106可以是單個層或多層結構。在一些實施例中，第一金屬特徵108包括插塞及金屬線。所述插塞可包括形成在層間介電層中的接觸件（contacts）以及形成在金屬間介電層中的通孔（vias）。所述接觸件形成在底部金屬線與位於下方的第一裝置層之間且與底部金屬線與位於下方的第一裝置層接觸。所述通孔形成在兩條金屬線之間且與所述兩條金屬線接觸。第一金屬特徵108可包含鎢（W）、銅（Cu）、銅合金、鋁（Al）、鋁合金或其組合。在一些實施例中，可在第一金屬特徵108與第一絕緣層106之間設置障壁層，以防止第一金屬特徵108的材料遷移到位於下方的第一裝置層。障壁層包含例如Ta、TaN、Ti、TiN、CoW或其組合。在一些實施例中，第一內連結構104是通過雙鑲嵌製程形成。在替代實施例中，第一內連結構104是通過多個單鑲嵌製程形成。在另一些替代實施例中，第一內連結構104是通過電鍍製程形成。
第一密封環圖案SP1設置在第一半導體基底102的第一側（例如，前側）之上。具體來說，第一密封環圖案SP1設置在第一裝置層之上且與第一裝置層電絕緣，且在第一密封環區12內位於第一內連結構104旁邊。在一些實施例中，第一密封環圖案SP1具有格柵狀形狀、條帶形狀、環形形狀或任意適當的形狀。在一些實施例中，第一內連結構104被排列成形成第一密封環圖案SP1。也就是說，在形成第一內連結構104期間形成第一密封環圖案SP1。
本文中，當元件被闡述為「處於實質上相同的水平高度（at substantially the same level）」時，這些元件是在相同的層中形成於實質上相同的高度，或者具有被相同的層嵌置的相同的位置。在一些實施例中，處於實質上相同的水平高度的元件是使用相同的製程步驟由相同的材料形成。在一些實施例中，處於實質上相同的水平高度的元件的頂部實質上共面。舉例來說，如圖1所示，第一密封環圖案SP1與第一內連結構104處於實質上相同的水平高度處。具體來說，第一密封環圖案SP1的頂表面與第一內連結構104的第一頂部金屬特徵108a及108b的頂表面實質上共面。
第一對準標記AM1設置在第一半導體基底102的第一側（例如，前側）之上。具體來說，第一對準標記AM1設置在第一裝置層之上且與第一裝置層電絕緣，且在第一積體電路區10內位於第一內連結構104的第一頂部金屬特徵108a與108b之間。在一些實施例中，第一對準標記AM1處於浮動電位。在一些實施例中，第一內連結構104被排列成形成第一對準標記AM1。具體來說，在形成第一內連結構104的第一頂部金屬特徵108a及108b期間形成第一對準標記AM1。在一些實施例中，第一對準標記AM1包含金屬，例如銅。在一些實施例中，第一對準標記AM1與第一內連結構104的第一頂部金屬特徵108a及108b處於實質上同一水平高度處。具體來說，如圖1所示，第一對準標記AM1的頂表面與第一內連結構104的第一頂部金屬特徵108a及108b的頂表面實質上共面。
在一些實施例中，第一對準標記AM1是正方形、矩形、多邊形、圓形、橢圓形、條帶形、T形、L形、盒形（box-shaped）、十字形的或任意適當的形狀。舉例來說，第一對準標記AM1被設計為正方形盒（square box）或正方形圖案，如圖2及圖3中所示。
在一些實施例中，在實行用於界定圖案的光阻層的曝光製程之前，利用安裝在曝光設備上的成像裝置偵測對準標記。在一些實施例中，可將對準標記稱為交疊標記（overlay marks）。具體來說，在將兩個層、元件或晶粒彼此接合時，可基於上部對準標記與下部對準標記是否準確地彼此對準而檢查兩個層、元件或晶粒的對準標記以查看交疊準確性。因此，對準標記可充當交疊標記。在一些實施例中，在說明書通篇中，將第一對準標記AM1稱為第一交疊標記。
在一些實施例中，在第一積體電路區10中設置多個第一對準標記AM1。在一些實施例中，在第一積體電路區10的成對角的隅角中設置兩個第一對準標記AM1，如圖2所示。在替代實施例中，在第一積體電路區10的四個隅角中設置四個第一對準標記AM1，如圖4所示。
第一接合結構BS1設置在第一內連結構104的第一側（例如，前側）之上。具體來說，第一接合結構BS1在第一積體電路區10內設置在第一內連結構104之上。在一些實施例中，第一接合結構BS1包括至少一個第一接合介電層BDL1及多個第一接合金屬特徵。在一些實施例中，第一接合介電層BDL1包含氧化矽、氮化矽、聚合物或其組合。第一接合金屬特徵設置在第一接合介電層BDL1中且彼此電連接。在一些實施例中，第一接合金屬特徵包括電連接到第一內連結構104的第一接合通孔BV1以及電連接到第一接合通孔BV1的第一接合墊BP1。第一接合金屬特徵可包含鎢（W）、銅（Cu）、銅合金、鋁（Al）、鋁合金或其組合。在一些實施例中，可在第一接合金屬特徵與第一接合介電層BDL1之間設置障壁層。所述障壁層例如包含Ta、TaN、Ti、TiN、CoW或其組合。在一些實施例中，第一接合結構BS1是通過雙鑲嵌製程形成。在替代實施例中，第一接合結構BS1是通過多個單鑲嵌製程形成。在另一些替代實施例中，第一接合結構BS1是通過電鍍製程形成。
仍參照圖1，提供第二晶粒200。第二晶粒200可例如為應用專用積體電路（ASIC）晶片、類比晶片、感測器晶片、無線及射頻晶片、電壓調節器晶片或存儲晶片。第二晶粒200與第一晶粒100可為同一類型的晶粒或不同類型的晶粒。在一些實施例中，第二晶粒200可為主動元件或被動元件。在一些實施例中，第二晶粒200小於第一晶粒100。
在一些實施例中，第二晶粒200類似于第一晶粒100。類似地，第二晶粒200包括第二半導體基底202、第二內連結構204、多個第二密封環圖案SP2、第二對準標記AM2以及第二接合結構BS2。因此，以下詳細示出第二晶粒200與第一晶粒100之間的差異，且在本文中不再對所述兩者之間的相似之處進行贅述。
第二半導體基底202類似於第一半導體基底102。類似地，第二半導體基底202包括第二積體電路區20及位於第二積體電路區20周圍或環繞第二積體電路區20的第二密封環區22。第二積體電路區20以及第二密封環區22構成第二晶粒200的第二晶粒區或晶片區。
第二內連結構204類似於第一內連結構104。類似地，第二內連結構204設置在第二半導體基底202的第一側（例如，前側）之上。具體來說，第二內連結構204在第二積體電路區20內設置在第二裝置層之上且電連接到所述第二裝置層。在一些實施例中，第二內連結構204包括至少一個第二絕緣層206以及多個第二金屬特徵208。第二金屬特徵208設置在第二絕緣層206中且彼此電連接。第二金屬特徵208的一部分（例如，第二頂部金屬特徵208a）被第二絕緣層206暴露出。
第二接合結構BS2類似於第一接合結構BS1。類似地，第二接合結構BS2設置在第二內連結構204的第一側（例如，前側）之上。具體來說，第二接合結構BS2在第二積體電路區20內設置在第二內連結構204之上。在一些實施例中，第二接合結構BS2包括至少一個第二接合介電層BDL2及多個第二接合金屬特徵。第二接合金屬特徵設置在第二接合介電層BDL2中且彼此電連接。在一些實施例中，第二接合金屬特徵包括電連接到第二內連結構204的第二接合通孔BV2以及電連接到第二接合通孔BV2的第二接合墊BP2。
第二密封環圖案SP2類似於第一密封環圖案SP1。類似地，第二密封環圖案SP2設置在第二半導體基底202的第一側（例如，前側）之上。具體來說，第二密封環圖案SP2設置在第二裝置層之上且與第二裝置層電絕緣，且在第二密封環區22內位於第二內連結構204旁邊。在一些實施例中，第二密封環圖案SP2具有格柵狀形狀、條帶形狀、環形形狀或任意適當的形狀。在一些實施例中，第二內連結構204被排列成形成第二密封環圖案SP2。也就是說，在形成第二內連結構204期間形成第二密封環圖案SP2。如圖1所示，第二密封環圖案SP2與第二內連結構204處於實質上同一水平高度處。具體來說，第二密封環圖案SP2的頂表面與第二內連結構204的第二頂部金屬特徵208a的頂表面實質上共面。
第二對準標記AM2設置在第二半導體基底202的第一側（例如，前側）之上。具體來說，第二對準標記AM2設置在第二裝置層之上且與第二裝置層電絕緣，且在第二密封環區22內位於第二密封環圖案SP2之間。在一些實施例中，第二對準標記AM2處於浮動電位。在一些實施例中，第二內連結構204被排列成形成第二對準標記AM2。在一些實施例中，第二對準標記AM2包含金屬，例如銅。具體來說，在形成第二內連結構204的第二頂部金屬特徵208a期間形成第二對準標記AM2。在一些實施例中，第二對準標記AM2與第二內連結構204的第二頂部金屬特徵208a處於實質上同一水平高度處。具體來說，如圖1所示，第二對準標記AM2的頂表面與第二內連結構204的第二頂部金屬特徵208a的頂表面實質上共面。
在一些實施例中，第二對準標記AM2是正方形、矩形、多邊形、圓形、橢圓形、條帶形、T形、L形、盒形、十字形的或任意適當的形狀。舉例來說，第二對準標記AM2被設計為四個正方形島（square islands）或正方形圖案，如圖2及圖3中所示。
在一些實施例中，在說明書通篇中將第二對準標記AM2稱為第二交疊標記。在一些實施例中，在第二密封環區22中設置多個第二對準標記AM2。在一些實施例中，在第二密封環區22的成對角的隅角中設置兩個第二對準標記AM2，如圖2所示。在替代實施例中，在第二密封環區22的四個隅角中設置四個第二對準標記AM2，如圖4所示。
第二晶粒200與第一晶粒100之間的一個差異在於晶粒大小。在一些實施例中，第二晶粒200的大小不同於（例如，小於）第一晶粒100的大小。在本文中，用語「大小」是指長度、寬度及/或面積。舉例來說，如在圖2及圖4的俯視圖中所示，第二晶粒200的大小或面積小於第一晶粒100的大小或面積。
第二晶粒200與第一晶粒100之間的另一個差異在於對準標記的位置。具體來說，第二晶粒200的第二對準標記AM2位於第二密封環區22內，而第一晶粒100的第一對準標記AM1位於第一積體電路區10內。
繼續參照圖1，將第二晶粒200上下倒置並安裝在第一晶粒100上。在一些實施例中，通過第二接合結構BS2及第一接合結構BS1將第二晶粒200及第一晶粒100面對面地接合在一起。在一些實施例中，在將第二晶粒200接合到第一晶粒100之前，將第二接合結構BS2與第一接合結構BS1對準，使得第二接合墊BP2接合到第一接合墊BP1，且第二接合介電層BDL2接合到第一接合介電層BDL1。在一些實施例中，可利用光學感測方法實現第一接合結構BS1與第二接合結構BS2的對準。在實現對準之後，通過混合接合（hybrid bonding）將第一接合結構BS1及第二接合結構BS2接合在一起，所述混合接合包括金屬對金屬接合及介電質對介電質接合。
在將第二晶粒200接合到第一晶粒100之後，第二對準標記AM2對應於第一對準標記AM1，用於檢查第一晶粒100的第一對準標記AM1（或稱為第一交疊標記）與第二晶粒200的第二對準標記AM2（或稱為第二交疊標記）之間的交疊準確性。在一些實施例中，交疊測量是指在光學上測量不同晶粒的交疊標記的相對位置。在一些實施例中，通過光學工具（例如，光學顯微鏡）測量對準標記。
應注意，從圖2及圖3的俯視圖看，第一對準標記AM1及第二對準標記AM2兩者都位於第二晶粒200的第二密封環區22的隅角內。具體來說，第二晶粒200包括第二積體電路區20、位於第二積體電路區20周圍的第二密封環區22、以及位於第二密封環區22內的對準標記區21。更具體來說，在俯視圖中，第一對準標記AM1及第二對準標記AM2兩者都位於第二晶粒200的對準標記區21內。在一些實施例中，從俯視圖看，第一晶粒100的第一對準標記AM1環繞第二晶粒200的第二對準標記AM2，且第二密封環圖案SP2環繞第一對準標記AM1。第二密封環圖案SP2與第一對準標記AM1分隔開一定距離。
在一些實施例中，第一對準標記AM1被設計為正方形盒，且第二對準標記AM2被設計為所述正方形盒內的四個正方形島，如在圖2到圖5中所示。在一些實施例中，如在圖5中所示，第二對準標記AM2的一個正方形島的尺寸W為約2.5微米或大於2.5微米，第二對準標記AM2的一個正方形島與第一對準標記AM1的正方形盒之間的第一距離（例如，垂直距離）D1為約2.5微米或大於2.5微米，且第二對準標記AM2的一個正方形島與第一對準標記AM1的正方形盒之間的第二距離（例如，水平距離）D2為約2.5微米或大於2.5微米。
在一些實施例中，在圖1所示的三維積體電路結構中更包括介電包封體DE、多個介電穿孔TDV、重佈線層結構302、多個墊308以及鈍化層310。
介電包封體DE設置在第一晶粒100之上且設置在第二晶粒200旁邊。具體來說，介電包封體DE環繞第二晶粒200的側壁，暴露出第二晶粒200的頂部並覆蓋第一晶粒100的第一側（例如，前側）。在一些實施例中，第二晶粒200的第二側（例如，後側）與介電包封體DE的頂表面實質上是平面的。在一些實施例中，介電包封體DE包含模制化合物。所述模制化合物可包括樹脂及填料。在替代實施例中，介電包封體DE包含氧化矽、氮化矽或其組合。介電包封體DE可通過旋轉塗布、層壓、沉積等形成。在一些實施例中，貫穿第二半導體基底202形成多個基底穿孔（through-substrate via，TSV），且所述多個基底穿孔電連接到第二內連結構204。
介電穿孔TDV設置在介電包封體DE中且與第一內連結構104及待形成的重佈線層結構302電連接。在一些實施例中，介電穿孔TDV包括導電通孔。導電通孔包含銅、銅合金、鋁、鋁合金或其組合。在一些實施例中，介電穿孔TDV更包括位於導電通孔與介電包封體DE之間的擴散障壁層。所述擴散障壁層包含Ta、TaN、Ti、TiN、CoW或其組合。
重佈線層結構302設置在第二晶粒200的第二側（例如，後側）之上以及介電包封體DE之上。重佈線層結構302包括交替地堆疊的至少一個介電層304及至少一個導電層306。在一些實施例中，重佈線層結構302的一部分電連接到介電穿孔TDV。在一些實施例中，重佈線層結構302的另一部分電連接到矽穿孔。在一些實施例中，介電層304包含感光性材料，例如聚苯並惡唑（PBO）、聚醯亞胺（PI）、苯並環丁烯（BCB）、或其組合等。在一些實施例中，導電層306包含銅、鎳、鈦、或其組合等。
墊308設置在重佈線層結構302之上。在一些實施例中，墊308為用於安裝導電連接件（例如金屬柱、或μ-凸塊等）的凸塊下金屬（under bump metallization，UBM）墊。墊308包含金屬或金屬合金。墊308包含鋁、銅、鎳或其合金。
鈍化層310覆蓋介電層304及墊308的邊緣部分，並暴露出墊308的中心部分。在一些實施例中，鈍化層110包含氧化矽、氮化矽、苯並環丁烯（BCB）聚合物、聚醯亞胺（PI）、聚苯並惡唑（PBO）或其組合。
提供其中第一對準標記AM1被設計為具有盒形圖案且第二對準標記AM2被設計為具有四個正方形圖案的上述實施例是用於例示目的，而不應被解釋為限制本公開。可視需要設計第一對準標記AM1及第二對準標記AM2中的每一者的圖案數量、圖案大小及形狀。在一些實施例中，從俯視圖看，第一對準標記AM1包括與第二對準標記AM2的形狀互補的形狀。
在一些實施例中，如在圖6中所示，第一對準標記AM1被設計為具有盒形圖案，第二對準標記AM2被設計為具有三個正方形圖案，且第二對準標記AM2的正方形圖案位於第一對準標記AM1的盒形圖案內。
在一些實施例中，如在圖7中所示，第一對準標記AM1被設計為具有四個圓形圖案，第二對準標記AM2被設計為具有十字形圖案，且當第一對準標記與第二對準標記對準時，第一對準標記AM1的圓形圖案位於第二對準標記AM2的十字形圖案周圍。
在一些實施例中，如在圖8中所示，第一對準標記AM1被設計為具有四個正方形圖案，第二對準標記AM2被設計為具有十字形圖案，且當第一對準標記與第二對準標記對準時，第一對準標記AM1的正方形圖案位於第二對準標記AM2的十字形圖案周圍。
在一些實施例中，如在圖9中所示，第一對準標記AM1被設計為具有盒形圖案，第二對準標記AM2被設計為具有十字形圖案，且當第一對準標記與第二對準標記對準時，第二對準標記AM2的十字形圖案位元於第一對準標記AM1的盒形圖案內。
在一些實施例中，如在圖10中所示，第一對準標記AM1被設計為具有盒形圖案，第二對準標記AM2被設計為具有另一盒形圖案，且當第一對準標記與第二對準標記對準時，第二對準標記AM2的盒形圖案位於第一對準標記AM1的盒形圖案內。
提供其中針對下部元件、裝置或晶粒設計第一對準標記AM1且針對上部元件、裝置或晶粒設計第二對準標記AM2的上述實施例是用於例示目的，而不應被解釋為限制本公開。
圖5到圖10所示的第一對準標記AM1及第二對準標記AM2可進行交換。具體來說，在一些實施例中，可針對上部元件、裝置或晶粒設計第一對準標記AM1且可針對下部元件、裝置或晶粒設計第二對準標記AM2，如在圖11到圖16中所示。
在一些實施例中，如在圖1中所示，三維積體電路結構1包括第一晶粒100以及接合到第一晶粒100的第二晶粒200。第一晶粒100包括第一積體電路區10以及圍繞第一積體電路區10的第一密封環區12，且具有位於第一積體電路區10內的第一對準標記AM1。第二晶粒200包括第二積體電路區20以及圍繞第二積體電路區20的第二密封環區22，且具有位於第二密封環區22內且與第一對準標記AM1對應的第二對準標記AM2。
在一些實施例中，從俯視圖看，第一對準標記AM1位於第二密封環區22內。在一些實施例中，第一晶粒100更具有多個第一密封環圖案SP1，從俯視圖看，所述多個第一密封環圖案SP1位於第一密封環區12內且位於第二密封環區22外。在一些實施例中，第二晶粒200更具有多個第二密封環圖案SP2，所述多個第二密封環圖案SP2位於第二密封環區22內且環繞第二對準標記AM2。在一些實施例中，從俯視圖看，第二晶粒200的第二密封環圖案SP2落在第一晶粒100內。在一些實施例中，第一晶粒100更具有第一內連結構104，且第一內連結構104的第一頂部金屬特徵108a/108b處於與第一對準標記AM1的水平高度實質上相同的水平高度。在一些實施例中，第二晶粒200更具有第二內連結構204，且第二內連結構204的第二頂部金屬特徵208a處於與第二對準標記AM2的水平高度實質上相同的水平高度。在一些實施例中，第一對準標記AM1及第二對準標記AM2中的每一者的形狀是正方形、矩形、多邊形、圓形、橢圓形、條帶形、T形、L形、盒形或十字形。在一些實施例中，第二晶粒200通過混合接合而接合到第一晶粒100，所述混合接合包括金屬對金屬接合及介電質對介電質接合。
在一些實施例中，如在圖1中所示，三維積體電路結構1包括第一晶粒100以及第二晶粒200。第一晶粒100包括第一半導體基底102、位於第一半導體基底102之上的第一內連結構104、位於第一半導體基底102之上且位於第一內連結構104旁邊的第一對準標記AM1以及位於第一內連結構104和第一對準標記AM1之上的第一接合結構BS1。第二晶粒200包括第二半導體基底202、位於第二半導體基底202之上的第二內連結構204、位於第二半導體基底202之上且位於第二內連結構204旁邊的第二對準標記AM2以及位於第二內連結構204和第二對準標記AM2之上的第二接合結構BS2。使用第一接合結構BS1及第二接合結構BS2將第一晶粒100接合到第二晶粒200。第二晶粒200更包括位於第二內連結構204旁邊且環繞第二對準標記AM2的第二密封環圖案SP2。
在一些實施例中，從俯視圖看，第一對準標記AM1及第二對準標記AM2位於第二晶粒200的第二密封環區22的隅角內。在一些實施例中，三維積體電路結構1更包括位於第一晶粒100之上且環繞第二晶粒200的多個介電穿孔TDV。在一些實施例中，三維積體電路結構1更包括位於第二晶粒200之上且電連接到所述多個介電穿孔TDV的重佈線層結構302。在一些實施例中，第一接合結構BS1的第一接合墊BP1接合到第二接合結構BS2的第二接合墊BP2，且第一接合結構BS1的第一接合介電層BDL1接合到第二接合結構BS2的第二接合介電層BDL2。
在以上實施例中，針對兩個元件、裝置或晶粒需要兩個對準標記（或稱為交疊標記）用於檢查所述兩個元件、裝置或晶粒之間的交疊準確性。然而，本公開並不僅限於此。在替代實施例中，針對兩個元件、裝置或晶粒僅需要一個對準標記（或稱為交疊標記）用於檢查所述兩個元件、裝置或晶粒之間的交疊準確性。
圖17是根據替代實施例的三維積體電路結構的剖視圖。圖18是根據替代實施例的三維積體電路結構的簡化俯視圖。具體來說，圖17是沿圖18所示的線I-I截取的剖視圖。為使說明簡化及清晰，僅在圖18所示的簡化俯視圖中示出了例如第一晶粒和第二晶粒以及第一對準標記和第二對準標記等少數元件，且該些元件未必位於同一平面中。圖19是圖18所示部分A的放大俯視圖。
圖17所示的三維積體電路結構2類似於圖1所示的三維積體電路結構1。因此，以下詳細示出三維積體電路結構2與三維積體電路結構1之間的差異，且在本文中對所述兩者之間的相似之處不再進行贅述。
參照圖17，三維積體電路結構2包括第一晶粒100以及接合到第一晶粒100的第二晶粒200。在一些實施例中，第二晶粒200通過混合接合而接合到第一晶粒100，所述混合接合包括金屬對金屬接合及介電質對介電質接合。第一晶粒100包括第一積體電路區10及圍繞第一積體電路區10的第一密封環區12。第二晶粒200包括第二積體電路區20及圍繞第二積體電路區20的第二密封環區22。
在一些實施例中，第一晶粒100具有位於第一積體電路區10內的第一對準標記AM1。從俯視圖看，第一對準標記AM1位於第二密封環區22的隅角周圍，如在圖18及圖19中所示。在一些實施例中，第一晶粒100更具有位於第一密封環區12內位於第一對準標記AM1周圍的第一密封環圖案SP1。在一些實施例中，從俯視圖看，第一對準標記AM1的一部分被放置在第一密封環圖案SP1與第二密封環圖案SP2之間，如在圖17中所示。
三維積體電路結構2與三維積體電路結構1之間的一個差異在於，從俯視圖看，在圖17中的第一晶粒100的第一對準標記AM1位於第二密封環區22之外，而圖1中的第一晶粒100的第一對準標記AM1位於第二密封環區22內。
在一些實施例中，在第二密封環區22的隅角內不存在對準標記，如在圖18及圖19中所示。具體來說，在第二晶粒200的第二密封環區22的隅角中僅配置第二密封環圖案SP2。
三維積體電路結構2與三維積體電路結構1之間的另一個差異在於，針對圖1中的三維積體電路結構1配置了第二晶粒200的第二對準標記AM2，而未針對圖17中的三維積體電路結構2配置此種元件。相反，第二密封環區22的密封環邊界充當圖17中的三維積體電路結構2的第二晶粒200的第二對準標記。
在一些實施例中，第一對準標記AM1是正方形、矩形、多邊形、條帶形、T形、L形、盒形、十字形或任意適當的形狀。舉例來說，第一對準標記AM1被設計為正方形盒，如在圖17及圖18中所示。
在一些實施例中，在第一積體電路區10中設置多個第一對準標記AM1。在一些實施例中，在第二密封環區22的成對角的隅角周圍設置兩個第一對準標記AM1，如在圖18中所示。在替代實施例中，在第二密封環區22的四個隅角周圍設置四個第一對準標記AM1，如圖20中所示。
在一些實施例中，第一對準標記AM1包括與第二密封環區22的第一邊界SB1平行的第一對準圖案AP1以及與第二密封環區22的第二邊界SB2平行的第二對準圖案AP2，如圖19中所示。在一些實施例中，第一對準標記AM1的第一對準圖案AP1與第二密封環區22的第一邊界SB1之間的第一距離（例如，垂直距離）D1為約2微米到約10微米，且第一對準標記AM1的第二對準圖案AP2與第二密封環區22的第二邊界SB2之間的第二距離（例如，水平距離）D2為約2微米到約10微米。
在一些實施例中，第一對準標記AM1的第一對準圖案AP1及第二對準圖案AP2彼此連接。在替代實施例中，第一對準標記AM1的第一對準圖案AP1及第二對準圖案AP2可彼此分隔開。
在一些實施例中，第一對準標記AM1被設計為正方形盒，且從俯視圖看，第一晶粒100的第一對準標記AM1與第二晶粒200的第二密封環圖案SP2局部地交疊，如在圖17到圖20中所示。
在替代實施例中，第一對準標記AM1被設計為具有L形，且從俯視圖看，第一晶粒100的第一對準標記AM1不與第二晶粒200的第二密封環圖案SP2交疊，如在圖21到圖22中所示。
在本申請案中，以空間節省方式配置三維積體電路結構的對準標記。具體來說，在傳統的晶粒堆疊結構中，將兩個對準標記放置在兩個相接合的晶粒的積體電路區中，因此減小了可用的晶片面積。相反，在本申請案中，在一些實施例中，兩個相接合的晶粒的兩個對準標記被放置在一個晶粒的密封環區的至少一個隅角中，而不會減小可用的晶片面積。在替代實施例中，僅將一個對準標記放置在相接合的結構的一個晶粒的密封環區的至少一個隅角周圍，且因此不僅節省了晶片面積而且簡化了佈局設計。
綜上所述，本文中提供的經改善的晶粒對晶粒對準技術利用在一個晶粒的密封環區內或周圍形成對準標記（或交疊標記）。通過在一個晶粒的密封環區內或周圍提供對準標記（或交疊標記），可在不減小可用的晶片面積的情況下改善晶粒對晶粒對準。本公開設想上述實例的許多變型。應理解，不同的實施例可具有不同的優點，且所有的實施例未必需要特定的優點。
根據本公開的一些實施例，一種三維積體電路結構包括第一晶粒及接合到所述第一晶粒的第二晶粒。所述第一晶粒包括第一積體電路區以及圍繞所述第一積體電路區的第一密封環區，且具有位於所述第一積體電路區內的第一對準標記。所述第二晶粒包括第二積體電路區以及圍繞所述第二積體電路區的第二密封環區，且具有位於所述第二密封環區內且與所述第一對準標記對應的第二對準標記。
在所述的三維積體電路結構中，從俯視圖看，所述第一對準標記位於所述第二密封環區內。
在所述的三維積體電路結構中，所述第一晶粒更具有多個第一密封環圖案，從俯視圖看，所述多個第一密封環圖案位於所述第一密封環區內且位於所述第二密封環區外。
在所述的三維積體電路結構中，所述第二晶粒更具有多個第二密封環圖案，所述多個第二密封環圖案位於所述第二密封環區內且環繞所述第二對準標記。
在所述的三維積體電路結構中，所述第一晶粒更具有第一內連結構，且所述第一內連結構的第一頂部金屬特徵處於與所述第一對準標記的水平高度實質上相同的水平高度。
在所述的三維積體電路結構中，所述第二晶粒更具有第二內連結構，且所述第二內連結構的第二頂部金屬特徵處於與所述第二對準標記的水平高度實質上相同的水平高度。
在所述的三維積體電路結構中，所述第一對準標記及所述第二對準標記中的每一者的形狀是正方形、矩形、多邊形、圓形、橢圓形、條帶形、T形、L形、盒形或十字形。
在所述的三維積體電路結構中，所述第二晶粒通過混合接合而接合到所述第一晶粒，所述混合接合包括金屬對金屬接合及介電質對介電質接合。
根據本公開的替代實施例，一種三維積體電路結構包括第一晶粒及接合到所述第一晶粒的第二晶粒。所述第一晶粒包括第一積體電路區以及圍繞所述第一積體電路區的第一密封環區，且具有位於所述第一積體電路區內的第一對準標記。所述第二晶粒包括第二積體電路區及環繞所述第二積體電路區的第二密封環區。從俯視圖看，所述第一對準標記位於所述第二密封環區的隅角周圍。
在所述的三維積體電路結構中，所述第一對準標記包括與所述第二密封環區的第一邊界平行的第一對準圖案及與所述第二密封環區的第二邊界平行的第二對準圖案。
在所述的三維積體電路結構中，在所述第二密封環區的所述隅角內不存在對準標記。
在所述的三維積體電路結構中，從俯視圖看，所述第一晶粒的所述第一對準標記與所述第二晶粒的密封環圖案局部地交疊。
在所述的三維積體電路結構中，從俯視圖看，所述第一晶粒的所述第一對準標記不與所述第二晶粒的密封環圖案交疊。
在所述的三維積體電路結構中，所述第二晶粒通過混合接合而接合到所述第一晶粒，所述混合接合包括金屬對金屬接合及介電質對介電質接合。
根據本公開的又一些替代實施例，一種三維積體電路結構包括第一晶粒及第二晶粒。所述第一晶粒包括第一半導體基底、位於所述第一半導體基底之上的第一內連結構、位於所述第一半導體基底之上且位於所述第一內連結構旁邊的第一對準標記以及位於所述第一內連結構和所述第一對準標記之上的第一接合結構。所述第二晶粒包括第二半導體基底、位於所述第二半導體基底之上的第二內連結構、位於所述第二半導體基底之上且位於所述第二內連結構旁邊的第二對準標記以及位於所述第二內連結構和所述第二對準標記之上的第二接合結構。所述第一晶粒使用所述第一接合結構及所述第二接合結構接合到所述第二晶粒。所述第二晶粒更包括位於所述第二內連結構旁邊且環繞所述第二對準標記的密封環圖案。
在所述的三維積體電路結構中，從俯視圖看，所述第一對準標記及所述第二對準標記位於所述第二晶粒的第二密封環區的隅角內。
在所述的三維積體電路結構中，更包括位於所述第一晶粒之上且環繞所述第二晶粒的多個介電穿孔。
在所述的三維積體電路結構中，更包括位於所述第二晶粒之上且電連接到所述多個介電穿孔的重佈線層結構。
在所述的三維積體電路結構中，從俯視圖看，所述第一對準標記包括與所述第二對準標記的形狀互補的形狀。
在所述的三維積體電路結構中，從俯視圖看，所述第二晶粒的所述密封環圖案落在所述第一晶粒內。
本公開也可包括其他特徵及製程。舉例來說，可包括測試結構，以説明對三維（three-dimensional，3D）封裝或三維積體電路裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試墊，以使得能夠對三維封裝或三維積體電路進行測試、對探針及/或探針卡（probe card）進行使用等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可接合包括對已知良好晶粒（known good die）進行中間驗證的測試方法來使用，以提高良率並降低成本。
以上概述了若干實施例的特徵，以使所屬領域中的通常知識者可更好地理解本公開的各個方面。所屬領域中的通常知識者應理解，其可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的通常知識者更應認識到，這些等效構造並不背離本公開的精神及範圍，而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、替代及變更。
1、2‧‧‧三維積體電路結構10‧‧‧第一積體電路區12‧‧‧第一密封環區20‧‧‧第二積體電路區21‧‧‧對準標記區22‧‧‧第二密封環區100‧‧‧第一晶粒102‧‧‧第一半導體基底104‧‧‧第一內連結構106‧‧‧第一絕緣層108‧‧‧第一金屬特徵108a、108b‧‧‧第一頂部金屬特徵200‧‧‧第二晶粒202‧‧‧第二半導體基底204‧‧‧第二內連結構206‧‧‧第二絕緣層208‧‧‧第二金屬特徵208a‧‧‧第二頂部金屬特徵302‧‧‧重佈線層結構304‧‧‧介電層306‧‧‧導電層308‧‧‧墊310‧‧‧鈍化層A‧‧‧部分AM1‧‧‧第一對準標記AM2‧‧‧第二對準標記AP1‧‧‧第一對準圖案AP2‧‧‧第二對準圖案BDL1‧‧‧第一接合介電層BDL2‧‧‧第二接合介電層BP1‧‧‧第一接合墊BP2‧‧‧第二接合墊BS1‧‧‧第一接合結構BS2‧‧‧第二接合結構BV1‧‧‧第一接合通孔BV2‧‧‧第二接合通孔D1‧‧‧第一距離D2‧‧‧第二距離DE‧‧‧介電包封體SB1‧‧‧第一邊界SB2‧‧‧第二邊界SP1‧‧‧第一密封環圖案SP2‧‧‧第二密封環圖案TDV‧‧‧介電穿孔W‧‧‧尺寸
圖1是根據一些實施例的三維積體電路結構的剖視圖。 圖2是根據一些實施例的三維積體電路結構的簡化俯視圖。 圖3是圖2所示部分A的放大俯視圖。 圖4是根據一些實施例的三維積體電路結構的簡化俯視圖。 圖5到圖16是根據一些實施例的三維積體電路結構的對準標記（alignment marks）的俯視圖。 圖17是根據替代實施例的三維積體電路結構的剖視圖。 圖18是根據替代實施例的三維積體電路結構的簡化俯視圖。 圖19是圖18所示部分A的放大俯視圖。 圖20是根據替代實施例的三維積體電路結構的簡化俯視圖。 圖21到圖22是根據另一些替代實施例的三維積體電路結構的簡化俯視圖。
10‧‧‧第一積體電路區
12‧‧‧第一密封環區
20‧‧‧第二積體電路區
21‧‧‧對準標記區
22‧‧‧第二密封環區
A‧‧‧部分
AM1‧‧‧第一對準標記
AM2‧‧‧第二對準標記

Claims (1)

  1. 一種三維積體電路結構，包括： 第一晶粒，包括第一積體電路區、圍繞所述第一積體電路區的第一密封環區以及位於所述第一積體電路區內的第一對準標記；以及 第二晶粒，接合到所述第一晶粒，包括第二積體電路區、圍繞所述第二積體電路區的第二密封環區以及位於所述第二密封環區內且與所述第一對準標記對應的第二對準標記。
TW107132238A 2018-06-25 2018-09-13 三維積體電路結構 TW202002229A (zh)

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