TW201931549A - 包括半導體晶粒之多重瓦片式堆疊之半導體裝置總成 - Google Patents

包括半導體晶粒之多重瓦片式堆疊之半導體裝置總成 Download PDF

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TW201931549A
TW201931549A TW107133100A TW107133100A TW201931549A TW 201931549 A TW201931549 A TW 201931549A TW 107133100 A TW107133100 A TW 107133100A TW 107133100 A TW107133100 A TW 107133100A TW 201931549 A TW201931549 A TW 201931549A
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stack
semiconductor
tiled
substrate
semiconductor device
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TW107133100A
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TWI725338B (zh
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宏遠 黃
阿克斯海 Ｎ 辛
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美商美光科技公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • G—PHYSICS
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    • G11C—STATIC STORES
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    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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Abstract

本發明提供一種半導體裝置總成，其包括：一基板，其具有複數個外部連接件；半導體晶粒之一第一瓦片式堆疊，其係直接安置於該基板上之一第一位置上方且經電耦合至該複數個外部連接件之一第一子組；及半導體晶粒之一第二瓦片式堆疊，其係直接安置於該基板上之一第二位置上方且經電耦合至該複數個外部連接件之一第二子組。該半導體裝置總成進一步包括一囊封劑，該囊封劑至少部分地囊封該基板、該第一瓦片式堆疊，及該第二瓦片式堆疊。

Description

包括半導體晶粒之多重瓦片式堆疊之半導體裝置總成
本發明大體上係關於半導體裝置，且更特定言之係關於包括半導體晶粒之多重瓦片式堆疊之半導體裝置總成。
包括記憶體晶片、微處理器晶片及成像器晶片之封裝式半導體晶粒通常包括安裝於一基板上且裝入一塑料保護覆蓋物中或由一導熱蓋覆蓋之一或多個半導體晶粒。晶粒可包括主動電路(例如，提供功能特徵，諸如記憶體胞、處理器電路及/或成像器裝置)及/或被動電路(例如，電容器、電阻器等)以及電連接至電路之接合墊。接合墊可電連接至保護覆蓋物外之端子以允許晶粒連接至更高階電路。
為提供額外功能，可將額外半導體晶粒新增至一半導體裝置總成。包括額外半導體晶粒之一種方法涉及將晶粒堆疊於基板上方。為促進將晶粒電連接至基板，可呈一瓦片式堆疊配置晶粒，其中各晶粒自一下方晶粒水平偏移以留下(例如，使用一線接合)可接合至基板上之一對應接合指部之晶粒之暴露接觸墊。此瓦片式堆疊方法之一缺點係歸因於新增至堆疊之各額外晶粒之懸垂量增加，而使可依此方式堆疊之晶粒之數目受限。
為解決此限制，晶粒之瓦片式堆疊可包括呈一瓦片式方式配置且沿相同方向(例如，如圖1中所展示)或沿相反方向(如圖2中所展示)偏移之晶粒之多個群組。在此方面，圖1繪示一半導體裝置總成100，其中一基板101上之晶粒之一瓦片式堆疊110包括晶粒104之兩個群組102及103，其等沿相同偏移方向疊置且藉由線接合121電連接至基板101上之接合指部120。參考圖1可見，晶粒104之第一群組102之線接合121位於第二群組103之一懸垂區域111下方，且因此必須在晶粒104之第二群組103堆疊於第一群組102上方之前形成。此外，第二群組103之最底部晶粒104必須在第一群組102之最頂部晶粒104上方隔開達一足夠距離(例如，由一較厚層晶粒附接材料105提供)以允許另存一線接合121。據此，此配置之缺點包括必須反覆地執行多次堆疊及線接合操作，並且晶粒附接材料厚度不同，從而增加製造成本及複雜性。
形成圖2中所繪示之半導體裝置總成存在類似挑戰，其中晶粒群組沿相反偏移方向疊置。在此方面，圖2繪示一半導體裝置總成200，其中一基板201上之晶粒之一瓦片式堆疊210包括晶粒204之兩個群組202及203，其等沿相反偏移方向疊置且藉由線接合221電連接至基板201上之接合指部220。如參考圖2可見，晶粒204之第一群組202之至少一些線接合221位於第二群組203之一懸垂區域211下方，且因此必須在晶粒204之第二群組203堆疊於第一群組202上方之前形成。因此，此配置之缺點包括必須反覆地執行多次堆疊及線接合操作，並且在基板中提供額外接合指部，從而增加製造成本及複雜性。
本發明揭示一種半導體裝置總成，其包含：一基板，其包括複數個外部連接件；半導體晶粒之一第一瓦片式堆疊，其直接安置於該基板上之一第一位置上方且電耦合至該複數個外部連接件之一第一子組；半導體晶粒之一第二瓦片式堆疊，其直接安置於該基板上之一第二位置上方且電耦合至該複數個外部連接件之一第二子組；及一囊封劑，其至少部分地囊封該基板、該第一瓦片式堆疊及該第二瓦片式堆疊。
本發明亦揭示一種製造一記憶體裝置之方法，其包含：提供一基板；在該基板上將第一複數個半導體晶粒堆疊成一第一瓦片式堆疊；在該基板上將第二複數個半導體晶粒堆疊成一第二瓦片式堆疊；在堆疊該第一瓦片式堆疊及該第二瓦片式堆疊之後，將該第一複數個半導體晶粒及該第二複數個半導體晶粒線接合至該基板；及提供一囊封劑以至少部分地囊封該基板、該第一瓦片式堆疊及該第二瓦片式堆疊。
在下文描述中，論述眾多特定細節以提供對本發明之實施例之一透徹且可行之描述。然而，熟習相關技術者將認知，可在無一或多個特定細節之情況下實踐本發明。在其他情況下，未展示或未詳細描述通常與半導體裝置相關聯之熟知結構或操作，以避免模糊本發明之其他態樣。一般言之，應理解，除本文中所揭示之彼等特定實施例之外之各種其他裝置、系統及方法可在本發明之範疇內。
如上文所論述，增加一半導體裝置總成中之一瓦片式堆疊中之半導體晶粒的數目存在克服成本昂貴的製造挑戰(例如，多次反覆堆疊及線接合操作，改變晶粒至晶粒間距等)。據此，根據本發明之半導體裝置總成之若干實施例可提供具有半導體晶粒之多重瓦片式堆疊之半導體裝置總成以克服此等挑戰。
在此方面，本發明之若干實施例涉及半導體裝置總成，其等包括：一基板，其具有複數個外部連接件；半導體晶粒之一第一瓦片式堆疊，其係直接安置於該基板上之一第一位置上方且經電耦合至該複數個外部連接件之一第一子組；及半導體晶粒之一第二瓦片式堆疊，其係直接安置於該基板上之一第二位置上方且經電耦合至該複數個外部連接件之一第二子組。該等半導體裝置總成可進一步包括一囊封劑，該囊封劑至少部分地囊封該基板、該第一瓦片式堆疊及該第二瓦片式堆疊。
下文描述半導體裝置之若干實施例的特定細節。術語「半導體裝置」通常指代包括一半導體材料之一固態裝置。一半導體裝置可包括例如自一晶圓或基板單粒化之一半導體基板、晶圓或晶粒。貫穿本發明，半導體裝置通常係在半導體晶粒之背景下描述；然而，半導體裝置不限於半導體晶粒。
術語「半導體裝置封裝」可指代具有經併入至一共同封裝中之一或多個半導體裝置之一配置。一半導體封裝可包括一外殼或殼體，該外殼或殼體部分地或完全地囊封至少一個半導體裝置。一半導體裝置封裝亦可包括一中介層基板，該中介層基板承載一或多個半導體裝置且經附接至該殼體或以其他方式併入至該殼體中。術語「半導體裝置總成」可指代一或多個半導體裝置、半導體裝置封裝及/或基板(例如，中介層、支撐件或其他合適基板)之一總成。半導體裝置總成可(例如)係以離散封裝形式、條帶或矩陣形式及/或晶圓面板形式製造。如本文中所使用，術語「垂直」、「橫向」、「上」及「下」可指代半導體裝置或裝置總成中的特徵鑑於附圖中所展示之定向的相對方向或位置。例如，「上」或「最上」可分別指代比相同特徵之另一特徵或部分更靠近或最接近一頁面之頂部定位之一特徵。然而，此等術語應被廣義地解釋為包括具有其他定向(諸如倒置或傾斜定向)之半導體裝置，其中頂部/底部、上面/下面、上方/下方、上/下及左/右可取決於定向而互換。
圖3係根據本發明之一實施例之包括半導體晶粒之多重瓦片式堆疊之一半導體裝置總成之一簡化截面圖。半導體裝置總成300包括至少部分地由一囊封劑330環繞之一基板301、半導體晶粒304之一第一瓦片式堆疊302及半導體晶粒304之一第二瓦片式堆疊303 (以虛線繪示以指示其自截面圖平面之凹陷位置)。如參考圖3可見，第一瓦片式堆疊302及第二瓦片式堆疊303之各者包括四個半導體晶粒304。各堆疊302及303之最底部晶粒直接耦合至基板301，且各堆疊302及303中之各晶粒304 (除最底部晶粒之外)沿大致相同方向自緊鄰其下方之一晶粒304偏移達約相同距離(例如，不同於圖1及圖2中所繪示之瓦片式堆疊，其中一堆疊中之偏移距離可變化(如圖1中)，或其中一堆疊中之偏移方向可變化(如圖2中))。
半導體裝置總成300進一步包括將各堆疊302及303中之各晶粒304連接至基板301之線接合321。更特定言之，各堆疊302及303中之各晶粒304經連接至基板301上之一或多個接合指部320，一或多個接合指部320各繼而(例如，經由一通孔322)連接至總成300之對應一或多個外部觸點，諸如焊料球323。在此方面，因為任一堆疊302及303中無晶粒304位於另一晶粒304之一懸垂物下方(例如，不同於圖1及圖2)，所以可在單次操作中形成線接合321 (例如，不受另一堆疊操作干擾)，且各接合指部320可僅連接至單個線接合321 (例如，不同於圖1)。
根據本發明之一個態樣，一半導體裝置總成可在基板上之不同位置中具有半導體晶粒之多重瓦片式堆疊。此參考圖4更好地可見，圖4繪示根據本發明之一實施例之包括半導體晶粒之多重瓦片式堆疊之一半導體裝置總成之一簡化平面圖。半導體裝置總成400包括一基板401、半導體晶粒404之一第一瓦片式堆疊402及半導體晶粒404之一第二瓦片式堆疊403。第一瓦片式堆疊402經安置於基板401上之一第一位置中，且第二瓦片式堆疊403經安置於自第一位置橫向偏移之一第二位置中。如參考圖4可見，第一瓦片式堆疊402及第二瓦片式堆疊403之各者包括八個半導體晶粒404。各堆疊402及403之最底部晶粒直接耦合至基板401，且各堆疊402及403中之各晶粒404 (除最底部晶粒之外)沿大致相同方向自緊鄰其下方之一晶粒404偏移達約相同距離(例如，不同於圖1及圖2中所繪示之瓦片式堆疊，其中一堆疊中之偏移距離可變化(如圖1中)，或其中一堆疊中之偏移方向可變化(如圖2中))。
半導體裝置總成400進一步包括將各堆疊402及403中之各晶粒404連接至基板401之線接合421。更特定言之，各堆疊402及403中之各晶粒404藉由複數個線接合421連接至基板401上之對應複數個接合指部420。因為任一堆疊402及403中無晶粒404位於另一晶粒404之一懸垂物下方(例如，不同於圖1及圖2)，所以可在單次操作中形成線接合421 (例如，不受另一堆疊操作干擾)，且各接合指部420可僅連接至單個線接合421 (例如，不同於圖1)。
如上文所陳述，一半導體裝置總成中之半導體晶粒可包括提供各種不同功能之晶粒(例如，邏輯、記憶體、感測器等)。在其中瓦片式記憶體晶粒之堆疊包括於一半導體裝置總成中之一實施例中，包括記憶體晶粒之多重堆疊之一優點係可將記憶體晶粒之不同堆疊專用於不同記憶體通道(例如，在其中各堆疊對應於一個通道之1對1關係中，或在其中多重堆疊對應於各通道或甚至多個通道對應於各堆疊之n 對1或1對n 關係中)。
根據本發明之一個態樣，與單一較大堆疊相反，在一半導體裝置總成中包括半導體晶粒之雙重或更多重瓦片式堆疊之另一優點係在總成之佈局中提供額外靈活性，其可允許額外裝置硬體包括於總成中。例如，半導體裝置總成400包括I/O擴充器440，I/O擴充器440可方便地定位成相鄰於半導體晶粒404之各堆疊402及403之接合指部420，以在半導體裝置總成400係一封裝式記憶體裝置時促進額外連接性。
根據本發明之一個態樣，在一半導體裝置總成中提供晶粒之多重瓦片式堆疊之又一優點係可達成之封裝高度降低(例如，藉由使用較少晶粒之多重堆疊，而非晶粒之單一較高堆疊)。替代地，另一優點可包括使用較厚半導體晶粒(例如，其可比較薄晶粒更容易製造)，同時維持類似於使用具有較多數目個較薄晶粒之單一堆疊之一半導體裝置總成之一封裝高度。
根據本發明之一個態樣，與單一較大堆疊相反，在一半導體裝置總成中包括半導體晶粒之雙重或更多重瓦片式堆疊之一額外優點係總成所經歷之翹曲減少及總成之外部觸點上之物理應力對應地減小。在此方面，具有通常被安置於總成中間之晶粒之單一堆疊之一總成在通常位於堆疊之下方及周邊內之一區域中經歷物理應力升高(例如，歸因於翹曲及熱效應)，該區域對應於封裝基板之一大體上中心區域(例如，其中諸多總成焊料接點可專用於發信號及供電)。此會降低總成與更高階電路(例如，一模組板、封裝上封裝中介層或類似者)之間之焊料接點的可靠性。在其中晶粒之雙重或更多重堆疊係安置於總成基板上之不同位置中之一總成中，總成中間之物理應力傾向於較低，若可能，則在封裝之較周邊區域中發生應力升高(例如，其中封裝觸點可僅專用於機械堅固性，且其中成功地操作總成無需電連接)。
與具有單一堆疊之總成相比，本發明之又一優點涉及具有半導體晶粒之多重堆疊之一半導體裝置總成所經歷的熱改良。在此方面，歸因於由矽及底部填充層、膠帶附接或其他黏合劑之交替層引起的熱障，具有較少晶粒(例如，具有較少晶粒至晶粒介面)之一堆疊之熱阻抗低於具有較多晶粒之一堆疊，即使具有較厚晶粒之堆疊亦係如此。據此，與具有較多半導體晶粒之單一堆疊之一半導體裝置總成相比，使用改良式熱阻抗，具有半導體晶粒之多重堆疊之一半導體裝置總成可在一較大輸入功率下操作，同時在一可接受溫度範圍內執行。
儘管在前述實例中已結合半導體晶粒之雙重瓦片式堆疊來描述及繪示半導體裝置總成，但在其他實施例中可包括更多堆疊。例如，圖5係根據本發明之一實施例之包括半導體晶粒之四重瓦片式堆疊之一半導體裝置總成之一簡化平面圖。如參考圖5可見，半導體裝置總成500包括一基板501及半導體晶粒之四重瓦片式堆疊502至505，其中特徵類似於上文參考圖3及圖4更詳細論述之彼等特徵。瓦片式堆疊502至505之各者經安置於基板501上之一不同位置中(例如，在相鄰、非重疊位置中)。儘管在圖5中所繪示之實例中瓦片式堆疊502至505被展示為彼此間隔開，但在其他實施例中，半導體裝置總成可包括彼此緊鄰之瓦片式堆疊(例如，在基板上之不同非重疊位置中，但其等之間無空間)。
儘管在前述實例中已結合各具有不同偏移方向之半導體晶粒之瓦片式堆疊描述及繪示半導體裝置總成，但在其他實施例中晶粒之一些或所有瓦片式堆疊可共用一偏移方向。例如，圖6係根據本發明之一實施例之包括半導體晶粒之多重瓦片式堆疊之一半導體裝置總成之一簡化平面圖。如參考圖6可見，半導體裝置總成600包括一基板601及半導體晶粒之四重瓦片式堆疊602至605，其中特徵類似於上文參考圖3及圖4更詳細論述之彼等特徵。瓦片式堆疊602至605之各者經安置於基板601上之一不同位置中(例如，在相鄰、非重疊位置中)，且瓦片式堆疊皆共用一相同偏移方向。在圖7中所繪示之又一實施例中，一半導體裝置總成700包括一基板701及半導體晶粒之四重瓦片式堆疊702至705。一些堆疊共用一個偏移方向(例如，堆疊702及703)，且其他堆疊共用一相反偏移方向(例如，堆疊704及705)。
儘管在一些實施例中提供半導體晶粒之多重瓦片式堆疊可允許僅需要單個線接合步驟之一製造方法，但在其他實施例中一半導體裝置總成可包括其中晶粒偏移方向或晶粒偏移距離在單一堆疊內變化之半導體晶粒之多重瓦片式堆疊。例如，圖8繪示根據本發明之一實施例之包括半導體晶粒之多重瓦片式堆疊之一半導體裝置總成之一簡化截面圖。半導體裝置總成800包括一基板801及半導體晶粒之雙重堆疊802及803。堆疊802及803之各者包括瓦片式半導體晶粒之群組，其中晶粒群組之間的疊置偏移量具有一不連續性。儘管此等不連續性可能需要反覆堆疊及線接合步驟，但圖8中所繪示之半導體裝置總成800仍擁有歸於半導體裝置總成具有較少半導體晶粒之多重堆疊代替較多晶粒之單一堆疊之優點(例如，改進式剛性、熱效能、功率處置等)。類似地，圖9繪示根據本發明之一實施例之包括半導體晶粒之多重瓦片式堆疊之一半導體裝置總成之一簡化截面圖。半導體裝置總成900包括一基板901及半導體晶粒之雙重堆疊902及903。堆疊902及903之各者包括瓦片式半導體晶粒之群組，其中晶粒群組之間的疊置偏移量具有一不連續性。儘管此等不連續性可能需要反覆堆疊及線接合步驟，但圖9中所繪示之半導體裝置總成900仍擁有歸於半導體裝置總成具有較少半導體晶粒之多重堆疊代替較多晶粒之單一堆疊之優點(例如，改進式剛性、熱效能、功率處置等)。
圖10係繪示製造一半導體裝置總成之一方法之一流程圖。該方法包括：提供一基板(框1010)；在該基板上將第一複數個半導體晶粒堆疊成一第一瓦片式堆疊(框1020)；及在該基板上將第二複數個半導體晶粒堆疊成一第二瓦片式堆疊(框1030)。在此方面，該第一複數個半導體晶粒可直接堆疊於該基板上之一第一位置上，且該第二複數個半導體晶粒可直接堆疊於該基板上之一第二位置上。該方法進一步包括：將該第一複數個半導體晶粒及該第二複數個半導體晶粒線接合至該基板(框1040)，其可在堆疊該第一瓦片式堆疊及該第二瓦片式堆疊之後執行；及提供一囊封劑以至少部分地囊封該基板、該第一瓦片式堆疊及該第二瓦片式堆疊(框1050)。該線接合可在不受任何堆疊干擾之單次操作中執行。
該方法亦可進一步包括：將第三複數個半導體晶粒堆疊成一第三瓦片式堆疊；將第四複數個半導體晶粒堆疊成一第四瓦片式堆疊；及在堆疊該第三瓦片式堆疊及該第四瓦片式堆疊之後，將該第三複數個半導體晶粒及該第四複數個半導體晶粒線接合至該基板。在一項實施例中，將該第一複數個半導體晶粒及該第二複數個半導體晶粒線接合至該基板可在堆疊該第三瓦片式堆疊及該第四瓦片式堆疊之後執行。
儘管在前述實例中，半導體裝置總成已被繪示及描述為包括半導體晶粒之瓦片式堆疊，但在本發明之其他實施例中，半導體裝置總成可包括利用不同拓撲(例如，垂直堆疊、部分瓦片式堆疊等)及互連技術(例如，TSV、光學互連、電感互連等)之半導體晶粒之多重堆疊。
上文參考圖3至圖10所描述之半導體裝置總成之任一者可併入至無數更大及/或更複雜系統之任一者中，該等系統之一代表性實例係圖11中示意性地展示之系統1100。系統1100可包括一半導體裝置總成1102、一電源1104、一驅動器1106、一處理器1108及/或其他子系統或組件1110。半導體裝置總成1102可包括大體上類似於上文參考圖3至圖10所描述之半導體裝置之彼等特徵之特徵。所得系統1100可執行各種功能之任一者，諸如記憶體儲存、資料處理及/或其他合適功能。據此，代表性系統1100可包括但不限於手持型裝置(例如，行動電話、平板電腦、數位閱讀器及數位音訊播放器)、電腦、車輛、電器及其他產品。系統1100之組件可經容置於單個單元中或經分佈於多個互連單元上(例如，透過一通信網絡)。系統1100之組件亦可包括遠端裝置及各種電腦可讀媒體之任一者。
自前文將明白，本文中已出於闡釋目描述本發明之特定實施例，但可在不脫離本發明之範疇之情況下進行各種修改。據此，除隨附申請專利範圍之外，本發明不受限。
101‧‧‧基板
102‧‧‧第一群組
103‧‧‧第二群組
104‧‧‧晶粒
105‧‧‧晶粒附接材料
111‧‧‧懸垂區域
120‧‧‧接合指部
121‧‧‧線接合
200‧‧‧半導體裝置總成
201‧‧‧基板
202‧‧‧第一群組
203‧‧‧第二群組
204‧‧‧晶粒
205‧‧‧晶粒附接材料
211‧‧‧懸垂區域
220‧‧‧接合指部
221‧‧‧線接合
300‧‧‧半導體裝置總成
301‧‧‧基板
302‧‧‧第一瓦片式堆疊
303‧‧‧第二瓦片式堆疊
304‧‧‧半導體晶粒
320‧‧‧接合指部
321‧‧‧線接合
322‧‧‧通孔
323‧‧‧焊料球
330‧‧‧囊封劑
401‧‧‧基板
402‧‧‧第一瓦片式堆疊
403‧‧‧第二瓦片式堆疊
404‧‧‧半導體晶粒
420‧‧‧接合指部
421‧‧‧線接合
440‧‧‧I/O擴充器
500‧‧‧半導體裝置總成
501‧‧‧基板
502‧‧‧瓦片式堆疊
503‧‧‧瓦片式堆疊
504‧‧‧瓦片式堆疊
505‧‧‧瓦片式堆疊
600‧‧‧半導體裝置總成
601‧‧‧基板
602‧‧‧瓦片式堆疊
603‧‧‧瓦片式堆疊
604‧‧‧瓦片式堆疊
605‧‧‧瓦片式堆疊
700‧‧‧半導體裝置總成
701‧‧‧基板
702‧‧‧瓦片式堆疊
703‧‧‧瓦片式堆疊
704‧‧‧瓦片式堆疊
705‧‧‧瓦片式堆疊
800‧‧‧半導體裝置總成
801‧‧‧基板
802‧‧‧瓦片式堆疊
803‧‧‧瓦片式堆疊
900‧‧‧半導體裝置總成
901‧‧‧基板
902‧‧‧瓦片式堆疊
903‧‧‧瓦片式堆疊
1010‧‧‧步驟
1020‧‧‧步驟
1030‧‧‧步驟
1040‧‧‧步驟
1050‧‧‧步驟
1100‧‧‧系統
1102‧‧‧半導體裝置總成
1104‧‧‧電源
1106‧‧‧驅動器
1108‧‧‧處理器
1110‧‧‧其他子系統或組件
圖1繪示包括半導體晶粒之一瓦片式堆疊之一半導體裝置總成。
圖2繪示包括半導體晶粒之一瓦片式堆疊之一半導體裝置總成。
圖3繪示根據本發明之一實施例之包括半導體晶粒之多重瓦片式堆疊之一半導體裝置總成之一簡化截面圖。
圖4繪示根據本發明之一實施例之包括半導體晶粒之多重瓦片式堆疊之一半導體裝置總成之一簡化平面圖。
圖5繪示根據本發明之一實施例之包括半導體晶粒之多重瓦片式堆疊之一半導體裝置總成之一簡化平面圖。
圖6繪示根據本發明之一實施例之包括半導體晶粒之多重瓦片式堆疊之一半導體裝置總成之一簡化平面圖。
圖7繪示根據本發明之一實施例之包括半導體晶粒之多重瓦片式堆疊之一半導體裝置總成之一簡化平面圖。
圖8繪示根據本發明之一實施例之包括半導體晶粒之多重瓦片式堆疊之一半導體裝置總成之一簡化截面圖。
圖9繪示根據本發明之一實施例之包括半導體晶粒之多重瓦片式堆疊之一半導體裝置總成之一簡化截面圖。
圖10係繪示根據本發明之一項實施例之製造一半導體裝置總成之一方法之一流程圖。
圖11係展示包括根據本發明之一實施例組態之一半導體裝置總成之一系統之一示意圖。

Claims (20)

  1. 一種半導體裝置總成，其包含： 一基板，其包括複數個外部連接件； 半導體晶粒之一第一瓦片式堆疊，其係直接安置於該基板上之一第一位置上方且經電耦合至該複數個外部連接件之一第一子組； 半導體晶粒之一第二瓦片式堆疊，其係直接安置於該基板上之一第二位置上方且經電耦合至該複數個外部連接件之一第二子組；及 一囊封劑，其至少部分地囊封該基板、該第一瓦片式堆疊及該第二瓦片式堆疊。
  2. 如請求項1之半導體裝置總成，其中： 半導體晶粒之該第一瓦片式堆疊係藉由第一複數個線接合電連接至該複數個外部連接件之該第一子組，且 半導體晶粒之該第二瓦片式堆疊係藉由第二複數個線接合電連接至該複數個外部連接件之該第二子組。
  3. 如請求項1之半導體裝置總成，其中： 該基板包括對應於該第一瓦片式堆疊之第一複數個接合指部及對應於該第二瓦片式堆疊之第二複數個接合指部， 該第一複數個接合指部之各者係直接耦合至該第一複數個線接合之僅一者，且 該第二複數個接合指部之各者係直接耦合至該第二複數個線接合之僅一者。
  4. 如請求項1之半導體裝置總成，其中該第一瓦片式堆疊及該第二瓦片式堆疊包括相同數目個半導體晶粒。
  5. 如請求項4之半導體裝置總成，其中該等數目係兩個、四個、八個或十六個之一者。
  6. 如請求項1之半導體裝置總成，其中： 該第一瓦片式堆疊包括該第一瓦片式堆疊之一最低半導體晶粒及經堆疊於該第一瓦片式堆疊之該最低半導體晶粒上方之至少一個上半導體晶粒，且 該第一瓦片式堆疊之各上半導體晶粒沿一第一方向自一正下方半導體晶粒偏移達一第一偏移量。
  7. 如請求項6之半導體裝置總成，其中： 該第二瓦片式堆疊包括該第二瓦片式堆疊之一最低半導體晶粒及經堆疊於該第二瓦片式堆疊之該最低半導體晶粒上方之至少一個上半導體晶粒，且 該第二瓦片式堆疊之各上半導體晶粒沿一第二方向自一正下方半導體晶粒偏移達一第二偏移量。
  8. 如請求項7之半導體裝置總成，其中該第一偏移量係實質上等於該第二偏移量。
  9. 如請求項7之半導體裝置總成，其中該第一方向係實質上等同於該第二方向。
  10. 如請求項7之半導體裝置總成，其中該第一方向與該第二方向係實質上相反。
  11. 如請求項7之半導體裝置總成，其中該第一方向與該第二方向係實質上正交。
  12. 如請求項1之半導體裝置總成，進一步包含至少一個I/O擴充器，該至少一個I/O擴充器經電耦合至該複數個外部連接件之一第三子組。
  13. 如請求項1之半導體裝置總成，其中： 半導體晶粒之該第一瓦片式堆疊包含對應於一第一記憶體通道之記憶體晶粒，且 半導體晶粒之該第二瓦片式堆疊包含對應於一第二記憶體通道之記憶體晶粒。
  14. 如請求項1之半導體裝置總成，進一步包含： 半導體晶粒之一第三瓦片式堆疊，其係直接安置於該基板上之一第三位置上方且經電耦合至該複數個外部連接件之一第三子組；且 半導體晶粒之一第四瓦片式堆疊，其係直接安置於該基板上之一第四位置上方且經電耦合至該複數個外部連接件之一第四子組。
  15. 如請求項14之半導體裝置總成，其中： 半導體晶粒之該第三瓦片式堆疊包含對應於一第三記憶體通道之記憶體晶粒，且 半導體晶粒之該第四瓦片式堆疊包含對應於一第四記憶體通道之記憶體晶粒。
  16. 一種製造一記憶體裝置之方法，其包含： 提供一基板； 在該基板上，將第一複數個半導體晶粒堆疊成一第一瓦片式堆疊； 在該基板上，將第二複數個半導體晶粒堆疊成一第二瓦片式堆疊； 在堆疊該第一瓦片式堆疊及該第二瓦片式堆疊之後，將該第一複數個半導體晶粒及該第二複數個半導體晶粒線接合至該基板；及 提供一囊封劑，以至少部分地囊封該基板、該第一瓦片式堆疊及該第二瓦片式堆疊。
  17. 如請求項16之方法，其中該線接合係在不受任何堆疊干擾之單次操作中執行。
  18. 如請求項17之方法，其中： 該第一複數個半導體晶粒係直接堆疊於該基板上之一第一位置上方，且 該第二複數個半導體晶粒係直接堆疊於該基板上之一第二位置上方。
  19. 如請求項17之方法，進一步包含： 將第三複數個半導體晶粒堆疊成一第三瓦片式堆疊； 將第四複數個半導體晶粒堆疊成一第四瓦片式堆疊；且 在堆疊該第三瓦片式堆疊及該第四瓦片式堆疊之後，將該第三複數個半導體晶粒及該第四複數個半導體晶粒線接合至該基板。
  20. 如請求項19之方法，其中將該第一複數個半導體晶粒及該第二複數個半導體晶粒線接合至該基板係在堆疊該第三瓦片式堆疊及該第四瓦片式堆疊之後執行。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10312219B2 (en) * 2017-11-08 2019-06-04 Micron Technology, Inc. Semiconductor device assemblies including multiple shingled stacks of semiconductor dies
KR20210044508A (ko) * 2019-10-15 2021-04-23 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
US11309281B2 (en) * 2020-08-26 2022-04-19 Micron Technology, Inc. Overlapping die stacks for NAND package architecture
KR20220055112A (ko) 2020-10-26 2022-05-03 삼성전자주식회사 반도체 칩들을 갖는 반도체 패키지
KR20220067572A (ko) 2020-11-16 2022-05-25 삼성전자주식회사 메모리 패키지 및 이를 포함하는 저장 장치
US11942430B2 (en) * 2021-07-12 2024-03-26 Micron Technology, Inc. Stacked die modules for semiconductor device assemblies and methods of manufacturing stacked die modules
US11869626B2 (en) * 2021-10-15 2024-01-09 Micron Technology, Inc. Internal and external data transfer for stacked memory dies

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060041538A (ko) 2004-11-09 2006-05-12 삼성전자주식회사 단일 에지 패드를 갖는 반도체 칩을 포함하는 반도체 패키지
US20060267173A1 (en) * 2005-05-26 2006-11-30 Sandisk Corporation Integrated circuit package having stacked integrated circuits and method therefor
TW200814249A (en) 2006-09-12 2008-03-16 Chipmos Technologies Inc Stacked chip package structure with lead-frame having bus bar
US7687921B2 (en) * 2008-05-05 2010-03-30 Super Talent Electronics, Inc. High density memory device manufacturing using isolated step pads
KR20110138788A (ko) 2010-06-22 2011-12-28 하나 마이크론(주) 적층형 반도체 패키지
US8415808B2 (en) * 2010-07-28 2013-04-09 Sandisk Technologies Inc. Semiconductor device with die stack arrangement including staggered die and efficient wire bonding
KR101831692B1 (ko) * 2011-08-17 2018-02-26 삼성전자주식회사 기능적으로 비대칭인 전도성 구성 요소들을 갖는 반도체 소자, 패키지 기판, 반도체 패키지, 패키지 적층 구조물 및 전자 시스템
KR20130090173A (ko) * 2012-02-03 2013-08-13 삼성전자주식회사 반도체 패키지
US8796098B1 (en) * 2013-02-26 2014-08-05 Cypress Semiconductor Corporation Embedded SONOS based memory cells
KR20140109134A (ko) * 2013-03-05 2014-09-15 삼성전자주식회사 멀티-채널을 갖는 반도체 패키지 및 관련된 전자 장치
KR102001880B1 (ko) * 2013-06-11 2019-07-19 에스케이하이닉스 주식회사 적층 패키지 및 제조 방법
KR102247916B1 (ko) * 2014-01-16 2021-05-04 삼성전자주식회사 계단식 적층 구조를 갖는 반도체 패키지
US9418974B2 (en) 2014-04-29 2016-08-16 Micron Technology, Inc. Stacked semiconductor die assemblies with support members and associated systems and methods
KR102192848B1 (ko) 2014-05-26 2020-12-21 삼성전자주식회사 메모리 장치
KR102254104B1 (ko) * 2014-09-29 2021-05-20 삼성전자주식회사 반도체 패키지
US9478494B1 (en) * 2015-05-12 2016-10-25 Harris Corporation Digital data device interconnects
US10312219B2 (en) * 2017-11-08 2019-06-04 Micron Technology, Inc. Semiconductor device assemblies including multiple shingled stacks of semiconductor dies

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