TW201926554A - 形成半導體裝置的方法 - Google Patents

形成半導體裝置的方法 Download PDF

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Publication number
TW201926554A
TW201926554A TW107117930A TW107117930A TW201926554A TW 201926554 A TW201926554 A TW 201926554A TW 107117930 A TW107117930 A TW 107117930A TW 107117930 A TW107117930 A TW 107117930A TW 201926554 A TW201926554 A TW 201926554A
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Taiwan
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source
layer
drain structure
drain
gallium
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TW107117930A
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English (en)
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劭銘 許
李振銘
楊復凱
王美勻
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台灣積體電路製造股份有限公司
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Publication of TW201926554A publication Critical patent/TW201926554A/zh

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    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Abstract

提供半導體裝置與其形成方法。在一實施例中，方法包括提供結構，其包括：基板；第一閘極結構與第二閘極結構，位於基板上；第一源極/汲極結構，包括矽並與第一閘極結構相鄰；第二源極/汲極結構，包括矽鍺並與第二閘極結構相鄰；以及一或多個介電層，位於第一閘極結構與第二閘極結構的側壁上，並位於第一源極/汲極結構與第二源極/汲極結構上。方法更包含蝕刻介電層，形成開口以露出該第一源極/汲極結構與該第二源極/汲極結構；形成遮罩層於第一源極/汲極結構上；在遮罩層位於第一源極/汲極結構上時，佈植鎵至第二源極/汲極結構；移除遮罩層；以及以含氧原子的蝕刻劑蝕刻第一源極/汲極結構與第二源極/汲極結構。

Description

形成半導體裝置的方法
本發明實施例關於半導體裝置與其形成方法，更特別關於形成源極/汲極接點於半導體裝置(特別是鰭狀場效電晶體)中。
半導體積體電路產業已經歷指數成長。積體電路材料與設計的技術進展，使每一代的積體電路均比前一代具有更小且更複雜的電路。在積體電路的演進中，功能密度(單位晶片面積所具有的內連線裝置數目)通常隨著幾何尺寸(如最小構件或線路)減少而增加。尺寸縮小的製程通常有利於增加產能並降低相關成本。上述尺寸縮小亦增加積體電路之製程複雜度。為實現上述進展，積體電路製程亦需類似進展。
舉例來說，在形成源極/汲極接點以用於小尺寸電晶體如具有鰭狀通道的場效電晶體(一般稱作鰭狀場效電晶體)時，有時需使源極/汲極結構凹陷化以降低接點電阻。然而使源極/汲極結構凹陷化的製程有時會移除過多預應力的磊晶材料，造成應力損失並劣化裝置效能。
如此一來，需要改善源極/汲極接點的形成方法。
本發明一實施例提供之形成半導體裝置的方法，包括：提供結構，其包括：基板；第一閘極結構與第二閘極結 構，位於基板上；第一源極/汲極結構，包括矽並與第一閘極結構相鄰；第二源極/汲極結構，包括矽鍺並與第二閘極結構相鄰；以及一或多個介電層，位於第一閘極結構與第二閘極結構的側壁上，並位於第一源極/汲極結構與第二源極/汲極結構上；蝕刻介電層，形成多個開口以露出第一源極/汲極結構與第二源極/汲極結構；形成遮罩層於第一源極/汲極結構上；在遮罩層位於第一源極/汲極結構上時，佈植鎵至第二源極/汲極結構；移除遮罩層；以及以含氧原子的蝕刻劑蝕刻第一源極/汲極結構與第二源極/汲極結構。
d1、d2‧‧‧深度
12、14、15、16、17、18、19、19X、20、21、21X、22、23、23X、24、25、25X、26、27、28、30、32、34‧‧‧步驟
100‧‧‧半導體裝置
102‧‧‧基板
102A‧‧‧n型場效電晶體區
102B‧‧‧p型場效電晶體區
103‧‧‧鰭狀物
105‧‧‧隔離結構
104A、104A’、104B、104B’‧‧‧源極/汲極結構
106A、106B‧‧‧閘極堆疊
108‧‧‧閘極間隔物
110‧‧‧接點蝕刻停止層
112‧‧‧介電層
114‧‧‧蝕刻遮罩
116A、116B‧‧‧開口
118‧‧‧保護介電層
120‧‧‧遮罩層
124‧‧‧佈植層
126‧‧‧頂部
128A、128B‧‧‧矽化物結構
130‧‧‧源極/汲極接點
1100、1200、1300‧‧‧方法
第1A與1B圖係本發明實施例中，形成半導體裝置的方法其流程圖。
第2A與2B圖係本發明實施例中，形成半導體裝置的另一方法其流程圖。
第3A與3B圖係本發明實施例中，形成半導體裝置的又一方法其流程圖。
第4A、5A、6A、7A、13A、14A、15A、與16A圖係本發明實施例中，依據第1A、1B、2A、2B、3A、與3B圖的方法形成之半導體裝置的部份，於多種製作階段中沿著鰭狀物長度方向的剖視圖。
第4B、5B、6B、7B、13B、14B、15B、與16B圖係本發明實施例中，依據第1A、1B、2A、2B、3A、與3B圖的方法形成之半導體裝置的部份，於多種製作階段中沿著鰭狀物寬度方向 的剖視圖。
第8A、9A、10A、11A、與12A圖係本發明實施例中，依據第1A與1B圖的方法形成之半導體裝置的部份，於多種製作階段中沿著鰭狀物長度方向的剖視圖。
第8B、9B、10B、11B、與12B圖係本發明實施例中，依據第1A與1B圖的方法形成之半導體裝置的部份，於多種製作階段中沿著鰭狀物寬度方向的剖視圖。
第17A、18A、19A、20A、與21A圖係本發明實施例中，依據第2A與2B圖的方法形成之半導體裝置的部份，於多種製作階段中沿著鰭狀物長度方向的剖視圖。
第17B、18B、19B、20B、與21B圖係本發明實施例中，依據第2A與2B圖的方法形成之半導體裝置的部份，於多種製作階段中沿著鰭狀物寬度方向的剖視圖。
第22A、23A、24A、與25A圖係本發明實施例中，依據第3A與3B圖的方法形成之半導體裝置的部份，於多種製作階段中沿著鰭狀物長度方向的剖視圖。
第22B、23B、24B、與25B圖係本發明實施例中，依據第3A與3B圖的方法形成之半導體裝置的部份，於多種製作階段中沿著鰭狀物寬度方向的剖視圖。
下述揭露內容提供許多不同實施例或實例以實施本發明的不同結構。下述特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而 非直接接觸。此外，本發明的多個實例可採用重複標號及/或符號使說明簡化及明確，但這些重複不代表多種實施例中相同標號的元件之間具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
本發明實施例關於半導體裝置與其形成方法，更特別關於形成源極/汲極接點於半導體裝置(特別是鰭狀場效電晶體)中。本發明實施例的主題之一為形成源極/汲極接點時，減少應力磊晶結構的損失。本發明實施例的另一主題為n型場效電晶體的源極/汲極結構與p型場效電晶體的源極/汲極結構的隆起高度不同，以降低源極/汲極接點的接點電阻，並維持源極/汲極結構中的內置應力。更特別的是，本發明實施例以鎵佈植p型場效電晶體的源極/汲極結構，接著取含氧蝕刻劑氧化佈植的鎵以形成氧化鎵。氧化鎵的存在可在源極/汲極結構凹陷化的製程中減緩源極/汲極結構的蝕刻速率，進而避免在p型場效電晶體的源極/汲極結構中產生不想要的應力損失。
第1A與1B圖係形成半導體裝置100的方法1100其流程圖。方法1100將搭配第4A-16B圖說明，且上述圖式為半導體裝置100於製程的多種階段中的剖視圖。特別的是，第4A、5A、6A、7A、8A、9A、10A、11A、12A、13A、14A、15A、 與16A圖係半導體裝置100其部份沿著鰭狀物的長度方向的剖視圖，而第4B、5B、6B、7B、8B、9B、10B、11B、12B、13B、14B、15B、與16B圖係半導體裝置100其部份沿著鰭狀物的寬度方向的剖視圖。
第2A與2B圖形成半導體裝置100的方法1200其流程圖。方法1200將搭配第4A-7B、17A-21B、與13A-16B圖說明，且上述圖式為半導體裝置100於製程的多種階段中的剖視圖。特別的是，第4A、5A、6A、7A、17A、18A、19A、20A、21A、13A、14A、15A、與16A圖係半導體裝置100其部份沿著鰭狀物的長度方向的剖視圖，而第4B、5B、6B、7B、17B、18B、19B、20B、21B、13B、14B、15B、與16B圖係半導體裝置100其部份沿著鰭狀物的寬度方向的剖視圖。
第3A與3B圖係形成半導體裝置100的方法1300其流程圖。方法1300將搭配第4A-7B、22A-25B、與13A-16B圖說明，且上述圖式為半導體裝置100於製程的多種階段中的剖視圖。特別的是，第4A、5A、6A、7A、22A、23A、24A、25A、13A、14A、15A、與16A圖係半導體裝置100其部份沿著鰭狀物的長度方向的剖視圖，而第4B、5B、6B、7B、22B、23B、24B、25B、13B、14B、15B、與16B圖係半導體裝置100其部份沿著鰭狀物的寬度方向的剖視圖。
方法1100、1200、與1300僅用以舉例，而非侷限本發明至申請專利範圍未明確主張的範疇內。在方法1100、1200、與1300之前、之中、與之後可進行額外步驟，且方法的額外實施例可取代、省略、或調換一些下述步驟。
第1A與1B圖係方法1100的流程圖。半導體裝置100僅用以說明，不必限縮本發明實施例至任何裝置數目、任何區域數目、或結構或區域的任何設置。此外，第4A至25B圖所示的半導體裝置100可為製作積體電路時的中間裝置或其部份，其可包含靜態隨機存取記憶體及/或邏輯電路、被動構件(如電阻、電容、或電感)、主動構件(如p型場效電晶體、n型場效電晶體、多閘極場效電晶體如鰭狀場效電晶體、金氧半場效電晶體、互補式金氧半電晶體、雙極電晶體、高電壓電晶體、高頻電晶體、或其他記憶單元)、或上述之組合。
如第1A圖所示，方法1100的步驟12提供半導體裝置100的結構，如第4A與4B圖所示。如第4A與4B圖所示，半導體裝置100包含基板102與多種結構形成其中或其上。基板102含有兩個基板區如n型場效電晶體區102A與p型場效電晶體區102B。在此實施例中，n型場效電晶體區102A用於形成一或多個n型鰭狀場效電晶體裝置，而p型場效電晶體區102B用於形成一或多個p型鰭狀場效電晶體裝置。N型場效電晶體區102A與p型場效電晶體區102B各自包含一或多個半導體的鰭狀物103，且鰭狀物103之間隔有隔離結構105(見第4B圖)。特別的是，第4A圖為半導體裝置100沿著鰭狀物103的長度(x方向)的剖視圖，而第4B圖為半導體裝置100的源極/汲極區中沿著鰭狀物103的寬度(y方向)的剖視圖。在n型場效電晶體區102A中，半導體裝置100更包含鰭狀物103上的源極/汲極結構104A，以及與鰭狀物103的通道區相鄰並夾設於相鄰的源極/汲極結構104A之間的閘極堆疊106A。在p型場效電晶體區102B中，半導 體裝置100更包含鰭狀物103上的源極/汲極結構104B，以及與鰭狀物103的通道區相鄰並夾設於相鄰的源極/汲極結構104B之間的閘極堆疊106B。半導體裝置100更包含閘極堆疊106A與106B其側壁上的閘極間隔物108、閘極間隔物108與源極/汲極結構104A與104B上的接點蝕刻停止層110、與接點蝕刻停止層110上並填入相鄰的閘極間隔物108之間的介電層112。半導體裝置100的多種結構(或構件)將進一步說明於下。閘極堆疊如閘極堆疊106A與106B，有時可稱作閘極結構。
在此實施例中，基板102為矽基板。在其他實施例中，基板102包含其他半導體元素如鍺；半導體化合物如碳化矽、砷化鎵、砷化銦、或磷化銦；或半導體合金如碳化矽鍺、磷砷化鎵、或磷化鎵銦。在實施例中，基板102可包含絕緣層上矽基板、具有應力以增進效能、包含磊晶區或摻雜區、及/或包含其他合適結構或層狀物。
鰭狀物103可由任何合適的方法圖案化。舉例來說，鰭狀物103的圖案化方法可採用一或多道的光微影製程，比如雙重圖案化或多重圖案化製程。一般而言，雙重圖案化或多重圖案化製程結合光微影與自對準製程，其產生的圖案間距小於單一直接光微影製程形成的圖案間距。舉例來說，一實施例形成犧牲層於基板上，並採用光微影製程圖案化犧牲層。間隔物可沿著圖案化的犧牲層形成，且其形成方法可為自對準製程。接著移除犧牲層，而保留的間隔物或芯之後可作為圖案化鰭狀物103所用的遮罩元件。舉例來說，遮罩元件可用於蝕刻凹陷至基板102中，並保留鰭狀物103於基板102上的步驟。蝕 刻製程可包含乾蝕刻、濕蝕刻、反應性離子蝕刻、及/或其他合適製程。舉例來說，乾蝕刻製程可採用含氧氣體、含氟氣體(如四氟化碳、六氟化硫、二氟甲烷、氟仿、及/或六氟乙烷)、含氯氣體(如氯氣、氯仿、四氯化碳、及/或三氯化硼)、含溴氣體(如溴化氫及/或溴仿)、含碘氣體、其他合適氣體及/或電漿、及/或上述之組合。舉例來說，濕蝕刻製程可包含稀氫氟酸、氫氧化鉀溶液、氨、含氫氟酸、硝酸、及/或醋酸的溶液、或其他合適的濕蝕刻劑中的蝕刻。多種其他實施例的方法可適於形成鰭狀物。
源極/汲極結構104A與104B可包含磊晶半導體材料，以提供合適的應力並增進半導體裝置100的效能。舉例來說，源極/汲極結構104A可包含磊晶成長的矽或碳化矽，而源極/汲極結構104B可包含磊晶成長的矽鍺。此外，源極/汲極結構104A與104B可摻雜合適的摻質，以適用於個別的n型與p型裝置。舉例來說，源極/汲極結構104A可摻雜n型摻質如磷或砷，而源極/汲極結構104B可摻雜p型摻質如硼或銦。在一實施方式中，源極/汲極結構104A的組成為摻雜磷的磊晶成長矽，而源極/汲極結構104B的組成為摻雜硼的磊晶成長矽鍺。在一實施例中，源極/汲極結構104A與104B各自的形成方法為蝕刻鰭狀物103、磊晶成長合適的半導體材料於鰭狀物103上、並摻雜(原位或異位)合適的摻質至磊晶成長的材料中。在一些實施例中，相鄰的源極/汲極結構104A可彼此分隔(未圖示)或合併(比如第4B圖中合併的兩個源極/汲極結構104A)。同樣地，一些實施例中相鄰的源頰/汲極結構104B可彼此分隔(如第4B圖 所示)或合併(未圖示)。此外，每一源極/汲極結構104A與104B可具有多晶面的形狀。
隔離結構105可包含氧化矽、氮化矽、氮氧化矽、摻雜氟的矽酸鹽玻璃、低介電常數的介電材料、及/或其他合適的絕緣材料。在一實施例中，隔離結構105的形成方法為蝕刻溝槽於基板102中(比如形成鰭狀物103的製程其一部份)、將絕緣材料填入溝槽、以及對包含絕緣材料的基板102進行化學機械研磨製程。隔離結構亦可採用其他合適種類，比如場氧化物或局部氧化矽。
每一閘極堆疊106A與106B為多層結構。舉例來說，每一閘極堆疊106A與106B可包含介電界面層、介電界面層上的閘極介電層、以及閘極介電層上的閘極層。在一實施例中，閘極堆疊106A與106B為之後置換為高介電常數介電層與金屬閘極的虛置閘極，即後續製程將置換閘極堆疊106A與106B中的一或多層。在另一實施例中，閘極堆疊106A與106B包含高介電常數的閘極介電層、高介電常數的閘極介電層上的功函數層、以及功函數層上的金屬層。在多種實施例中，介電界面層可包含介電材料如氧化矽或氮氧化矽，且其形成方法可為化學氧化、熱氧化、原子層沉積、化學氣相沉積、及/或其他合適的方法。閘極介電層可包含氧化矽。高介電常數的閘極介電層可包含氧化鉿、氧化鋯、氧化鑭、氧化鈦、氧化釔、鈦酸鍶、其他合適的金屬氧化物、或上述之組合，且其形成方法可為原子層沉積及/或其他合適方法。閘極層可包含多晶矽或金屬如鋁、鎢、鈷、銅、及/或其他合適材料。功函數層可為 用於閘極堆疊106B的p型或用於閘極堆疊106A的n型。p型功函數層包含的金屬具有夠大的有效功函數，其擇自但不限於氮化鈦、氮化鉭、釕、鉬、鎢、鉑、或上述之組合。n型功函數層包含的金屬具有夠小的有效功函數，其擇自但不限於鈦、鋁、碳化鉭、氮碳化鉭、氮化鉭矽、或上述之組合。p型或n型功函數層可包含多層，且其沉積方法可為化學氣相沉積、物理氣相沉積、及/或其他合適製程。
閘極間隔物108可為單層或多層結構。在一些實施例中，閘極間隔物108包含介電材料如氧化矽、氮化矽、氮氧化矽、其他介電材料、或上述之組合。在一例中，閘極間隔物108的形成方法為沉積第一介電層的毯狀層(如具有一致厚度的氧化矽層)，以作為具有閘極堆疊106A與106B的半導體裝置100上的襯墊層。上述方法亦沉積第二介電層(如氮化矽層)於第一介電層上以作為主要D形的間隔物。上述方法接著進行非等向蝕刻移除介電層的部份，以形成閘極間隔物108。
接點蝕刻停止層110可包含氮化矽、氮氧化矽、具有氧元素或碳元素的氮化矽、及/或其他材料。在一例中，接點蝕刻停止層110包含氮化矽，其固有應力大於或等於1GPa。固有應力可為壓縮應力以用於p型通道裝置，或拉伸應力以用於n型通道裝置。接點蝕刻停止層110的形成方法可為電漿增強化學氣相沉積製程及/或其他合適的沉積或氧化製程。接點蝕刻停止層110覆蓋源極/汲極結構104A與104B的外側表面、閘極間隔物108的側壁、以及隔離結構105的上表面。
介電層(或層間介電層)112可包含的材料為四乙氧 基矽烷氧化物、未摻雜的矽酸鹽玻璃、或摻雜的氧化矽如硼磷矽酸鹽玻璃、熔融二氧化矽玻璃、磷矽酸鹽玻璃、摻雜硼的矽玻璃、及/或其他合適的介電材料。介電層112的沉積方法可為電漿增強化學氣相沉積製程、可流動的化學氣相沉積製程、或其他合適的沉積技術。在一實施例中，接點蝕刻停止層110沉積如毯並位於基板102上以覆蓋其上的多種結構，且介電層112沉積於接點蝕刻停止層110上以填入閘極堆疊106A與106B之間的溝槽。
方法1100的步驟14(見第1A圖)蝕刻介電層112與接點蝕刻停止層110並露出源極/汲極結構104A與104B，以準備形成源極/汲極接點於個別的源極/汲極結構上。此步驟關於多種製程如沉積、光微影、與蝕刻。如第5A與5B圖所示，蝕刻遮罩114形成於半導體裝置100上，並形成開口116A與116B以露出半導體裝置100的多種部份。開口116A與116B對應半導體裝置100中，即將形成源極/汲極接點以用於源極/汲極結構104A與104B的區域。在多種實施例中，蝕刻遮罩114可包含硬遮罩層(如氮化矽或氧化矽)、光阻層、或上述之組合。如第6A與6B圖所示，經由開口116A與116B蝕刻半導體裝置100，以移除介電層112的露出部份，且蝕刻製程可採用乾蝕刻製程、濕蝕刻製程、或反應性離子蝕刻製程。在此實施例中，蝕刻製程對介電層112的材料具有選擇性，而不會(或不明顯地)蝕刻閘極堆疊106A與106B、閘極間隔物108、以及接點蝕刻停止層110。參考第7A與7B圖。經由開口116A與116B蝕刻半導體裝置100，以移除開口116A與116B其底部之接點蝕刻停止層110的部份，且 蝕刻製程可採用乾蝕刻製程、濕蝕刻製程、或反應性離子蝕刻製程。特別的是，此蝕刻製程為非等向。如此一來，在完成蝕刻製程後，可保留接點蝕刻停止層110於閘極堆疊106A與106B的側壁上。此外，此蝕刻製程對接點蝕刻停止層110具有選擇性，且不會(或不明顯地)蝕刻閘極堆疊106A與106B以及閘極間隔物108。雖然此實施例採用兩個分開的蝕刻製程蝕刻介電層112與接點蝕刻停止層110，但多種實施例可改用一共同的蝕刻製程或超過兩個蝕刻製程。
如第8A與8B圖所示，方法1100的步驟16(見第1A圖)形成遮罩層120於n型場效電晶體區102A中的源極/汲極結構104A上，而p型場效電晶體區102B中的源極/汲極結構104B仍經由開口116B露出。在多種實施例中，遮罩層120與蝕刻遮罩114類似，可包含硬遮罩層(如氮化矽或氧化矽)、光阻層、或上述之組合。如第8A與8B圖所示的一些實施例，遮罩層120的上表面與蝕刻遮罩114的上表面齊平。在其他實施例中(未圖示)，遮罩層120可覆蓋蝕刻遮罩114的部份。在下述的步驟18中，遮罩層120的目的在於避免鎵離子佈植至與源極/汲極結構104A。只要符合上述目的，遮罩層120可為任何合適厚度或設置，且其組成可為任何合適的遮罩材料。
如第9A與9B圖所示，方法1100的步驟18(見第1A圖)佈植鎵離子(或鎵離子與硼離子)至p型場效電晶體區102B中露出的源極/汲極結構104B，而遮罩層120遮罩n型場效電晶體區102A中的源極/汲極結構104A。在一些實施例中，步驟18中鎵離子佈植的佈植能量介於1keV至10keV之間。在一些實施方 式中，步驟18的鎵離子佈植中的鎵離子劑量介於1E15cm-2至1E17cm-2之間。在佈植鎵離子與硼離子的步驟18中，可同時或分開佈植硼離子與鎵離子。舉例來說，可先進行硼離子佈植，其佈植能量可介於1keV至5keV之間，且其硼離子劑量可介於1E15cm-2至1E16cm-2之間。在硼離子佈植之後，接著進行鎵離子佈植。在一些例子中，鎵離子佈植的摻雜能量可介於1keV至10keV之間，且其鎵離子劑量可介於1E15cm-2至1E17cm-2之間。在一些實施方式中，硼離子佈植與鎵離子佈植的順序可顛倒，即先進行鎵離子佈植。在一些其他實施例中，可同時進行鎵離子佈植與硼離子佈植。舉例來說，步驟18佈植源極/汲極結構104B的硼離子摻雜能量可介於1keV至10keV之間，硼離子劑量介於1E15cm-2至1E16cm-2之間，而鎵離子劑量介於1E15cm-2至1E17cm-2之間。如第10A與10B圖所示，步驟18形成佈植層124於源極/汲極結構104B的頂部中，而未形成於遮罩層120遮罩的源極/汲極結構104A的頂部中。
方法1100的步驟20(見第1A圖)移除源極/汲極結構104A上的遮罩層120，如第10A與10B圖所示。步驟20可由蝕刻完成。蝕刻步驟可包含乾蝕刻、濕蝕刻、反應性離子蝕刻、及/或其他合適製程。
方法1100的步驟22(見第1A圖)，退火具有鎵摻質(或具有鎵與硼摻質)的源極/汲極結構104B，以活化佈植層124中的鎵原子(或鎵與硼原子)。步驟22可擇自多種退火製程。舉例來說，步驟22可採用一或多道退火製程，比如微波退火製程、微秒退火製程、快速熱退火製程、動態尖峰退火製程、熔 融雷射退火製程、及/或其他合適的退火製程。然而步驟22的溫度預算需考慮閘極堆疊106A與106B的材料，即不應損傷閘極堆疊。步驟22可移除源極/汲極結構104B中因鎵/硼離子佈植所產生的空洞、非晶層、與結晶缺陷。
在一些實施例中，在完成步驟14之後，閘極堆疊106A與106B的側壁上的接點蝕刻停止層110的部份(可稱作接點蝕刻停止層110的側壁)可能變的過薄。舉例來說，蝕刻介電層112與接點蝕刻停止層110的蝕刻製程，可能會部份地消耗接點蝕刻停止層110，且接點蝕刻停止層110一開始可能就具有薄的輪廓。接點蝕刻停止層110的側壁過薄，可能造成閘極堆疊106A與106B以及源極/汲極結構104A與104B中的材料最後互相混合，造成裝置缺陷(如短路)。接點蝕刻停止層110的側壁過薄亦可能在電壓偏置時崩潰，最後導致個別源極/汲極結構與閘極堆疊短路。在此實施例中，保護介電層118形成於接點蝕刻停止層110的側壁上，以增加閘極堆疊106A與106B上的介電層厚度。
方法1100的步驟24(見第1A圖)進行沉積製程與蝕刻製程，以形成保護介電層118於開口116A與116B中的接點蝕刻停止層其側壁上。如第11A與11B圖所示，方法1100沉積保護介電層118於半導體裝置100上，特別是開口116A與116B的側壁以及源極/汲極結構104A與104B的頂部上。在一實施例中，保護介電層118包含氮化矽。在其他實施例中，保護介電層118可包含氮氧化矽、氮碳化矽、或其他合適材料。保護介電層118的沉積方法可採用化學氣相沉積、物理氣相沉積、或 原子層沉積。如第12A與12B圖所示，方法1100的步驟24非等向蝕刻保護介電層118，保留保護介電層118的部份於開口116A與116B之側壁上，特別是保留於接點蝕刻停止層110的側壁上以作為保護層(有時可稱作保護側壁)。保護介電層118有利於增加閘極堆疊106A與106B之側壁上的介電層厚度。在一實施例中，蝕刻製程為乾蝕刻。在方法1100的一些實施例中，接點蝕刻停止層110的側壁具有足夠厚度，因此可省略步驟24。在步驟24的蝕刻製程之後，經由開口116A與116B露出源極/汲極結構104A與104B(或其部份)以及佈植層124，如第12A與12B圖所示。
在一些實施例中，在前述的多種蝕刻製程(如蝕刻接點蝕刻停止層110與視情況蝕刻介電層118)中，可蝕刻源極/汲極結構104A與104B。舉例來說，在蝕刻接點蝕刻停止層110以露出源極/汲極結構104A與104B時，可進行一些過蝕刻以確保不有介電物殘留在個別的源極/汲極結構上。另一方面，源極/汲極接點電阻可能過高，或電路開路缺陷可能連續產生。然而這些過蝕刻可能不經意地蝕刻源極/汲極結構104A與104B。在一些實施例中，可刻意蝕刻源極/汲極結構104A與104B以增加用於源極/汲極接點的界面面積。不論是不經意的過蝕刻或刻意蝕刻，均可能改變源極/汲極結構並影響裝置效能。在特定例子中，源極/汲極結構104B包含矽鍺以施加應力至p型場效電晶體，而蝕刻源極/汲極結構104B通常會鬆馳應力(不想要的結果)。為強化或增加源極/汲極結構104B中的應力，此實施例的方法1100摻雜鎵離子至源極/汲極結構104B中。
方法1100的步驟26(見第1B圖)對源極/汲極結構104A與104B進行選擇性蝕刻製程。在一些實施例中，步驟26關於乾蝕刻製程，其採用六氟化硫與氧的製程氣體混合物作為乾蝕刻劑。在一些其他實施例中，步驟26的蝕刻製程為濕蝕刻製程，其採用水相的氫氧化鉀溶液作為濕蝕刻劑。在這些實施例中，六氟化硫與氧的氣體混合物以及氫氧化鉀溶液含有一些氧，其可統稱為含氧蝕刻劑或含氧原子蝕刻劑。如第13A與13B圖所示的一些實施例，步驟26所用的含氧蝕刻劑與佈植層124中的鎵原子反應，以形成氧化鎵於佈植層124的頂部126中，而佈植層124的底部實質上不含氧化鎵。一旦佈植層124的頂部126與含氧蝕刻劑產生化學反應並轉變成含氧化鎵的層狀物，即可作為蝕刻保護層以減緩含氧蝕刻劑對佈植層124的蝕刻。氧化鎵可減緩蝕刻，進而避免佈植層124下的源極/汲極結構104B中應力磊晶材料的損失。氧化鎵可減緩蝕刻，並避免佈植層124下的源極/汲極結構104B中的應力磊晶材料損失。在一些實施例中，應力磊晶材料可為摻雜會未摻雜的矽鍺。相反地，由於沒有鎵離子佈植至源極/汲極結構104A中，含氧蝕刻劑蝕刻至源極/汲極結構104A中的蝕刻速率不會減緩。如此一來，這些實施例中在進行步驟26之後，蝕刻製程使源極/汲極結構104A凹陷化的程度大於使源極/汲極結構104B凹陷化的程度。在一些實施方式中，步驟24中非等向蝕刻保護介電層118與步驟26的選擇性蝕刻，可依序採用非氧化蝕刻劑於步驟24中，並採用含氧或含氧原子的蝕刻劑於步驟26中。在一些其他實施例中，步驟26的選擇性蝕刻與步驟24中非等向蝕刻保護介電層 118，可一起採用相同的蝕刻化學劑。
更特別的是，如第13A與13B圖所示，源極/汲極結構104A被蝕刻(或被部份地移除)一段垂直距離(或深度d1)，源極/汲極結構104B被蝕刻(或被部份地移除)一段深度d2，且深度d1大於深度d2。如第13A圖所示的一實施例，d1可為被蝕刻的源極/汲極結構104A之上表面最低點，至相鄰的閘極間隔物108之下表面之間的距離。另一方面，d1可為被蝕刻的源極/汲極結構104A之上表面最低點，至相鄰的未蝕刻之源極/汲極結構104A’之上表面的對應點之間的距離。上述的上表面最低點與上表面的對應點在相同的y軸上，但在不同的x軸上，如第13B圖所示。第13B圖顯示蝕刻後的源極/汲極結構104A的y-z剖面與未蝕刻的源極/汲極結構104A’的另一y-z剖面重疊(或位於未蝕刻的源極/汲極結構104A’的另一y-z剖面之前)。沿著z方向的兩個點之間的垂直距離，即蝕刻至源極/汲極結構104A中的深度。深度d2的量測方法與上述類似。特別的是，第13B圖顯示蝕刻後的源極/汲極結構104B的y-z剖面與未蝕刻的源極/汲極結構104B’的另一y-z剖面重疊(或位於未蝕刻的源極/汲極結構104B’的另一y-z剖面之前)。沿著z方向的兩個點之間的垂直距離，即蝕刻至源極/汲極結構104B中的深度。在多種實施例中，深度d1比深度d2大至少5nm。在n型場效電晶體區102A中，源極/汲極結構104A中的較大蝕刻深度，通常可增加用於源極/汲極接點的界面面積，因此降低源極/汲極接點電阻。在p型場效電晶體區102B中，源極/汲極結構104B中的較小蝕刻深度，有助於維持源極/汲極結構104B中內置的應力。此外，步驟26的 蝕刻製程可調整為不蝕刻閘極堆疊106A與106B、閘極間隔物108、接點蝕刻停止層110、與介電層118。此處所述的垂直距離，指的是沿著一方向的距離，且方向垂直於基板102的表面。
如第14A與14B圖所示，方法1100的步驟28(見第1B圖)清潔源極/汲極結構104A與104B的表面，以準備進行後續的矽化製程。在一些實施例中，步驟28移除佈植層124的頂部126中的氧化鎵。步驟28亦可稱作預清潔步驟。步驟28可採用乾式清潔製程或濕式清潔製程。舉例來說，乾式清潔製程可採用SiConi蝕刻，其為遠端電漿輔助的乾蝕刻製程，可同時暴露至氫、三氟化氮、與氨電漿的副產物。舉例來說，濕式清潔製程可採用稀氫氟酸溶液，以清潔源極/汲極結構104A與104B的表面。
如第15A與15B圖所示，方法1100的步驟30(見第1B圖)分別形成矽化物結構(或矽化物層)128A與128B於源極/汲極結構104A與104B上，以降低源極/汲極接點電阻。在例示性的實施例中，方法1100的步驟30沉積金屬層於源極/汲極結構104A與104B上，進行退火製程使金屬層與下方的半導體材料反應形成金屬矽化物，並移除多餘的未反應金屬。保留的金屬矽化物即矽化物結構128A與128B，如第15A與15B圖所示。舉例來說，金屬層的厚度可小於或等於約10nm，比如小於或等於5nm。在一些實施例中，相同金屬層可用於矽化n型場效電晶體區102A中的源極/汲極結構104A以及p型場效電晶體區102B中的源極/汲極結構104B。另一方面，用於矽化源極/汲極結構104A的金屬層可不同於矽化源極/汲極結構104B的金屬層。在 多種實施例中，金屬層可包含鈦、鎳、鈷、鉭、鉺、釔、鐿、鉑、或上述之組合。此外，由於源極/汲極結構104A與104B具有不同組成，形成的矽化物結構128A與128B亦具有不同組成。
方法1100的步驟32(見第1B圖)沉積材料於開口116A與116B中，以形成源極/汲極接點130於矽化物結構128A與128B上。如第16A圖所示，源極/汲極接點130分別填入開口116A與116B，並經由矽化物結構128A與128B覆蓋源極/汲極結構104A與104B其上表面與側表面。在實施例中，源極/汲極接點130可包含鎢、鈷、銅、其他金屬元素、金屬氮化物(如氮化鈦、氮化鈦鋁、氮化鎢、氮化鉭)、或上述之組合，且其形成方法可為化學氣相沉積、物理氣相沉積、電鍍、及/或其他合適製程。在一實施例中，在沉積金屬以用於源極/汲極接點130之前，先移除蝕刻遮罩114。此外，可進行化學機械研磨以平坦化半導體裝置100的上表面，以得第16A圖所示的結構。
如第16A圖所示，n型場效電晶體區102A中的源極/汲極接點130其下表面，低於p型場效電晶體區102B中的源極/汲極接點130其下表面。由於氧化鎵存在於源極/汲極結構104B中，造成步驟26的蝕刻製程差異。在p型場效電晶體區102B中，源極/汲極接點130位於含有p型的源極/汲極結構104B、含鎵的佈植層124、與矽化物結構128B的多層結構上。此外，源極/汲極接點130的側壁夾設於接點蝕刻停止層110、閘極間隔物108、與n型場效電晶體區102A中的閘極堆疊106A與p型場效電晶體區102B中的閘極堆疊106B之間。
方法1100的步驟34(見第1B圖)可進行後續步驟以 完成製作半導體裝置100。舉例來說，步驟34可包含形成電性連接閘極堆疊106A與106B的閘極接點，並形成連接鰭狀場效電晶體與半導體裝置100的其他部份的金屬內連線，以形成完整的積體電路。
第2A與2B圖係方法1200的流程圖。方法1200亦採用方法1100的步驟12與14。方法1200自步驟14持續進行至步驟15，接著進行步驟19、21、23、25、與27。在步驟27之後，方法1200繼續進行步驟26、28、30、32、與34。步驟15、19、21、23、25、與27將搭配第17A-21B圖說明如下。
如第17A與17B圖所示，方法1200的步驟15(見第2A圖)沉積保護介電層118於半導體裝置100上，特別是沉積於開口116A與116B的側壁與源極/汲極結構104A與104B的頂部上。在一實施例中，保護介電層118包含氮化矽。在其他實施例中，保護介電層118可包含氮氧化矽、氮碳化矽、或其他合適材料。保護介電層118的沉積方法可採用化學氣相沉積、物理氣相沉積、或原子層沉積。
方法1200的步驟19(見第2A圖)形成遮罩層120於n型電晶體區102A中的源極/汲極結構104A上的開口116A上，而p型電晶體區102B中的源極/汲極結構104B仍經由開口116B露出。在多種實施例中，遮罩層120與蝕刻遮罩114類似，可包含硬遮罩層(如氮化矽或氧化矽)、光阻層、或上述之組合。如第18A圖所示的一些實施例，遮罩層120其上表面與蝕刻遮罩114上的保護介電層118其上表面齊平。在其他實施例中(未圖示)，遮罩層120可覆蓋蝕刻遮罩114上的保護介電層118其部份。遮 罩層120的目的在於避免鎵離子佈植至源極/汲極結構104A。只要符合上述目的，遮罩層120可為任何合適厚度或設置，且其組成可為任何合適的遮罩材料。
如第19A與19B圖所示，方法1200的步驟21(見第2A圖)佈植鎵離子(或鎵離子與硼離子)至p型場效電晶體區102B的開口116B中露出的保護介電層118與源極/汲極結構104B，此時遮罩層120遮罩n型場效電晶體區102A的開口116A中的保護介電層118與源極/汲極結構104A。在一些實施例中，步驟21中鎵離子佈植的佈植能量介於1keV至10keV之間。在一些實施方式中，步驟21的鎵離子佈植中的鎵離子劑量介於1E15cm-2至1E17cm-2之間。在佈植鎵離子與硼離子的步驟21中，可同時或分開佈植硼離子與鎵離子。舉例來說，可先進行硼離子佈植，其佈植能量可介於1keV至5keV之間，且其硼離子劑量可介於1E15cm-2至1E16cm-2之間。在硼離子佈植之後，接著進行鎵離子佈植。在一些例子中，鎵離子佈植的摻雜能量可介於1keV至10keV之間，且其鎵離子劑量可介於1E15cm-2至1E17cm-2之間。在一些實施方式中，硼離子佈植與鎵離子佈植的順序可顛倒，即先進行鎵離子佈植。在一些其他實施例中，可同時進行鎵離子佈植與硼離子佈植。舉例來說，步驟21佈植開口116B中的源極/汲極結構104B與保護介電層118，其硼離子摻雜能量可介於1keV至10keV之間，硼離子劑量介於1E15cm-2至1E16cm-2之間，而鎵離子劑量介於1E15cm-2至1E17cm-2之間。如第20A與20B圖所示，步驟21形成佈植層124於源極/汲極結構104B的頂部以及其上的保護介電層118的頂部中，而未形成於 遮罩層120遮罩的源極/汲極結構104A的頂部中。佈植層124包含鎵。在一些例子中，步驟21後的含鎵佈植層124，自源極/汲極結構124上的保護介電層118延伸至源極/汲極結構104B的頂部。
方法1200的步驟23(見第2A圖)移除開口116A上的遮罩層120，如第20A與20B圖所示。步驟23可由蝕刻完成。蝕刻製程可包含乾蝕刻、濕蝕刻、反應性離子蝕刻、及/或其他合適製程。 方法1200的步驟25(見第2A圖)對開口116B中佈植鎵摻質(或鎵與硼摻質)的源極/汲極結構104B與保護介電層118進行退火，以活化佈植層124中的鎵原子(或鎵與硼原子)。步驟25可擇自多種退火製程，其包含但不限於微波退火製程、微秒退火製程、快速熱退火製程、動態尖峰退火製程、熔融雷射退火製程、及/或其他合適的退火製程。步驟25亦可移除源極/汲極結構104B與其上的保護電層118中因鎵/硼離子佈植所產生的空洞、非晶層、與結晶缺陷。
如第21A與21B圖所示，方法1200的步驟27(見第2A圖)非等向的蝕刻保護介電層118，保留保護介電層118的部份於開口116的側壁上，特別是接點蝕刻停止層110的側壁。在一些實施例中，在步驟27的蝕刻製程之後，可經由開口116A與116B露出源極/汲極結構104A與104B(或其部份)以及佈植層124，如第21A與21B圖所示。在一些實施例中，步驟27與後續的步驟26可依序採用非氧化蝕刻劑於步驟27中，並採用含氧或含氧原子的蝕刻劑於步驟26中。在一些其他實施例中，步驟27 與後續的步驟26可連續地採用含氧蝕刻劑或含氧原子蝕刻劑，比如六氟化硫與氧的製程氣體混合物，或水相氫氧化鉀溶液。
方法1200(見第2B圖)繼續進行步驟26、28、30、32、與34，在此不重述以簡化說明。
第3A與3B圖係方法1300的流程圖。方法1300亦採用方法1100與1200的步驟12與14。方法1300自步驟14持續進行至步驟17，接著進行步驟19X、21X、23X、與25X。在步驟25X之後，方法1300繼續進行步驟26、28、30、32、與34。步驟17、19X、21X、23X、與25X將搭配第22A-25B圖說明如下。
如第22A與22B圖所示，方法1300的步驟17(見第3A圖)沉積保護介電層118於半導體裝置100上，特別是沉積於開口116A與116B的側壁以及源極/汲極結構104A與104B的頂部上。在一實施例中，保護介電層118包含氮化矽。在其他實施例中，保護介電層118可包含氮氧化矽、氮碳化矽、或其他合適材料。保護介電層118的沉積方法可採用化學氣相沉積、物理氣相沉積、或原子層沉積。非等向蝕刻保護介電層118，以保留保護介電層118的部份於開口116的側壁上，特別是接點蝕刻停止層110的側壁上。在一些實施例中，在步驟17的蝕刻製程之後，可經由開口116A與116B露出源極/汲極結構104A與104B(或其部份)以及佈植層124，如第22A與22B圖所示。
如第23A與23B圖所示，方法1300之步驟19X(見第3A圖)形成遮罩層120於n型電晶體區102A中的源極/汲極結構104A上的開口116A上，而p型電晶體區102B中的源極/汲極結 構104B仍經由開口116B露出。在多種實施例中，遮罩層120與蝕刻遮罩114類似，可包含硬遮罩層(如氮化矽或氧化矽)、光阻層、或上述之組合。如第23A圖所示的一些實施例，遮罩層120的上表面與蝕刻遮罩114的上表面齊平。在其他實施例中(未圖示)，遮罩層120可覆蓋蝕刻遮罩114的部份。遮罩層120的目的在於避免鎵離子佈植至保護介電層118(覆蓋源極/汲極結構104A)與源極/汲極結構104A。只要符合上述目的，遮罩層120可為任何合適厚度或設置，且其組成可為任何合適的遮罩材料。
如第24A與24B圖所示，方法1300的步驟21X(見第3A圖)佈植鎵離子(或鎵離子與硼離子)至p型場效電晶體區102B的開口116B中露出的源極/汲極結構104B，此時遮罩層120遮罩n型場效電晶體區102A的開口116A中的源極/汲極結構104A。此步驟的佈植劑量與佈植能量等級與前述之步驟18類似。在佈植鎵離子與硼離子的實施例中，可在佈植硼離子之前、之中、或之後佈植鎵離子。如第25A與25B圖所示，步驟21X形成佈植層124於源極/汲極結構104B其頂部中，而不形成於遮罩層120遮罩的源極/汲極結構104A其頂部中。
方法1300的步驟23X(見第3A圖)移除開口116A上的遮罩層120，如第25A與25B圖所示。步驟23X可由蝕刻完成。蝕刻製程可包含乾蝕刻、濕蝕刻、反應性離子蝕刻、及/或其他合適製程。
方法1300的步驟25X(見第3A圖)對含有鎵摻質(或鎵與硼摻質)的源極/汲極結構104B進行退火，以活化佈植層 124中的鎵原子(或鎵與硼原子)。步驟25X可擇自多種退火製程，其包含但不限於微波退火製程、微秒退火製程、快速熱退火製程、動態尖峰退火製程、熔融雷射退火製程、及/或其他合適的退火製程。步驟25X亦可移除源極/汲極結構104B與其上的保護電層118中因鎵/硼離子佈植所產生的空洞、非晶層、與結晶缺陷。
方法1300(見第3B圖)繼續進行步驟26、28、30、32、與34，在此不重述以簡化說明。
本發明一或多個實施例提供許多優點至半導體裝置與其形成製程，但不限於此。舉例來說，佈植至p型場效電晶體區的源極/汲極結構中的鎵離子不只可作為p型摻質，還可被含氧的蝕刻劑氧化形成氧化鎵以作為蝕刻減緩層。含氧化鎵的蝕刻減緩層避免過度移除應力源極/汲極結構(如矽鍺磊晶結構)，其可避免源極/汲極結構中的應力釋放(不想要的結果)。上述主題可輕易整合至現有的積體電路製程，且可應用至許多不同製程節點。
在本發明一例示性的實施例中，形成半導體裝置的方法包括：提供結構，其包括：基板；第一閘極結構與第二閘極結構，位於基板上；第一源極/汲極結構，包括矽並與第一閘極結構相鄰；第二源極/汲極結構，包括矽鍺並與第二閘極結構相鄰；以及一或多個介電層，位於第一閘極結構與第二閘極結構的側壁上，並位於第一源極/汲極結構與第二源極/汲極結構上。方法更包含蝕刻介電層，形成開口以露出該第一源極/汲極結構與該第二源極/汲極結構；形成遮罩層於第一源極/ 汲極結構上；在遮罩層位於第一源極/汲極結構上時，佈植鎵至第二源極/汲極結構；移除遮罩層；以及以含氧原子的蝕刻劑蝕刻第一源極/汲極結構與第二源極/汲極結構。
在一些實施例中，上述方法更包括在遮罩層位於第一源極/汲極結構上時，摻雜硼至第二源極/汲極結構。在一些實施例中，上述方法更包括在形成遮罩層於第一源極/汲極結構上之前，形成保護介電層於第一源極/汲極結構與第二源極/汲極結構上。在一些實施方式中，上述方法更包括退火第二源極/汲極結構以活化鎵。在一些例子中，上述方法在退火該第二源極/汲極結構以活化鎵之後，更包括形成保護介電層於露出第一源極/汲極結構與第二源極/汲極結構的開口其側壁上。在一些實施例中，含氧原子的蝕刻劑為六氟化硫與氧的氣體混合物。在一些例子中，含氧原子的蝕刻劑為氫氧化鉀溶液。在一些實施例中，佈植鎵的步驟產生含鎵的佈植層於第二源極/汲極結構上。在一些實施方式中，以含氧原子的蝕刻劑蝕刻第一源極/汲極結構與第二源極/汲極結構之步驟，將含鎵的佈植層頂部轉變為含氧化鎵層，並保留含鎵的佈植層底部於第二源極/汲極結構上。在一些實施例中，上述方法更包括移除含氧化鎵層。在一些其他實施例中，上述方法在移除含氧化鎵層之後，更包括沉積金屬層於第一源極/汲極結構與第二源極/汲極結構上。在一些例子中，佈植鎵的步驟採用的摻雜能量介於1keV至10keV之間，且摻雜劑量介於1E15cm-2至1E17cm-2之間。
在本發明另一例示性的實施例中，形成半導體裝 置的方法包括：提供結構，其包含基板；第一閘極結構與第二閘極結構，位於基板上；第一源極/汲極結構，包含n型摻雜的矽並與第一閘極結構相鄰；第二源極/汲極結構，包含矽鍺並與第二閘極結構相鄰；以及一或多個介電層，位於第一閘極結構與第二閘極結構的側壁上，並位於第一源極/汲極結構與第二源極/汲極結構上。上述方法更包含蝕刻介電層以露出第一源極/汲極結構與第二源極/汲極結構；形成遮罩層於第一源極/汲極結構上；在遮罩層位於第一源極/汲極結構上時，佈植鎵至第二源極/汲極結構，以形成含鎵佈植層於第二源極/汲極結構上；移除遮罩層；以含氧原子的蝕刻劑蝕刻第一源極/汲極結構與第二源極/汲極結構，使含鎵佈植層的頂部轉變為含氧化鎵層，並保留含鎵佈植層的底部於第二源極/汲極結構上；移除含氧化鎵層；沉積金屬層於第一源極/汲極結構上，與第二源極/汲極結構上的含鎵佈植層的底部上；以及退火第一源極/汲極結構與第二源極/汲極結構。
在一些實施例中，上述方法更包括在遮罩層位於第一源極/汲極結構上時，摻雜硼至第二源極/汲極結構。在一些實施例中，上述方法包括退火第二源極/汲極結構以活化鎵。在一些實施方式中，含氧原子的蝕刻劑包括六氟化硫與氧的氣體混合物，或氫氧化鉀溶液。在一些實施方式中，佈植鎵至第二源極/汲極結構之步驟採用的摻雜能量介於1keV至10keV之間，且摻雜劑量介於1E15cm-2至1E17cm-2之間。
在本發明又一例示性的實施例中，半導體裝置包括n型鰭狀場效電晶體區，其包含第一閘極堆疊；第一閘極間 隔物，位於第一閘極堆疊的側壁上；n型磊晶結構，位於n型鰭狀場效電晶體區的源極/汲極區中；以及第一金屬矽化物層，位於n型磊晶結構上。上述半導體裝置亦包括p型鰭狀場效電晶體區，其包含第二閘極堆疊；第二閘極間隔物，位於第二閘極堆疊的側壁上；矽鍺磊晶結構，位於p型鰭狀場效電晶體區的源極/汲極區中，其中矽鍺磊晶區的頂部包含鎵；以及第二金屬矽化物層，位於矽鍺磊晶結構的頂部上。
在一些實施例中，矽鍺磊晶結構更包含硼。在一些實施例中，第一閘極間隔物的下表面與n型磊晶結構的上表面之最低點之間的第一垂直距離，大於第二閘極間隔物的下表面與矽鍺磊晶結構的上表面之最低點之間的第二垂直距離。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明精神與範疇，並可在未脫離本發明之申請專利範圍的精神與範疇的前提下進行改變、替換、或更動。

Claims (1)

  1. 一種形成半導體裝置的方法，包括：提供一結構，其包括：一基板；一第一閘極結構與一第二閘極結構，位於該基板上；一第一源極/汲極結構，包括矽並與該第一閘極結構相鄰；一第二源極/汲極結構，包括矽鍺並與該第二閘極結構相鄰；一或多個介電層，位於該第一閘極結構與該第二閘極結構的側壁上，並位於該第一源極/汲極結構與該第二源極/汲極結構上；蝕刻該或該些介電層，形成多個開口以露出該第一源極/汲極結構與該第二源極/汲極結構；形成一遮罩層於該第一源極/汲極結構上；在該遮罩層位於該第一源極/汲極結構上時，佈植鎵至該第二源極/汲極結構；移除該遮罩層；以及以一含氧原子的蝕刻劑蝕刻該第一源極/汲極結構與該第二源極/汲極結構。
TW107117930A 2017-11-21 2018-05-25 形成半導體裝置的方法 TW201926554A (zh)

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