TW201918140A - Multi-layered printed circuit board - Google Patents

Multi-layered printed circuit board Download PDF

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Publication number
TW201918140A
TW201918140A TW107114061A TW107114061A TW201918140A TW 201918140 A TW201918140 A TW 201918140A TW 107114061 A TW107114061 A TW 107114061A TW 107114061 A TW107114061 A TW 107114061A TW 201918140 A TW201918140 A TW 201918140A
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layer
conductive pattern
metal
laminate
pattern layer
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TW107114061A
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Chinese (zh)
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TWI788346B (en
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朴庸鎭
姜明杉
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南韓商三星電機股份有限公司
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

A multi-layered printed circuit board is disclosed. The multi-layered printed circuit board in accordance with one aspect of the present invention includes: lower substrate including first conductive pattern layer; interposer substrate including second conductive pattern layer and disposed on the lower substrate; bonding insulating layer interposed between the lower substrate and the interposer substrate so as to bond the lower substrate with the interposer substrate; and metal bonding part penetrating the bonding insulating layer so as to interconnect the first conductive pattern layer and the second conductive pattern layer. The metal bonding part includes seed metal layer, which is formed on the second conductive pattern layer, metal pillar, and low-melting-point metal layer, which has a melting point lower than a melting point of the metal pillar.

Description

多層印刷電路板Multilayer printed circuit board

本發明是有關於一種多層印刷電路板。This invention relates to a multilayer printed circuit board.

隨著各種電子裝置變得日益多功能化且越來越小,該些電子裝置中的每一者的尺寸變得越來越小,但輸入/輸出(input/output,I/O)的數目正在增加。因此,電子裝置的輸入/輸出的線寬度及電子裝置的各輸入/輸出之間的距離(即,節距)已逐漸變得越來越小。As various electronic devices become more and more multifunctional and smaller, the size of each of these electronic devices becomes smaller and smaller, but the number of input/output (I/O) Is increasing. Therefore, the line width of the input/output of the electronic device and the distance (i.e., pitch) between the respective inputs/outputs of the electronic device have gradually become smaller and smaller.

因此,安裝有電子裝置的封裝板亦需要減小各導電圖案之間的距離以及各導電圖案之間的節距及線寬度。此外,需要使訊號通路最小化以減少雜訊且加快訊號轉移。Therefore, the package board on which the electronic device is mounted also needs to reduce the distance between the respective conductive patterns and the pitch and line width between the respective conductive patterns. In addition, the signal path needs to be minimized to reduce noise and speed up signal transfer.

為了滿足封裝板的該些需要,已開發出一種新技術來在用於封裝的傳統印刷電路板與主動裝置之間設置矽系中介層。在替代技術中,在用於封裝的印刷電路板上達成足以對應中介層的精密導電圖案層。In order to meet these needs of package boards, a new technology has been developed to provide a lanthanide interposer between a conventional printed circuit board for packaging and an active device. In an alternative technique, a precision conductive pattern layer sufficient to correspond to the interposer is achieved on a printed circuit board for packaging.

相關技術闡述於韓國專利公開案第10-2011-0066044號(2011年6月16日)中。The related art is described in Korean Patent Publication No. 10-2011-0066044 (June 16, 2011).

本發明的實施例可提供一種具有提高的製造良率的多層印刷電路板。Embodiments of the present invention can provide a multilayer printed circuit board with improved manufacturing yield.

本發明的另一實施例可提供一種具有提高的平坦度的多層印刷電路板。Another embodiment of the present invention can provide a multilayer printed circuit board having improved flatness.

提供以下詳細說明是為了幫助讀者獲得對本文所述的方法、設備及/或系統的全面理解。然而,本文所述的方法、設備及/或系統的各種變化、修改及等效形式將對此項技術中具有通常知識者顯而易見。本文所述的操作的順序僅為實例,且並非受限於本文所述的順序,而是除了必需按某一次序發生的操作以外,可如將對此項技術中具有通常知識者顯而易見般進行改變。此外,為增加清晰性及簡明性,對此項技術中具有通常知識者眾所習知的功能及構造的說明可被省略。The following detailed description is provided to assist the reader in a comprehensive understanding of the methods, devices and/or systems described herein. Various changes, modifications, and equivalents of the methods, devices, and/or systems described herein will be apparent to those of ordinary skill in the art. The order of the operations described herein is merely an example, and is not limited to the order described herein, but may be performed as would be apparent to one of ordinary skill in the art, except where operations must occur in a certain order. change. Moreover, in order to increase clarity and conciseness, descriptions of functions and configurations well known to those of ordinary skill in the art may be omitted.

本文所述的特徵可被實施為諸多不同的形式,而不應被視為僅限於本文所述的實例。更確切而言,提供本文所述的實例是為了使本揭露透徹及完整,且將向此項技術中具有通常知識者傳達本揭露的全部範圍。The features described herein can be implemented in many different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein are provided to be thorough and complete, and the full scope of the disclosure will be conveyed to those of ordinary skill in the art.

除非另外定義,否則本文所使用的包括技術用語及科學用語的所有用語具有與本揭露所屬技術中具有通常知識者對所述用語所通常理解的含義相同的含義。在常用字典中定義的任何用語應被理解為在相關技術的上下文中具有相同的含義,且除非另外明確地定義,否則不應將其解釋為具有理想或過於正式的含義。Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Any term defined in a commonly used dictionary should be understood to have the same meaning in the context of the related art, and should not be interpreted as having an ideal or too formal meaning unless explicitly defined otherwise.

無論圖編號如何,相同或對應的元件將給出相同的參考編號,且將不再重複對相同或對應的元件進行任何冗餘說明。本揭露的說明通篇中,當闡述某一相關傳統技術被確定為避開本揭露的要點時,將省略有關的詳細說明。在闡述各種元件時可使用例如「第一」及「第二」等用語,但以上元件不應侷限於以上用語。以上用語僅用於區分各個元件。在附圖中,一些元件可被誇大、省略或簡要說明,且元件的尺寸未必反映該些元件的實際尺寸。Regardless of the figure number, the same or corresponding elements will be given the same reference numerals, and any redundant description of the same or corresponding elements will not be repeated. Throughout the description of the disclosure, the detailed description will be omitted when it is stated that a related conventional technique is determined to avoid the gist of the disclosure. Terms such as "first" and "second" may be used in the description of various elements, but the above elements should not be limited to the above terms. The above terms are only used to distinguish between components. In the figures, some of the elements may be exaggerated, omitted or briefly described, and the dimensions of the elements do not necessarily reflect the actual dimensions of the elements.

以下,將參照附圖詳細闡述本揭露的某些實施例。多層印刷電路板 (一個實施例)Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Multilayer printed circuit board (one embodiment)

圖1示出根據本發明實施例的多層印刷電路板。Figure 1 shows a multilayer printed circuit board in accordance with an embodiment of the present invention.

參照圖1,根據本發明實施例的多層印刷電路板1000包括下部基板100、中介基板200、接合絕緣層300及金屬接合部400。Referring to FIG. 1, a multilayer printed circuit board 1000 according to an embodiment of the present invention includes a lower substrate 100, an interposer substrate 200, a bonding insulating layer 300, and a metal bonding portion 400.

以下,為便於闡述,將下部基板稱為第一積層板100,且將中介基板稱為第二積層板200。Hereinafter, for convenience of explanation, the lower substrate is referred to as a first laminate 100, and the intermediate substrate is referred to as a second laminate 200.

第一積層板100及第二積層板200可分別包括:至少二或更多個導電圖案層11、21;絕緣層110、210,夾置於相鄰的導電圖案層之間;以及通孔V1、V2,形成於絕緣層中以對相鄰的導電圖案層進行電性內連。The first laminate 100 and the second laminate 200 may respectively include: at least two or more conductive pattern layers 11, 21; insulating layers 110, 210 sandwiched between adjacent conductive pattern layers; and through holes V1 And V2 are formed in the insulating layer to electrically interconnect the adjacent conductive pattern layers.

亦即,第一積層板100形成有多個第一通孔V1,所述多個第一通孔V1用於對多個第一絕緣層110、多個第一導電圖案層11及相鄰的第一導電圖案層進行內連。此外,第二積層板200形成有多個第二通孔V2,所述多個第二通孔V2用於對多個第二絕緣層210、多個第二導電圖案層21及相鄰的第二導電圖案層進行內連。That is, the first laminate 100 is formed with a plurality of first vias V1 for the plurality of first insulating layers 110, the plurality of first conductive pattern layers 11 and adjacent ones. The first conductive pattern layer is interconnected. In addition, the second laminate 200 is formed with a plurality of second vias V2 for pairing the plurality of second insulating layers 210, the plurality of second conductive pattern layers 21, and adjacent ones The two conductive pattern layers are interconnected.

第一絕緣層110及第二絕緣層210分別夾置於彼此相鄰的導電圖案層之間,以使相鄰的導電圖案層彼此電性絕緣。亦即,第一絕緣層110夾置於彼此相鄰的第一導電圖案層11之間,以使相鄰的第一導電圖案層11彼此電性絕緣。相似地,第二絕緣層210夾置於彼此相鄰的第二導電圖案層21之間,以使相鄰的第二導電圖案層21彼此電性絕緣。The first insulating layer 110 and the second insulating layer 210 are respectively sandwiched between the conductive pattern layers adjacent to each other to electrically insulate adjacent conductive pattern layers from each other. That is, the first insulating layer 110 is sandwiched between the first conductive pattern layers 11 adjacent to each other to electrically insulate the adjacent first conductive pattern layers 11 from each other. Similarly, the second insulating layer 210 is sandwiched between the second conductive pattern layers 21 adjacent to each other to electrically insulate the adjacent second conductive pattern layers 21 from each other.

第一絕緣層110及第二絕緣層210可分別包含例如環氧樹脂等電性絕緣樹脂。第二絕緣層210可為含有感光性絕緣樹脂的感光性絕緣層。The first insulating layer 110 and the second insulating layer 210 may respectively contain an electrically insulating resin such as an epoxy resin. The second insulating layer 210 may be a photosensitive insulating layer containing a photosensitive insulating resin.

第一絕緣層110及第二絕緣層210可分別包含電性絕緣樹脂中所含有的加強材。加強材可為玻璃布、玻璃纖維、無機填料及有機填料中的任一種。加強材可增強第一絕緣層110及第二絕緣層210的剛性且降低第一絕緣層110及第二絕緣層210的熱膨脹係數。Each of the first insulating layer 110 and the second insulating layer 210 may include a reinforcing material contained in the electrically insulating resin. The reinforcing material may be any one of glass cloth, glass fiber, inorganic filler, and organic filler. The reinforcing material can enhance the rigidity of the first insulating layer 110 and the second insulating layer 210 and reduce the thermal expansion coefficients of the first insulating layer 110 and the second insulating layer 210.

第二絕緣層210可薄於第一絕緣層110。亦即,由於第二絕緣層210構成作為第二積層板200的中介基板,因此第二絕緣層210可薄於與傳統印刷電路板對應的第一積層板100的第一絕緣層110。The second insulating layer 210 may be thinner than the first insulating layer 110. That is, since the second insulating layer 210 constitutes an interposer as the second laminate 200, the second insulating layer 210 can be thinner than the first insulating layer 110 of the first laminate 100 corresponding to the conventional printed circuit board.

所使用的無機填料可為選自由以下組成的群組中的至少一者:二氧化矽(SiO2 )、氧化鋁(Al2 O3 )、碳化矽(SiC)、硫酸鋇(BaSO4 )、滑石、黏土、雲母粉、氫氧化鋁(AlOH3 )、氫氧化鎂(Mg(OH)2 )、碳酸鈣(CaCO3 )、碳酸鎂(MgCO3 )、氧化鎂(MgO)、氮化硼(BN)、硼酸鋁(AlBO3 )、鈦酸鋇(BaTiO3 )及鋯酸鈣(CaZrO3 )。The inorganic filler used may be at least one selected from the group consisting of cerium oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), cerium carbide (SiC), barium sulfate (BaSO 4 ), Talc, clay, mica powder, aluminum hydroxide (AlOH 3 ), magnesium hydroxide (Mg(OH) 2 ), calcium carbonate (CaCO 3 ), magnesium carbonate (MgCO 3 ), magnesium oxide (MgO), boron nitride ( BN), aluminum borate (AlBO 3 ), barium titanate (BaTiO 3 ) and calcium zirconate (CaZrO 3 ).

第一導電圖案層11及第二導電圖案層21可分別包括通孔接墊、訊號圖案、電源圖案、接地圖案及外部連接端子中的至少一者。The first conductive pattern layer 11 and the second conductive pattern layer 21 may respectively include at least one of a via pad, a signal pattern, a power supply pattern, a ground pattern, and an external connection terminal.

所述多個第一導電圖案層11可採用相同的圖案來形成或可採用不同的圖案來形成。相似地,所述多個第二導電圖案層21可採用相同的圖案來形成或可採用不同的圖案來形成。The plurality of first conductive pattern layers 11 may be formed using the same pattern or may be formed using different patterns. Similarly, the plurality of second conductive pattern layers 21 may be formed using the same pattern or may be formed using different patterns.

形成於中介基板上的第二積層板200(即,第二導電圖案層21)所具有的各圖案之間的節距、各圖案之間的距離及圖案的寬度相對小於第一導電圖案層11的各圖案之間的節距、各圖案之間的距離及圖案的寬度。換言之,第二導電圖案層21被形成為較第一導電圖案層11精密。The pitch between the respective patterns of the second laminate 200 (ie, the second conductive pattern layer 21) formed on the interposer substrate, the distance between the patterns, and the width of the pattern are relatively smaller than the first conductive pattern layer 11 The pitch between the patterns, the distance between the patterns, and the width of the pattern. In other words, the second conductive pattern layer 21 is formed to be more precise than the first conductive pattern layer 11.

設置於所述多個第二導電圖案層21的最外層上的第二導電圖案層21嵌置於第二積層板200中以經由第二積層板200的一個表面而被暴露出。具體而言,參照圖1,形成於第二積層板200的最下部處的第二導電圖案層21嵌置於第二積層板200中,且第二導電圖案層21的下表面經由第二積層板200的下表面被暴露出。The second conductive pattern layer 21 disposed on the outermost layer of the plurality of second conductive pattern layers 21 is embedded in the second laminate 200 to be exposed through one surface of the second laminate 200. Specifically, referring to FIG. 1, the second conductive pattern layer 21 formed at the lowermost portion of the second build-up board 200 is embedded in the second build-up board 200, and the lower surface of the second conductive pattern layer 21 is passed through the second build-up layer. The lower surface of the board 200 is exposed.

設置於所述多個第二導電圖案層21的最外層上的第二導電圖案層21的一個表面中形成有溝槽R,以使得第二導電圖案層21的一個區突出超過第二導電圖案層21的另一區。具體而言,參照圖1,設置於第二積層板200的最外層上的第二導電圖案層的下表面中形成有溝槽R。因此,第二導電圖案層21的下表面的一個區突出超過第二導電圖案層21的下表面的另一區。A trench R is formed in one surface of the second conductive pattern layer 21 disposed on the outermost layer of the plurality of second conductive pattern layers 21 such that one region of the second conductive pattern layer 21 protrudes beyond the second conductive pattern Another area of layer 21. Specifically, referring to FIG. 1, a groove R is formed in a lower surface of a second conductive pattern layer provided on the outermost layer of the second laminate 200. Therefore, one region of the lower surface of the second conductive pattern layer 21 protrudes beyond another region of the lower surface of the second conductive pattern layer 21.

第一導電圖案層11、第二導電圖案層21、第一通孔V1及第二通孔V2可分別由具有優異的電性性質的銅(Cu)、銀(Ag)、鈀(Pd)、鋁(Al)、鎳(Ni)、鈦(Ti)、金(Au)或鉑(Pt)製成。The first conductive pattern layer 11, the second conductive pattern layer 21, the first via hole V1, and the second via hole V2 may be respectively made of copper (Cu), silver (Ag), palladium (Pd), or the like having excellent electrical properties. Made of aluminum (Al), nickel (Ni), titanium (Ti), gold (Au) or platinum (Pt).

形成第一積層板100的所述多個第一絕緣層100中的任一者可為利用其中玻璃布浸入於絕緣樹脂中的預浸體形成的核心絕緣層,且所述多個第一絕緣層100中的其餘者可分別為利用例如味之素增層膜(Ajinomoto Build-up Film,ABF)等增層膜形成的增層絕緣層。換言之,第一積層板100可被結構化為其中不同的第一絕緣層增層於第一絕緣層的任一表面上的核心基板。Any one of the plurality of first insulating layers 100 forming the first laminate 100 may be a core insulating layer formed using a prepreg in which a glass cloth is immersed in an insulating resin, and the plurality of first insulating layers The remaining one of the layers 100 may be a build-up insulating layer formed using a build-up film such as Ajinomoto Build-up Film (ABF). In other words, the first laminate 100 may be structured as a core substrate in which different first insulating layers are layered on either surface of the first insulating layer.

第二積層板200設置於第一積層板100上。第二積層板200可不包括核心絕緣層。舉例而言,第二積層板200可被結構化為其中連續積層感光性絕緣層的無核心基板。The second laminate 200 is disposed on the first laminate 100. The second laminate 200 may not include a core insulating layer. For example, the second laminate 200 may be structured as a coreless substrate in which a photosensitive insulating layer is continuously laminated.

可在第二積層板200上設置例如積體電路晶片或記憶體晶片等電子裝置(圖中未示出)。第二積層板200可解決第一積層板100的輸入/輸出的節距(及/或數目)與電子裝置的輸入/輸出的節距(及/或數目)之間的失配。在其中多個電子裝置設置於第二積層板200上的情形中,第二積層板200將所述多個電子裝置電性內連。An electronic device (not shown) such as an integrated circuit wafer or a memory chip can be disposed on the second laminate 200. The second laminate 200 can solve the mismatch between the pitch (and/or number) of the input/output of the first laminate 100 and the pitch (and/or number) of the input/output of the electronic device. In the case where a plurality of electronic devices are disposed on the second laminate 200, the second laminate 200 electrically interconnects the plurality of electronic devices.

接合絕緣層300將分離地且個別地形成的第一積層板100與第二積層板200彼此接合。亦即,接合絕緣層300設置於第一積層板100的一個表面與第二積層板200的一個表面之間以將第一基層板100與第二積層板200彼此接合。具體而言,接合絕緣層300將形成第一積層板100的最外層的第一絕緣層110與形成第二積層板200的最外層的第二絕緣層210接合。The bonding insulating layer 300 bonds the first laminate 100 and the second laminate 200 which are separately and individually formed to each other. That is, the bonding insulating layer 300 is disposed between one surface of the first laminate 100 and one surface of the second laminate 200 to bond the first substrate 100 and the second laminate 200 to each other. Specifically, the bonding insulating layer 300 bonds the first insulating layer 110 forming the outermost layer of the first laminated board 100 with the second insulating layer 210 forming the outermost layer of the second laminated board 200.

接合絕緣層300可利用阻焊膜或感光性絕緣膜來形成。如隨後將闡述,接合絕緣層300藉由在第一積層板100與第二積層板200接合時被完全硬化(C階段)來將第一積層板100與第二積層板200接合。The bonding insulating layer 300 can be formed using a solder resist film or a photosensitive insulating film. As will be explained later, the bonding insulating layer 300 bonds the first laminate 100 and the second laminate 200 by being completely hardened (C-stage) when the first laminate 100 is joined to the second laminate 200.

金屬接合部400貫穿接合絕緣層300以將第一導電圖案層11與第二導電圖案層21內連。金屬接合部400包括:晶種金屬層410,形成於第二導電圖案層21的突出的區中;金屬柱420,形成於晶種金屬層410上;以及低熔點金屬層430,具有較金屬柱420的熔點低的熔點。The metal joint 400 penetrates the insulating layer 300 to interconnect the first conductive pattern layer 11 and the second conductive pattern layer 21. The metal bonding portion 400 includes: a seed metal layer 410 formed in a protruding region of the second conductive pattern layer 21; a metal pillar 420 formed on the seed metal layer 410; and a low melting metal layer 430 having a relatively metal pillar The melting point of 420 is low.

當用於製造第二積層板200的製程中的載體(圖4中的C)的超薄金屬箔(圖4中CF2)的一些部分餘留在第二積層板200上時,可形成晶種金屬層410。作為另一選擇,可藉由無電鍍覆來形成晶種金屬層410。晶種金屬層410可含有但不限於銅。When some portions of the ultra-thin metal foil (CF2 in FIG. 4) of the carrier (C in FIG. 4) in the process for manufacturing the second laminate 200 are left on the second laminate 200, a seed crystal can be formed. Metal layer 410. Alternatively, the seed metal layer 410 can be formed by electroless plating. The seed metal layer 410 can include, but is not limited to, copper.

金屬柱420形成於晶種金屬層410上。金屬柱420可由具有優異的電性性質的銅(Cu)、銀(Ag)、鈀(Pd)、鋁(Al)、鎳(Ni)、鈦(Ti)、金(Au)或鉑(Pt)製成。金屬柱420可由(但不限於)與形成第一導電圖案層11及第二導電圖案層21的導電材料相同的材料製成。Metal pillars 420 are formed on the seed metal layer 410. The metal pillar 420 may be made of copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au) or platinum (Pt) having excellent electrical properties. production. The metal pillars 420 may be made of, but not limited to, the same material as the conductive material forming the first conductive pattern layer 11 and the second conductive pattern layer 21.

低熔點金屬層430形成於金屬柱420與第一導電圖案層11之間。亦即,低熔點金屬層430將金屬柱420與第一導電圖案層11電性連接。The low melting point metal layer 430 is formed between the metal pillar 420 and the first conductive pattern layer 11. That is, the low melting point metal layer 430 electrically connects the metal post 420 to the first conductive pattern layer 11.

低熔點金屬層430可由焊料材料製成。此處,「焊料」是指可用於進行焊接且可為含有但不限於鉛(Pb)的合金的金屬材料。舉例而言,焊料可為錫(Sn)、銀(Ag)、銅(Cu)、或選自前述元素的金屬的合金。具體而言,用於本發明實施例中的焊料可為錫的含量為90%或大於90%的錫、銀及銅的合金。The low melting point metal layer 430 may be made of a solder material. Here, "solder" means a metal material which can be used for welding and which may be an alloy containing, but not limited to, lead (Pb). For example, the solder may be an alloy of tin (Sn), silver (Ag), copper (Cu), or a metal selected from the foregoing elements. Specifically, the solder used in the embodiment of the present invention may be an alloy of tin, silver, and copper having a tin content of 90% or more.

低熔點金屬層430的熔點低於金屬柱420的熔點。因此,在比低熔點金屬層430的熔點高且比金屬柱420的熔點低的溫度下執行的第一積層板100與第二積層板200的接合製程期間,低熔點金屬層430的至少一些部分被熔融。由於經熔融的低熔點金屬層430具有流動性,因此低熔點金屬層430可在第一導電圖案層11、金屬柱420、晶種金屬層410及第二導電圖案層21周圍形成。The melting point of the low melting point metal layer 430 is lower than the melting point of the metal pillar 420. Therefore, at least some portions of the low melting point metal layer 430 during the bonding process of the first laminate 100 and the second laminate 200 performed at a temperature higher than the melting point of the low melting point metal layer 430 and lower than the melting point of the metal pillar 420 Being melted. Since the molten low-melting-point metal layer 430 has fluidity, the low-melting-point metal layer 430 may be formed around the first conductive pattern layer 11, the metal pillar 420, the seed metal layer 410, and the second conductive pattern layer 21.

接合絕緣層300可形成有開口310,開口310暴露出第一導電圖案層11及第二導電圖案層21中的每一者的至少一部分,且熔融的低熔點金屬層430可填充開口310的至少一部分。The bonding insulating layer 300 may be formed with an opening 310 exposing at least a portion of each of the first conductive pattern layer 11 and the second conductive pattern layer 21, and the molten low melting point metal layer 430 may fill at least the opening 310 portion.

由於低熔點金屬層430的至少一些部分在第一積層板100與第二積層板200的接合製程期間被熔融,因此會在低熔點金屬層430與第一導電圖案層11、金屬柱420、晶種金屬層410及第二導電圖案層21中的至少一者之間形成金屬間化合物(inter-metallic compound,IMC)層。金屬間化合物層可由含有錫及銅的合金製成。Since at least some portions of the low-melting-point metal layer 430 are melted during the bonding process of the first laminate 100 and the second laminate 200, the low-melting-point metal layer 430 and the first conductive pattern layer 11, the metal pillar 420, and the crystal An inter-metallic compound (IMC) layer is formed between at least one of the metal layer 410 and the second conductive pattern layer 21. The intermetallic compound layer may be made of an alloy containing tin and copper.

根據本實施例的多層印刷電路板1000可更包括形成於第一積層板100與第二積層板200相對的表面上的阻焊(solder resist,SR)層。 (另一實施例)The multilayer printed circuit board 1000 according to the present embodiment may further include a solder resist (SR) layer formed on a surface of the first build-up board 100 opposite to the second build-up board 200. (Another embodiment)

圖2示出根據本發明另一實施例的多層印刷電路板。2 illustrates a multilayer printed circuit board in accordance with another embodiment of the present invention.

在根據本實施例的多層印刷電路板2000與根據本發明所述一個實施例的多層印刷電路板1000之間,金屬接合部40及接合絕緣層300是不同的,且下文將主要闡述該些不同之處。Between the multilayer printed circuit board 2000 according to the present embodiment and the multilayer printed circuit board 1000 according to one embodiment of the present invention, the metal joint portion 40 and the joint insulating layer 300 are different, and the differences will be mainly explained below. Where.

本實施例中的第一積層板100、第二積層板200、第一導電圖案層11、第二導電圖案層21、第一絕緣層110及第二絕緣層210與結合本發明的所述一個實施例闡述的相應元件實質上相同。The first laminate 100, the second laminate 200, the first conductive pattern layer 11, the second conductive pattern layer 21, the first insulating layer 110, and the second insulating layer 210 in this embodiment are combined with the one of the present invention. The corresponding elements set forth in the embodiments are substantially identical.

在本實施例與本發明的所述一個實施例之間,金屬接合部400的耦合關係是不同的。具體而言,在本實施例中,金屬柱420形成於第一導電圖案層11上,且低熔點金屬層430形成於晶種金屬層410與金屬柱420之間。Between the present embodiment and the one embodiment of the present invention, the coupling relationship of the metal joints 400 is different. Specifically, in the present embodiment, the metal pillars 420 are formed on the first conductive pattern layer 11 and the low-melting-point metal layer 430 is formed between the seed metal layer 410 and the metal pillars 420.

與根據本發明的所述一個實施例的接合絕緣層300不同,在本實施例中,接合絕緣層300可利用例如味之素增層膜等傳統增層膜來形成。製造多層印刷電路板的方法 (一個實施例)Unlike the bonding insulating layer 300 according to the one embodiment of the present invention, in the present embodiment, the bonding insulating layer 300 can be formed using a conventional build-up film such as a masonic agglomerate film. Method of manufacturing a multilayer printed circuit board (one embodiment)

圖3至圖10示出根據本發明一個實施例的一種製造多層印刷電路板的方法。3 through 10 illustrate a method of fabricating a multilayer printed circuit board in accordance with one embodiment of the present invention.

具體而言,圖3示出在根據本發明一個實施例的製造多層印刷電路板的方法中在第一積層板上形成的接合絕緣層,且圖4至圖8示出在根據本發明一個實施例的製造多層印刷電路板的方法中製造第二積層板的連續製程。圖9及圖10示出接合第一積層板與第二積層板。 (製造第一積層板)Specifically, FIG. 3 illustrates a bonding insulating layer formed on a first laminate in a method of manufacturing a multilayer printed circuit board according to an embodiment of the present invention, and FIGS. 4 to 8 illustrate an implementation in accordance with the present invention. A continuous process for manufacturing a second laminate in the method of manufacturing a multilayer printed circuit board. 9 and 10 illustrate joining the first laminate and the second laminate. (manufacturing the first laminate)

圖3示出在根據本發明一個實施例的製造多層印刷電路板的方法中在第一積層板上形成的接合絕緣層。3 illustrates a bonding insulating layer formed on a first laminate in a method of manufacturing a multilayer printed circuit board in accordance with one embodiment of the present invention.

參照圖3,形成第一積層板,且在第一積層板上形成接合絕緣層。Referring to FIG. 3, a first build-up board is formed, and a joint insulating layer is formed on the first build-up board.

第一積層板100可利用傳統有核心方法或無核心方法來形成。以下,第一積層板100將被闡述成利用有核心方法來形成,但本發明的範圍不應侷限於本文所述內容。The first laminate 100 can be formed using a conventional core method or a coreless method. Hereinafter, the first laminate 100 will be described as being formed using a core method, but the scope of the present invention should not be limited to the contents described herein.

利用有核心方法而形成的第一積層板100可藉由以下製程來形成。The first laminate 100 formed by the core method can be formed by the following process.

在作為核心絕緣層的第一絕緣層110中加工通孔孔洞。然後,藉由無電鍍覆在包括通孔孔洞的核心絕緣層的表面上形成晶種層。接下來,在核心絕緣層的兩個表面上積層乾膜之後,藉由微影製程來形成鍍覆抗蝕劑。然後,藉由利用電鍍在鍍覆抗蝕劑的開口中沈澱導電材料來形成第一導電圖案層11。接下來,移除鍍覆抗蝕劑,且移除被暴露的晶種層。最後,可藉由將傳統增層製程重複若干次來製造圖3所示的第一積層板100。藉由該些製程,可製造形成有多個第一絕緣層110、多個第一導電圖案層11及多個第一通孔V1的第一積層板100。A via hole is formed in the first insulating layer 110 as a core insulating layer. Then, a seed layer is formed on the surface of the core insulating layer including the via holes by electroless plating. Next, after laminating a dry film on both surfaces of the core insulating layer, a plating resist is formed by a lithography process. Then, the first conductive pattern layer 11 is formed by precipitating a conductive material in the opening of the plating resist by electroplating. Next, the plating resist is removed and the exposed seed layer is removed. Finally, the first laminate 100 shown in Fig. 3 can be manufactured by repeating the conventional build-up process several times. By the processes, the first laminate 100 in which the plurality of first insulating layers 110, the plurality of first conductive pattern layers 11 and the plurality of first via holes V1 are formed can be manufactured.

上述多個第一導電圖案層11可分別利用減成製程、半加成製程及經修改半加成製程中的任一種來形成。The plurality of first conductive pattern layers 11 may be formed by any one of a subtractive process, a semi-additive process, and a modified half-addition process, respectively.

可藉由在第一積層板100上積層阻焊膜或感光性絕緣膜來形成接合絕緣層300。然後,藉由微影製程形成開口310,開口310用於暴露出第一積層板100的最外層的第一導電圖案層11(例如,圖1中的第一積層板的最上層)的至少一部分。The bonding insulating layer 300 can be formed by laminating a solder resist film or a photosensitive insulating film on the first laminate 100. Then, the opening 310 is formed by a lithography process for exposing at least a portion of the first conductive pattern layer 11 of the outermost layer of the first laminate 100 (for example, the uppermost layer of the first laminate in FIG. 1) .

同時,即使在該些製程完成之後,接合絕緣層300仍未完全硬化(即,C階段)。亦即,在第一積層板100上形成接合絕緣層300之後直至隨後將闡述的接合製程,接合絕緣層300是半硬化的(即,B階段)。 (製造第二積層板)At the same time, even after the processes are completed, the bonding insulating layer 300 is not completely hardened (i.e., stage C). That is, after the bonding insulating layer 300 is formed on the first build-up board 100 until the bonding process to be described later, the bonding insulating layer 300 is semi-hardened (ie, the B-stage). (Manufacture of second laminate)

參照圖4,在載體上交替地形成第二導電圖案層與第二絕緣層。Referring to FIG. 4, a second conductive pattern layer and a second insulating layer are alternately formed on a carrier.

載體C可為用於實施無核心方法的傳統輔助材料。亦即,載體C可包括支撐板S、形成於支撐板S的任一表面上的載體金屬箔CF1及分別形成於載體金屬箔CF1上的超薄金屬箔CF2。Carrier C can be a conventional ancillary material for implementing a coreless process. That is, the carrier C may include a support plate S, a carrier metal foil CF1 formed on any surface of the support plate S, and an ultra-thin metal foil CF2 formed on the carrier metal foil CF1, respectively.

形成於圖4中最下部分處的第二導電圖案層21可藉由電鍍、使用超薄金屬箔CF2作為電力供應層來形成。亦即,第二導電圖案層21可藉由以下方式形成於第二積層板的最下部分處:在載體C的超薄金屬箔CF2上積層乾膜,藉由微影製程形成鍍覆抗蝕劑,在鍍覆抗蝕劑的開口中沈澱導電材料,及移除乾膜。The second conductive pattern layer 21 formed at the lowermost portion in FIG. 4 can be formed by electroplating using the ultra-thin metal foil CF2 as a power supply layer. That is, the second conductive pattern layer 21 can be formed at the lowermost portion of the second laminate by: laminating a dry film on the ultra-thin metal foil CF2 of the carrier C, and forming a plating resist by a lithography process The agent deposits a conductive material in the opening of the plating resist and removes the dry film.

在利用在印刷電路板的領域中形成電路的製程的情形中,第二導電圖案層21及第二通孔V2可利用半加成製程或經修改半加成製程來形成。作為另一選擇,第二導電圖案層可利用在半導體的領域中形成導電材料的方法而非在印刷電路板的領域中形成電路的製程來形成。亦即,第二導電圖案層可利用例如化學氣相沈積(Chemical Vapor Deposition,CVD)或物理氣相沈積(Physical Vapor Deposition,PVD)等沈積製程來形成。In the case of a process of forming a circuit in the field of a printed circuit board, the second conductive pattern layer 21 and the second via hole V2 may be formed using a semi-additive process or a modified half-addition process. Alternatively, the second conductive pattern layer may be formed using a method of forming a conductive material in the field of semiconductors rather than a process of forming a circuit in the field of printed circuit boards. That is, the second conductive pattern layer can be formed by a deposition process such as Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD).

第二絕緣層210可藉由在載體C上積層感光性絕緣膜來形成。作為另一選擇,第二絕緣層210可藉由在載體C上積層例如味之素增層膜等增層絕緣膜來形成。在其中第二絕緣層210是使用感光性絕緣膜來形成的情形中,可藉由單個微影製程同時地形成多個通孔孔洞,所述多個通孔孔洞形成於第二絕緣層210中的任一者中以形成第二通孔V2。The second insulating layer 210 can be formed by laminating a photosensitive insulating film on the carrier C. Alternatively, the second insulating layer 210 may be formed by laminating a build-up insulating film such as a muscarinic buildup film on the carrier C. In the case where the second insulating layer 210 is formed using a photosensitive insulating film, a plurality of via holes may be simultaneously formed by a single lithography process, the plurality of via holes being formed in the second insulating layer 210 Any of them forms a second through hole V2.

儘管圖4中示出第二導電圖案層21與第二絕緣層210交替地形成於載體C的一側上,然而本發明不應僅限於本文中所示內容。亦即,上述製程可在載體C的兩側上執行。Although the second conductive pattern layer 21 and the second insulating layer 210 are alternately formed on one side of the carrier C in FIG. 4, the present invention should not be limited to the contents shown herein. That is, the above process can be performed on both sides of the carrier C.

接下來,參照圖5,形成保護層,且接著移除載體。Next, referring to FIG. 5, a protective layer is formed, and then the carrier is removed.

保護層PL可包括分離層。保護層PL根據本實施例保護及支撐第二積層板200,直至接合製程完成。The protective layer PL may include a separation layer. The protective layer PL protects and supports the second laminate 200 according to the present embodiment until the bonding process is completed.

在載體金屬箔CF1與超薄金屬箔CF2之間的介面處發生分離,且自第二積層板移除載體C。因此,超薄金屬箔CF2在此步驟完成之後餘留在第二積層板200上。Separation takes place at the interface between the carrier metal foil CF1 and the ultra-thin metal foil CF2, and the carrier C is removed from the second laminate. Therefore, the ultra-thin metal foil CF2 remains on the second laminate 200 after this step is completed.

然後,參照圖6,在第二積層板的上面留有超薄金屬箔的一個表面上形成鍍覆抗蝕劑。Then, referring to Fig. 6, a plating resist is formed on one surface of the second laminate which is left with an ultra-thin metal foil.

鍍覆抗蝕劑PR1可藉由在第二積層板200的一個表面上積層乾膜且接著執行微影製程來形成。鍍覆抗蝕劑PR1形成有開口以暴露出超薄金屬箔CF2的至少一部分。The plating resist PR1 can be formed by laminating a dry film on one surface of the second laminate 200 and then performing a lithography process. The plating resist PR1 is formed with an opening to expose at least a portion of the ultra-thin metal foil CF2.

接下來,參照圖7,在鍍覆抗蝕劑的開口中形成金屬柱及低熔點金屬層。Next, referring to Fig. 7, a metal post and a low melting point metal layer are formed in the opening of the plating resist.

金屬柱420可藉由電解鍍銅來形成。低熔點金屬層430可藉由電鍍或膏印刷來形成。金屬柱420可藉由自下而上方法、使用超薄金屬箔CF2作為電力供應層來形成。The metal post 420 can be formed by electrolytic copper plating. The low melting point metal layer 430 can be formed by electroplating or paste printing. The metal post 420 can be formed by a bottom-up method using an ultra-thin metal foil CF2 as a power supply layer.

然後,參照圖8,移除鍍覆抗蝕劑,且移除超薄金屬箔的其中不形成金屬柱的部分。Then, referring to FIG. 8, the plating resist is removed, and the portion of the ultra-thin metal foil in which the metal pillar is not formed is removed.

超薄金屬箔CF2可藉由閃速蝕刻(flash etching)或半蝕刻(half etching)來移除。此處,在其中超薄金屬箔CF2與第二導電圖案層21是由同一種金屬製成的情形中,第二導電圖案層21的一部分可與超薄金屬箔CF2一起移除。亦即,在第二導電圖案層21的一個表面中形成溝槽R。The ultra-thin metal foil CF2 can be removed by flash etching or half etching. Here, in the case where the ultra-thin metal foil CF2 and the second conductive pattern layer 21 are made of the same metal, a part of the second conductive pattern layer 21 may be removed together with the ultra-thin metal foil CF2. That is, the groove R is formed in one surface of the second conductive pattern layer 21.

藉由移除超薄金屬箔CF2的一部分來形成晶種金屬層410。金屬接合部400是由以下構成:晶種金屬層410,形成於第二導電圖案層21上;金屬柱420,形成於晶種金屬層410上;以及低熔點金屬層430,形成於金屬柱420上。 (接合第一積層板與第二積層板)The seed metal layer 410 is formed by removing a portion of the ultra-thin metal foil CF2. The metal bonding portion 400 is composed of a seed metal layer 410 formed on the second conductive pattern layer 21, a metal pillar 420 formed on the seed metal layer 410, and a low melting metal layer 430 formed on the metal pillar 420. on. (joining the first laminate and the second laminate)

參照圖9,將第一積層板與第二積層板對準。Referring to Figure 9, the first laminate is aligned with the second laminate.

第一積層板100與第二積層板200被排列成第一積層板100及第二積層板200各自的一個表面面對彼此。形成有開口310的接合絕緣層300形成於第一積層板100的一個表面上,且金屬接合部400形成於第二積層板200的一個表面上。The first laminate 100 and the second laminate 200 are arranged such that one surface of each of the first laminate 100 and the second laminate 200 faces each other. A bonding insulating layer 300 formed with an opening 310 is formed on one surface of the first laminate 100, and a metal bonding portion 400 is formed on one surface of the second laminate 200.

第一積層板100與第二積層板200可利用例如對準標記來進行對準。此處,第一積層板100與第二積層板200可被對準成使得金屬接合部400的位置對應於接合絕緣層300的開口310的位置。The first laminate 100 and the second laminate 200 may be aligned using, for example, alignment marks. Here, the first laminate 100 and the second laminate 200 may be aligned such that the position of the metal joint 400 corresponds to the position of the opening 310 of the bonding insulating layer 300.

參照圖10,藉由對第一積層板及第二積層板進行加熱及按壓來將第一積層板與第二積層板彼此接合。Referring to Fig. 10, the first laminate and the second laminate are joined to each other by heating and pressing the first laminate and the second laminate.

接合製程是在比低熔點金屬層430的熔點高且比金屬柱420的熔點低的溫度下執行。因此,低熔點金屬層430的至少一些部分被熔融以填充接合絕緣層300的開口310的至少一部分。The bonding process is performed at a temperature higher than the melting point of the low melting point metal layer 430 and lower than the melting point of the metal pillar 420. Accordingly, at least some portions of the low melting point metal layer 430 are fused to fill at least a portion of the opening 310 of the bonding insulating layer 300.

儘管圖中未示出,然而可在第一積層板100的下部部分處形成保護層以保護及支撐第一積層板100。Although not shown in the drawings, a protective layer may be formed at a lower portion of the first laminate 100 to protect and support the first laminate 100.

接下來,儘管圖中未示出,然而在移除分別形成於第一積層板100及第二積層板200上的保護層PL之後,分別在第一積層板100的下表面以及第二積層板200的另一表面上形成阻焊層SR(示於圖1中),由此製造圖1所示的根據本發明一個實施例的多層印刷電路板1000。 (另一實施例)Next, although not shown in the drawing, after removing the protective layers PL respectively formed on the first build-up board 100 and the second build-up board 200, respectively, the lower surface of the first build-up board 100 and the second build-up board A solder resist layer SR (shown in FIG. 1) is formed on the other surface of 200, thereby manufacturing the multilayer printed circuit board 1000 according to an embodiment of the present invention shown in FIG. (Another embodiment)

圖11至圖20示出根據本發明另一實施例的一種製造多層印刷電路板的方法。11 through 20 illustrate a method of fabricating a multilayer printed circuit board in accordance with another embodiment of the present invention.

具體而言,圖11至圖15示出在根據本發明另一實施例的製造多層印刷電路板的方法中在第一積層板上形成接合絕緣層及金屬柱,且圖16至圖18示出在根據本發明另一實施例的製造多層印刷電路板的方法中製造第二積層板的連續製程。圖19及圖20示出將第一積層板與第二積層板接合。 (製造第一積層板)Specifically, FIGS. 11 to 15 illustrate forming a bonding insulating layer and a metal pillar on a first laminate in a method of manufacturing a multilayer printed circuit board according to another embodiment of the present invention, and FIGS. 16 to 18 illustrate A continuous process for manufacturing a second laminate in the method of manufacturing a multilayer printed circuit board according to another embodiment of the present invention. 19 and 20 show the joining of the first laminate to the second laminate. (manufacturing the first laminate)

圖11至圖15示出在根據本發明另一實施例的製造多層印刷電路板的方法中連續地形成第一積層板、接合絕緣層及金屬柱。11 to 15 illustrate that a first build-up board, a joint insulating layer, and a metal post are continuously formed in a method of manufacturing a multilayer printed circuit board according to another embodiment of the present invention.

參照圖11,形成第一積層板。Referring to Figure 11, a first laminate is formed.

第一積層板100可利用傳統有核心方法或無核心方法來形成。以下,第一積層板100將被闡述成利用有核心方法來形成,但本發明的範圍不應侷限於本文所述內容。The first laminate 100 can be formed using a conventional core method or a coreless method. Hereinafter, the first laminate 100 will be described as being formed using a core method, but the scope of the present invention should not be limited to the contents described herein.

利用有核心方法而形成的第一積層板100可藉由以下製程來形成。The first laminate 100 formed by the core method can be formed by the following process.

在作為核心絕緣層的第一絕緣層110中加工通孔孔洞。然後,藉由無電鍍覆在包括通孔孔洞的核心絕緣層的表面上形成晶種層。接下來,在核心絕緣層的兩個表面上積層乾膜之後,藉由微影製程來形成鍍覆抗蝕劑。然後,藉由利用電鍍在鍍覆抗蝕劑的開口中沈澱導電材料來形成第一導電圖案層11。接下來,移除鍍覆抗蝕劑,且移除被暴露的晶種層。最後,可藉由將傳統增層製程重複若干次來製造圖11所示的第一積層板100。藉由該些製程,可製造形成有多個第一絕緣層110、多個第一導電圖案層11及多個第一通孔V1的第一積層板100。A via hole is formed in the first insulating layer 110 as a core insulating layer. Then, a seed layer is formed on the surface of the core insulating layer including the via holes by electroless plating. Next, after laminating a dry film on both surfaces of the core insulating layer, a plating resist is formed by a lithography process. Then, the first conductive pattern layer 11 is formed by precipitating a conductive material in the opening of the plating resist by electroplating. Next, the plating resist is removed and the exposed seed layer is removed. Finally, the first laminate 100 shown in Fig. 11 can be manufactured by repeating the conventional build-up process several times. By the processes, the first laminate 100 in which the plurality of first insulating layers 110, the plurality of first conductive pattern layers 11 and the plurality of first via holes V1 are formed can be manufactured.

此處,最外第一導電圖案層因用於形成最外第一絕緣層的樹脂塗佈銅(resin coated copper,RCC)的銅箔而被電性斷開。Here, the outermost first conductive pattern layer is electrically disconnected by a resin coated copper (RCC) copper foil for forming the outermost first insulating layer.

上述多個第一導電圖案層11可分別利用減成製程、半加成製程及經修改半加成製程中的任一種來形成。The plurality of first conductive pattern layers 11 may be formed by any one of a subtractive process, a semi-additive process, and a modified half-addition process, respectively.

接下來,參照圖12,在第一積層板的一個表面上形成鍍覆抗蝕劑以用於形成金屬柱。Next, referring to Fig. 12, a plating resist is formed on one surface of the first laminate to form a metal pillar.

鍍覆抗蝕劑PR2可藉由在第一積層板100的一個表面上積層乾膜且接著執行微影製程來形成。鍍覆抗蝕劑PR2形成有開口以暴露出第一導電圖案層11的至少一部分。The plating resist PR2 can be formed by laminating a dry film on one surface of the first laminate 100 and then performing a lithography process. The plating resist PR2 is formed with an opening to expose at least a portion of the first conductive pattern layer 11.

可在第一積層板100的另一表面上形成保護層。與鍍覆抗蝕劑PR2相同,保護層可利用乾膜來形成。保護層阻止在第一積層板的一個表面上形成金屬柱的電鍍製程期間在第一積層板的另一表面上執行不需要的鍍覆。A protective layer may be formed on the other surface of the first laminate 100. Like the plating resist PR2, the protective layer can be formed using a dry film. The protective layer prevents unnecessary plating from being performed on the other surface of the first laminate during an electroplating process in which a metal pillar is formed on one surface of the first laminate.

接下來,參照圖13,在第一積層板的一個表面上形成金屬柱,且在移除鍍覆抗蝕劑之後,移除被暴露的銅箔。Next, referring to Fig. 13, a metal pillar is formed on one surface of the first laminate, and after the plating resist is removed, the exposed copper foil is removed.

金屬柱420可藉由自下而上方法在經由鍍覆抗蝕劑PR2的開口而暴露的第一導電圖案層11上形成。The metal post 420 can be formed on the first conductive pattern layer 11 exposed through the opening of the plating resist PR2 by a bottom-up method.

在移除鍍覆抗蝕劑PR2之後,可藉由閃速蝕刻或半蝕刻來移除被暴露的銅箔。藉由此步驟,最外第一導電圖案層11不再被電性斷開。After the plating resist PR2 is removed, the exposed copper foil can be removed by flash etching or half etching. By this step, the outermost first conductive pattern layer 11 is no longer electrically disconnected.

然後,參照圖14,在第一積層板的另一表面上形成阻焊層。Then, referring to Fig. 14, a solder resist layer is formed on the other surface of the first laminate.

阻焊層SR可藉由在第一積層板的另一表面上積層阻焊膜來形成。阻焊層SR可形成有開口,以暴露出圖14所示的最下第一導電圖案層11的一部分。所述開口可藉由微影製程來形成。The solder resist layer SR can be formed by laminating a solder resist film on the other surface of the first laminate. The solder resist layer SR may be formed with an opening to expose a portion of the lowermost first conductive pattern layer 11 shown in FIG. The opening can be formed by a lithography process.

在此步驟中,阻焊層SR被完全硬化(即,C階段)。完全硬化(C階段)的阻焊層SR在接下來的接合製程中保護並支撐第一積層板。In this step, the solder resist layer SR is completely hardened (i.e., stage C). The fully hardened (C-stage) solder mask SR protects and supports the first laminate in the subsequent bonding process.

接下來,參照圖15,在第一積層板的一個表面上形成接合絕緣層。Next, referring to Fig. 15, a bonding insulating layer is formed on one surface of the first laminate.

接合絕緣層300可藉由在第一積層板的一個表面上積層例如味之素增層膜等增層膜來形成。The bonding insulating layer 300 can be formed by laminating a buildup film such as an Ajinomoto-germenting film on one surface of the first laminate.

接合絕緣層300暴露出金屬柱420的上表面。因此,可在第一積層板100的一個表面上積層較金屬柱420厚的絕緣膜,且接著可對絕緣膜進行研磨以暴露出金屬柱420的上表面。然後,藉由蝕刻掉被暴露的金屬柱420的一些部分,形成接納溝槽。可經由接納溝槽插入隨後將闡述的形成於第二積層板上的低熔點金屬層(參見圖19)。 (製造第二積層板)The bonding insulating layer 300 exposes the upper surface of the metal post 420. Therefore, an insulating film thicker than the metal pillars 420 may be laminated on one surface of the first laminate 100, and then the insulating film may be ground to expose the upper surface of the metal pillars 420. The receiving trench is then formed by etching away portions of the exposed metal pillars 420. A low melting point metal layer formed on the second buildup layer, which will be described later, can be inserted via the receiving trench (see FIG. 19). (Manufacture of second laminate)

參照圖16至圖18,在載體上形成第二積層板,且在第二積層板的一個表面上形成晶種金屬層及低熔點金屬層。Referring to FIGS. 16 to 18, a second laminate is formed on the carrier, and a seed metal layer and a low melting metal layer are formed on one surface of the second laminate.

圖16及圖17所示的步驟與根據本發明一個實施例的製造多層印刷電路板的方法的圖4及圖5所示的步驟相同。因此,與圖4及圖5相關聯的說明可同樣適用於圖16及圖17。The steps shown in Figs. 16 and 17 are the same as those shown in Figs. 4 and 5 of the method of manufacturing a multilayer printed circuit board according to an embodiment of the present invention. Therefore, the description associated with FIGS. 4 and 5 is equally applicable to FIGS. 16 and 17.

接下來參照圖18,在第二積層板的上面留有超薄金屬箔的一個表面上形成鍍覆抗蝕劑,且在鍍覆抗蝕劑的開口中形成低熔點金屬層,並且然後移除鍍覆抗蝕劑且移除超薄金屬箔的其中不形成金屬柱的部分。Referring next to FIG. 18, a plating resist is formed on one surface of the second laminate which is left with the ultra-thin metal foil, and a low-melting-point metal layer is formed in the opening of the plating resist, and then removed. The resist is plated and the portion of the ultra-thin metal foil in which the metal pillar is not formed is removed.

鍍覆抗蝕劑可藉由在第二積層板200的一個表面上積層乾膜且接著執行微影製程來形成。鍍覆抗蝕劑形成有開口以暴露出超薄金屬箔CF2的至少一部分。The plating resist can be formed by laminating a dry film on one surface of the second laminate 200 and then performing a lithography process. The plating resist is formed with an opening to expose at least a portion of the ultra-thin metal foil CF2.

低熔點金屬層430可藉由電鍍或膏印刷形成於鍍覆抗蝕劑的開口中。The low melting point metal layer 430 can be formed in the opening of the plating resist by electroplating or paste printing.

在移除鍍覆抗蝕劑之後,可藉由閃速蝕刻或半蝕刻來移除超薄金屬箔CF2。此處,在其中超薄金屬箔CF2與第二導電圖案層21是由同一種金屬製成的情形中,第二導電圖案層21的一部分可與超薄金屬箔CF2一起移除。亦即,在第二導電圖案層21的一個表面上形成溝槽R。After the plating resist is removed, the ultra-thin metal foil CF2 can be removed by flash etching or half etching. Here, in the case where the ultra-thin metal foil CF2 and the second conductive pattern layer 21 are made of the same metal, a part of the second conductive pattern layer 21 may be removed together with the ultra-thin metal foil CF2. That is, the groove R is formed on one surface of the second conductive pattern layer 21.

藉由移除超薄金屬箔CF2的一部分來形成晶種金屬層410。 (接合第一積層板與第二積層板)The seed metal layer 410 is formed by removing a portion of the ultra-thin metal foil CF2. (joining the first laminate and the second laminate)

圖19及圖20示出將根據本實施例的第一積層板與第二積層板接合的步驟。19 and 20 show the steps of joining the first laminate and the second laminate according to the present embodiment.

該些步驟與根據本發明一個實施例的製造多層印刷電路板的方法的步驟相似。亦即,與圖9及圖10相關聯的說明可同樣適用於圖19及圖20或經容易地修改而適合於圖19及圖20。These steps are similar to the steps of the method of fabricating a multilayer printed circuit board in accordance with one embodiment of the present invention. That is, the description associated with FIGS. 9 and 10 is equally applicable to FIGS. 19 and 20 or is easily modified to be suitable for FIGS. 19 and 20.

儘管本揭露包括具體實例,然而對於此項技術中具有通常知識者而言將顯而易見的是,在不背離申請專利範圍及其等效範圍的精神及範圍的條件下,可對該些實例作出各種形式及細節上的變化。本文所述的實例應被視為僅具有說明性意義而非用於限制。每一實例中的特徵或態樣的說明應被視為可適用於其他實例中的相似的特徵或態樣。若所述技術以不同次序來執行及/或若所述系統、架構、裝置或電路中的組件以不同的方式進行組合及/或藉由其他組件或其等效形式來替換或補充,則可達成合適的結果。因此,本揭露的範圍並非由詳細說明來界定,而是由申請專利範圍及其等效範圍來界定,且處於申請專利範圍及其等效範圍的範圍內的所有變型應被視為包括在本揭露中。Although the present disclosure includes specific examples, it will be apparent to those skilled in the art that various examples can be made without departing from the spirit and scope of the scope of the claims Changes in form and detail. The examples described herein are considered to be illustrative only and not limiting. Descriptions of features or aspects in each instance are considered to be applicable to similar features or aspects in other examples. If the techniques are performed in a different order and/or if the components in the system, architecture, device, or circuit are combined in a different manner and/or replaced or supplemented by other components or equivalents thereof, Achieve the right results. Therefore, the scope of the disclosure is not to be limited by the description, but is defined by the scope of the claims and its equivalents, and all modifications within the scope of the claims and their equivalents are Revealed.

11‧‧‧第一導電圖案層11‧‧‧First conductive pattern layer

21‧‧‧第二導電圖案層21‧‧‧Second conductive pattern layer

100‧‧‧第一積層板100‧‧‧First laminate

110‧‧‧第一絕緣層110‧‧‧First insulation

200‧‧‧第二積層板200‧‧‧Second laminate

210‧‧‧第二絕緣層210‧‧‧Second insulation

300‧‧‧接合絕緣層300‧‧‧Join insulation

310‧‧‧開口310‧‧‧ openings

400‧‧‧金屬接合部400‧‧‧Metal joints

410‧‧‧晶種金屬層410‧‧‧ seed metal layer

420‧‧‧金屬柱420‧‧‧Metal column

430‧‧‧低熔點金屬層430‧‧‧low melting point metal layer

1000、2000‧‧‧多層印刷電路板1000, 2000‧‧‧Multilayer printed circuit boards

C‧‧‧載體C‧‧‧ Carrier

CF1‧‧‧載體金屬箔CF1‧‧‧ carrier metal foil

CF2‧‧‧超薄金屬箔CF2‧‧‧ ultra-thin metal foil

PL‧‧‧保護層PL‧‧‧ protective layer

PR1、PR2‧‧‧鍍覆抗蝕劑PR1, PR2‧‧‧ plating resist

R‧‧‧溝槽R‧‧‧ trench

S‧‧‧支撐板S‧‧‧ support plate

SR‧‧‧阻焊層SR‧‧‧ solder mask

V1‧‧‧第一通孔V1‧‧‧ first through hole

V2‧‧‧第二通孔V2‧‧‧ second through hole

圖1示出根據本發明實施例的多層印刷電路板。 圖2示出根據本發明另一實施例的多層印刷電路板。 圖3至圖10示出根據本發明實施例的一種製造多層印刷電路板的方法。 圖11至圖20示出根據本發明另一實施例的一種製造多層印刷電路板的方法。Figure 1 shows a multilayer printed circuit board in accordance with an embodiment of the present invention. 2 illustrates a multilayer printed circuit board in accordance with another embodiment of the present invention. 3 through 10 illustrate a method of fabricating a multilayer printed circuit board in accordance with an embodiment of the present invention. 11 through 20 illustrate a method of fabricating a multilayer printed circuit board in accordance with another embodiment of the present invention.

Claims (12)

一種多層印刷電路板,包括: 下部基板,包括第一導電圖案層; 中介基板,包括第二導電圖案層且設置於所述下部基板上; 接合絕緣層,夾置於所述下部基板與所述中介基板之間以接合所述下部基板與所述中介基板;以及 金屬接合部,貫穿所述接合絕緣層以將所述第一導電圖案層與所述第二導電圖案層內連, 其中所述金屬接合部包括晶種金屬層、金屬柱及低熔點金屬層,所述晶種金屬層形成於所述第二導電圖案層上,所述低熔點金屬層具有較所述金屬柱的熔點低的熔點。A multilayer printed circuit board comprising: a lower substrate comprising a first conductive pattern layer; an interposer substrate comprising a second conductive pattern layer disposed on the lower substrate; a bonding insulating layer interposed on the lower substrate and the Interposing the lower substrate and the interposer between the interposer substrates; and a metal bonding portion penetrating the bonding insulating layer to interconnect the first conductive pattern layer and the second conductive pattern layer, wherein The metal junction portion includes a seed metal layer, a metal pillar and a low melting point metal layer, the seed metal layer being formed on the second conductive pattern layer, the low melting point metal layer having a lower melting point than the metal pillar Melting point. 如申請專利範圍第1項所述的多層印刷電路板,其中所述金屬柱形成於所述晶種金屬層上,且 其中所述低熔點金屬層形成於所述金屬柱與所述第一導電圖案層之間。The multilayer printed circuit board of claim 1, wherein the metal pillar is formed on the seed metal layer, and wherein the low melting point metal layer is formed on the metal pillar and the first conductive Between the pattern layers. 如申請專利範圍第2項所述的多層印刷電路板,更包括開口,所述開口形成於所述接合絕緣層中且暴露出所述第一導電圖案層及所述第二導電圖案層中的每一者的至少一部分, 其中所述低熔點金屬層填充所述開口的至少一部分。The multilayer printed circuit board of claim 2, further comprising an opening formed in the bonding insulating layer and exposing the first conductive pattern layer and the second conductive pattern layer At least a portion of each of the low melting point metal layers filling at least a portion of the opening. 如申請專利範圍第2項所述的多層印刷電路板,其中所述接合絕緣層包含感光性材料。The multilayer printed circuit board of claim 2, wherein the bonding insulating layer comprises a photosensitive material. 如申請專利範圍第1項所述的多層印刷電路板,其中所述金屬柱形成於所述第一導電圖案層上,且 其中所述低熔點金屬層形成於所述晶種金屬層與所述金屬柱之間。The multilayer printed circuit board of claim 1, wherein the metal pillar is formed on the first conductive pattern layer, and wherein the low melting point metal layer is formed on the seed metal layer and Between metal columns. 如申請專利範圍第1項所述的多層印刷電路板,其中在所述第二導電圖案層的面對所述第一導電圖案層的一個表面中形成有溝槽,以使得所述第二導電圖案層的一個區突出超過所述第二導電圖案層的另一區,且 其中所述晶種金屬層形成於所述第二導電圖案層的所述一個區中。The multilayer printed circuit board of claim 1, wherein a groove is formed in one surface of the second conductive pattern layer facing the first conductive pattern layer, such that the second conductive One region of the pattern layer protrudes beyond another region of the second conductive pattern layer, and wherein the seed metal layer is formed in the one region of the second conductive pattern layer. 如申請專利範圍第1項所述的多層印刷電路板,其中所述下部基板更包括其中形成有所述第一導電圖案層的第一絕緣層, 其中所述中介基板更包括其中形成有所述第二導電圖案層的第二絕緣層,且 其中所述第二導電圖案層嵌置於所述第二絕緣層中,使得所述第二導電圖案層的一個表面經由所述第二絕緣層的一個表面而暴露。The multilayer printed circuit board of claim 1, wherein the lower substrate further comprises a first insulating layer in which the first conductive pattern layer is formed, wherein the interposer further comprises the a second insulating layer of the second conductive pattern layer, and wherein the second conductive pattern layer is embedded in the second insulating layer such that one surface of the second conductive pattern layer is via the second insulating layer One surface is exposed. 如申請專利範圍第7項所述的多層印刷電路板,其中在所述第二導電圖案層的所述一個表面中形成有溝槽。The multilayer printed circuit board of claim 7, wherein a groove is formed in the one surface of the second conductive pattern layer. 一種多層印刷電路板,包括: 第一積層板,包括第一導電圖案層; 第二積層板,包括第二導電圖案層且設置於所述第一積層板上; 接合絕緣層,夾置於所述第一積層板的一個表面與所述第二積層板的一個表面之間以接合所述第一積層板與所述第二積層板;以及 金屬接合部,貫穿所述接合絕緣層以將所述第一導電圖案層與所述第二導電圖案層彼此電性連接, 其中所述第二導電圖案層的一個區突出超過所述第二導電圖案層的另一區,且 其中所述金屬接合部包括晶種金屬層、金屬柱及低熔點金屬層,所述晶種金屬層形成於所述第二導電圖案層的所述一個區中,所述低熔點金屬層具有較所述金屬柱的熔點低的熔點。A multilayer printed circuit board comprising: a first laminate comprising a first conductive pattern layer; a second laminate comprising a second conductive pattern layer disposed on the first laminate; bonding an insulating layer, sandwiched between Between one surface of the first laminate and one surface of the second laminate to join the first laminate and the second laminate; and a metal joint extending through the joint insulating layer The first conductive pattern layer and the second conductive pattern layer are electrically connected to each other, wherein one region of the second conductive pattern layer protrudes beyond another region of the second conductive pattern layer, and wherein the metal bond The portion includes a seed metal layer, a metal pillar and a low melting point metal layer, the seed metal layer being formed in the one region of the second conductive pattern layer, the low melting point metal layer having a smaller than the metal pillar a melting point with a low melting point. 如申請專利範圍第9項所述的多層印刷電路板,其中所述第二導電圖案層嵌置於所述第二積層板中,使得所述第二導電圖案層的一個表面經由所述第二積層板的與所述接合絕緣層接觸的一個表面而暴露。The multilayer printed circuit board of claim 9, wherein the second conductive pattern layer is embedded in the second laminate such that one surface of the second conductive pattern layer passes through the second The surface of the laminate is exposed to a surface in contact with the bonding insulating layer. 如申請專利範圍第9項所述的多層印刷電路板,其中所述金屬柱形成於所述晶種金屬層上,且 其中所述低熔點金屬層形成於所述金屬柱與所述第一導電圖案層之間。The multilayer printed circuit board of claim 9, wherein the metal pillar is formed on the seed metal layer, and wherein the low melting point metal layer is formed on the metal pillar and the first conductive Between the pattern layers. 如申請專利範圍第9項所述的多層印刷電路板,其中所述金屬柱形成於所述第一導電圖案層上,且 其中所述低熔點金屬層形成於所述晶種金屬層與所述金屬柱之間。The multilayer printed circuit board of claim 9, wherein the metal pillar is formed on the first conductive pattern layer, and wherein the low melting point metal layer is formed on the seed metal layer and Between metal columns.
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