JP2012079767A - Printed wiring board, manufacturing method thereof, multilayer printed wiring board, and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve connection reliability on the bottom surface of a via hole used for interlayer conduction.SOLUTION: An printed wiring board includes: a first isolation layer 21a that has flexibility; a seed layer 22a that is provided on a first main surface of the first isolation layer 21a; a first conductor circuit 23a provided on the seed layer 22a; a conductor layer 28a that is provided on the seed layer 22a exposed on the bottom surface of a via hole penetrating through the first isolation layer 21a; and an interlayer conduction part 24a that is embedded in the via hole and contacts the conductor layer 28a exposed on the bottom surface of the via hole. The compatibility between the interlayer conduction part 24a and the conductor layer 28a is higher than the compatibility between the interlayer conduction part 24a and the seed layer 22a.

Description

  The present invention relates to a flexible printed wiring board, a manufacturing method thereof, a multilayer printed wiring board in which a plurality of printed wiring boards are stacked, and a manufacturing method thereof.

  As electronic devices become smaller and more functional, electronic components incorporated in electronic devices are also becoming smaller, and the wiring of a printed wiring board on which the electronic components are mounted has become finer.

  In a multilayer wiring board having flexibility, a so-called flexible multilayer wiring board, a resin film (CCL: Copper Clad Laminate) bonded with a copper foil is used as an insulating layer. However, when a wiring pattern is formed by etching a copper layer such as CCL by the subtractive method, the edge of the wiring pattern is excessively removed, and it is difficult to make the wiring fine, and there is a problem that it is not suitable for high-speed transmission. In order to solve this problem, a method of forming a wiring pattern using a semi-additive method is conceivable.

  Conventionally, a multilayer wiring board has been proposed in which multiple insulation layers with circuit wiring formed on a copper foil are layered by bonding with an interlayer adhesive, and via holes formed in each insulation layer are filled with conductive paste to achieve interlayer conduction. (See Patent Document 1).

  In Patent Document 1, since a via hole used for interlayer conduction is filled with a conductive paste, a mounting component or another via hole can be arranged immediately above the via hole, and the via hole can be arranged at an arbitrary position or layer. it can. Further, since the plating step can be omitted, the outermost layer wiring does not become thick, and a fine wiring can be easily formed.

Japanese Patent No. 4195619

  However, when a seed layer made of a material different from the copper foil is formed on the insulating layer, and a multilayer wiring board is formed using a resin film in which the copper foil is formed on the seed layer, the bottom surface of the via hole A seed layer is exposed. Therefore, the conductive paste filled in the via hole comes into contact with the seed layer. Since the seed layer is made of a material that hardly forms an alloy layer with the conductive paste compared to the copper foil, the connection reliability between the seed layer and the conductive paste may be reduced. .

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and its object is to provide a printed wiring board with improved connection reliability at the bottom surface of a via hole used for interlayer conduction, a manufacturing method thereof, a multilayer printed wiring board, and a manufacturing method thereof. Is to provide.

  According to a first aspect of the present invention, there is provided a first insulating layer having flexibility, a seed layer disposed on a first main surface of the first insulating layer, and a first layer disposed on the seed layer. A conductor layer disposed on the seed layer exposed on the bottom surface of the via hole penetrating the first insulating layer, and a conductor layer embedded in the via hole and exposed on the bottom surface of the via hole. It is a printed wiring board provided with the interlayer conduction | electrical_connection part which contacts, Comprising: The affinity of an interlayer conduction | electrical_connection part and a conductor layer is higher than the affinity of an interlayer conduction | electrical_connection part and a seed layer. Here, “affinity” indicates the ease of forming an alloy between two or more different metals.

  In the first feature of the present invention, an alloy layer made of an alloy of the conductor layer and the interlayer conductive portion may be interposed at the interface between the conductor layer and the interlayer conductive portion.

  In the first feature of the present invention, the interlayer conductive portion has at least one kind of low electrical resistance metal particles selected from nickel, silver and copper, and at least one kind selected from tin, bismuth, indium and lead. It is desirable that the conductive paste containing the low melting point metal particles is heated and cured.

  In the first feature of the present invention, the metal component contained in the conductor layer is at least one kind of low electrical resistance metal selected from copper, silver, and gold, and at the interface between the conductor layer and the interlayer conductive portion. An alloy layer made of an alloy of the low electrical resistance metal in the conductor layer and the low melting point metal in the conductive paste may be interposed.

  In the first feature of the present invention, the interface between the conductor layer and the interlayer conductive portion may have an uneven shape.

  A second feature of the present invention is a printed wiring board related to the first feature, and a second flexible member bonded to a second main surface opposite to the first main surface of the first insulating layer. The insulating layer, the adhesive layer that bonds the second insulating layer and the first insulating layer, the first insulating layer and the second insulating layer, and is in contact with the interlayer conductive portion; and The gist of the invention is a multilayer printed wiring board including a second conductive circuit containing the same metal component as the conductive layer.

  The third feature of the present invention is that a first step of forming a circuit pattern comprising a seed layer and a first conductor circuit on a first main surface of a flexible first insulating layer, A second step of forming a via hole from the second main surface opposite to the first main surface of the insulating layer and exposing the seed layer to the bottom surface of the via hole, and a seed layer exposed to the bottom surface of the via hole A method for manufacturing a printed wiring board, comprising: a third step of depositing a conductor layer; and a fourth step of filling a conductive paste in a via hole whose conductor layer is exposed on the bottom surface. The affinity between the conductive paste and the conductor layer is higher than the affinity between the conductive paste and the seed layer.

  In the third feature of the present invention, in the third step, a conductor layer may be plated on the seed layer exposed on the bottom surface of the via hole.

  Furthermore, in the third step, a conductor layer may be selectively deposited on the seed layer exposed on the bottom surface of the via hole by electrolytic plating.

  Furthermore, the thickness of the conductor layer deposited in the third step is preferably 3 μm or more and 5 μm or less.

  In the third feature of the present invention, the method for manufacturing a printed wiring board may further include a step of subjecting the surface of the conductor layer exposed to the bottom surface of the via hole to an unevenness process before the fourth step.

  According to a fourth aspect of the present invention, there is provided a printed wiring board manufactured by the method for manufacturing a printed wiring board related to the third characteristic, and the first insulating layer formed with the second conductor circuit is provided with the first insulating layer. The main surface is superposed on the second main surface of the first insulating layer via the adhesive layer, and the first insulating layer and the second insulating layer are heated to cure the adhesive layer, whereby the first insulation is achieved. The gist of the present invention is a method for producing a multilayer printed wiring board in which a conductive paste is cured at the same time as bonding a layer and a second insulating layer.

  According to the printed wiring board of the present invention, the connection reliability at the bottom surface of the via hole can be improved compared to the case where the interlayer conductive portion contacts the conductor layer at the bottom surface of the via hole, as compared with the contact with the seed layer. .

  According to the printed wiring board manufacturing method of the present invention, the conductive paste is filled into a conductive layer having a higher affinity than the seed layer by filling the via hole whose conductive layer is exposed on the bottom surface with the conductive paste. Can be contacted. Therefore, the connection reliability at the bottom surface of the via hole can be improved as compared with the case where the seed layer and the conductive paste are connected at the bottom surface of the via hole.

It is sectional drawing which shows an example of the whole structure of the multilayer printed wiring board in connection with the 1st Embodiment of this invention. 2A is a cross-sectional view showing the overall configuration of the first printed wiring board 11, and FIG. 2B is a cross-sectional view showing the overall configuration of the second printed wiring board 12, and FIG. ) Is a cross-sectional view showing the overall configuration of the third printed wiring board 13. FIG. 3A to FIG. 3H are cross-sectional views showing main steps in the method for manufacturing the multilayer printed wiring board shown in FIG. 1, and show a portion surrounded by a one-dot chain line G in FIG.

  Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same parts are denoted by the same reference numerals.

  First, an overall configuration of a multilayer printed wiring board according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2A to 2C. The multilayer printed wiring board shown in FIG. 1 includes a first printed wiring board 11 shown in FIG. 2A, a second printed wiring board 12 shown in FIG. 2B, and a second printed wiring board shown in FIG. 3 printed wiring boards 13. A second printed wiring board 12 is laminated on the third printed wiring board 13, and a first printed wiring board 11 is laminated on the second printed wiring board 12.

  The first printed wiring board 11 is disposed on the first insulating layer 21a having flexibility, the seed layer 22a disposed on the first main surface of the first insulating layer 21a, and the seed layer 22a. First conductor circuit 23a formed, conductor layer 28a disposed on seed layer 22a exposed on the bottom surface of the via hole penetrating first insulating layer 21a, and interlayer conductive portion embedded in the via hole 24a and an adhesive layer 25a disposed on the second main surface of the first insulating layer 21a.

  Similarly, the second printed wiring board 12 includes a flexible second insulating layer 21b, a seed layer 22b disposed on the first main surface of the second insulating layer 21b, and a seed layer 22b. Embedded in the via hole, the second conductor circuit 23b disposed above, the conductor layer 28b disposed on the seed layer 22b exposed on the bottom surface of the via hole penetrating the second insulating layer 21b, and Interlayer conduction part 24b and adhesive layer 25b arranged on the second main surface of second insulating layer 21b are provided.

  The third printed wiring board 13 is disposed on the flexible third insulating layer 21c, the seed layer 22c disposed on the first main surface of the third insulating layer 21c, and the seed layer 22c. Third conductor circuit 23c.

  The second main surface of the first insulating layer 21a and the first main surface of the second insulating layer 21b are bonded via an adhesive layer 25a, and the second main surface of the second insulating layer 21b The third insulating layer 21c is bonded to the first main surface via an adhesive layer 25b. The second conductor circuit 23b contains the same metal component as that of the conductor layer 28a and is in contact with the interlayer conductive portion 24a. Similarly, the third conductor circuit 23c contains the same metal component as the conductor layer 28b and is in contact with the interlayer conductive portion 24b.

  The affinity between the interlayer conductive portion 24a and the conductor layer 28a is higher than the affinity between the interlayer conductive portion 24a and the seed layer 22a. The interlayer conductive portion 24a has a higher affinity than the seed layer 22a at the bottom of the via hole. It is in contact with the high conductor layer 28a. Similarly, the affinity between the interlayer conductive portion 24b and the conductor layer 28b is higher than the affinity between the interlayer conductive portion 24b and the seed layer 22b, and the interlayer conductive portion 24b is lower at the bottom surface of the via hole than the seed layer 22b. It is in contact with the conductor layer 28b having high affinity.

  An alloy layer 27a made of an alloy of the conductor layer 28a and the interlayer conductive portion 24a is interposed at the interface between the conductor layer 28a and the interlayer conductive portion 24a. Similarly, an alloy layer 27b made of an alloy of the conductor layer 28b and the interlayer conductive portion 24b is interposed at the interface between the conductor layer 28b and the interlayer conductive portion 24b.

  The interlayer conductive portions 24a and 24b include at least one kind of low electrical resistance metal particles selected from nickel, silver and copper and at least one kind of low melting point metal particles selected from tin, bismuth, indium and lead. The conductive paste is heated and cured.

  The metal component contained in the conductor layers 28a and 28b is at least one kind of low electrical resistance metal selected from copper, silver, and gold. The alloy layer 27a interposed at the interface between the conductor layer 28a and the interlayer conductive portion 24a is made of an alloy of a low electrical resistance metal in the conductor layer 28a and a low melting point metal in the conductive paste (interlayer conductive portion 24a). The alloy layer 27b interposed at the interface between the conductor layer 28b and the interlayer conductive portion 24b is made of an alloy of a low electrical resistance metal in the conductor layer 28b and a low melting point metal in the conductive paste (interlayer conductive portion 24b).

  The metal component contained in common in the second conductor circuit 23b and the conductor layer 28a is at least one low electrical resistance metal selected from copper, silver, and gold. The metal component contained in common in the third conductor circuit 23c and the conductor layer 27b is at least one low electrical resistance metal selected from copper, silver, and gold. The first conductor circuit 23a, the second conductor circuit 23b, and the third conductor circuit 23c contain the same metal component.

  The material of the seed layers 22a, 22b, and 22c includes at least one metal selected from nickel, chromium, titanium, tungsten, and an alloy of titanium and tungsten. The seed layers 22a, 22b, and 22c absorb the surface roughness of the first main surface of the first insulating layer 21a, the second insulating layer 21b, and the third insulating layer 21c. Thereby, the flatness of the first conductor circuit 23a, the second conductor circuit 23b, and the third conductor circuit 23c is improved, and the electrical characteristics are improved. Moreover, the flatness at the time of laminating | stacking a some printed wiring board also improves. Further, since the seed layers 22a, 22b, and 22c are formed of a material having a relatively high hardness, the thickness direction of the first conductor circuit 23a, the second conductor circuit 23b, and the third conductor circuit 23c is determined. Can be suppressed. Further, the adhesion strength between the first insulating layer 21a and the first conductor circuit 23a and between the second insulating layer 21b and the second conductor circuit 23b can be increased.

  Although not shown in FIGS. 1 and 2A to 2C, the interface between the conductor layer 28a and the interlayer conductive portion 24a and the interface between the conductor layer 28b and the interlayer conductive portion 24b have concavo-convex shapes. You may do it. Specifically, it is a fine concavo-convex shape formed by a roughening process such as irradiating a laser or the like to the conductor layers 28a and 28b exposed on the bottom surface of the via hole. For example, the arithmetic average roughness Ra of the bottom surface of the via hole may be 0.1 to 0.8 μm, preferably 0.1 to 0.5 μm.

  In the multilayer printed wiring board shown in FIG. 1, the shapes of the first conductor circuit 23a, the second conductor circuit 23b, and the third conductor circuit 23c are arbitrarily set, and via holes are arranged at arbitrary positions and layers. Can be. Therefore, the configuration of the multilayer printed wiring board shown in FIG. 1 is an example, and the shapes and positions of the conductor circuits 23a to 23c and the positions of the interlayer conductive portions 24a and 24b can be changed.

  Next, with reference to FIGS. 3A to 3H, main steps in the method for manufacturing the multilayer printed wiring board shown in FIG. 1 will be described. 3A to 3H show a manufacturing process of a portion surrounded by a one-dot chain line G in FIG. The first printed wiring board 11, the second printed wiring board 12, and the third printed wiring board 13 can be manufactured by substantially the same method. Here, the first printed wiring board 11 will be described as an example.

  First, as shown in FIG. 3B, a circuit pattern CP including a seed layer 22a and a first conductor circuit 23a is formed on the first main surface of the flexible first insulating layer 21a (see FIG. 3B). First step). Specifically, as shown in FIG. 3A, a single-sided copper-clad plate (CCL) in which a seed layer 22a is formed on a polyimide film by electroless plating, sputtering, and vapor deposition, and an electrolytic copper plating 23a is grown. prepare.

  Then, an etching resist pattern (etching mask) corresponding to a desired circuit pattern is formed on the electrolytic copper plating 23a by photolithography. Thereafter, the electrolytic copper plating 23a and the seed layer 22a are selectively removed using the resist pattern as an etching mask. The electrolytic copper plating 23a is removed by wet etching using a chemical solution mainly composed of ferric chloride, cupric chloride, sulfuric acid / hydrogen peroxide, sulfuric acid, or hydrochloric acid. The seed layer 22a is removed by wet etching using a nitric acid / hydrogen peroxide based chemical. Thereafter, by removing the resist pattern, a circuit pattern CP including the seed layer 22a and the first conductor circuit 23a is formed as shown in FIG.

  Considering suppression of film thickness variation and fine circuit pattern formation, the seed layer 22a preferably has a thickness of 0.01 to 3 μm, and the first conductor circuit 23a has a thickness of 3 to 20 μm. A range is desirable. Further, as the first insulating layer 21a, a polyimide film having a thickness of 12 to 50 μm or a plastic film such as a liquid crystal polymer is used.

  Next, as shown in FIG. 3C, an epoxy-based thermosetting resin film having a thickness of 25 μm is applied to the second main surface opposite to the first main surface of the first insulating layer 21a by thermocompression bonding. Affixing and forming the adhesive layer 25a. On the adhesive layer 25a, a polyimide thermosetting resin film having a thickness of 25 μm is attached by thermocompression bonding to form a resin film 26a. For thermocompression bonding, a vacuum laminator is used, and in a reduced pressure atmosphere, the film is pressed and bonded at a temperature not higher than the curing temperature of the thermosetting resin film, for example, 100 ° C. to 140 ° C. at a pressure of about 0.25 MPa.

  As a material for the adhesive layer 25a, an adhesive such as an acrylic resin or a thermoplastic adhesive represented by thermoplastic polyimide can be used instead of the epoxy thermosetting resin. Further, the adhesive layer 25a can be formed by applying, for example, a varnish-like resin adhesive to the second main surface of the first insulating layer 21a instead of the film-like material.

  As the resin film 26a, a plastic film such as PET (polyethylene terephthalate) or PEN (polyethylene naphthalate) may be used instead of polyimide, and the surface of the adhesive layer 25a is covered with a film that can be bonded or peeled off by UV irradiation. You may form.

  As shown in FIG. 3D, a via hole VH is formed from the second main surface of the first insulating layer 21a, and the seed layer 22a is exposed on the bottom surface BF1 of the via hole VH (second step). Specifically, a via hole VH penetrating the first insulating layer 21a, the adhesive layer 25a, and the resin film 26a is formed. The via hole VH is formed from the second main surface side of the first insulating layer 21a at a position where the first conductor circuit 23a is formed. Therefore, the seed layer 22a is exposed on the bottom surface BF1 of the via hole VH.

Specifically, a via hole VH having a diameter of 100 μm is formed by drilling the first insulating layer 21a, the adhesive layer 25a, and the resin film 26a with a YAG laser so as to penetrate from the second main surface side. . Thereafter, in order to remove smear generated during drilling, plasma desmear treatment with a mixed gas of carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ) is performed.

  The via hole VH can also be formed by laser processing using a carbon dioxide laser or excimer laser, drill processing, or chemical etching.

In addition, the plasma desmear process is not limited to the mixed gas of CF ₄ and O ₂ as the type of gas used, and other inert gas such as argon (Ar) can be used. You may apply the wet desmear process by a chemical | medical solution.

  (D) A conductor layer 28a is deposited on the seed layer 22a exposed on the bottom surface BF1 of the via hole VH (third step). Specifically, the conductor layer 28a is plated on the seed layer 22a exposed on the bottom surface BF1 of the via hole VH. For example, the conductor layer 28a may be selectively deposited on the seed layer 22a exposed on the bottom surface BF1 of the via hole VH by electrolytic plating to cover the entire seed layer 22a. At this time, electric power necessary for electrolytic plating is supplied from the first conductor circuit 23a, and the first conductor circuit 23a is covered with a plating resist (not shown) so that unnecessary plating is not applied to the first conductor circuit 23a. And peeled off after plating. In the third step, the conductor layer 28a may be deposited by a method such as sputtering or vapor deposition instead of plating.

  If the thickness of the conductor layer 28a deposited in the third step is too thin, the low melting point metal diffusing from the interlayer conductive portion 24a to the conductor layer 28a passes through the conductor layer 28a in the formation of the alloy layer 27a described later, and passes through the conductor layer 28a. 22a is reached. As a result, the seed layer 22a and the low melting point metal in the interlayer conductive portion 24a come into contact with each other, and the connection reliability is lowered. On the other hand, if the thickness of the conductor layer 28a deposited in the third step is too thick, the cost increases. Therefore, the thickness of the conductor layer 28a deposited in the third step is desirably 3 to 5 μm.

  The conductive paste 31a is filled into the via hole VH in which the conductor layer 28a is exposed on the bottom surface BF2 (fourth step). Specifically, the via hole VH is filled with the conductive paste 31a by screen printing until each space is filled. The conductive paste 31a includes at least one low electrical resistance metal particle selected from nickel, silver, and copper, and at least one low melting point metal particle selected from tin, bismuth, indium, and lead. It is composed of a paste in which a binder component mainly composed of an epoxy resin is mixed. The conductive paste 31a is a metal that is easy to be alloyed at a low temperature, such as the curing temperature of the adhesive layer 25a, with metal particles being diffusion bonded to each other or diffusion bonded to the conductor layer 28a or the second conductor circuit 23b. Use composition.

  In the embodiment of the present invention, a step of subjecting the surface of the conductor layer 28a exposed to the bottom surface BF2 of the via hole VH to an unevenness process may be performed before the fourth step. Specifically, a fine uneven shape is formed by a roughening process such as irradiating a laser or the like to the conductor layer 28a exposed on the bottom surface BF2 of the via hole VH. For example, the arithmetic average roughness Ra of the bottom surface BF2 of the via hole VH may be 0.1 to 0.8 μm, preferably 0.1 to 0.5 μm.

  Thereafter, the resin film 26a is peeled off. As a result, the tip (lower surface) portion of the printed and filled conductive paste 31a is exposed with a height corresponding to the thickness dimension of the peeled resin film 26a and protruding toward the lower surface side of the adhesive layer 25a. Thus, the resin film 26a adjusts the protrusion height of the conductive paste 31a that will later become the interlayer conductive portion 24a by appropriately selecting the thickness thereof. Through the above steps, a portion to be the first printed wiring board 11 is formed.

  As described above, the manufacturing process of the second printed wiring board 12 in FIG. 2B is the same as that of the first printed wiring board 11, and the description and illustration thereof are omitted. Further, the manufacturing process of the third printed wiring board 13 in FIG. 2C is the same as the first process shown in FIG.

  Next, the first printed wiring board 11, the second printed wiring board 12, and the third printed wiring board 13 are overlaid. Specifically, as shown in FIG. 3G, the first main surface of the second insulating layer 21b on which the second conductor circuit 23b is formed is the second main surface of the first insulating layer 21a. Are overlaid through the adhesive layer 25a. In the drawing, a part of the first printed wiring board 11 and the second printed wiring board 12 is shown, and the other parts are not shown.

  Then, as shown in FIG. 3 (h), the first printed wiring board 11 and the second printed wiring board 12 are heated at a temperature lower than the curing temperature of the adhesive layers 25a and 25b and the conductive pastes 31a and 31b. And the 3rd printed wiring board 13 is temporarily fixed. At this time, alignment is performed so that the lower end of the conductive paste 31a overlaps the second conductor circuit 23b. Similarly, although illustration is omitted, alignment is performed so that the lower end of the conductive paste 31b overlaps the third conductor circuit 23c.

  The 1st printed wiring board 11, the 2nd printed wiring board 12, and the 3rd printed wiring board 13 which were laminated | stacked by temporary fixing are 1 kPa at the heating temperature of 150 to 200 degreeC using a vacuum curing press apparatus. The thermocompression bonding is performed collectively in the following reduced pressure atmosphere. This method is called a batch lamination method. At the time of thermocompression bonding, the adhesive layer 25a is thermally cured, the first insulating layer 21a and the second insulating layer 21b are joined, the adhesive layer 25b is thermally cured, and the second insulating layer 21b and the third insulating layer 21b. Insulating layer 21c is joined. In addition, the conductive pastes 31a and 31b are also thermally cured to form sintered bodies, that is, interlayer conductive portions 24a and 24b.

  At the same time, an alloy layer 27a made of an alloy of the conductor layer 28a and the interlayer conductive portion 24a is formed at the interface between the conductor layer 28a and the interlayer conductive portion 24a. Similarly, an alloy layer 27b made of an alloy of the conductor layer 28b and the interlayer conductive portion 24b is formed at the interface between the conductor layer 28b and the interlayer conductive portion 24b. In this way, the multilayer printed wiring board shown in FIG. 1 is completed.

  As described above, according to the embodiment of the present invention, the following effects can be obtained.

  Compared to the case where the interlayer conductive portions 24a and 24b are in contact with the conductor layers 28a and 28b having higher affinity than the seed layers 22a and 22b, respectively, on the bottom surface BF2 of the via hole VH, thereby contacting the seed layers 22a and 22b. Thus, the connection reliability at the bottom surface BF2 of the via hole VH can be improved.

  Alloy layers 27a and 27b made of an alloy of the conductor layers 28a and 28b and the interlayer conductive portions 24a and 24b are interposed at the interfaces between the conductor layers 28a and 28b and the interlayer conductive portions 24a and 24b. Thereby, the connection reliability between the conductor layers 28a and 28b and the interlayer conductive portions 24a and 24b is improved, and the electrical resistance between the conductor layers 28a and 28b and the interlayer conductive portions 24a and 24b is also reduced. In addition, since the seed layers 22a and 22b are arranged around the conductor layers 28a and 28b exposed on the bottom surface BF2 of the via hole VH, in forming the alloy layers 27a and 27b, the conductive pastes 31a and 31b (interlayer conduction) It is possible to suppress excessive diffusion of the metal components in the parts 24a and 24b) to the first conductor circuit 23a and the second conductor circuit 23b. Thereby, it can suppress that the brittleness of an interlayer conduction | electrical_connection part increases and it becomes intensity | strength insufficient, for example.

  The interlayer conductive portions 24a and 24b include at least one kind of low electrical resistance metal particles selected from nickel, silver and copper and at least one kind of low melting point metal particles selected from tin, bismuth, indium and lead. The conductive paste is heated and cured. The conductive paste is cured by heating the conductive paste, and at the same time, an alloy is formed at the interface with the conductor layer 28a. Thereby, the connection reliability with the conductor layer 28a is improved.

  The alloy layers 27a and 27b existing at the interface between the conductor layers 28a and 28b and the interlayer conductive portions 24a and 24b are formed of the low electrical resistance metal contained in the conductor layers 28a and 28b and the conductive pastes 31a and 31b (interlayer conductive portions 24a). 24b) and an alloy with a low melting point metal. As a result, the connection between the conductor layers 28a and 28b and the interlayer conductive portions 24a and 24b is strengthened and the electrical resistance can be lowered, so that the connection reliability is improved.

  The interface between the conductor layers 28a and 28b and the interlayer conductive portions 24a and 24b may have an uneven shape. For example, the arithmetic average roughness Ra of the interface between the conductor layers 28a and 28b and the interlayer conductive portions 24a and 24b may be 0.1 to 0.8 μm, preferably 0.1 to 0.5 μm. This increases the contact area between the conductor layers 28a and 28b and the interlayer conductive portions 24a and 24b, further improving the connection reliability.

  The second conductor circuit 23b is in contact with the interlayer conductive portion 24a and contains the same metal component as the conductor layer 28a. Thereby, as the material of the interlayer conductive portion 24a, it is only necessary to consider the affinity between the material common to the conductor layer 28a and the second conductor circuit 23b, so that the range of material selection is widened.

  The interlayer conductive portions 24a and 24b are formed of conductive pastes 31a and 31b that are cured at the curing temperature of the adhesive layers 25a and 25b. When the adhesive layers 25a and 25b are cured to bond the first insulating layer 21a, the second insulating layer 21b, and the third insulating layer 21c, at the same time, the conductive pastes 31a and 31b are cured so that the interlayer conductive portion 24a and 24b can be formed. Therefore, it contributes to simplification of the manufacturing method of a multilayer printed wiring board. Further, the curing of the adhesive layers 25a and 25b and the curing of the conductive pastes 31a and 31b are simultaneously achieved by one heating.

  In the third step, the conductive paste 31a is filled into the conductor layer 28a having higher affinity than the seed layer 22a by filling the via hole VH in which the conductor layer 28a is exposed on the bottom surface BF2 with the conductive paste 31a. Can be contacted. Therefore, the connection reliability at the bottom surface BF2 of the via hole VH can be improved as compared with the case where the seed layer 22a and the conductive paste 31a are connected at the bottom surface BF2 of the via hole VH.

  In the third step, the conductor layer 28a is plated on the seed layer 22a exposed on the bottom surface BF2 of the via hole VH. Thereby, since the thickness of the conductor layer 28a can be adjusted easily, a favorable electrical property is acquired.

  In the third step, the conductor layer 28a is selectively deposited on the seed layer 22a exposed on the bottom surface BF2 of the via hole VH by electrolytic plating. If the electroplating method using the seed layer 22a or the first conductor circuit 23a as a cathode electrode is performed, the conductor layer 28a can be selectively plated only on the seed layer 22a, so that the manufacturing process can be simplified. .

  The thickness of the conductor layer 28a deposited in the third step is 3 μm or more and 5 μm or less. Thereby, the low melting point metal in the conductive paste 31a does not pass through the conductor layer 28a and is diffused to the seed layer 22a, and the manufacturing cost can be kept low.

  Before the fourth step, a step of performing unevenness processing on the surface of the conductor layer 28a exposed on the bottom surface BF2 of the via hole VH may be performed. For example, the arithmetic average roughness Ra of the interface between the conductor layer 28a and the interlayer conductive portion 24a may be 0.1 to 0.8 μm, preferably 0.1 to 0.5 μm. As a result, the contact area between the conductor layer 28a and the conductive paste 31a increases, and the connection reliability is further improved.

  The insulating layers 21a to 21c are heated to cure the adhesive layers 25a and 25b, thereby bonding the insulating layers 21a to 21c and simultaneously curing the conductive pastes 31a and 31b. Thereby, the conductive pastes 31a and 31b are heated and cured, and at the same time, an alloy is formed at the interface between the conductive pastes 31a and 31b and the conductor layers 28a and 28b. Therefore, the connection reliability between the conductive pastes 31a and 31b and the conductor layers 28a and 28b is improved. Further, since the curing of the adhesive layers 25a and 25b and the curing of the conductive pastes 31a and 31b can be performed at the same time, the manufacturing method can be simplified. Furthermore, since the seed layers 22a and 22b are disposed around the conductor layers 28a and 28b, the metal components in the conductive pastes 31a and 31b are used as the first conductor circuit 23a and the second conductor in forming the alloy. It is possible to suppress excessive diffusion to the circuit 23b. Thereby, it can suppress that the brittleness of an interlayer conduction | electrical_connection part increases and it becomes intensity | strength insufficient, for example.

  The conductive paste 31a is a metal that is easy to be alloyed at a low temperature, such as the curing temperature of the adhesive layer 25a, with metal particles being diffusion bonded to each other or diffusion bonded to the conductor layer 28a or the second conductor circuit 23b. Use composition. Thereby, connection reliability equivalent to the interlayer connection by bulk metal or plating can be secured. In addition, since the conductive paste 31a is also excellent in thermal conductivity, it is possible to obtain an effect of conducting and dissipating generated heat to the outside.

  As described above, the present invention has been described by way of one embodiment, but it should not be understood that the discussion and drawings that form part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  Although the multilayer printed wiring board which laminated | stacked the 1st-3rd printed wiring boards 11, 12, and 13 was demonstrated, the multilayer printed wiring board may have a laminated structure of 2 layers or 4 layers or more.

21a 1st insulating layer 21b 2nd insulating layer 22a seed layer 23a 1st conductor circuit 23b 2nd conductor circuit 24a interlayer conduction part 25a adhesive layer 27a alloy layer 28a conductor layer 31a conductive paste CP circuit pattern BF1, BF2 Bottom VH Via hole

Claims (12)

A first insulating layer having flexibility;
A seed layer disposed on a first main surface of the first insulating layer;
A first conductor circuit disposed on the seed layer;
A conductor layer disposed on the seed layer exposed on the bottom surface of the via hole penetrating the first insulating layer;
An interlayer conductive portion embedded in the via hole and in contact with the conductor layer exposed on the bottom surface of the via hole, and
The printed wiring board, wherein the affinity between the interlayer conductive portion and the conductor layer is higher than the affinity between the interlayer conductive portion and the seed layer.   The printed wiring board according to claim 1, wherein an alloy layer made of an alloy of the conductor layer and the interlayer conductive portion is interposed at an interface between the conductor layer and the interlayer conductive portion.   The interlayer conductive portion includes at least one type of low electrical resistance metal particles selected from nickel, silver, and copper and at least one type of low melting point metal particles selected from tin, bismuth, indium, and lead. The printed wiring board according to claim 1 or 2, wherein the paste is cured by heating.   The metal component contained in the conductor layer is at least one kind of low electrical resistance metal selected from copper, silver, and gold, and the interface between the conductor layer and the interlayer conductive portion is in the conductor layer. 4. The printed wiring board according to claim 3, wherein an alloy layer made of an alloy of a low electrical resistance metal and a low melting point metal in the conductive paste is interposed.   The printed wiring board according to claim 1, wherein an interface between the conductor layer and the interlayer conductive portion has an uneven shape. The printed wiring board according to any one of claims 1 to 5,
A flexible second insulating layer bonded to a second main surface opposite to the first main surface of the first insulating layer;
An adhesive layer for bonding the second insulating layer and the first insulating layer;
A second conductor circuit disposed between the first insulating layer and the second insulating layer, in contact with the interlayer conductive portion, and containing the same metal component as the conductor layer;
A multilayer printed wiring board comprising: A first step of forming a circuit pattern comprising a seed layer and a first conductor circuit on the first main surface of the first insulating layer having flexibility;
A second step of forming a via hole from a second main surface facing the first main surface of the first insulating layer, and exposing the seed layer on a bottom surface of the via hole;
A third step of depositing a conductor layer on the seed layer exposed on the bottom surface of the via hole;
A fourth step of filling a conductive paste into the via hole in which the conductor layer is exposed on the bottom surface,
The method for producing a printed wiring board, wherein the affinity between the conductive paste and the conductor layer is higher than the affinity between the conductive paste and the seed layer.   8. The method of manufacturing a printed wiring board according to claim 7, wherein, in the third step, the conductor layer is plated on the seed layer exposed on the bottom surface of the via hole.   9. The printed wiring board according to claim 8, wherein in the third step, the conductor layer is selectively deposited on the seed layer exposed on the bottom surface of the via hole by an electrolytic plating method. Method.   The method for manufacturing a printed wiring board according to any one of claims 7 to 9, wherein the conductor layer deposited in the third step has a thickness of 3 µm or more and 5 µm or less.   The print according to any one of claims 7 to 10, further comprising a step of subjecting the surface of the conductor layer exposed on the bottom surface of the via hole to a concavo-convex process before the fourth step. A method for manufacturing a wiring board. A printed wiring board manufactured by the method for manufacturing a printed wiring board according to any one of claims 7 to 11 is prepared,
The first main surface of the second insulating layer on which the second conductor circuit is formed is superimposed on the second main surface of the first insulating layer via an adhesive layer,
The first insulating layer and the second insulating layer are heated to cure the adhesive layer, thereby bonding the first insulating layer and the second insulating layer and simultaneously curing the conductive paste. A method for producing a multilayer printed wiring board, characterized by comprising:

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