TW201918129A - Printed circuit board - Google Patents

Abstract

A printed circuit board in accordance with an aspect of the present invention includes: first substrate constituted with a plurality of first insulating layers and formed with cavity that is open upwardly; and second substrate constituted with a plurality of second insulating layers and placed inside the cavity. A dielectric dissipation factor of the second insulating layer is smaller than a dielectric dissipation factor of the first insulating layer.

Description

A printed circuit board

This invention relates to a printed circuit board.

Many countries, including South Korea and Japan, are doing everything they can to develop technologies globally to commercialize 5G mobile telecommunication. However, in the 5G era, traditional materials and structures may not be able to cope with the requirement of a smooth transmission band of 10 GHz or higher. Therefore, efforts have been made to develop new materials and structures for transmitting received high frequency signals to the main board without any signal loss.

Related art is described in Korean Patent Publication No. 10-2011-0002112 (January 6, 2011).

The present invention is directed to a printed circuit board having reduced signal loss.

An aspect of the present invention provides a printed circuit board including: a first substrate composed of a plurality of first insulating layers and formed with a cavity that is open upward; and a second substrate Two insulating layers are formed and placed in the cavity. The dielectric dissipation factor of the second insulating layer is smaller than the dielectric dissipation factor of the first insulating layer.

The following detailed description is provided to assist the reader in a comprehensive understanding of the methods, devices and/or systems described herein. Various modifications, adaptations, and equivalents of the methods, devices, and/or systems described herein will be apparent to those skilled in the art. The order of operations described herein is merely an example, and is not limited to the order of operations referred to herein, but will be apparent to those of ordinary skill in the art, except where the operations must occur in a particular order. Other than that, it can be changed. In addition, descriptions of well-known functions and constructions of those skilled in the art can be omitted for clarity and clarity.

Features described herein can be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided to be thorough and complete, and the full scope of the present invention will be conveyed to those of ordinary skill in the art.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning meaning meaning Any term defined in a commonly used dictionary should be interpreted as having the same meaning as in the context of the related art, and should not be construed as having an idealized or overly formal meaning unless explicitly defined otherwise.

The same reference numerals will be given to the same or corresponding elements, and the same or corresponding elements will not be described again. Throughout the description of the present invention, the detailed description will be omitted when it is stated that the specific related conventional techniques are not related to the viewpoint of the present invention. Terms such as "first" and "second" may be used when describing various components, but the above elements should not be limited to the above terms. The above terms are only used to distinguish between components. In the figures, some of the elements may be exaggerated, omitted or briefly shown, and the dimensions of the elements do not necessarily reflect the actual dimensions of the elements.

In the following, specific embodiments of the invention will be described in detail with reference to the drawings.

1A and 1B show a terminal 1 in which a printed circuit board according to an embodiment of the present invention is applied.

Referring to FIGS. 1A and 1B, a printed circuit board 10 is mounted in the terminal 1. Here, the printed circuit board 10 can be a main board. The printed circuit board 10 is composed of the first substrate 100 and the second substrate 200, and the dielectric loss of the second substrate 200 is smaller than the dielectric loss of the first substrate 100. In particular, the dielectric dissipation factor of the second insulating layer 210 constituting the second substrate 200 is smaller than the dielectric dissipation factor of the first insulating layer 110 constituting the first substrate 100.

The first substrate 100 occupies most of the printed circuit board 10, which is a main board, and the second substrate 200 is limitedly formed in a predetermined area of the printed circuit board 10. Specifically, the printed circuit board 10 can be equipped with a first device 300, a second device 400, a third device 410, etc., and the first device 300 can be a radio frequency (RF) processing unit, and the second device 400 It can be an intermediate frequency (IF) processing unit. The second substrate 200 may be formed on a periphery of the connection circuit 500 that connects the first device 300 and the second device 400.

1A shows a first device 300 and a second device 400 mounted on a printed circuit board 10, and FIG. 1B shows printing before the first device 300 and the second device 400 are mounted on the printed circuit board 10. The circuit board 10 shows the mounting area 300' of the first device 300 and the mounting area 400' of the second device 400.

Referring to FIG. 1B, a second substrate 200 is formed on the periphery of the connection circuit 500 to connect the first device 300 with the second device 400. A high frequency signal of 10 GHz or higher than 10 GHz may be connected to the first device 300 and The connection circuit 500 of the second device 400 flows. Therefore, the signal loss can be reduced by providing an insulating layer having a small dielectric dissipation factor on the periphery of the connection circuit 500 in which the high-frequency signal flows, and the dielectric loss can be minimized by using the minimum dielectric power. The insulation layer of the dissipation factor is used to save costs.

Although the connection circuit 500 is shown exposed to the outside in FIGS. 1A and 1B, the connection circuit 500 may be embedded in the second substrate 200 and not exposed to the outside.

Hereinafter, a printed circuit board according to an embodiment of the present invention will be described in detail with reference to FIGS. 1A through 3.

Figure 2 illustrates a printed circuit board in accordance with one embodiment of the present invention.

Referring to FIG. 2, a printed circuit board according to an embodiment of the present invention includes a first substrate 100 and a second substrate 200. Here, the dielectric loss of the second substrate 200 is smaller than the dielectric loss of the first substrate 100. Dielectric loss refers to the power loss that occurs when an alternating electric field is formed at a dielectric substance.

The first substrate 100 is composed of a plurality of first insulating layers 110 and has a cavity C that is open upward. That is, the cavity C penetrates two or more of the plurality of first insulating layers 110 at the uppermost portion.

The second substrate 200 is inserted into the cavity C of the first substrate 100. The second substrate 200 is composed of a plurality of second insulating layers 210.

The first insulating layer 110 and the second insulating layer 210 may each be made of any one of various resins such as a thermosetting resin or a thermoplastic resin, and specifically may be an epoxy resin. Resin or polyimide (PI). Here, the epoxy resin may be, but not limited to, a naphthalene epoxy resin, a bisphenol A type epoxy resin, or a bisphenol F type epoxy resin. ), novolak epoxy resin, cresol novolak epoxy resin, rubber modified epoxy resin, ring-type aliphatic epoxy resin (ring- A type of epoxy epoxy resin, a silicon epoxy resin, a nitrogen epoxy resin, or a phosphor epoxy resin.

The first insulating layer 110 and the second insulating layer 210 may each have a fiber stiffener (for example, a glass cloth) or an inorganic filler contained in the resin. An example of the former is a prepreg (PPG), and an example of the latter is a constituent film such as Ajinomoto Build-up Film (ABF).

The dielectric dissipation factor (Df) of the second insulating layer 210 is smaller than the dielectric dissipation factor of the first insulating layer 110. The dielectric dissipation factor is the ratio of dielectric loss and is proportional to the dielectric loss.

The resin of the second insulating layer 210 and the resin of the first insulating layer 110 may be mainly made of the same material. For example, the first insulating layer 110 and the second insulating layer 210 may both be PPG, ABF or PI. Nonetheless, the second insulating layer 210 may have a dielectric dissipation factor of about 0.003, which can be achieved by adjusting the type and amount of material (eg, filler) included in the PPG, ABF, or PI.

The second insulating layer 210 may be made of a material that is completely different from the material of the first insulating layer 110. Specifically, the second insulating layer 210 may be a liquid crystal polymer (LCP), a polytetrafluoroethylene (PTFE), or a polyphenylene ether (Polyphenylene Ether) having a dielectric dissipation factor of between 0.002 and 0.0001. , PPE), at least one of Cyclo Olefin Polymer (COP) and Perfluoroalkoxy (PFA).

At the same time, the dielectric constant and dielectric constant (Dk) of the second insulating layer 210 are smaller than the dielectric constant and dielectric constant of the first insulating layer 110.

The first insulating layer 110 constituting the first substrate 100 may be formed in plurality, and the number thereof is the same as the number of layers of the second substrate 200 inserted into the first substrate 100, and the first insulating layer 110 may be composed of at least three layers. For example, in the case where the printed circuit board is a main board mounted in a smart phone, the first substrate 100 may be constituted by 11 first insulating layers 110 to form 12 circuit layers.

The second substrate 200 is a substrate inserted into the cavity C of the first substrate 100. A plurality of second insulating layers 210 constituting the second substrate 200 are also formed. As described above, the position of the second substrate 200 (ie, the position of the cavity C of the first substrate 100) may be determined based on the position of the connection circuit 500. That is, the second substrate 200 is formed on the periphery of the connection circuit 500. Further, the position of the connection circuit 500 can be determined based on the position of the first device 300, the position of the second device 400, and the position of the connection via 510. This will be explained in more detail later.

The thickness of the second substrate 200 may be smaller than the thickness of the first substrate 100. The thickness of the second substrate 200 may be almost the same as the thickness of the cavity C of the first substrate 100. Further, the number of the first insulating layers 110 penetrated by the cavity C is the same as the number of the second insulating layers 210 constituting the second substrate 200. That is, in the case where the cavity C penetrates the N first insulating layers 110, N is a natural number, and the number of the second insulating layers 210 constituting the second substrate 200 may also be N. Here, the thickness of the first insulating layer 110 and the thickness of the second insulating layer 210 may be substantially the same as each other, respectively. Therefore, the upper surface of the first substrate 100 and the upper surface of the second substrate 200 may be substantially coplanar.

The printed circuit board may be provided with a first device 300, a second device 400, a third device 410, and the like.

The first device 300 can be equipped with an antenna and can process high frequency signals. For example, the first device 300 can be an RF processing portion. The RF processing unit removes noise from the signal received from the antenna, amplifies the signal and/or downconverts the signal, and transmits the signal to the second device 400. On the contrary, the RF processing unit can amplify the signal received from the second device 400 and transmit the signal to the antenna. The RF processing unit may be constituted by an antenna, an amplifier, a mixer, a filter, or the like. The first device 300 may be provided in plurality. The terminal 1 shown in Figures 1A and 1B has two first devices 300, 300a.

The second device 400 is coupled to the first device 300 and processes the intermediate frequency. The second device 400 can be an IF processing portion. The second device 400 can perform signal communication with the first device 300, and the signal communicated between the first device 300 and the second device 400 can have a frequency of 10 GHz or higher, for example, 11.2 GHz. high frequency. Although the signal received by the second device 400 from the first device 300 is an analog signal, the signal processed by the second device 400 and transmitted to the third device 410 is a digital signal.

Although a plurality of first devices 300 are formed, a single second device 400 may be formed. In the terminal 1 shown in Fig. 1, two first devices 300 are formed, but only one second device 400 is formed. Nevertheless, this should not preclude the possibility of forming a plurality of second devices 400.

The third device 410 is coupled to the second device 400 and processes a low-frequency base band signal.

The first device is mounted on the first substrate 100 or the second substrate 200. The second device 400 is also mounted on the first substrate 100 or the second substrate 200. The first device 300 and the second device 400 can be mounted by the first substrate 100 and the second substrate 200. That is, the first device 300 and the second device 400 may be mounted on at least one of the first substrate 100 and the second substrate 200. Meanwhile, the third device 410 is mounted on the first substrate 100 and if the signal loss ratio at the circuit connected to the third device 410 processing the low frequency signal is not very high, the third device 410 regardless of the second substrate 200 Both can be mounted on the first substrate 100. The device may be mounted on a pad 220' formed on the uppermost insulating layer of the first substrate 100 or the second substrate 200 by a bonding agent such as a solder ball.

The first device 300 and the second device 400 are electrically connected to each other via the connection circuit 500.

In the case where the first device 300 is formed in plurality, each of the first devices 300 requires the connection circuit 500 to be connected to the single second device 400, and thus the connection circuit 500 may be formed in plurality. Meanwhile, the single first device 300 and the single second device 400 may be connected by a plurality of connection circuits 500. In the case where a plurality of connection circuits 500 are present, the connection circuit 500 may be formed on the same layer or different layers of the second substrate 200 in such a manner that the connection circuits 500 do not overlap each other.

Further, the first device 300 and the second device 400 are connected to each other via the connection circuit 500 and the connection via 510. The connection via can be formed by penetrating the first substrate 100 or the second substrate 200. A plurality of connection vias 510 connecting each device to the connection circuit 500 may be formed.

At least a portion of the connection circuit 500 is formed in the second substrate 200. The second insulating layer 210 is formed to surround at least a portion of the connection circuit 500. For example, at least a portion of the connection circuit 500 can be placed between the two second insulating layers 210.

Here, "portion" may mean a predetermined area in a single connection circuit 500 or may mean a single (or several) connection circuits 500 selected from a plurality of connection circuits 500. In addition, "partial" may mean both before and after.

That is, forming at least a portion of the connection circuit 500 in the second substrate 200 may mean that a part or the entirety of the single connection circuit 500 connecting the single first device 300 and the second device 400 is formed in the second substrate 200.

Alternatively, forming at least a portion of the connection circuit 500 in the second substrate 200 may mean that the connection circuit 500 is formed in plurality and one or more connection circuits 500 selected from the plurality of connection circuits 500 are formed in the second Inside the substrate 200.

Alternatively, it may include both of the above meanings.

Meanwhile, a portion of the connection circuit 500 that is not formed in the second substrate 200 or one or more connection circuits 500 that are not formed in the second substrate 200 among the plurality of connection circuits 500 is formed in the first substrate 100.

Hereinafter, the case where the single connection circuit 500 is integrally formed in the second substrate 200, the case where a part of the single connection circuit 500 is formed in the second substrate 200, and the several of the plurality of connection circuits 500 will be separately explained. The second connection circuit 500 is formed in the second substrate 200. However, this should not be construed as limiting the invention to only those circumstances.

First, for the case of 1, a case in which a single connection circuit 500 exists will be explained herein. That is, in this case, each of the single first device 300 and the single second device 400 is formed. However, the same description can be applied to the case where a plurality of first devices 300 are formed.

In the case where the first device 300 and the second device 400 are mounted on the printed circuit board and the first device 300 and the second device 400 are connected to the connection circuit 500 through the connection via 510 formed in the second substrate 200, The connection circuit 500 is surrounded by the second insulating layer 210 of the second substrate 200, and an integral portion of the connection circuit 500 is placed in the second substrate 200.

In other words, the cavity C of the first substrate 100 is formed to integrally surround the connection via 510 region and the connection circuit 500 region, and therefore, the second substrate 200 is also formed to integrally cover the connection via 510 region and the connection circuit 500. Area. This can be understood by reading the example diagram in Figure 1B. Although each of the first device 300 and the second device 400 is illustrated in FIG. 1B having one connection via 510, the connection via 510 of each of the first device 300 and the second device 400 may be formed with Multiple.

In the case where the first device 300 is provided in plurality, the second substrate 200 may also be formed in plurality, and thus each of the second substrates 200 may include one connection circuit 500.

For the case of 2, a case in which a single first device 300 and a second device 400 exist will be explained, but the same content will be applied to the case where a plurality of first devices 300 are present.

Although not shown in the drawings, in the case where the connection via 510 connecting the first device 300 and the connection circuit 500 penetrates the first substrate 100, the second substrate 200 is formed to surround the connection circuit 500 but not surround the connection. The vias 510, and thus portions of the connection circuit 500, may be located outside of the second substrate 200 region. Nevertheless, in this case, the connection circuit 500 is also mainly placed in the second substrate 200, and thus the signal loss reduction effect can be partially achieved.

The same applies to the case where the connection via 510 connecting the second device 400 and the connection circuit 500 penetrates the first substrate 100 and the plurality of connection vias 510 in which each of the devices and the connection circuit 500 are connected. At least one of the cases penetrates the first substrate 100.

For the case of 3, it is assumed that the connection circuit 500 is formed in plurality, and this may be, for example, a case in which the first device 300 is formed in plurality or may be explained with reference to FIGS. 1A and 1B. In FIGS. 1A and 1B, two first devices 300 are mounted on a printed circuit board, and there are two connection circuits 500 connecting the first device 300 and the second device 400. Nevertheless, the second substrate 200 is formed to surround only one connection circuit 500. The remaining connection circuits 500 are formed in the first substrate 100.

The connection circuit 500 formed in the plurality of connection circuits 500 to be longer than a predetermined length may be formed in the second substrate 200. The length of the connection circuit 500 can be determined based on the distance between the first device 300 and the second device 400. The longer the length of the connection circuit 500, the higher the loss ratio of the signal transmitted via the connection circuit 500. Therefore, only in the case where the length of the connection circuit 500 is larger than a predetermined length, an attempt can be made to save cost by placing the second substrate on the periphery of the connection circuit 500.

Here, for each user, the "predetermined length" may vary and may be configured by considering the signal loss ratio based on the length of the circuit.

In FIGS. 1A and 1B, one of the two connection circuits 500, 500' (connection circuit 500) is longer than the other of the two connection circuits 500, 500' (connection circuit 500'). This is because one first device 300 is further away from the second device 400 than the other first device 300a. Therefore, the longer connection circuit 500 is included only in the second substrate 200, and the shorter connection circuit 500' is included in the first substrate 100. Of course, the longer connection circuit 500 is formed to be longer than the above-mentioned "predetermined length". Further, the shorter connection circuit 500' is formed to be shorter than "predetermined length". In other words, the second substrate 200 is placed only on the periphery of the connection circuit 500 longer than the predetermined length.

The first substrate 100 may include a first circuit 120. The first circuit 120 may be formed on each of the plurality of first insulating layers 110. The first via holes 130 may be formed, thereby performing interlayer connection between the first circuits 120 formed on the different layers.

The first circuit 120 may not be connected to the connection circuit 500, but may be connected to the connection circuit 500 depending on the circuit design.

Meanwhile, a portion of the first circuit 120' may be exposed through the cavity C, and may contact the second insulating layer 210 when the second substrate 200 is inserted into the cavity C.

The second substrate 200 may include a second circuit 220. The second circuit 220 may be formed on each of the plurality of second insulating layers 210. The second via holes 230 may be formed, thereby performing interlayer connection between the second circuits 220 formed on the different layers. Further, a portion of the second circuit placed at the uppermost portion becomes the pad 220'.

The second circuit 220 may not be connected to the connection circuit 500, but is connected to the connection circuit 500 depending on the visual circuit design. In FIGS. 2 and 3, the second via 230 is shown not to be connected to the connection circuit 500 and thus is shown in dashed lines.

The first circuit 120 and the second circuit 220 may be connected to each other. The first circuit 120 and the second circuit 220 may be connected to each other via a second through hole 230 penetrating the second substrate 200.

The printed circuit board according to an embodiment of the present invention may further include a solder resist layer 600 formed on the upper surface of the first substrate 100 and the upper surface of the second substrate 200. The solder resist layer 600 may extend over the first substrate 100 and the second substrate 200.

Figure 3 illustrates a printed circuit board in accordance with another embodiment of the present invention.

Referring to FIG. 3, the printed circuit board according to another embodiment of the present invention is similar to the embodiment according to the present invention, except that the printed circuit board according to another embodiment of the present invention further includes an adhesive layer A. Printed circuit board.

The adhesive layer A can be sandwiched between the first substrate 100 and the second substrate 200. The adhesive layer A is significantly thinner than the single second insulating layer 210 and thus may not affect the overall thickness of the second substrate 200. Since the dielectric dissipation factor of the adhesive layer A is smaller than the dielectric dissipation factor of the first insulating layer 110, the adhesive layer A may not affect the dielectric loss of the second substrate 200. The dielectric dissipation factor of the adhesive layer A can be similar to the dielectric dissipation factor of the second insulating layer 210.

The first circuit 120' placed in the bottom surface of the cavity C in the first circuit 120 of the first substrate 100 may penetrate the adhesive layer A.

The remaining description of the printed circuit board according to another embodiment of the present invention is the same as that of the printed circuit board according to one embodiment of the present invention, and thus will not be described herein.

4 illustrates a method of fabricating a printed circuit board in accordance with one embodiment of the present invention, and FIG. 5 illustrates a portion of FIG. 4, specifically, the portion labeled (i) of FIG.

In the method of manufacturing a printed circuit board according to an embodiment of the present invention, the first substrate 100 is fabricated by laminating two surfaces of a core, and as the first substrate 100 is successively manufactured, the second substrate 200 was manufactured in succession at the same time.

Specifically, referring to FIG. 4, a portion of the first substrate 100 is fabricated by laminating on both sides between (a) and (h). In particular, a raw material having a metal foil M laminated on both sides of the first insulating layer 110 is used, and the first circuit 120 and the first via 130 are formed using a tenting process. When the first circuit 120 is formed using the capping process, the resist R corresponding to the region of the first circuit 120 may be used. Nevertheless, the first circuit 120 and the first via 130 may be formed using a process other than the capping process.

In the present embodiment, the first substrate 100 of the printed circuit board is composed of a total of nine first insulating layers 110, and the second substrate 200 is composed of two second insulating layers 210, thereby forming 10 layers. The printed circuit board.

After the first substrate 100 (h) is fabricated using the five first insulating layers 110, the second insulating layer 210(i) constituting the second substrate 200 is laminated. Next, a typical first insulating layer 110 is laminated on the lower side of the partially fabricated first substrate 100 by laminating the both sides, but laminated on the upper side of the first substrate 110 has a correspondence with the second insulating layer 210 The first insulating layer 110(j) of the hole. After the first circuit 120, the second circuit 220, and the connection circuit 500(k) are simultaneously formed, the first insulating layer 110 and the second insulating layer 210(1) are laminated again using the same process. Next, if necessary, the first circuit 120, the second circuit 220, the first via 130, and the second via 230 are formed together with the connection via 510 (m). Finally, the solder resist layer 600 is laminated on the first substrate 100 and the second substrate 200, but a portion of the first circuit 120 or the second circuit 220 positioned at the uppermost portion is exposed to become a pad for mounting the device. 220' (m).

FIG. 5 shows a transfer method of laminating the second insulating layer 210 on the partially fabricated first substrate 100. The second insulating layer 210 is temporarily attached to the lower surface of the roll-type transfer paper P which is rolled and moved while the first substrate 100 is formed by the contact portion by, for example, a separation layer, and may be The second insulating layer 210 is laminated on the first substrate 100 by removing the separation layer. The transfer paper P may be made of a bendable material such as PI or polyethylene terephthalate (PET).

For efficiency, printed circuit board fabrication including transfer can be performed in units of strips, and the printed circuit board can be separated by the unit.

6 through 8 illustrate a method of fabricating a printed circuit board in accordance with another embodiment of the present invention.

In the method of manufacturing a printed circuit board according to another embodiment of the present invention, the first substrate 100 and the second substrate 200 are fabricated in a separate process, and then the second substrate 200 is inserted into the cavity C of the first substrate 100. .

FIG. 6 shows a process of fabricating the second substrate 200.

On the raw material having the metal foil M laminated on both sides of the second insulating layer 210, the connection circuit 500, the connection via 510, and the second circuit 220 are formed by, for example, a covering process ((a) to (g)). And a second through hole (not shown). The second insulating layer 210 is laminated again, and if necessary, an adhesive layer A is formed on the lower portion of the second substrate 200. The second substrate 200 fabricated as described above may be temporarily attached to the lower surface of the transfer paper P by a separation layer.

FIG. 7 shows a process of fabricating the first substrate 100.

On the raw material having the metal foil M laminated on both sides of the first insulating layer 110, the first circuit 120 and the first via hole 130 are formed by using a resist R, for example, by a capping process. This process can be repeated until the desired number of layers ((a) to (g)) are reached. This is the same as the method of manufacturing a printed circuit board described with reference to FIG. Thereafter, the cavity C is formed by laminating the first insulating layer 110 formed with holes on the upper portion of the first substrate 100 and laminating a typical first insulating layer 110 not formed with holes on the lower portion of the first substrate 100. (h). If necessary, the first insulating layer 100 not formed with holes may be laminated on both sides of the first substrate 100, and then the cavity C may be machined.

FIG. 8 illustrates a process of inserting the second substrate 200 into the cavity C of the first substrate 100.

The insertion of the second substrate 200 into the cavity C of the first substrate 100 can be achieved by a transfer method. The second substrate 200 temporarily bonded to the lower surface of the transfer paper P by the separation layer is transferred into the cavity C of the first substrate 100. Here, the first substrate 100 and the second substrate 200 may be bonded to each other by the adhesive layer A.

Thereafter, a process of forming the solder resist layer 600 may be added.

Although the present invention includes specific examples, it will be apparent to those skilled in the art that various forms can be made in the examples without departing from the spirit and scope of the scope of the claims. And changes in the details. The examples described herein are to be considered as illustrative only and not as limiting. Descriptions of features or aspects in each instance should be considered as suitable features or aspects in other examples. If the techniques are performed in a different order and/or if components in the system, architecture, apparatus, or circuitry are combined and/or replaced or supplemented with other components or equivalent components thereof, Achieve a suitable result. Therefore, the scope of the invention is not to be limited by the details of the invention, but the scope of the claims and the equivalents thereof in.

1‧‧‧ Terminal

10‧‧‧Printed circuit board

100‧‧‧First substrate

110‧‧‧First insulation

120, 120'‧‧‧ first circuit

130‧‧‧First through hole

200‧‧‧second substrate

210‧‧‧Second insulation

220‧‧‧second circuit

220'‧‧‧ pads

230‧‧‧Second through hole

300, 300a‧‧‧ first device

300', 400'‧‧‧ installation area

400‧‧‧second device

410‧‧‧ third device

500, 500'‧‧‧ connection circuit

510‧‧‧Connecting through hole

600‧‧‧ solder mask

A‧‧‧ adhesive layer

C‧‧‧cavity

M‧‧‧metal foil

P‧‧‧Transfer paper

R‧‧‧Resist

(a), (b), (c), (d), (e), (f), (g), (h), (i), (j), (k), (l), (m) )‧‧‧step

1A and 1B illustrate a terminal in which a printed circuit board according to an embodiment of the present invention is applied. Figure 2 illustrates a printed circuit board in accordance with one embodiment of the present invention. Figure 3 illustrates a printed circuit board in accordance with another embodiment of the present invention. 4 illustrates a method of fabricating a printed circuit board in accordance with one embodiment of the present invention. Figure 5 shows a portion of Figure 4. 6 through 8 illustrate a method of fabricating a printed circuit board in accordance with another embodiment of the present invention.

Claims (20)

A printed circuit board comprising: a first substrate composed of a plurality of first insulating layers and formed with a cavity open upward; and a second substrate composed of a plurality of second insulating layers and placed in the cavity The dielectric dissipation factor of the second insulating layer is smaller than the dielectric dissipation factor of the first insulating layer. The printed circuit board of claim 1, wherein the dielectric loss of the second insulating layer is less than the dielectric loss of the first insulating layer. The printed circuit board of claim 1, further comprising: a first device and a second device mounted on at least one of the first device and the second device; and a connection circuit, The first device and the second device are electrically connected to each other, wherein at least a portion of the connection circuit is formed in the second substrate. The printed circuit board of claim 3, wherein the first device and the second device are connected to the connection circuit through a connection via, and wherein the connection via is formed in the second In the substrate. The printed circuit board of claim 4, wherein the connection circuit is integrally formed in the second substrate. The printed circuit board of claim 3, wherein the first substrate comprises a first circuit, and wherein the first circuit and the connection circuit are electrically disconnected from each other. The printed circuit board of claim 6, wherein the second substrate further comprises a second circuit electrically disconnected from the connection circuit, and wherein the second circuit is connected to the first circuit . The printed circuit board of claim 6, wherein a portion of the first circuit contacts the second insulating layer. The printed circuit board of claim 8, wherein the first device comprises a radio frequency processing portion, and wherein the second device comprises an intermediate frequency processing portion. The printed circuit board of claim 3, wherein the signal transmitted through the connection circuit has a frequency of 10 GHz or higher. The printed circuit board of claim 3, wherein the connection circuit is formed in plurality, and wherein at least one of the plurality of connection circuits is formed in the second substrate. The printed circuit board of claim 11, wherein the first device is formed in plurality, and wherein the plurality of first devices are connected to the second device through respective ones of the connection circuits. The printed circuit board according to claim 11, wherein one or more of the plurality of connection circuits formed to be longer than or equal to a predetermined length are formed in the second substrate. The printed circuit board of claim 13, wherein one or more of the plurality of connection circuits formed to be shorter than a predetermined length are formed in the first substrate. The printed circuit board of claim 1, wherein an upper surface of the first substrate is coplanar with an upper surface of the second substrate. The printed circuit board of claim 1, further comprising: a solder resist layer formed on an upper surface of the first substrate and an upper surface of the second substrate. The printed circuit board of claim 1, wherein the thickness of the first substrate is greater than the thickness of the second substrate. The printed circuit board according to claim 1, wherein an adhesive layer is interposed between the first substrate and the second substrate. The printed circuit board of claim 18, wherein the adhesive layer has a dielectric dissipation factor that is less than a dielectric dissipation factor of the first insulating layer. The printed circuit board of claim 1, wherein the first insulating layer is made of epoxy resin, and wherein the second insulating layer is made of liquid crystal polymer (LCP), polytetrafluoroethylene At least one of (PTFE), polyphenylene ether (PPE), cycloolefin polymer (COP), and perfluoroalkoxy (PFA).