TWI823523B - Circuit board and method for manufacturing the same - Google Patents

Circuit board and method for manufacturing the same Download PDF

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TWI823523B
TWI823523B TW111131048A TW111131048A TWI823523B TW I823523 B TWI823523 B TW I823523B TW 111131048 A TW111131048 A TW 111131048A TW 111131048 A TW111131048 A TW 111131048A TW I823523 B TWI823523 B TW I823523B
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substrate
cavity
layer
circuit
circuit substrate
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TW111131048A
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TW202410761A (en
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廖中興
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先豐通訊股份有限公司
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Abstract

A circuit board includes a third circuit substrate, a second adhesive layer, a second circuit substrate, a first adhesive layer, a first circuit substrate, a third adhesive layer, and a fourth circuit substrate which are stacked in that order. The circuit board defines a first cavity and a second cavity. The first cavity penetrates the third adhesive layer, the first circuit substrate, and the second adhesive layer. The second cavity penetrates the third adhesive layer, the first circuit substrate, the first adhesive layer, the second circuit substrate, and the second adhesive layer. A side wall of the first cavity is covered with a first metal layer, a side wall of the second cavity is covered with a second metal layer. The second circuit substrate includes a first metal pad, the first metal pad is exposed in the first cavity and is spaced apart from the first metal layer by a predetermined distance. The third circuit substrate includes a second metal pad, the second metal pad is exposed in the second cavity and is spaced apart from the second metal layer by a predetermined.

Description

電路板及其製作方法 Circuit board and method of making the same

本申請涉及電路板技術領域,尤其涉及一種具有空氣波導的電路板及其製作方法。 The present application relates to the technical field of circuit boards, and in particular, to a circuit board with an air waveguide and a manufacturing method thereof.

在微波毫米波頻段,隨著頻帶的擁擠,信號傳輸所需要的頻率逐漸升高。如果採用傳統的微帶線和帶狀線,其損耗已經不能忽視,嚴重影響信號的傳輸品質。一種解決方案是使用波導結構,波導結構由於具有很好的遮罩特性,能夠保證以很小的損耗傳輸高功率底色散的微波毫米波信號。現有具有波導結構的電路板,一般僅用於在外層之間傳送電波信號,使用受限。 In the microwave and millimeter wave frequency bands, as the frequency band becomes crowded, the frequency required for signal transmission gradually increases. If traditional microstrip lines and strip lines are used, their losses cannot be ignored and seriously affect the signal transmission quality. One solution is to use a waveguide structure. Due to its good shielding characteristics, the waveguide structure can ensure the transmission of high-power bottom-dispersed microwave and millimeter-wave signals with very little loss. Existing circuit boards with waveguide structures are generally only used to transmit radio wave signals between outer layers, and their use is limited.

有鑑於此,有必要提供一種能夠解決上述技術問題的電路板及其製作方法。 In view of this, it is necessary to provide a circuit board and a manufacturing method thereof that can solve the above technical problems.

本申請第一方面提供一種電路板,包括依次堆疊設置的第三電路基板、第二膠層、第二電路基板、第一膠層、第一電路基板、第三膠層和第四電路基板,所述電路板開設有第一空腔和第二空腔,所述第一空腔貫通所述第三膠層、所述第一電路基板和所述第二膠層,所述第二空腔貫通所述第三膠層、所述第一電路基板、所述第一膠層、所述第二電路基板和所述第二膠層,所述第一空腔的側壁覆蓋有第一金屬層,所述第二空腔的側壁覆蓋有第二金屬層,所述第二電路基板包括第一金屬墊,所述第一金屬墊暴露於所述第一空腔中並 與所述第一金屬層間隔預設距離,所述第三電路基板包括第二金屬墊,所述第二金屬墊暴露於所述第二空腔中並與所述第二金屬層間隔預設距離。 A first aspect of the application provides a circuit board, including a third circuit substrate, a second adhesive layer, a second circuit substrate, a first adhesive layer, a first circuit substrate, a third adhesive layer and a fourth circuit substrate that are stacked in sequence. The circuit board is provided with a first cavity and a second cavity. The first cavity penetrates the third glue layer, the first circuit substrate and the second glue layer. The second cavity Penetrating the third glue layer, the first circuit substrate, the first glue layer, the second circuit substrate and the second glue layer, the side wall of the first cavity is covered with a first metal layer , the side walls of the second cavity are covered with a second metal layer, the second circuit substrate includes a first metal pad, the first metal pad is exposed in the first cavity and Separated from the first metal layer by a preset distance, the third circuit substrate includes a second metal pad, the second metal pad is exposed in the second cavity and is spaced from the second metal layer by a preset distance. distance.

在一些實施例中,所述電路板還包括夾設於所述第四電路基板和所述第一電路基板之間的第一導電膏和第二導電膏,所述第一導電膏環繞所述第一空腔的開口設置並與所述第一金屬層連接,所述第二導電膏環繞所述第二空腔的開口設置並與所述第二金屬層連接。 In some embodiments, the circuit board further includes first conductive paste and second conductive paste sandwiched between the fourth circuit substrate and the first circuit substrate, the first conductive paste surrounding the The opening of the first cavity is disposed and connected to the first metal layer, and the second conductive paste is disposed around the opening of the second cavity and connected to the second metal layer.

在一些實施例中,所述電路板還包括夾設於所述第三電路基板和所述第二電路基板之間的第三導電膏,所述第三導電膏環繞所述第二空腔的開口設置並與所述第二金屬層連接。 In some embodiments, the circuit board further includes a third conductive paste sandwiched between the third circuit substrate and the second circuit substrate, the third conductive paste surrounding the second cavity The opening is provided and connected to the second metal layer.

在一些實施例中,所述電路板還包括第一透氣孔和第二透氣孔,所述第一透氣孔貫通所述第四電路基板並與所述第一空腔連通,所述第二透氣孔貫通所述第四電路基板並與所述第二空腔連通。 In some embodiments, the circuit board further includes a first ventilation hole and a second ventilation hole. The first ventilation hole penetrates the fourth circuit substrate and communicates with the first cavity. The second ventilation hole The hole penetrates the fourth circuit substrate and communicates with the second cavity.

在一些實施例中,所述電路板還包括位於外側的兩個覆蓋層,其中一個覆蓋層覆蓋所述第三電路基板,另一個覆蓋層覆蓋所述第四電路基板。 In some embodiments, the circuit board further includes two covering layers located on the outside, one covering layer covering the third circuit substrate, and the other covering layer covering the fourth circuit substrate.

本申請第二方面提供一種電路板的製作方法,包括以下步驟:依次堆疊並壓合第一基板、第二膠層、第二電路基板、第一膠層和第一電路基板形成中間體,所述第二電路基板包括與所述第一膠層相貼合第一金屬墊,所述第一基板包括與所述第二膠層相貼合的第二金屬墊;形成貫通所述第一電路基板和所述第一膠層並暴露所述第一金屬墊的第一空腔,形成貫通所述第一電路基板、所述第一膠層、所述第二電路基板和所述第二膠層並暴露所述第二金屬墊的第二空腔;對所述第一空腔和所述第二空腔進行電鍍,在所述第一空腔的側壁和底壁分別形成第一金屬層和第三金屬層,在所述第二空腔的側壁和底壁分別形成第二金屬層和第四金屬層;去除所述第三金屬層以露出所述第一金屬墊,去除所述第四金屬層以露出所述第二金屬墊,所述第一金屬墊與所述第一金屬層之間間隔預設距離,所述第二金屬墊與所述第二金屬層之間間隔預設距離; 依次堆疊並壓合所述中間體、第三膠層和第二基板,所述第二基板封蓋所述第一空腔和所述第二空腔的開口;對所述第一基板和所述第二基板進行線路製作得到第三電路基板和第四電路基板。 A second aspect of the present application provides a method for manufacturing a circuit board, which includes the following steps: sequentially stacking and pressing a first substrate, a second adhesive layer, a second circuit substrate, a first adhesive layer and a first circuit substrate to form an intermediate body. The second circuit substrate includes a first metal pad that is bonded to the first adhesive layer, and the first substrate includes a second metal pad that is bonded to the second adhesive layer; forming a penetrating first circuit The substrate and the first glue layer expose the first cavity of the first metal pad, forming a structure that penetrates the first circuit substrate, the first glue layer, the second circuit substrate and the second glue. layer and expose the second cavity of the second metal pad; perform electroplating on the first cavity and the second cavity, and form a first metal layer on the side wall and bottom wall of the first cavity respectively. and a third metal layer. A second metal layer and a fourth metal layer are respectively formed on the side walls and bottom walls of the second cavity; the third metal layer is removed to expose the first metal pad, and the third metal layer is removed. Four metal layers are used to expose the second metal pad. There is a preset distance between the first metal pad and the first metal layer, and a preset distance between the second metal pad and the second metal layer. distance; Stack and press the intermediate body, the third glue layer and the second substrate in sequence, and the second substrate covers the openings of the first cavity and the second cavity; The second substrate is subjected to circuit fabrication to obtain a third circuit substrate and a fourth circuit substrate.

在一些實施例中,在步驟“依次堆疊並壓合所述中間體、第三膠層和第二基板”之前還包括以下步驟:在所述第一電路基板上形成第一導電膏和第二導電膏,所述第一導電膏環繞所述第一空腔的開口設置,所述第二導電膏環繞所述第二空腔的開口設置;在依次堆疊並壓合所述中間體、第三膠層和第二基板之後,所述第一導電膏夾設於所述第一電路基板和所述第二基板之間並與所述第一金屬層連接,所述第二導電膏夾設於所述第一電路基板和所述第二基板之間並與所述第二金屬層連接。 In some embodiments, before the step of "sequentially stacking and pressing the intermediate body, the third adhesive layer and the second substrate", the following steps are also included: forming a first conductive paste and a second conductive paste on the first circuit substrate. Conductive paste, the first conductive paste is placed around the opening of the first cavity, the second conductive paste is placed around the opening of the second cavity; the intermediate body, the third conductive paste are sequentially stacked and pressed After the glue layer and the second substrate, the first conductive paste is sandwiched between the first circuit substrate and the second substrate and connected to the first metal layer, and the second conductive paste is sandwiched between The first circuit substrate and the second substrate are connected to the second metal layer.

在一些實施例中,還包括以下步驟:形成貫通所述第四電路基板的第一透氣孔和第二透氣孔,所述第一透氣孔與所述第一空腔連接,所述第二透氣孔與所述第二空腔連通。 In some embodiments, the method further includes the following steps: forming a first ventilation hole and a second ventilation hole penetrating the fourth circuit substrate, the first ventilation hole being connected to the first cavity, and the second ventilation hole being connected to the first cavity. The hole communicates with the second cavity.

本申請第三方面提供一種電路板的製作方法,包括以下步驟:依次堆疊壓合第二電路基板、第一膠層和第一電路基板形成中間體,所述第二電路基板包括第一金屬墊;形成貫通所述第一電路基板和所述第一膠層並暴露出所述第一金屬墊的第一空腔,形成貫通所述中間體的第二空腔;對所述第一空腔和所述第二空腔進行電鍍,在所述第一空腔的側壁和底壁分別形成第一金屬層和第三金屬層,在所述第二空腔的側壁形成第二金屬層;去除所述第三金屬層以露出所述第一金屬墊,所述第一金屬墊與所述第一金屬層間隔預設距離;依次堆疊並壓合第一基板、第二膠層、所述中間體、第三膠層和第二基板,所述第一基板包括第二金屬墊,所述第二基板封蓋所述第一空腔和所述第二空腔位於同一側的開口,所述第一基板封蓋所述第二空腔另一側的開口並使所述 第二金屬墊暴露於所述第二空腔中,所述第二金屬墊與所述第二金屬層間隔預設距離;對所述第一基板和所述第二基板進行線路製作得到第三電路基板和第四電路基板。 A third aspect of the present application provides a method for manufacturing a circuit board, including the following steps: sequentially stacking and laminating a second circuit substrate, a first adhesive layer and a first circuit substrate to form an intermediate body, the second circuit substrate including a first metal pad ; Form a first cavity that penetrates the first circuit substrate and the first glue layer and exposes the first metal pad, and form a second cavity that penetrates the intermediate body; to the first cavity Perform electroplating with the second cavity to form a first metal layer and a third metal layer on the side walls and bottom walls of the first cavity respectively, and form a second metal layer on the side walls of the second cavity; remove The third metal layer exposes the first metal pad, and the first metal pad is separated from the first metal layer by a preset distance; the first substrate, the second glue layer, and the middle layer are sequentially stacked and pressed together. body, a third glue layer and a second substrate, the first substrate includes a second metal pad, the second substrate covers the opening of the first cavity and the second cavity located on the same side, the The first substrate covers the opening on the other side of the second cavity and allows the The second metal pad is exposed in the second cavity, and the second metal pad is separated from the second metal layer by a preset distance; circuit fabrication is performed on the first substrate and the second substrate to obtain a third circuit substrate and a fourth circuit substrate.

在一些實施例中,在步驟“依次堆疊並壓合第一基板、第二膠層、所述中間體、第三膠層和第二基板”之前,還包括以下步驟:在所述第一電路基板上形成第一導電膏和第二導電膏,所述第一導電膏和所述第二導電膏分別環繞所述第一空腔和所述第二空腔位於一側的開口設置;在第一基板上形成第三導電膏,所述第三導電膏環繞所述第二金屬墊設置並與所述第二金屬墊間隔預設距離;在依次堆疊並壓合第一基板、第二膠層、所述中間體、第三膠層和第二基板之後,所述第一導電膏夾設於所述第一電路基板和所述第二基板之間並與所述第一金屬層連接,所述第二導電膏夾設於所述第一電路基板和所述第二基板之間並與所述第二金屬層連接,所述第三導電膏夾設於所述第二電路基板和所述第一基板之間並與所述第二金屬層連接。 In some embodiments, before the step of "sequentially stacking and pressing the first substrate, the second glue layer, the intermediate, the third glue layer and the second substrate", the following steps are also included: A first conductive paste and a second conductive paste are formed on the substrate, and the first conductive paste and the second conductive paste are respectively arranged around the opening on one side of the first cavity and the second cavity; A third conductive paste is formed on a substrate, and the third conductive paste is arranged around the second metal pad and spaced a preset distance from the second metal pad; the first substrate and the second adhesive layer are sequentially stacked and pressed , after the intermediate, the third glue layer and the second substrate, the first conductive paste is sandwiched between the first circuit substrate and the second substrate and connected to the first metal layer, so The second conductive paste is sandwiched between the first circuit substrate and the second substrate and connected to the second metal layer, and the third conductive paste is sandwiched between the second circuit substrate and the second metal layer. between the first substrate and the second metal layer.

本申請提供的電路板及其製作方法中,藉由在電路板的厚度方向上設計具有不同長度的第一空腔和第二空腔,其中,所述第一空腔構成的空氣波導用於在內層的電路基板和外層的電路基板之間傳送電波信號,可以縮短傳輸路徑以降低損耗,提供了更好的電氣特性,並能夠搭配多層天線發射以具有不同天線特性,且所述第二空腔構成的空氣波導可用於在位於外層的電路基板之間傳送電波信號,提高了設計自由度。 In the circuit board and its manufacturing method provided by this application, first cavities and second cavities with different lengths are designed in the thickness direction of the circuit board, wherein the air waveguide formed by the first cavity is used for Transmitting radio wave signals between the inner circuit substrate and the outer circuit substrate can shorten the transmission path to reduce losses, provide better electrical characteristics, and can be transmitted with multi-layer antennas to have different antenna characteristics, and the second The air waveguide formed by the cavity can be used to transmit electric wave signals between the circuit substrates located on the outer layer, increasing the degree of design freedom.

100、100’:電路板 100, 100’: circuit board

10:第一電路基板 10: First circuit substrate

11:第一基材層 11: First base material layer

12:第一導電線路層 12: First conductive circuit layer

14:第一導電結構 14: First conductive structure

15:第一內層導電線路層 15: First inner conductive circuit layer

20:第二電路基板 20: Second circuit substrate

21:第二基材層 21: Second base material layer

22:第二導電線路層 22: Second conductive circuit layer

24:第二導電結構 24: Second conductive structure

25:第二內層導電線路層 25: Second inner conductive circuit layer

26:第三導電結構 26:Third conductive structure

401:第一基板 401: First substrate

30:第一膠層 30: First glue layer

50:第二膠層 50: Second glue layer

60、60’:中間體 60, 60’: intermediate

41:第三基材層 41: The third base material layer

42:第三導電線路層 42: The third conductive circuit layer

43:第一導體層 43: First conductor layer

61:第一空腔 61: First cavity

62、62’:第二空腔 62, 62’: Second cavity

63、63’:工具孔 63, 63’: Tool hole

221:第一金屬墊 221:First metal pad

421:第二金屬墊 421: Second metal pad

611:第一金屬層 611: First metal layer

612:第三金屬層 612: The third metal layer

621、621’:第二金屬層 621, 621’: Second metal layer

622:第四金屬層 622: The fourth metal layer

613:第一導電膏 613:The first conductive paste

623:第二導電膏 623: Second conductive paste

70:第三膠層 70:Third adhesive layer

801:第二基板 801: Second substrate

81:第四基材層 81: The fourth base material layer

82:第四導電線路層 82: The fourth conductive circuit layer

83:第二導體層 83: Second conductor layer

110:第四導電結構 110: The fourth conductive structure

40:第三電路基板 40:Third circuit substrate

80:第四電路基板 80: Fourth circuit substrate

90:覆蓋層 90: Covering layer

624:第三導電膏 624:Third conductive paste

91:第一透氣孔 91: First ventilation hole

92:第二透氣孔 92: Second ventilation hole

圖1為本申請第一實施方式提供的第一電路基板的截面示意圖。 FIG. 1 is a schematic cross-sectional view of the first circuit substrate provided by the first embodiment of the present application.

圖2為本申請第一實施方式提供的第二電路基板的截面示意圖。 FIG. 2 is a schematic cross-sectional view of the second circuit substrate provided by the first embodiment of the present application.

圖3為本申請第一實施例提供的第一基板、第二膠層、第二電路基板、第一膠層和第一電路基板依次堆疊的截面示意圖。 FIG. 3 is a schematic cross-sectional view of the first substrate, the second adhesive layer, the second circuit substrate, the first adhesive layer and the first circuit substrate provided in the first embodiment of the present application.

圖4為將圖3所示第一基板、第二膠層、第二電路基板、第一膠層和第一電路基壓合在一起形成的中間體的截面示意圖。 FIG. 4 is a schematic cross-sectional view of an intermediate body formed by laminating the first substrate, the second adhesive layer, the second circuit substrate, the first adhesive layer and the first circuit base shown in FIG. 3 together.

圖5為在圖4所示中間體上形成第一空腔和第二空腔後的截面示意圖。 FIG. 5 is a schematic cross-sectional view after forming the first cavity and the second cavity on the intermediate body shown in FIG. 4 .

圖6為將圖5所示中間體、第三膠層和第二基板依次堆疊的截面示意圖。 Figure 6 is a schematic cross-sectional view of the intermediate body, the third adhesive layer and the second substrate shown in Figure 5 being stacked in sequence.

圖7為將圖6所示中間體、第三膠層和第二基板壓合在一起後的截面示意圖。 Figure 7 is a schematic cross-sectional view of the intermediate body, the third adhesive layer and the second substrate shown in Figure 6 after they are pressed together.

圖8為本申請第一實施例提供的電路板的截面示意圖。 Figure 8 is a schematic cross-sectional view of a circuit board provided by the first embodiment of the present application.

圖9為本申請第二實施例提供的第二電路基板、第一膠層和第一電路基板依次堆疊的截面示意圖。 FIG. 9 is a schematic cross-sectional view of a second circuit substrate, a first adhesive layer and a first circuit substrate stacked in sequence according to the second embodiment of the present application.

圖10為將圖9所示第二電路基板、第一膠層和第一電路基板壓合在一起形成的中間體的截面示意圖。 FIG. 10 is a schematic cross-sectional view of an intermediate body formed by laminating the second circuit substrate, the first adhesive layer and the first circuit substrate shown in FIG. 9 together.

圖11為在圖10所示中間體上形成第一空腔和第二空腔後的截面示意圖。 FIG. 11 is a schematic cross-sectional view after forming the first cavity and the second cavity on the intermediate body shown in FIG. 10 .

圖12為在圖11所示第一空腔和第二空腔的側壁上分別形成第一金屬層和第三金屬層後的截面示意圖。 FIG. 12 is a schematic cross-sectional view after forming a first metal layer and a third metal layer on the side walls of the first cavity and the second cavity shown in FIG. 11 respectively.

圖13為在圖12所示第一空腔中形成第一金屬墊後的截面示意圖。 FIG. 13 is a schematic cross-sectional view after forming the first metal pad in the first cavity shown in FIG. 12 .

圖14為將本申請第二實施例提供的第一基板、第二膠層、中間體、第三膠層和第二基板依次堆疊的截面示意圖。 Figure 14 is a schematic cross-sectional view of the first substrate, the second glue layer, the intermediate, the third glue layer and the second substrate provided in the second embodiment of the present application.

圖15為本申請第二實施例提供的電路板的截面示意圖。 Figure 15 is a schematic cross-sectional view of a circuit board provided by the second embodiment of the present application.

下面將對本發明實施方式中的技術方案進行清楚、完整地描述,顯然,所描述的實施方式僅僅是本發明一部分實施方式,而不是全部的實施方 式。基於本發明中的實施方式,本領域普通技術人員在沒有付出創造性勞動前提下所獲得的所有其他實施方式,都屬於本發明保護的範圍。 The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Mode. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

需要說明的是,除非另有定義,本文所使用的所有的技術和科學術語與屬於本發明的技術領域的技術人員通常理解的含義相同。在本發明實施方式中使用的術語是僅僅出於描述特定實施方式的目的,而非旨在限制本發明。 It should be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the technical field belonging to the present invention. The terminology used in the embodiments of the present invention is for the purpose of describing particular embodiments only and is not intended to limit the present invention.

請參閱圖1至圖8,本申請第一實施例提供一種電路板100的製作方法,其包括以下步驟: Referring to Figures 1 to 8, a first embodiment of the present application provides a method of manufacturing a circuit board 100, which includes the following steps:

步驟S1,請參閱圖1,提供第一電路基板10,所述第一電路基板10包括第一基材層11以及設置於所述第一基材層11上的第一導電線路層12。所述第一導電線路層12位於所述第一電路基板10的外側。所述第一導電線路層12的數量可以為一個或兩個。本實施例中,所述第一導電線路層12的數量為兩個,兩個第一導電線路層12均位於所述第一電路基板10的外側並相對設置,所述第一基材層11電性隔離所述兩個第一導電線路層12,所述兩個第一導電線路層12藉由貫通所述第一基材層11的第一導電結構14電連接。 Step S1, please refer to FIG. 1 to provide a first circuit substrate 10. The first circuit substrate 10 includes a first base material layer 11 and a first conductive circuit layer 12 disposed on the first base material layer 11. The first conductive circuit layer 12 is located outside the first circuit substrate 10 . The number of the first conductive circuit layers 12 may be one or two. In this embodiment, the number of the first conductive circuit layers 12 is two. The two first conductive circuit layers 12 are located outside the first circuit substrate 10 and arranged oppositely. The first base material layer 11 The two first conductive circuit layers 12 are electrically isolated, and the two first conductive circuit layers 12 are electrically connected through the first conductive structure 14 penetrating the first base material layer 11 .

所述第一電路基板10可以為單層基板或多層基板,例如第一導電線路層12貼合於第一基材層11的至少一表面構成單層基板。本申請中的“貼合”指的是相互接觸且無間隙配合。本實施例中,所述第一電路基板10為多層基板,第一電路基板10包括複數第一基材層11以及複數第一內層導電線路層15,每個第一內層導電線路層15貼合於相應的第一基材層11的表面,相鄰的兩個第一基材層11之間設置有膠層16以將相鄰的兩個第一基材層11粘接在一起,所述兩個第一導電線路層12貼合於位於外側的兩個第一基材層11上,所述第一導電結構14貫通所述複數第一基材層11和所述膠層16並電連接所述兩個第一導電線路層12和所述複數第一內層導電線路層15。 The first circuit substrate 10 may be a single-layer substrate or a multi-layer substrate. For example, the first conductive circuit layer 12 is bonded to at least one surface of the first base material layer 11 to form a single-layer substrate. "Fit" in this application means contacting each other and fitting without clearance. In this embodiment, the first circuit substrate 10 is a multi-layer substrate. The first circuit substrate 10 includes a plurality of first base material layers 11 and a plurality of first inner conductive circuit layers 15. Each first inner conductive circuit layer 15 Adhering to the surface of the corresponding first base material layer 11, an adhesive layer 16 is provided between two adjacent first base material layers 11 to bond the two adjacent first base material layers 11 together. The two first conductive circuit layers 12 are attached to the two first base material layers 11 located on the outside, and the first conductive structure 14 penetrates the plurality of first base material layers 11 and the adhesive layer 16. The two first conductive circuit layers 12 and the plurality of first inner conductive circuit layers 15 are electrically connected.

所述第一基材層11的材質可為但不限於玻璃纖維環氧樹脂(FR-4)、聚萘二甲酸乙二醇酯(PEN),聚醯亞胺(PI)、聚乙烯對苯二甲酸乙二醇酯(PET)、 聚乙烯(PE)或聚碳酸酯(PC)中的一種或多種。本實施例中,所述第一基材層11的材質為FR-4。 The material of the first base material layer 11 can be, but is not limited to, fiberglass epoxy resin (FR-4), polyethylene naphthalate (PEN), polyimide (PI), polyethylene terephthalate. Ethylene glycol diformate (PET), One or more of polyethylene (PE) or polycarbonate (PC). In this embodiment, the material of the first base material layer 11 is FR-4.

所述膠層16的材質可為半固化片或樹脂,樹脂包括酚醛樹脂、聚氯乙烯樹脂、聚酯樹脂、環氧樹脂,聚氨酯、聚乙烯基酯、聚氟樹脂、聚氟碳樹脂、聚雙馬來醯亞胺樹脂、聚馬來西亞胺三嗪樹脂、聚醯亞胺樹脂、聚氰酸酯樹脂或環氧基聚苯醚。本實施例中,所述膠層16的材質為樹脂。 The material of the adhesive layer 16 can be prepreg or resin. The resin includes phenolic resin, polyvinyl chloride resin, polyester resin, epoxy resin, polyurethane, polyvinyl ester, polyfluorocarbon resin, polyfluorocarbon resin, and polysulfide resin. Leimide resin, polymethyleneamine triazine resin, polyimide resin, polycyanate resin or epoxy polyphenylene ether. In this embodiment, the glue layer 16 is made of resin.

所述第一導電結構14可以為導電柱或導電孔。本實施例中,所述第一導電結構14為藉由電鍍形成的導電孔,導電孔中可填充有樹脂。 The first conductive structure 14 may be a conductive pillar or a conductive hole. In this embodiment, the first conductive structure 14 is a conductive hole formed by electroplating, and the conductive hole may be filled with resin.

在一些實施例中,第一電路基板10採用本領域常用電路板製作方法製得。例如,對一個覆銅板進行壓膜、曝光、顯影、線路蝕刻形成第一電路基板10;或者,分別對複數覆銅板進行壓膜、曝光、顯影、線路蝕刻,然後將經過線路蝕刻的複數覆銅板與膠層16進行壓合形成第一電路基板10。所述壓膜、曝光、顯影、線路蝕刻、壓合等步驟為本領域常用技術手段,在此不再贅述。 In some embodiments, the first circuit substrate 10 is manufactured using a circuit board manufacturing method commonly used in the art. For example, lamination, exposure, development, and circuit etching are performed on one copper-clad laminate to form the first circuit substrate 10; or lamination, exposure, development, and circuit etching are performed on a plurality of copper-clad laminates, and then the plurality of copper-clad laminates that have undergone circuit etching are It is pressed with the adhesive layer 16 to form the first circuit substrate 10 . The lamination, exposure, development, circuit etching, lamination and other steps are commonly used technical means in this field and will not be described in detail here.

步驟S2,請參閱圖2,提供第二電路基板20,所述第二電路基板20包括第二基材層21以及設置於所述第二基材層21上的第二導電線路層22。所述第二導電線路層22位於所述第二電路基板20的外側並包括第一金屬墊221。所述第一金屬墊221用於形成共振。所述第二導電線路層22的數量可以為一個或兩個。本實施例中,所述第二導電線路層22的數量為兩個,兩個第二導電線路層22均位於所述第二電路基板20的外側並相對設置,所述第二基材層21電性隔離所述兩個第二導電線路層22,所述兩個第二導電線路層22藉由貫通所述第二基材層21的第二導電結構24電連接。 Step S2, please refer to FIG. 2 to provide a second circuit substrate 20. The second circuit substrate 20 includes a second base material layer 21 and a second conductive circuit layer 22 disposed on the second base material layer 21. The second conductive circuit layer 22 is located outside the second circuit substrate 20 and includes a first metal pad 221 . The first metal pad 221 is used to form resonance. The number of the second conductive circuit layers 22 may be one or two. In this embodiment, the number of the second conductive circuit layers 22 is two. The two second conductive circuit layers 22 are located outside the second circuit substrate 20 and arranged oppositely. The second base material layer 21 The two second conductive circuit layers 22 are electrically isolated, and the two second conductive circuit layers 22 are electrically connected through the second conductive structure 24 penetrating the second base material layer 21 .

所述第二電路基板20可以為單層基板或多層基板,例如第二導電線路層22貼合於第二基材層21的至少一表面構成單層基板。本申請中的“貼合”指的是相互接觸且無間隙配合。本實施例中,所述第二電路基板20為多層基板,第二電路基板20包括複數第二基材層21以及複數第二內層導電線路層25,每個第二內層導電線路層25貼合於相應的第二基材層21的表面,相鄰的兩個第二 基材層21之間設置有膠層16以將相鄰的兩個第二基材層21粘接在一起,所述兩個第二導電線路層22貼合於位於外側的兩個第二基材層21上,所述第二導電結構24貫通所述複數第二基材層21和所述膠層16並電連接所述兩個第二導電線路層22和所述複數第二內層導電線路層25。 The second circuit substrate 20 may be a single-layer substrate or a multi-layer substrate. For example, the second conductive circuit layer 22 is bonded to at least one surface of the second base material layer 21 to form a single-layer substrate. "Fit" in this application means contacting each other and fitting without clearance. In this embodiment, the second circuit substrate 20 is a multi-layer substrate. The second circuit substrate 20 includes a plurality of second base material layers 21 and a plurality of second inner conductive circuit layers 25. Each second inner conductive circuit layer 25 Adhering to the surface of the corresponding second base material layer 21, two adjacent second An adhesive layer 16 is provided between the base material layers 21 to bond the two adjacent second base material layers 21 together. The two second conductive circuit layers 22 are attached to the two second base material layers 22 located outside. On the material layer 21, the second conductive structure 24 penetrates the second base material layer 21 and the adhesive layer 16 and electrically connects the two second conductive circuit layers 22 and the plurality of second inner conductive layers. Line layer 25.

在一些實施例中,所述第二電路基板20還包括第三導電結構26,所述第三導電結構26貫通所述第二基材層21和所述膠層16並電連接一個第二導電線路層22和一個第二內層導電線路層25。 In some embodiments, the second circuit substrate 20 further includes a third conductive structure 26 that penetrates the second base material layer 21 and the adhesive layer 16 and is electrically connected to a second conductive structure 26 . Circuit layer 22 and a second inner conductive circuit layer 25.

所述第二基材層21的材質選用具有低介電常數及低介電損耗的材料,例如可為但不限於液晶聚合物(LCP)、聚四氟乙烯(PTFE)、聚醚醚酮(PEEK)、聚苯醚(PPO)中的一種或多種。 The material of the second base material layer 21 is selected from materials with low dielectric constant and low dielectric loss, such as but not limited to liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), polyetheretherketone ( One or more of PEEK) and polyphenylene ether (PPO).

所述第二導電結構24可以為導電柱或導電孔。本實施例中,所述第二導電結構24為藉由電鍍形成的導電孔,導電孔中可填充有樹脂。 The second conductive structure 24 may be a conductive pillar or a conductive hole. In this embodiment, the second conductive structure 24 is a conductive hole formed by electroplating, and the conductive hole may be filled with resin.

步驟S3,請參閱圖3和圖4,提供第一基板401、第一膠層30和第二膠層50,依次堆疊並壓合所述第一基板401、所述第二膠層50、所述第二電路基板20、所述第一膠層30和所述第一電路基板10,得到中間體60。 Step S3, please refer to Figures 3 and 4. A first substrate 401, a first glue layer 30 and a second glue layer 50 are provided, and the first substrate 401, the second glue layer 50, and the above are sequentially stacked and pressed. The second circuit substrate 20 , the first adhesive layer 30 and the first circuit substrate 10 are combined to obtain an intermediate 60 .

所述第一基板401包括第三基材層41和設置於所述第三基材層41相對兩表面的第三導電線路層42和第一導體層43。所述第三導電線路層42與所述第二膠層50相貼合,所述第一導體層43位於所述中間體60的外側。所述第三導電線路層42包括第二金屬墊421。所述第二金屬墊421用於形成共振。 The first substrate 401 includes a third base material layer 41 and a third conductive circuit layer 42 and a first conductor layer 43 disposed on opposite surfaces of the third base material layer 41 . The third conductive circuit layer 42 is attached to the second adhesive layer 50 , and the first conductor layer 43 is located outside the intermediate body 60 . The third conductive circuit layer 42 includes a second metal pad 421 . The second metal pad 421 is used to form resonance.

所述第一膠層30的材質可為半固化片或樹脂,樹脂包括酚醛樹脂、聚氯乙烯樹脂、聚酯樹脂、環氧樹脂,聚氨酯、聚乙烯基酯、聚氟樹脂、聚氟碳樹脂、聚雙馬來醯亞胺樹脂、聚馬來西亞胺三嗪樹脂、聚醯亞胺樹脂、聚氰酸酯樹脂或環氧基聚苯醚。本實施例中,所述第一膠層30的材質為樹脂。 The material of the first adhesive layer 30 can be prepreg or resin, and the resin includes phenolic resin, polyvinyl chloride resin, polyester resin, epoxy resin, polyurethane, polyvinyl ester, polyfluorocarbon resin, polyfluorocarbon resin, polyfluorocarbon resin, Bismaleimide resin, polymaleimide resin, polyimide resin, polycyanurate resin or epoxy polyphenylene ether. In this embodiment, the first glue layer 30 is made of resin.

所述第三基材層41和所述第二膠層50的材質均可選用具有低介電常數及低介電損耗的材料,例如可為但不限於LCP、PTFE、PEEK、PPO中的一種或多種。 The third base material layer 41 and the second adhesive layer 50 can be made of materials with low dielectric constant and low dielectric loss, such as but not limited to one of LCP, PTFE, PEEK, and PPO. or more.

壓合後,所述第一電路基板10的一個第一導電線路層12和所述第一導體層43位於所述中間體60的外側,所述第三導電線路層42與所述第二膠層50相貼合,所述第二電路基板20的一個第二導電線路層22與所述第一膠層30相貼合。 After lamination, a first conductive circuit layer 12 and the first conductor layer 43 of the first circuit substrate 10 are located outside the intermediate body 60, and the third conductive circuit layer 42 and the second glue are The layers 50 are bonded together, and a second conductive circuit layer 22 of the second circuit substrate 20 is bonded with the first adhesive layer 30 .

步驟S4,請參閱圖4和圖5,形成貫通所述第一電路基板10和所述第一膠層30並暴露出所述第一金屬墊221的第一空腔61,形成貫通所述第一電路基板10、所述第一膠層30、所述第二電路基板20和所述第二膠層50並暴露出所述第二金屬墊421的第二空腔62,形成貫通所述中間體60的工具孔63。 Step S4, please refer to FIG. 4 and FIG. 5 to form a first cavity 61 penetrating the first circuit substrate 10 and the first adhesive layer 30 and exposing the first metal pad 221. A circuit substrate 10, the first adhesive layer 30, the second circuit substrate 20 and the second adhesive layer 50 expose the second cavity 62 of the second metal pad 421, forming a connection through the middle The tool hole 63 of the body 60.

所述第一空腔61、所述第二空腔62和所述工具孔63均可藉由機械鑽孔或鐳射燒蝕的方式形成。本實施例中,所述第一空腔61和所述第二空腔62均藉由帶有深度控制的機械鑽孔機進行鑽孔形成。 The first cavity 61 , the second cavity 62 and the tool hole 63 can be formed by mechanical drilling or laser ablation. In this embodiment, the first cavity 61 and the second cavity 62 are drilled by a mechanical drilling machine with depth control.

步驟S5,請參閱圖5,對所述第一空腔61和所述第二空腔62進行電鍍,在所述第一空腔61的側壁和底壁分別形成第一金屬層611和第三金屬層612,在所述第二空腔62的側壁和底壁分別形成第二金屬層621和第四金屬層622。 Step S5, please refer to Figure 5. The first cavity 61 and the second cavity 62 are electroplated, and a first metal layer 611 and a third metal layer are formed on the side walls and bottom walls of the first cavity 61 respectively. Metal layer 612, a second metal layer 621 and a fourth metal layer 622 are respectively formed on the side walls and bottom walls of the second cavity 62.

所述第一金屬層611覆蓋所述第一空腔61的整個側壁,並與所述第一導電線路層12和所述第二導電線路層22連接。所述第三金屬層612覆蓋所述第一金屬墊221並與所述第一金屬層611連接。所述第二金屬層621覆蓋所述第二空腔62的整個側壁,並與所述第一導電線路層12和所述第三導電線路層42連接。所述第四金屬層622覆蓋所述第二金屬墊421並與所述第二金屬層621連接。 The first metal layer 611 covers the entire side wall of the first cavity 61 and is connected to the first conductive circuit layer 12 and the second conductive circuit layer 22 . The third metal layer 612 covers the first metal pad 221 and is connected to the first metal layer 611 . The second metal layer 621 covers the entire side wall of the second cavity 62 and is connected to the first conductive circuit layer 12 and the third conductive circuit layer 42 . The fourth metal layer 622 covers the second metal pad 421 and is connected to the second metal layer 621 .

步驟S6,請參閱圖5和圖6,去除所述第三金屬層612以露出所述第一金屬墊221,去除所述第四金屬層622以露出所述第二金屬墊421,所述第一金屬墊221與所述第一金屬層611之間間隔預設距離,所述第二金屬墊421與所述第二金屬層621之間間隔預設距離。 Step S6, please refer to Figures 5 and 6. The third metal layer 612 is removed to expose the first metal pad 221, and the fourth metal layer 622 is removed to expose the second metal pad 421. A metal pad 221 is spaced a preset distance from the first metal layer 611 , and a preset distance is spaced between the second metal pad 421 and the second metal layer 621 .

在一些實施例中,利用具有深度控制的機械鑽孔機,去除所述第三金屬層612和所述第四金屬層622。藉由深度控制,可保證在形成所述第一金屬墊221和所述第二金屬墊421的過程中不會對所述第一金屬層611、所述第一金屬墊221、所述第二金屬層621和所述第二金屬墊421造成損傷。 In some embodiments, the third metal layer 612 and the fourth metal layer 622 are removed using a mechanical drill with depth control. Through depth control, it can be ensured that the first metal layer 611 , the first metal pad 221 , and the second metal pad 421 will not be damaged during the formation of the first metal pad 221 and the second metal pad 421 . The metal layer 621 and the second metal pad 421 cause damage.

步驟S7,請參閱圖6和圖7,在所述第一導電線路層12上形成第一導電膏613和第二導電膏623,所述第一導電膏613環繞所述第一空腔61的開口設置,所述第二導電膏623環繞所述第二空腔62的開口設置;依次堆疊並壓合所述中間體60、第三膠層70和第二基板801。所述第二基板801覆蓋所述第三膠層70、所述第一導電膏613和所述第二導電膏623,並封蓋所述第一空腔61和所述第二空腔62的開口。 Step S7, please refer to FIGS. 6 and 7 , forming a first conductive paste 613 and a second conductive paste 623 on the first conductive circuit layer 12 , and the first conductive paste 613 surrounds the first cavity 61 The second conductive paste 623 is arranged around the opening of the second cavity 62; the intermediate body 60, the third glue layer 70 and the second substrate 801 are sequentially stacked and pressed. The second substrate 801 covers the third glue layer 70 , the first conductive paste 613 and the second conductive paste 623 , and seals the first cavity 61 and the second cavity 62 Open your mouth.

所述第一導電膏613和所述第二導電膏623的材質可以為金屬膏,例如為銅膏。所述第一導電膏613和所述第二導電膏623可以採用印刷方式形成。在其他實施例中,所述第一導電膏613還可以形成在所述第二基板801上。 The first conductive paste 613 and the second conductive paste 623 may be made of metal paste, such as copper paste. The first conductive paste 613 and the second conductive paste 623 can be formed by printing. In other embodiments, the first conductive paste 613 may also be formed on the second substrate 801 .

所述第二基板801包括第四基材層81和設置於所述第四基材層81相對的兩個表面上的第四導電線路層82和第二導體層83。所述第四基材層81的材質可選用具有低介電常數及低介電損耗的材料,例如可為但不限於LCP、PTFE、PEEK、PPO中的一種或多種。 The second substrate 801 includes a fourth base material layer 81 and a fourth conductive circuit layer 82 and a second conductor layer 83 disposed on two opposite surfaces of the fourth base material layer 81 . The fourth base material layer 81 can be made of a material with low dielectric constant and low dielectric loss, such as but not limited to one or more of LCP, PTFE, PEEK, and PPO.

所述第三膠層70覆蓋所述第一導電線路層12並與所述第四導電線路層82相貼合,用於粘接所述第二基板801和所述中間體60。所述第三膠層70的材質可為半固化片或樹脂,樹脂包括酚醛樹脂、聚氯乙烯樹脂、聚酯樹脂、環氧樹脂,聚氨酯、聚乙烯基酯、聚氟樹脂、聚氟碳樹脂、聚雙馬來醯亞胺樹脂、聚馬來西亞胺三嗪樹脂、聚醯亞胺樹脂、聚氰酸酯樹脂或環氧基聚苯醚。本實施例中,所述第三膠層70的材質為樹脂。 The third adhesive layer 70 covers the first conductive circuit layer 12 and is attached to the fourth conductive circuit layer 82 for bonding the second substrate 801 and the intermediate body 60 . The material of the third adhesive layer 70 can be prepreg or resin. The resin includes phenolic resin, polyvinyl chloride resin, polyester resin, epoxy resin, polyurethane, polyvinyl ester, polyfluorocarbon resin, polyfluorocarbon resin, polyfluorocarbon resin, etc. Bismaleimide resin, polymaleimide resin, polyimide resin, polycyanurate resin or epoxy polyphenylene ether. In this embodiment, the third glue layer 70 is made of resin.

所述第一導電膏613與所述第四導電線路層82和所述第一導電線路層12相貼合,以阻擋所述第三膠層70在壓合時流入所述第一空腔61中。所 述第二導電膏623與所述第四導電線路層82和所述第一導電線路層12相貼合,以阻擋所述第三膠層70在壓合時流入所述第二空腔62中。 The first conductive paste 613 is bonded to the fourth conductive circuit layer 82 and the first conductive circuit layer 12 to prevent the third adhesive layer 70 from flowing into the first cavity 61 during lamination. middle. Place The second conductive paste 623 is attached to the fourth conductive circuit layer 82 and the first conductive circuit layer 12 to prevent the third adhesive layer 70 from flowing into the second cavity 62 during lamination. .

步驟S8,請參閱圖7,形成複數第四導電結構110,用於電連接所述第二基板801和所述第一電路基板10、電連接所述第二導體層83和所述第四導電線路層82、電連接所述第一導體層43和所述第三導電線路層42。所述第四導電結構110可以為導電孔或導電柱。本實施例中,所述第四導電結構110為導電孔,其藉由鑽孔、電鍍形成。 Step S8, please refer to FIG. 7 to form a plurality of fourth conductive structures 110 for electrically connecting the second substrate 801 and the first circuit substrate 10, and electrically connecting the second conductive layer 83 and the fourth conductive structure. The circuit layer 82 electrically connects the first conductor layer 43 and the third conductive circuit layer 42 . The fourth conductive structure 110 may be a conductive hole or a conductive pillar. In this embodiment, the fourth conductive structure 110 is a conductive hole, which is formed by drilling and electroplating.

步驟S9,請參閱圖8,對所述第一導體層43和所述第二導體層83分別進行線路製作形成第三導電線路層42和第四導電線路層82,得到所述電路板100。 In step S9, please refer to FIG. 8. Circuit fabrication is performed on the first conductor layer 43 and the second conductor layer 83 to form a third conductive circuit layer 42 and a fourth conductive circuit layer 82, respectively, to obtain the circuit board 100.

所述第三基材層41和設置於所述第三基材層41相對兩側的兩個第三導電線路層42構成第三電路基板40。所述第四基材層81和設置於所述第四基材層81相對兩側的兩個第四導電線路層82構成第四電路基板80。 The third base material layer 41 and the two third conductive circuit layers 42 disposed on opposite sides of the third base material layer 41 constitute a third circuit substrate 40 . The fourth base material layer 81 and the two fourth conductive circuit layers 82 disposed on opposite sides of the fourth base material layer 81 constitute a fourth circuit substrate 80 .

在一些實施例,所述電路板100的製作方法還包括以下步驟: In some embodiments, the manufacturing method of the circuit board 100 further includes the following steps:

步驟S10,請參閱圖8,在所述電路板100的外側形成兩個覆蓋層(CVL)90。所述兩個覆蓋層90分別覆蓋所述第三導電線路層42和所述第四導電線路層82,用於保護導電線路。 In step S10 , please refer to FIG. 8 , two covering layers (CVL) 90 are formed on the outside of the circuit board 100 . The two covering layers 90 respectively cover the third conductive circuit layer 42 and the fourth conductive circuit layer 82 to protect the conductive circuits.

步驟S11,請參閱圖8,形成貫通所述第四電路基板80和其上的覆蓋層90的第一透氣孔91和第二透氣孔92。所述第一透氣孔91連通外界環境和所述第一空腔61,所述第二透氣孔92連通外界環境和所述第二空腔62,用於在後端組裝電路板100時避免產生爆板。 Step S11 , please refer to FIG. 8 , forming first ventilation holes 91 and second ventilation holes 92 penetrating the fourth circuit substrate 80 and the covering layer 90 thereon. The first ventilation hole 91 communicates with the external environment and the first cavity 61 , and the second ventilation hole 92 communicates with the external environment and the second cavity 62 , and is used to avoid the occurrence of noise when assembling the circuit board 100 at the rear end. Exploding board.

所述第一空腔61和所述第二空腔62中容納空氣介質構成空氣波導,所述電路板100能夠以所述第一空腔61和所述第二空腔62內的空氣作為傳導介質來傳遞電波信號。本申請中,藉由在所述電路板100的厚度方向上設計具有不同長度的第一空腔61和第二空腔62,其中所述第一空腔61構成的空氣波導用於在內層的電路基板和外層的電路基板之間傳送電波信號,可以縮短傳輸路 徑以降低損耗,提供了更好的電氣特性,並能夠搭配多層天線發射以具有不同天線特性,且所述第二空腔62構成的空氣波導可用於在位於外層的電路基板之間傳送電波信號,提高了設計自由度。 The first cavity 61 and the second cavity 62 contain air medium to form an air waveguide, and the circuit board 100 can use the air in the first cavity 61 and the second cavity 62 as conduction. medium to transmit radio signals. In this application, the first cavity 61 and the second cavity 62 with different lengths are designed in the thickness direction of the circuit board 100, wherein the air waveguide formed by the first cavity 61 is used in the inner layer. The electric wave signal is transmitted between the circuit substrate and the outer circuit substrate, which can shorten the transmission path. path to reduce loss, provide better electrical characteristics, and can be used with multi-layer antenna transmission to have different antenna characteristics, and the air waveguide formed by the second cavity 62 can be used to transmit radio wave signals between circuit substrates located on the outer layer. , improving the design freedom.

所述第二導電線路層22、所述第一金屬層611、所述第一導電線路層12、所述第一導電膏613和所述第四導電線路層82電連接,能夠對所述第一空腔61中的電波信號進行阻擋,提供電磁遮罩效果。所述第三導電線路層42、所述第二金屬層621、所述第二導電膏623和所述第四導電線路層82電連接,能夠對所述第二空腔62中的電波信號進行阻擋,提供電磁遮罩效果。 The second conductive circuit layer 22, the first metal layer 611, the first conductive circuit layer 12, the first conductive paste 613 and the fourth conductive circuit layer 82 are electrically connected to the third conductive circuit layer 82. The radio wave signal in a cavity 61 is blocked to provide an electromagnetic shielding effect. The third conductive circuit layer 42 , the second metal layer 621 , the second conductive paste 623 and the fourth conductive circuit layer 82 are electrically connected to enable the radio wave signal in the second cavity 62 to be processed. Block, providing electromagnetic masking effect.

請參閱圖9至圖15,本申請第二實施例提供一種電路板100’的製作方法,其包括以下步驟: Referring to Figures 9 to 15, a second embodiment of the present application provides a method of manufacturing a circuit board 100', which includes the following steps:

步驟S1,請參閱圖9和圖10,依次堆疊壓合所述第二電路基板20、所述第一膠層30和所述第一電路基板10,形成中間體60’。 Step S1, please refer to Figures 9 and 10. The second circuit substrate 20, the first adhesive layer 30 and the first circuit substrate 10 are sequentially stacked and pressed to form an intermediate body 60'.

步驟S2,請參閱圖10和圖11,形成貫通所述第一電路基板10和所述第一膠層30並暴露出部分所述第一金屬墊221的第一空腔61,形成貫通所述中間體60’的第二空腔62’和工具孔63’。所述第二空腔62’和所述工具孔63’均貫通所述第一電路基板10、所述第一膠層30和所述第二電路基板20。 Step S2, please refer to Figures 10 and 11 to form a first cavity 61 penetrating the first circuit substrate 10 and the first adhesive layer 30 and exposing part of the first metal pad 221, forming a Second cavity 62' and tool hole 63' of intermediate body 60'. The second cavity 62' and the tool hole 63' both penetrate the first circuit substrate 10, the first adhesive layer 30 and the second circuit substrate 20.

步驟S3,請參閱圖12,對所述第一空腔61和所述第二空腔62’進行電鍍,在所述第一空腔61的側壁和底壁分別形成所述第一金屬層611和所述第三金屬層612,在所述第二空腔62’的側壁形成所述第二金屬層621’。所述第二金屬層621’覆蓋所述第二空腔62’的整個側壁,並與所述第一導電線路層12和所述第三導電線路層42連接。 Step S3, please refer to Figure 12, perform electroplating on the first cavity 61 and the second cavity 62', and form the first metal layer 611 on the side walls and bottom walls of the first cavity 61 respectively. and the third metal layer 612, and the second metal layer 621' is formed on the side wall of the second cavity 62'. The second metal layer 621′ covers the entire sidewall of the second cavity 62′ and is connected to the first conductive circuit layer 12 and the third conductive circuit layer 42.

步驟S4,請參閱圖12和圖13,去除所述第三金屬層612以露出所述第一金屬墊221。 Step S4, please refer to FIG. 12 and FIG. 13 , the third metal layer 612 is removed to expose the first metal pad 221 .

步驟S5,請參閱圖14和圖15,在所述第一基板401上形成第三導電膏624,在所述第一導電線路層12上形成所述第一導電膏613和所述第二導電膏623;依次堆疊並壓合所述第一基板401、所述第二膠層50、所述中間體 60’、所述第三膠層70和所述第二基板801。所述第三導電膏624形成於所述第三導電線路層42上並環繞所述第二金屬墊421設置,且與所述第二金屬墊421間隔預設距離。 Step S5, please refer to Figures 14 and 15. A third conductive paste 624 is formed on the first substrate 401, and the first conductive paste 613 and the second conductive paste are formed on the first conductive circuit layer 12. Paste 623; stack and press the first substrate 401, the second glue layer 50, and the intermediate in sequence 60’, the third glue layer 70 and the second substrate 801. The third conductive paste 624 is formed on the third conductive circuit layer 42 and is disposed around the second metal pad 421 and spaced apart from the second metal pad 421 by a predetermined distance.

壓合後,所述第二基板801封蓋所述第一空腔61和所述第二空腔62’位於同一側的開口,所述第一基板401封蓋所述第二空腔62’另一側的開口並使所述第二金屬墊421暴露於所述第二空腔62’中,所述第二膠層50夾設於所述第二電路基板20和所述第一基板401之間,所述第三導電膏624與所述第二電路基板20相貼合以阻擋所述第二膠層50流入所述第二空腔62’中,且所述第三導電膏624環繞所述第二空腔62’的開口設置並與所述第二金屬層621連接。 After pressing, the second substrate 801 covers the openings of the first cavity 61 and the second cavity 62' located on the same side, and the first substrate 401 covers the second cavity 62'. The opening on the other side exposes the second metal pad 421 to the second cavity 62 ′, and the second adhesive layer 50 is sandwiched between the second circuit substrate 20 and the first substrate 401 During this time, the third conductive paste 624 is attached to the second circuit substrate 20 to prevent the second adhesive layer 50 from flowing into the second cavity 62 ′, and the third conductive paste 624 surrounds the second cavity 62 ′. The opening of the second cavity 62' is disposed and connected to the second metal layer 621.

步驟S5,請參閱圖15,形成所述複數第四導電結構110,對所述第一導體層43和所述第二導體層83分別進行線路製作形成所述第三導電線路層42和所述第四導電線路層82,形成位於外側的所述兩個覆蓋層90,形成貫通所述第四電路基板80和其上的覆蓋層90的所述第一透氣孔91和所述第二透氣孔92,得到所述電路板100’。 Step S5, please refer to FIG. 15 to form the plurality of fourth conductive structures 110, and perform circuit fabrication on the first conductor layer 43 and the second conductor layer 83 to form the third conductive circuit layer 42 and the second conductor layer 83. The fourth conductive circuit layer 82 forms the two outer covering layers 90 and forms the first ventilation holes 91 and the second ventilation holes penetrating the fourth circuit substrate 80 and the covering layer 90 thereon. 92. Obtain the circuit board 100'.

另外,本領域技術人員還可在本發明精神內做其它變化,當然,這些依據本發明精神所做的變化,都應包含在本發明所要求保護的範圍內。 In addition, those skilled in the art can also make other changes within the spirit of the present invention. Of course, these changes made based on the spirit of the present invention should be included in the scope of protection claimed by the present invention.

100:電路板 100:Circuit board

10:第一電路基板 10: First circuit substrate

11:第一基材層 11: First base material layer

12:第一導電線路層 12: First conductive circuit layer

20:第二電路基板 20: Second circuit substrate

21:第二基材層 21: Second base material layer

22:第二導電線路層 22: Second conductive circuit layer

30:第一膠層 30: First glue layer

50:第二膠層 50: Second glue layer

41:第三基材層 41: The third base material layer

42:第三導電線路層 42: The third conductive circuit layer

61:第一空腔 61: First cavity

62:第二空腔 62:Second cavity

221:第一金屬墊 221:First metal pad

421:第二金屬墊 421: Second metal pad

611:第一金屬層 611: First metal layer

621:第二金屬層 621: Second metal layer

613:第一導電膏 613:The first conductive paste

623:第二導電膏 623: Second conductive paste

70:第三膠層 70:Third adhesive layer

81:第四基材層 81: The fourth base material layer

82:第四導電線路層 82: The fourth conductive circuit layer

110:第四導電結構 110: The fourth conductive structure

40:第三電路基板 40:Third circuit substrate

80:第四電路基板 80: Fourth circuit substrate

90:覆蓋層 90: Covering layer

91:第一透氣孔 91: First ventilation hole

92:第二透氣孔 92: Second ventilation hole

Claims (9)

一種電路板,其中,包括依次堆疊設置的第三電路基板、第二膠層、第二電路基板、第一膠層、第一電路基板、第三膠層和第四電路基板,所述電路板開設有第一空腔和第二空腔,所述第一空腔貫通所述第三膠層、所述第一電路基板和所述第二膠層,所述第二空腔貫通所述第三膠層、所述第一電路基板、所述第一膠層、所述第二電路基板和所述第二膠層,所述第一空腔的側壁覆蓋有第一金屬層,所述第二空腔的側壁覆蓋有第二金屬層,所述第二電路基板包括第一金屬墊,所述第一金屬墊暴露於所述第一空腔中並與所述第一金屬層間隔預設距離,所述第三電路基板包括第二金屬墊,所述第二金屬墊暴露於所述第二空腔中並與所述第二金屬層間隔預設距離;所述電路板還包括夾設於所述第四電路基板和所述第一電路基板之間的第一導電膏和第二導電膏,所述第一導電膏環繞所述第一空腔的開口設置並與所述第一金屬層連接,所述第二導電膏環繞所述第二空腔的開口設置並與所述第二金屬層連接。 A circuit board, which includes a third circuit substrate, a second glue layer, a second circuit substrate, a first glue layer, a first circuit substrate, a third glue layer and a fourth circuit substrate that are stacked in sequence, the circuit board A first cavity and a second cavity are provided. The first cavity penetrates the third glue layer, the first circuit substrate and the second glue layer. The second cavity penetrates the third glue layer. Three adhesive layers, the first circuit substrate, the first adhesive layer, the second circuit substrate and the second adhesive layer, the side wall of the first cavity is covered with a first metal layer, the third The side walls of the two cavities are covered with a second metal layer, the second circuit substrate includes a first metal pad, the first metal pad is exposed in the first cavity and is spaced a predetermined distance from the first metal layer. distance, the third circuit substrate includes a second metal pad, the second metal pad is exposed in the second cavity and is separated from the second metal layer by a preset distance; the circuit board also includes an intervening first conductive paste and second conductive paste between the fourth circuit substrate and the first circuit substrate, the first conductive paste is disposed around the opening of the first cavity and in contact with the first metal The second conductive paste is arranged around the opening of the second cavity and connected to the second metal layer. 如請求項1所述的電路板,其中,所述電路板還包括夾設於所述第三電路基板和所述第二電路基板之間的第三導電膏,所述第三導電膏環繞所述第二空腔的開口設置並與所述第二金屬層連接。 The circuit board of claim 1, wherein the circuit board further includes a third conductive paste sandwiched between the third circuit substrate and the second circuit substrate, the third conductive paste surrounding The opening of the second cavity is disposed and connected to the second metal layer. 如請求項1所述的電路板,其中,所述電路板還包括第一透氣孔和第二透氣孔,所述第一透氣孔貫通所述第四電路基板並與所述第一空腔連通,所述第二透氣孔貫通所述第四電路基板並與所述第二空腔連通。 The circuit board according to claim 1, wherein the circuit board further includes a first ventilation hole and a second ventilation hole, the first ventilation hole penetrating the fourth circuit substrate and communicating with the first cavity , the second ventilation hole penetrates the fourth circuit substrate and communicates with the second cavity. 如請求項1所述的電路板,其中,所述電路板還包括位於外側的兩個覆蓋層,其中一個覆蓋層覆蓋所述第三電路基板,另一個覆蓋層覆蓋所述第四電路基板。 The circuit board according to claim 1, wherein the circuit board further includes two covering layers located on the outside, one covering layer covers the third circuit substrate, and the other covering layer covers the fourth circuit substrate. 一種電路板的製作方法,其中,包括以下步驟:依次堆疊並壓合第一基板、第二膠層、第二電路基板、第一膠層和第一電路基板形成中間體,所述第二電路基板包括與所述第一膠層相貼合第一金屬墊,所述第一基板包括與所述第二膠層相貼合的第二金屬墊; 形成貫通所述第一電路基板和所述第一膠層並暴露所述第一金屬墊的第一空腔,形成貫通所述第一電路基板、所述第一膠層、所述第二電路基板和所述第二膠層並暴露所述第二金屬墊的第二空腔;對所述第一空腔和所述第二空腔進行電鍍,在所述第一空腔的側壁和底壁分別形成第一金屬層和第三金屬層,在所述第二空腔的側壁和底壁分別形成第二金屬層和第四金屬層;去除所述第三金屬層以露出所述第一金屬墊,去除所述第四金屬層以露出所述第二金屬墊,所述第一金屬墊與所述第一金屬層之間間隔預設距離,所述第二金屬墊與所述第二金屬層之間間隔預設距離;依次堆疊並壓合所述中間體、第三膠層和第二基板,所述第二基板封蓋所述第一空腔和所述第二空腔的開口;對所述第一基板和所述第二基板進行線路製作得到第三電路基板和第四電路基板。 A method for manufacturing a circuit board, which includes the following steps: sequentially stacking and pressing a first substrate, a second adhesive layer, a second circuit substrate, a first adhesive layer and a first circuit substrate to form an intermediate body, the second circuit The substrate includes a first metal pad that is bonded to the first glue layer, and the first substrate includes a second metal pad that is bonded to the second glue layer; Form a first cavity that penetrates the first circuit substrate and the first glue layer and exposes the first metal pad, and forms a first cavity that penetrates the first circuit substrate, the first glue layer, and the second circuit The substrate and the second glue layer are exposed to the second cavity of the second metal pad; the first cavity and the second cavity are electroplated, and the side walls and bottom of the first cavity are The walls respectively form a first metal layer and a third metal layer, and the side walls and bottom walls of the second cavity form a second metal layer and a fourth metal layer respectively; the third metal layer is removed to expose the first Metal pad, the fourth metal layer is removed to expose the second metal pad, the first metal pad is separated from the first metal layer by a preset distance, and the second metal pad is separated from the second metal pad. The metal layers are separated by a preset distance; the intermediate body, the third glue layer and the second substrate are sequentially stacked and pressed, and the second substrate covers the openings of the first cavity and the second cavity. ; Perform circuit fabrication on the first substrate and the second substrate to obtain a third circuit substrate and a fourth circuit substrate. 如請求項5所述的電路板的製作方法,其中,在步驟“依次堆疊並壓合所述中間體、第三膠層和第二基板”之前還包括以下步驟:在所述第一電路基板上形成第一導電膏和第二導電膏,所述第一導電膏環繞所述第一空腔的開口設置,所述第二導電膏環繞所述第二空腔的開口設置;在依次堆疊並壓合所述中間體、第三膠層和第二基板之後,所述第一導電膏夾設於所述第一電路基板和所述第二基板之間並與所述第一金屬層連接,所述第二導電膏夾設於所述第一電路基板和所述第二基板之間並與所述第二金屬層連接。 The manufacturing method of a circuit board as described in claim 5, wherein before the step of "sequentially stacking and pressing the intermediate, the third adhesive layer and the second substrate", the following steps are also included: A first conductive paste and a second conductive paste are formed on the top, the first conductive paste is arranged around the opening of the first cavity, and the second conductive paste is arranged around the opening of the second cavity; after being stacked in sequence and After pressing the intermediate body, the third adhesive layer and the second substrate, the first conductive paste is sandwiched between the first circuit substrate and the second substrate and connected to the first metal layer, The second conductive paste is sandwiched between the first circuit substrate and the second substrate and connected to the second metal layer. 如請求項5所述的電路板的製作方法,其中,還包括以下步驟:形成貫通所述第四電路基板的第一透氣孔和第二透氣孔,所述第一透氣孔與所述第一空腔連接,所述第二透氣孔與所述第二空腔連通。 The manufacturing method of a circuit board according to claim 5, further comprising the following steps: forming a first ventilation hole and a second ventilation hole penetrating the fourth circuit substrate, the first ventilation hole being in contact with the first ventilation hole. The cavities are connected, and the second ventilation hole is connected with the second cavity. 一種電路板的製作方法,其中,包括以下步驟: 依次堆疊壓合第二電路基板、第一膠層和第一電路基板形成中間體,所述第二電路基板包括第一金屬墊;形成貫通所述第一電路基板和所述第一膠層並暴露出所述第一金屬墊的第一空腔,形成貫通所述中間體的第二空腔;對所述第一空腔和所述第二空腔進行電鍍,在所述第一空腔的側壁和底壁分別形成第一金屬層和第三金屬層,在所述第二空腔的側壁形成第二金屬層;去除所述第三金屬層以露出所述第一金屬墊,所述第一金屬墊與所述第一金屬層間隔預設距離;依次堆疊並壓合第一基板、第二膠層、所述中間體、第三膠層和第二基板,所述第一基板包括第二金屬墊,所述第二基板封蓋所述第一空腔和所述第二空腔位於同一側的開口,所述第一基板封蓋所述第二空腔另一側的開口並使所述第二金屬墊暴露於所述第二空腔中,所述第二金屬墊與所述第二金屬層間隔預設距離;對所述第一基板和所述第二基板進行線路製作得到第三電路基板和第四電路基板。 A method of manufacturing a circuit board, which includes the following steps: A second circuit substrate, a first adhesive layer and a first circuit substrate are sequentially stacked and pressed to form an intermediate body. The second circuit substrate includes a first metal pad; The first cavity of the first metal pad is exposed to form a second cavity penetrating the intermediate body; the first cavity and the second cavity are electroplated, and the first cavity is A first metal layer and a third metal layer are formed on the side walls and bottom walls of the second cavity respectively, and a second metal layer is formed on the side wall of the second cavity; the third metal layer is removed to expose the first metal pad, and the The first metal pad is separated from the first metal layer by a preset distance; the first substrate, the second glue layer, the intermediate body, the third glue layer and the second substrate are sequentially stacked and pressed, and the first substrate includes The second metal pad, the second substrate covers the opening on the same side of the first cavity and the second cavity, the first substrate covers the opening on the other side of the second cavity and The second metal pad is exposed to the second cavity, and the second metal pad is separated from the second metal layer by a preset distance; performing circuit production on the first substrate and the second substrate A third circuit board and a fourth circuit board were obtained. 如請求項8所述的電路板的製作方法,其中,在步驟“依次堆疊並壓合第一基板、第二膠層、所述中間體、第三膠層和第二基板”之前,還包括以下步驟:在所述第一電路基板上形成第一導電膏和第二導電膏,所述第一導電膏和所述第二導電膏分別環繞所述第一空腔和所述第二空腔位於一側的開口設置;在第一基板上形成第三導電膏,所述第三導電膏環繞所述第二金屬墊設置並與所述第二金屬墊間隔預設距離;在依次堆疊並壓合第一基板、第二膠層、所述中間體、第三膠層和第二基板之後,所述第一導電膏夾設於所述第一電路基板和所述第二基板之間並與所述第一金屬層連接,所述第二導電膏夾設於所述第一電路基板和所述第二基板之間並與所述第二金屬層連接,所述第三導電膏夾設於所述第二電路基板和所述第一基板之間並與所述第二金屬層連接。 The manufacturing method of a circuit board as described in claim 8, wherein before the step of "sequentially stacking and pressing the first substrate, the second adhesive layer, the intermediate, the third adhesive layer and the second substrate", it also includes The following steps: forming a first conductive paste and a second conductive paste on the first circuit substrate, the first conductive paste and the second conductive paste surrounding the first cavity and the second cavity respectively. An opening is located on one side; a third conductive paste is formed on the first substrate, and the third conductive paste is arranged around the second metal pad and spaced a preset distance from the second metal pad; and is stacked and pressed in sequence. After the first substrate, the second adhesive layer, the intermediate, the third adhesive layer and the second substrate are combined, the first conductive paste is sandwiched between the first circuit substrate and the second substrate and connected with The first metal layer is connected, the second conductive paste is sandwiched between the first circuit substrate and the second substrate and connected to the second metal layer, and the third conductive paste is sandwiched between The second circuit substrate is connected to the first substrate and to the second metal layer.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201044939A (en) * 2009-06-02 2010-12-16 Sony Chem & Inf Device Corp Method for manufacturing multilayer printed wiring board
US20140190733A1 (en) * 2011-12-31 2014-07-10 Peking University Founder Group Co., Ltd. Printed circuit board and fabricating method thereof
US20220095462A1 (en) * 2020-09-18 2022-03-24 Advanced Semiconductor Engineering, Inc. Package substrate and method for manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201044939A (en) * 2009-06-02 2010-12-16 Sony Chem & Inf Device Corp Method for manufacturing multilayer printed wiring board
US20140190733A1 (en) * 2011-12-31 2014-07-10 Peking University Founder Group Co., Ltd. Printed circuit board and fabricating method thereof
US20220095462A1 (en) * 2020-09-18 2022-03-24 Advanced Semiconductor Engineering, Inc. Package substrate and method for manufacturing the same

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