KR20220150855A - Printed circuit board - Google Patents

Abstract

A printed circuit board according to one aspect of the present invention comprises: a first substrate which is made of a plurality of first insulating layers, and has a cavity upwardly opened; and a second substrate which is made of a plurality of second insulating layers, and is located in the cavity. A dielectric loss tangent of the second insulating layer is smaller than a dielectric loss tangent of the first insulating layer.

Description

Printed circuit board {PRINTED CIRCUIT BOARD}

The present invention relates to a printed circuit board.

Countries, including Korea and Japan, are concentrating their efforts on technology development for commercialization of 5G worldwide. For smooth signal transmission in the frequency band of 10 GHz or higher in the 5G era, it may be difficult to respond with existing materials and structures. Accordingly, new materials and structures are being developed for transmitting the received high-frequency signal to the main board without loss.

Patent Publication No. 10-2011-0002112 (published: 2011.01.06)

An object of the present invention is to provide a printed circuit board in which signal loss is reduced.

According to one aspect of the present invention, a first substrate made of a plurality of first insulating layers and having a cavity opened upward; and a second substrate comprising a plurality of second insulating layers and positioned within the cavity, wherein a dielectric loss tangent of the second insulating layer is smaller than that of the first insulating layer.

1A and 1B are diagrams illustrating a terminal to which a printed circuit board according to an embodiment of the present invention is applied.
2 is a view showing a printed circuit board according to an embodiment of the present invention.
3 is a view showing a printed circuit board according to another embodiment of the present invention.
4 is a view showing a method for manufacturing a printed circuit board according to an embodiment of the present invention.
Figure 5 is a view showing a part of Figure 4;
6 to 8 are diagrams illustrating a method of manufacturing a printed circuit board according to another embodiment of the present invention.

Embodiments of the printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings. to omit

In addition, terms such as first and second used below are only identification symbols for distinguishing the same or corresponding components, and the same or corresponding components are not limited by terms such as first and second. not.

In addition, coupling does not mean only the case of direct physical contact between each component in the contact relationship between each component, but another configuration intervenes between each component so that the component is in the other configuration. It should be used as a concept that encompasses even the case of contact with each other.

1A and 1B are diagrams illustrating a terminal 1 to which a printed circuit board according to an embodiment of the present invention is applied.

Referring to FIGS. 1A and 1B , a printed circuit board 10 is embedded in the electronic device terminal 1 . Here, the printed circuit board 10 may be a main board. The printed circuit board 10 includes a first substrate 100 and a second substrate 200, and dielectric loss of the second substrate 200 is smaller than dielectric loss of the first substrate 100. In particular, the dielectric loss tangent of the second insulating layer 210 forming the second substrate 200 is smaller than the dielectric loss tangent of the first insulating layer 110 forming the first substrate 100 .

The first substrate 100 occupies most of the main board, the printed circuit board 10 , and the second substrate 200 is formed only in a predetermined area of the printed circuit board 10 . In particular, the first element 300, the second element 400, the third element 410, etc. may be mounted on the printed circuit board 10, the first element 300 being an RF processing unit, and the second element 400 may be an IF processing unit. The second substrate 200 may be formed around a connection circuit 500 connecting the first element 300 and the second element 400 .

1A shows a first element 300 and a second element 400 mounted on a printed circuit board 10, and FIG. 1B shows a first element 300 and a second element 400 mounted on a printed circuit board ( 10), the mounting area 300' of the first element 300 and the mounting area 400' of the second element 400 are shown before being mounted.

Referring to FIG. 1B , the second substrate 200 is formed around a connection circuit 500 connecting the first element 300 and the second element 400 . A high-frequency signal of 10 GHz or higher may flow through the connection circuit 500 connecting the first element 300 and the second element 400 . Therefore, by disposing an insulating layer with a small dielectric loss tangent around the connection circuit 500 through which a high frequency signal flows, signal loss can be reduced, and cost reduction can be achieved by minimizing the use of an insulating layer with a small dielectric loss tangent. .

Meanwhile, although the connection circuit 500 is shown to be exposed to the outside for convenience in FIGS. 1A and 1B, the connection circuit 500 may be buried inside the second substrate 200 and not exposed to the outside.

Hereinafter, a printed circuit board according to an embodiment of the present invention will be described in detail with reference to FIGS. 1A to 3 .

2 is a diagram showing a printed circuit board according to an embodiment of the present invention.

Referring to FIG. 2 , a printed circuit board according to an embodiment of the present invention includes a first substrate 100 and a second substrate 200 . Here, the dielectric loss of the second substrate 200 is smaller than that of the first substrate 100 . Dielectric loss refers to power loss that occurs when an alternating electric field is formed in a dielectric.

The first substrate 100 is made of a plurality of first insulating layers 110 and has a cavity C that is open upward. That is, the cavity C passes through two or more uppermost layers of the plurality of first insulating layers 110 .

The second substrate 200 is inserted into the cavity C of the first substrate 100 . The second substrate 200 includes a plurality of second insulating layers 210 .

The first insulating layer 110 and the second insulating layer 210 are formed of various resins such as thermosetting resins and thermoplastic resins, and may be specifically epoxy resin or polyimide. Here, the epoxy resin is, for example, naphthalene type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, novolac type epoxy resin, cresol novolac type epoxy resin, rubber modified type epoxy resin, cyclic alipha It may be a tick-based epoxy resin, a silicone-based epoxy resin, a nitrogen-based epoxy resin, a phosphorus-based epoxy resin, and the like, but is not limited thereto.

The first insulating layer 110 and the second insulating layer 210 may include a fiber reinforcing material such as glass cloth in the resin or may be filled with an inorganic filler. As an example of the former, there is a prepreg (PPG), and as an example of the latter, there is a build up film such as ABF (Ajinomoto Build-up Film).

A dielectric dissipation factor (Df) of the second insulating layer 210 is smaller than that of the first insulating layer 110 . The dielectric loss tangent is the ratio of dielectric loss, and dielectric loss tangent and dielectric loss are proportional.

The resin of the second insulating layer 210 may have the same main material as the resin of the first insulating layer 110 . For example, the first insulating layer 110 and the second insulating layer 210 may be PPG, ABF, or PI. However, the second insulating layer 210 may have a dielectric loss tangent of about 0.003, which may be implemented by adjusting the type and content of materials (fillers, etc.) contained in PPG, ABF, and PI.

The second insulating layer 210 may be made of a completely different material from the first insulating layer 110, and in particular, the second insulating layer 210 has a dielectric loss tangent of 0.002 to 0.0001 LCP (Liquid Crystal Polymer) ), PTFE (Polytetrafluoroethylene), PPE (Polyphenylene Ether), COP (Cyclo Olefin Polymer), and PFA (Perfluoroalkoxy).

Meanwhile, the permittivity and dielectric constant (Dk) of the second insulating layer 210 are smaller than those of the first insulating layer 110 .

The first insulating layer 110 constituting the first substrate 100 is formed in plurality, and considering the number of layers of the second substrate 200 inserted into the first substrate 100, the first insulating layer 110 may consist of at least three layers. For example, when the printed circuit board is a main board embedded in a smart phone, the first substrate 100 may be composed of 11 first insulating layers 110 and have 12 layers based on circuit layers.

The second substrate 200 is a substrate inserted into the cavity C of the first substrate 100 . The second insulating layer 210 constituting the second substrate 200 is also formed in plurality. As described above, the position of the second substrate 200 (ie, the position of the cavity C of the first substrate 100) may be determined according to the position of the connection circuit 500. That is, the second substrate 200 is formed around the connection circuit 500 . Also, the location of the connection circuit 500 may be determined according to the locations of the first element 300 and the second element 400 and the connection via 510 . A detailed description of this will be described later.

The thickness of the second substrate 200 may be smaller than that of the first substrate 100 . The thickness of the second substrate 200 may be substantially the same as the thickness of the cavity C of the first substrate 100 . Also, the number of first insulating layers 110 through which the cavity C passes is equal to the number of second insulating layers 210 constituting the second substrate 200 . That is, the cavity C may pass through the N number of first insulating layers 110 , and the number of second insulating layers 210 constituting the second substrate 200 may also include N number. Here, each of the first insulating layer 110 and the second insulating layer 210 may have substantially the same thickness. Accordingly, the upper surface of the first substrate 100 and the upper surface of the second substrate 200 may be substantially positioned on the same plane.

The first element 300, the second element 400, the third element 410, and the like are mounted on the printed circuit board.

The first element 300 may include an antenna and process a high frequency signal such as RF. For example, the first element 300 may be an RF processor. The RF processing unit removes noise, amplifies the amplitude, and down-converts the signal received from the antenna, and transmits the signal to the second element 400 . Conversely, the signal received from the second element 400 may be amplified and transmitted to the antenna. The RF processing unit may be composed of an antenna, amp, mixer, filter, and the like. The number of first elements 300 may be plural. In the terminal 1 of FIG. 1, the first element is composed of two (300, 300a).

The second element 400 is connected to the first element 300 and processes an intermediate frequency. The second element 400 may be an IF processor. The second element 400 may transmit and receive signals to and from the first element 300, and signals exchanged between the first element 300 and the second element 400 may have a frequency of 10 GHz or higher, for example It may be a high frequency of about 11.2 GHz. Meanwhile, a signal received by the second element 400 from the first element 300 is an analog signal, whereas a signal processed by the second element 400 and transmitted to the third element 410 is a digital signal.

Even if the first element 300 is formed in plurality, the second element 400 may be formed as one. In the terminal 1 of FIG. 1 , the first element 300 is composed of two, but the second element 400 is composed of one. However, the present invention does not exclude the case where the second element 400 is formed in plurality.

The third element 410 is connected to the second element 400, and the third element 410 processes a low frequency base band signal.

The first element 300 is mounted on the first substrate 100 or the second substrate 200 . The second element 400 is also mounted on the first substrate 100 or the second substrate 200 . The first element 300 and the second element 400 may be mounted over the first substrate 100 and the second substrate 200 . That is, the first element 300 and the second element 400 may be mounted on at least one of the first substrate 100 and the second substrate 200 . Meanwhile, the third element 410 is mounted on the first substrate 100, and if the signal loss rate is not high in a circuit connected to the third element 410 that processes low frequencies, the first element 410 is independent of the second substrate 200. It may be mounted on the board 100 . The device may be mounted on a pad 220' formed on an insulating layer located on the uppermost layer of the first substrate 100 or the second substrate 200 through an adhesive such as a solder ball.

The first element 300 and the second element 400 are electrically connected through a connection circuit 500 . As described above, the signal transmitted through the connection circuit 500 may have a frequency of 10 GHz or higher.

When a plurality of first elements 300 are formed, each connection circuit 500 is required to connect each first element 300 to one second element 400, so the connection circuit 500 may be formed in plurality. Meanwhile, the number of connection circuits 500 connecting one first element 300 and one second element 400 may be plural. When there are a plurality of connection circuits 500 in this way, the connection circuits 500 may be formed on the same layer or different layers of the second substrate 200 so as not to overlap each other.

In addition, the first element 300 and the second element 400 are connected through the connection circuit 500 and the connection via 510 . The connection via 510 may be formed through the first substrate 100 or the second substrate 200 . The number of connection vias 510 connecting each element and the connection circuit 500 may be plural.

At least a part of the connection circuit 500 is formed in the second substrate 200 . The second insulating layer 210 is formed to surround at least a portion of the connection circuit 500 . For example, at least a portion of the connection circuit 500 may be positioned between the two second insulating layers 210 .

Here, 'part' may mean a predetermined area in one connection circuit 500 or one (or several) selected connection circuits 500 among a plurality of connection circuits 500 . Also, it may mean both the former and the latter.

That is, 'at least a part of the connection circuit 500 is formed in the second substrate 200' means that one connection circuit 500 connecting the first element 300 and the second element 400. It may mean that a part or all of it is formed within the second substrate 200 .

Alternatively, 'at least a part of the connection circuit 500 is formed in the second substrate 200' means that a plurality of connection circuits 500 are formed, and one or more connection circuits 500 selected from among the plurality of connection circuits 500 are formed. ) may mean that it is formed in the second substrate 200 .

Alternatively, it may encompass both of the above meanings.

Meanwhile, a portion of the connection circuit 500 that is not formed within the second substrate 200 or a portion that is not formed within the second substrate 200 among the plurality of connection circuits 500 is located within the first substrate 100 .

Hereinafter, ① when the entire area of one connection circuit 500 is formed in the second substrate 200, ② when only a part of one connection circuit 500 is formed in the second substrate 200, ③ a plurality of A case in which selected several of the connection circuits 500 are formed in the second substrate 200 will be separately described. However, the present invention is not limited only to this case.

In the case of ①, the case in which the connection circuit 500 is singular will be described first. That is, a case in which both the first element 300 and the second element 400 are formed one by one will be described first. However, the description may be equally applied even when the number of first elements 300 is plural.

The first element 300 and the second element 400 are mounted on the printed circuit board, and the first element 300 and the second element 400 are formed in the 'second substrate 200' Connection via 510 When connected to the connection circuit 500 through, the connection circuit 500 is surrounded by the second insulating layer 210 of the second substrate 200, and the entire area of the connection circuit 500 is covered by the second substrate 200. located within

In other words, the cavity C of the first substrate 100 is formed to include both the connection via 510 area and the connection circuit 500 area, and accordingly, the second substrate 200 also has a connection via ( 510) area and the connection circuit 500 area. This can be understood as shown in FIG. 1B. However, although one connection via 510 is shown in each of the first element 300 and the second element 400 in FIG. 1B, each connection via of the first element 300 and the second element 400 ( 510) may be formed in plurality.

If there are a plurality of first elements 300, a plurality of second substrates 200 may also be formed, so that one second substrate 200 may include one connection circuit 500.

In the case of ②, a case in which the first element 300 and the second element 400 are formed one by one will be described first, but the case where the first element 300 is plural is also the same.

Although not shown in the drawing, when the connection via 510 connecting the first element 300 and the connection circuit 500 passes through the 'first substrate 100', the second substrate 200 is connected to the connection circuit 500, but not formed around the connection via 510, some areas of the connection circuit 500 may deviate from the area of the second substrate 200. However, even in this case, since most of the area of the connection circuit 500 is located within the second substrate 200, the effect of reducing signal loss may be partially exhibited.

The same applies to the case where the connection via 510 connecting the second element 400 and the connection circuit 500 passes through the first substrate 100, and a plurality of connection vias connecting each element and the connection circuit 500. The same applies to the case where at least one of 510 passes through the first substrate 100 .

In the case of ③, it is assumed that a plurality of connection circuits 500 are formed, and this may be, for example, a case in which a plurality of first elements 300 are formed, and will be described with reference to FIGS. can do. 1A and 1B, two first elements 300 are mounted on a printed circuit board, and there are also two connection circuits 500 connecting each first element 300 and the second element 400. However, the second substrate 200 is formed only around one connection circuit 500 . The remaining connection circuits 500 are formed in the first substrate 100 .

Among the plurality of connection circuits 500 , only the connection circuit 500 having a predetermined length or more may be formed in the second substrate 200 . The length of the connection circuit 500 may be determined according to the distance between the first element 300 and the second element 400 . As the length of the connection circuit 500 increases, the loss rate of the signal transmitted through the connection circuit 500 increases. ), cost reduction can be achieved.

Here, the 'predetermined length' may be changed according to the user and may be set in consideration of the signal loss rate according to the circuit length.

1A and 1B, the length of one connection circuit 500 among the two connection circuits 500 and 500' is longer than the length of the other connection circuit 500'. This is because one first element 300 is further away from the second element 400 than the other one 300a. Accordingly, only the long connection circuit 500 is included in the second substrate 200 , and the short connection circuit 500 ′ is included in the first substrate 100 . Of course, the long connection circuit 500 is formed beyond the 'predetermined length' described above. In addition, the short connecting circuit 500' is formed with less than a 'predetermined length'. In other words, the length of the second substrate 200 is located only in the periphery of the connection circuit 500 longer than a predetermined length.

The first substrate 100 may include a first circuit 120 . The first circuit 120 may be formed on each layer of the plurality of first insulating layers 110 . A first via 130 may be formed between the first circuits 120 formed on different layers to make a connection between layers.

The first circuit 120 may not be connected to the connection circuit 500, but the first circuit 120 may be connected to the connection circuit 500 according to circuit design.

Meanwhile, a portion of the first circuit 120' is exposed through the cavity C, and when the second substrate 200 is inserted into the cavity C, it may come into contact with the second insulating layer 210.

The second substrate 200 may include the second circuit 220 . The second circuit 220 may be formed on each layer of the plurality of second insulating layers 210 . A second via 230 may be formed between the second circuits 220 formed on different layers to make a connection between layers. In addition, a part of the second circuit positioned at the top becomes a pad 220'.

The second circuit 220 may not be connected to the connection circuit 500, but the second circuit 220 may be connected to the connection circuit 500 according to circuit design. In FIGS. 2 and 3 , the second via 230 is not connected to the connection circuit 500 and is indicated by a dotted line.

The first circuit 120 and the second circuit 220 may be connected to each other. The first circuit 120 and the second circuit 220 may be connected through a second via 230 penetrating the second substrate 200 .

On the other hand, the printed circuit board according to an embodiment of the present invention may further include a solder resist layer 600, the solder resist layer 600 is a top surface of the first substrate 100 and the second substrate 200 formed on the upper surface. The solder resist layer 600 may be formed over the first substrate 100 and the second substrate 200 .

3 is a view showing a printed circuit board according to another embodiment of the present invention.

Referring to FIG. 3 , a printed circuit board according to another embodiment of the present invention is similar to the printed circuit board according to an embodiment of the present invention described with reference to FIG. 2 , but further includes an adhesive layer (A).

The adhesive layer (A) may be interposed between the first substrate 100 and the second substrate 200 . The thickness of the adhesive layer (A) is significantly smaller than the thickness of one second insulating layer 210, and may not affect the overall thickness of the second substrate 200. Since the dielectric loss tangent of the adhesive layer (A) is smaller than that of the first insulating layer 110 , the adhesive layer (A) may not affect the dielectric loss of the second substrate 200 . The dielectric loss tangent of the adhesive layer (A) may be similar to that of the second insulating layer 210 .

Among the first circuits 120 of the first substrate 100, the first circuit 120' located on the bottom of the cavity C may pass through the adhesive layer A.

Other descriptions are omitted because they are not different from the printed circuit board according to an embodiment of the present invention.

4 is a diagram showing a method for manufacturing a printed circuit board according to an embodiment of the present invention, and FIG. 5 is a view showing a part of FIG. 4, particularly FIG. 4(i).

In the printed circuit board manufacturing method according to an embodiment of the present invention, the first substrate 100 is manufactured by a double-sided lamination method using a core, and the first substrate 100 is sequentially manufactured, and at the same time, the second substrate 200 are produced sequentially.

Specifically, referring to FIG. 4 , a part of the first substrate 100 is manufactured by a double-sided lamination method from (a) to (h). In particular, the first circuit 120 and the first via 130 are formed by a tenting method using a raw material in which the metal foil M is laminated on both sides of the first insulating layer 110 . When forming the first circuit 120 by a tenting method, an etching resist R corresponding to a region of the first circuit 120 may be used. However, the first circuit 120 and the first via 130 may be formed in a method other than tenting.

In this embodiment, the first substrate 100 of the printed circuit board is composed of a total of nine first insulating layers 110 and the second substrate 200 is composed of two second insulating layers 200, the circuit layer As a standard, it is a 10-layer printed circuit board.

After the first substrate 100 is first manufactured with the five first insulating layers 110 (h), the second insulating layer 210 constituting the second substrate 200 is stacked (i). After that, by applying the double-sided lamination method, a general first insulating layer 110 is laminated on the lower part of the first substrate 100 that has been partially manufactured, but the upper part has a hole corresponding to the second insulating layer 210. 1 The insulating layer 110 is stacked (j). The first circuit 120, the second circuit 220, and the connection circuit 500 are simultaneously formed (k), and the first insulating layer 110 and the second insulating layer 210 are laminated once more in the same manner. (l). Then, if necessary, the first circuit 120, the second circuit 220, the first via 130, and the second via 230 are formed together with the connection via 510 (m). Finally, the solder resist layer 600 is laminated on the first substrate 100 and the second substrate 200, but a part of the first circuit 120 or the second circuit 220 at the top is for device mounting. It is exposed to become the pad 220' (m).

5 shows a transfer method of stacking a second insulating layer 210 on a partially manufactured first substrate 100 . A second insulating layer 210 is temporarily attached to the lower surface of the roll-shaped transfer paper P with a release layer or the like, and the transfer paper P rotates and moves while being in contact with the partially manufactured first substrate 100, As the release layer is separated, the second insulating layer 210 may be stacked on the first substrate 100 . The transfer paper (P) may be formed of a material such as PI or PET capable of bending.

For the efficiency of the process, printed circuit board manufacturing including transfer may be performed in strip units and finally separated by units.

6 to 8 are diagrams illustrating a method of manufacturing a printed circuit board according to another embodiment of the present invention.

In the printed circuit board manufacturing method according to another embodiment of the present invention, the first substrate 100 and the second substrate 200 are separately manufactured in a separate process and then placed in the cavity C of the first substrate 100. A method of inserting the second substrate 200 is taken.

6 shows a process of manufacturing the second substrate 200 .

Tenting the second circuit 220 and the second via (not shown), including the connection circuit 500 and the connection via 510, to the raw material in which the metal foil M is laminated on both sides of the second insulating layer 210 and so on ((a) to (g)). The second insulating layer 210 is further laminated, and an adhesive layer (A) is formed below the second substrate 200 if necessary. The second substrate 200 manufactured in this way may be temporarily attached to the lower surface of the transfer paper P as a release layer.

7 shows a process of manufacturing the first substrate 100 .

The first circuit 120 and the first via 130 are formed by a method such as tenting using an etching resist R on raw materials in which metal foil M is laminated on both sides of the first insulating layer 110. . This process may be repeated up to the desired number of layers ((a) to (g)). This is no different from the printed circuit board manufacturing method described with reference to FIG. 4 . Thereafter, the first insulating layer 110 with holes is stacked on the top and the general first insulating layer 110 without holes is stacked on the bottom to form a cavity (C) (h). If necessary, a method of performing a cavity (C) processing process after laminating the general first insulating layer 110 on both sides may be used.

8 illustrates a process of inserting the second substrate 200 into the cavity C of the first substrate 100 .

A process of inserting the second substrate 200 into the cavity C of the first substrate 100 may be performed by a transfer method. The second substrate 200 temporarily attached as a release layer to the lower surface of the transfer paper P is transferred into the cavity C of the first substrate 100 . At this time, the first substrate 100 and the second substrate 200 may be bonded by the adhesive layer (A).

After that, a process of forming the solder resist layer 600 may be added.

Although one embodiment of the present invention has been described above, those skilled in the art can add, change, delete, or add components within the scope not departing from the spirit of the present invention described in the claims. The present invention can be variously modified and changed by the like, and this will also be said to be included within the scope of the present invention.

1: Terminal
10: printed circuit board
100: first substrate
110: first insulating layer
120, 120': first circuit
130: first via
C: Cavity
200: second substrate
210: second insulating layer
220: second circuit
220': pad
230: second via
A: adhesive layer
300: first element
400: second element
410: third element
500: connection circuit
510: connection via
600: solder resist layer
M: metal foil
P: transfer paper
R: etch resist

Claims (34)

a first insulator;
a second insulator disposed on the first insulator and having a cavity; and
A connection structure disposed in the cavity and including a plurality of third insulating layers;
The dielectric loss tangent of at least one of the plurality of third insulating layers is smaller than the dielectric loss tangent of the second insulating part;
printed circuit board.
According to claim 1,
a plurality of first wiring layers respectively disposed on or within the first insulating part;
one or more first vias each disposed within the first insulating portion;
a plurality of second wiring layers respectively disposed on or within the second insulating portion; and
one or more second vias each disposed within the second insulating portion; Including more,
printed circuit board.
According to claim 2,
At least a portion of the plurality of first wiring layers is exposed to the cavity,
printed circuit board.
According to claim 1,
The first insulating part includes a plurality of first insulating layers,
The dielectric loss tangent of at least one of the plurality of third insulating layers is smaller than the dielectric loss tangent of each of the plurality of first insulating layers,
printed circuit board.
According to claim 1,
The second insulating part includes a plurality of second insulating layers,
The dielectric loss tangent of at least one of the plurality of third insulating layers is smaller than the dielectric loss tangent of each of the plurality of second insulating layers,
printed circuit board.
According to claim 1,
An adhesive layer disposed between the first insulating part and the connection structure; further comprising,
printed circuit board.
According to claim 6,
The thickness of the adhesive layer is smaller than the thickness of at least one of the plurality of third insulating layers,
printed circuit board.
According to claim 2,
The connection structure further comprises a plurality of third wiring layers disposed on or within the plurality of third insulating layers, respectively.
printed circuit board.
According to claim 8,
a first element disposed on the second insulating part and the connection structure; and
A second element disposed on the second insulating portion and the connection structure; further comprising,
printed circuit board.
According to claim 9,
The first element and the second element are electrically connected to each other by the plurality of third wiring layers,
The first element and the second element are electrically connected to the plurality of second wiring layers, respectively.
printed circuit board.
According to claim 10,
The transmission speed of the plurality of second wiring layers connected to the first element is smaller than the transmission speed of the plurality of third wiring layers connecting the first element and the second element;
printed circuit board.
According to claim 11,
A transmission speed of the plurality of second wiring layers connected to the second element is smaller than a transmission speed of the plurality of third wiring layers connecting the first element and the second element to each other;
printed circuit board.
According to claim 1,
An adhesive layer disposed between the first insulating part and the connection structure; further comprising,
The first insulating part and the second insulating part each include a plurality of first insulating layers and a plurality of second insulating layers,
The dielectric loss tangent of at least one of the plurality of third insulating layers is smaller than the dielectric loss tangent of each of the plurality of first insulating layers, the dielectric loss tangent of each of the plurality of second insulating layers, and the dielectric loss tangent of the adhesive layer,
printed circuit board.
According to claim 1,
An adhesive layer disposed between the first insulating part and the connection structure; further comprising,
The first insulating part and the second insulating part each include a plurality of first insulating layers and a plurality of second insulating layers,
The dielectric loss of at least one of the plurality of third insulating layers is smaller than the dielectric loss of each of the plurality of first insulating layers, the dielectric loss of each of the plurality of second insulating layers, and the dielectric loss of the adhesive layer,
printed circuit board.
a substrate including a first insulating part and a second insulating part disposed on the first insulating part and having a cavity;
a connection structure disposed in the cavity and including a third insulating layer and a third wiring layer buried in the third insulating layer and having one surface exposed to one surface of the third insulating layer; and
An adhesive layer disposed between the first insulating part and the connection structure; includes,
The thickness of the adhesive layer is smaller than the thickness of the third insulating layer,
printed circuit board.
According to claim 15,
The substrate may include a plurality of first wiring layers respectively disposed on or in the first insulating portion, one or more first vias respectively disposed in the first insulating portion, and a plurality of first vias respectively disposed on or in the second insulating portion. Further comprising a second wiring layer, and one or more second vias disposed in the second insulating portion,
printed circuit board.
According to claim 16,
At least a portion of the plurality of first wiring layers is exposed to the cavity;
The adhesive layer covers at least a portion of the plurality of first wiring layers.
printed circuit board.
According to claim 17,
The first insulating part includes a plurality of first insulating layers,
The second insulating part includes a plurality of second insulating layers,
printed circuit board.
According to claim 18,
a first element disposed on the substrate and the connection structure; and
A second element disposed on the substrate and the connection structure; further comprising,
printed circuit board.
According to claim 19,
The first element and the second element are electrically connected to each other by the third wiring layer,
The first element and the second element are electrically connected to the plurality of second wiring layers, respectively.
printed circuit board.
According to claim 20,
A transmission speed of the plurality of second wiring layers connected to the first element is smaller than a transmission speed of the third wiring layer connecting the first element and the second element to each other;
printed circuit board.
According to claim 21,
A transmission speed of the plurality of second wiring layers connected to the second element is smaller than a transmission speed of the third wiring layer connecting the first element and the second element to each other;
printed circuit board.
preparing a first insulating part;
forming a second insulating part on the first insulating part;
forming a cavity penetrating at least a portion of the second insulating portion; and
Disposing a connection structure including a plurality of third insulating layers in the cavity; includes,
The dielectric loss tangent of at least one of the plurality of third insulating layers is smaller than the dielectric loss tangent of the second insulating part;
A method for manufacturing a printed circuit board.
According to claim 23,
The step of preparing the first insulating portion includes forming a first wiring layer on or within the first insulating portion and forming one or more first vias in the first insulating portion, respectively;
Forming the second insulating portion on the first insulating portion may include forming a plurality of second wiring layers on or in the second insulating portion and forming one or more second vias in the second insulating portion, respectively. Including the steps of
A method for manufacturing a printed circuit board.
According to claim 24,
At least a portion of the plurality of first wiring layers is exposed to the cavity,
A method for manufacturing a printed circuit board.
According to claim 24,
The first insulating part includes a plurality of first insulating layers,
The dielectric loss tangent of at least one of the plurality of third insulating layers is smaller than the dielectric loss tangent of each of the plurality of first insulating layers,
A method for manufacturing a printed circuit board.
According to claim 24,
The second insulating part includes a plurality of second insulating layers,
The dielectric loss tangent of at least one of the plurality of third insulating layers is smaller than the dielectric loss tangent of each of the plurality of second insulating layers,
A method for manufacturing a printed circuit board.
According to claim 23,
The step of disposing the connection structure in the cavity consists of forming an adhesive layer on the first insulating portion and disposing the connection structure on the adhesive layer,
A method for manufacturing a printed circuit board.
According to claim 28,
The thickness of the adhesive layer is smaller than the thickness of at least one of the plurality of third insulating layers,
A method for manufacturing a printed circuit board.
According to claim 24,
The connection structure further comprises a plurality of third wiring layers disposed on or within the plurality of third insulating layers, respectively.
printed circuit board.
31. The method of claim 30,
disposing a first element on the second insulating part and the connection structure; and
Disposing a second element on the second insulating portion and the connection structure; further comprising,
A method for manufacturing a printed circuit board.
According to claim 31,
The first element and the second element are electrically connected to each other by the plurality of third wiring layers,
The first element and the second element are electrically connected to the plurality of second wiring layers, respectively.
A method for manufacturing a printed circuit board.
33. The method of claim 32,
The transmission speed of the plurality of second wiring layers connected to the first element is smaller than the transmission speed of the plurality of third wiring layers connecting the first element and the second element;
A method for manufacturing a printed circuit board.
34. The method of claim 33,
A transmission speed of the plurality of second wiring layers connected to the second element is smaller than a transmission speed of the plurality of third wiring layers connecting the first element and the second element to each other;
A method for manufacturing a printed circuit board.

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