TW201916252A - 積體電路構造及其製造方法 - Google Patents

積體電路構造及其製造方法 Download PDF

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TW201916252A
TW201916252A TW106142602A TW106142602A TW201916252A TW 201916252 A TW201916252 A TW 201916252A TW 106142602 A TW106142602 A TW 106142602A TW 106142602 A TW106142602 A TW 106142602A TW 201916252 A TW201916252 A TW 201916252A
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TW106142602A
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TWI664697B (zh
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蔡伩哲
謝旻諺
陳華豐
潘國華
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台灣積體電路製造股份有限公司
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    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates

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Abstract

本揭露提供一種方法，其包含形成隔離特徵於半導體基材中；形成第一鰭片和第二鰭片於半導體基材上，其中第一和第二鰭片係藉由隔離特徵在側向上分離；以及形成細長接觸特徵落在第一和第二鰭片上。此細長接觸特徵進一步嵌入隔離特徵內，在垂直方向上封入氣隙於細長接觸特徵與隔離特徵之間。

Description

具有受控氣隙的鰭式場效電晶體
在半導體科技中，藉由各種包含光微影製程、離子佈植、蝕刻以及沉積的製程，在基材上形成各種積體電路特徵(如摻雜區和閘極堆疊)。形成和配置互連結構(包含各種導電特徵，如接觸特徵、導孔結構和金屬導線)以連結積體電路特徵至功能電路中。舉例而言，可利用鑲嵌製程以形成多層銅互連。然而現存的方法造成各種問題，例如寄生電容和橋接(漏電)，對積體電路性能造成不利的影響，例如引進額外的時間延遲或造成電路故障。尤其當半導體技術向具有更小特徵尺寸的先進技術節點邁進時，如20nm、16nm或更小，寄生電容的問題更加惡化，進一步導致電路性能和可靠性的下降。
因此，本揭露提供一種互連結構及其製造方法，以處理上述問題。
100‧‧‧方法
102、104、106、108、110、112、114、116、118、120、122、124、126、128、130‧‧‧操作
200‧‧‧積體電路結構、半導體結構
210‧‧‧基材
215‧‧‧隔離特徵
218‧‧‧主動區域
220‧‧‧鰭片
222、224‧‧‧頂面
225‧‧‧閘極堆疊
228‧‧‧通道
230‧‧‧源極/汲極特徵
235、245‧‧‧層間介電質層
240‧‧‧金屬閘極堆疊
250‧‧‧接觸溝槽
252、275‧‧‧虛線圓圈
255、262‧‧‧溝槽尖端
260‧‧‧接觸特徵
265‧‧‧氣隙
270‧‧‧黏著層
Hfin‧‧‧尺寸、高度
D‧‧‧深度
AA'、BB'‧‧‧虛線
X、Y、Z‧‧‧方向
當結合隨附圖式閱讀時，自以下詳細說明將很好地理解本揭露之樣態。應注意，根據工業中的標準實務，各特徵並非按比例繪製。事實上，出於論述清晰之目的，可 任意增加或減小各特徵之尺寸。
第1圖為依據一些實施例中的一實施例形成一種積體電路結構之方法的流程圖。
第2A、3A、4A、5A、6A和7A圖繪示依據一些實施例所製造的藉第1圖之方法在不同製造階段的範例積體電路結構之頂視圖。
第2B、3B、4B、5B、6B和7B圖繪示依據一些實施例所製造的在各製造階段中範例積體電路結構沿虛線AA’之截面圖。
第2C、3C、4C、5C、6C和7C圖繪示依據一些實施例所製造的在各製造階段中範例積體電路結構沿虛線BB’之截面圖。
第4D、6D和7D圖繪示依據其他實施例所製造的在各製造階段中範例積體電路結構沿虛線AA’之截面圖。
第4E、6E和7E圖繪示依據其他實施例所製造的在各製造階段中範例積體電路結構沿虛線BB’之截面圖。
以下揭露提供眾多不同的實施例或範例，用於提供本揭露主要內容之不同特徵。下文描述特定範例之組件及配置以簡化本揭露。當然，此範例僅為示意性，且並不擬定限制。此外，本揭露可在各範例中重複使用元件符號及/或字母。此重複之目的為簡化及釐清，且其自身並不規定所討論的各實施例及/或配置之間的關係。並且，以下描述「第一特徵形成 在第二特徵之上方或之上」，於實施例中可包括第一特徵與第二特徵直接接觸，且亦可包括在第一特徵與第二特徵之間形成額外特徵使得第一特徵及第二特徵無直接接觸。
本揭露關於但不僅限於鰭式場效電晶體(fin field-effect transistors；FETs)裝置。舉例而言，鰭式場效電晶體裝置可為互補式金屬氧化半導體(complementary metal-oxide-semiconductor；CMOS)裝置，包含P型金屬氧化半導體(P-type metal-oxide-semiconductor,PMOS)鰭式場效電晶體裝置和N型金屬氧化半導體(N-type metal-oxide-semiconductor；NMOS)鰭式場效電晶體裝置。後續揭露將繼續以鰭式場效電晶體範例說明本揭露的各種實施例。然而應理解的是，本揭露並不限於特定型態的裝置，除非特別記載於申請專利範圍中。
第1圖為依據一些實施例的形成一種積體電路結構之方法100的流程圖。第2A、3A、4A、5A、6A以及7A圖繪示了依據一些實施例，在各製造階段的範例積體電路結構(或半導體結構)200的頂視圖。第2B、3B、4B、5B、6B以及7B圖繪示了依據一些實施例，在各製造階段沿虛線AA'的半導體結構200之截面圖。第2C、3C、4C、5C、6C以及7C圖繪示了依據一些實施例，在各製造階段沿虛線BB'的半導體結構200之截面圖。第4D、6D以及7D圖繪示了一些其他實施例，在各製造階段沿虛線AA'的半導體結構200之截面圖。第4E、6E以及7E圖，繪示了一些其他實施例，在各製造階段沿虛線BB'的半導體結構200之截面圖。關於 第1至7E圖，方法100和範例積體電路結構200於下文一起描述。
此方法起始於方塊102，提供或接收基材210，如第2A至2C圖所示，第2A圖為半導體結構之頂視圖；第2B圖為沿虛線AA'的半導體結構200之截面圖；第2C圖為沿虛線BB'的半導體結構200之截面圖。在一些實施例中，基材210包含矽。替代地，根據一些實施例，基材210可包括其他元素型半導體例如鍺。在一些實施例中，基材210額外地或替代性地包含化合物半導體，如碳化矽、砷化鎵、砷化銦和磷化銦。在一些實施例中，基材210包含合金半導體，如矽鍺、矽鍺碳化物、砷化鎵磷化物和磷化鎵銦。
基材210在組成上可為單一層或是包含多層。不同層可具有相似或不同組成，且在各種實施例中，一些基材層具有非單一組成以引起裝置應變，藉以調節基材之性能。基材210可包含磊晶層形成於其頂面上，例如磊晶半導體層覆蓋於基體晶圓上。在各種實施例中，基材210包含一或多種磊晶成長半導體材料。舉例而言，矽晶層磊晶成長於矽晶圓上。另一實例中，矽鍺層成長於矽晶圓上。又一實例中，矽和矽鍺交替磊晶成長於晶圓上。在一些實施例中，用於磊晶成長的適當沉積製程包括原子層沉積(atomic layer deposition；ALD)、化學氣相沉積(chemical vapor deposition；CVD)、高密度電漿化學氣相沉積(high-density plasma CVD；HDP-CVD)、物理氣相沉積(physical vapor deposition；PVD)和/或其他適 當之沉積製程。任何這些技術可用來成長具有含有漸變成份的任何成分的半導體層。
分層基材的實例包含絕緣層上矽(silicon-on-insulator；SOI)的基材210。舉例而言，基材可包含利用如氧離子植入矽晶隔離法(separation by implanted oxygen；SIMOX)形成埋入氧化層(buried oxide；BOX)。在一些這樣的例子中，基材210可包含嵌入絕緣層，例如氧化矽、氮化矽、氮氧化矽，或是其他適當的絕緣材料。
仍參照第1和第2A至2C圖，方法100包含操作104，其為形成一或多個隔離特徵215於基材210中。在本實施例中，隔離特徵215為淺溝槽隔離(shallow trench isolation；STI)特徵。淺溝槽隔離特徵215是藉由任何適當的製程來形成，製程包含沉積、光微影和/或蝕刻製程。在一實施例中，形成淺溝槽隔離特徵215的步驟包含形成第一硬遮罩層，透過第一遮罩層的開口將蝕刻製程用於基材210，以形成溝槽於基材210中，填入一或多種介電材料於溝槽中，以及進行化學機械研磨(chemical mechanical polishing；CMP)製程以移除多餘的介電材料並使頂面平坦化，藉以形成淺溝槽隔離特徵215並定義主動區域218。隔離特徵215在基材210上形成，以隔離各個主動區域218。隔離特徵215包含氧化矽、氮化矽、氮氧化矽、低介電係數材料、其他適當的介電材料或其組合。
在各種實例中，硬遮罩層的形成可藉由沉積材料層(例如：氮化矽)、以微影製程形成圖案化光阻層以及透 過圖案化光阻層的開口蝕刻該材料層，以形成圖案化的硬遮罩層。此外，化學機械研磨製程也可移除硬遮罩層。或者，在化學機械研磨後，以蝕刻製程移除硬遮罩層，例如，濕式蝕刻。例示的光微影製程可包含形成光阻層、藉由微影曝光製程曝光光阻、進行曝光後烘烤製程以及對光阻層顯影以形成圖案化光阻層。或者，該光微影製程可被其他技術替代，例如電子束寫入(e-beam writing)、離子束寫入(ion-beam writing)、無光罩圖案化(maskless patterning)或分子印刷(molecular printing)。在其他實施例中，圖案化光阻層直接利用圖案化遮罩層作為蝕刻製程的蝕刻遮罩，以形成基材210中的溝槽。在另一些其他實施例中，圖案化的硬遮罩層包含氧化矽、氮化矽、氮氧化矽或其他任何適當的介電材料。圖案化的硬遮罩層包含單一材料層或多樣材料層。圖案化的硬遮罩層可藉由熱氧化、化學氣相沉積、原子層沉積或任何其他適當之方法來形成。
參照第1和3A至3C圖，方法100包含操作106，其係形成鰭狀結構，使基材210上具有一或多個鰭片主動區域(或單純為鰭片)220。第3A圖為半導體結構200之俯視圖；第3B圖為半導體結構200沿虛線AA’之截面圖；以及第3C圖為半導體結構200沿虛線BB’之截面圖。鰭片220延伸至淺溝槽隔離特徵215之上方，使各種裝置，如場效電晶體，形成於鰭片220之多個表面上，以達到高耦合效率和裝置性能。如第3B和3C圖所示，淺溝槽隔離特徵215包含頂面222，並且鰭片220包含頂面224，其在垂直方向上，比頂 面222高一尺寸Hfin。
在一些實施例中，鰭片220的形成是透過適當的蝕刻製程使淺溝槽特徵215凹陷。利用設計用來選擇性移除淺溝槽特徵215的材料之蝕刻劑來選擇性蝕刻，以使淺溝槽特徵215凹陷。任何適當之蝕刻技術可用於使淺溝槽特徵215凹陷，包含乾式蝕刻、濕式蝕刻、反應性離子蝕刻(RIE)及/或其他蝕刻方法。在一實施例中，非等向性乾式蝕刻以適當之氣體來選擇性蝕刻淺溝槽特徵215，而不會對於鰭片218之半導體材料進行蝕刻，例如含氟或含氯氣體。鰭片200的高度Hfin取決於凹陷淺溝槽特徵215之蝕刻過程的蝕刻深度。
替代或附加地，選擇性磊晶成長可用於在主動區域上選擇性成長一或多種半導體材料，使主動區域垂直突出淺溝槽特徵215上，因而形成鰭片220。藉由選擇性磊晶成長，矽特徵、矽鍺特徵、碳化矽特徵及/或其他適當之半導體特徵在主動區上以結晶態生長。適當之磊晶成長製程包含化學氣相沉積技術，例如氣相磊晶(vapor-phase epitaxy；VPE)及/或超高真空化學氣相沉積(ultra-high vacuum CVD；HUVCVD)，分子束磊晶及/或其他適當之磊晶成長技術。
根據第1圖以及4A至4E圖，方法100包含操作108，其為形成閘極堆疊225於鰭片220上。第4A圖為半導體結構200之俯視圖；第4B和4C圖依序為在一些實施例中，半導體結構200沿虛線AA’和BB’之截面圖。第4D和4E圖依序為其他實施例中，半導體結構200沿虛線AA’和BB’之截面圖。閘極堆疊225形成於鰭片220之多個表面上，以達到堆疊閘極與 各自的通道區域228(對應之閘極堆疊下方的部分鰭片)之高電容耦合，來提高裝置性能，例如降低臨界電壓。
本實施例中，在稍後的製造階段，閘極堆疊225會被金屬閘極堆疊取代，也因此被稱為偽閘極堆疊。偽閘極堆疊225形成於鰭片220的通道區域上。在一些例子中，偽閘極堆疊225的形成包含沉積一含多晶矽或是其他適當材料之偽閘極層；以及圖案化偽閘極層以形成偽閘極堆疊。閘極硬遮罩可形成於偽閘極材料層上，且作為圖案化偽閘極層之蝕刻遮罩。閘極硬遮罩可包含任何適當材料，如氧化矽、氮化矽、碳化矽、氮氧化矽、其他適當材料或其組合。在一實施例中，閘極硬遮罩包含雙層遮罩膜，如氧化矽和氮化矽。在一些例子中，圖案化過程包含藉由光微影製程形成圖案化光阻層；利用該圖案化光阻層作為蝕刻遮罩，蝕刻該硬遮罩；以及利用圖案化硬遮罩作為蝕刻遮罩，蝕刻偽閘極層以形成偽閘極堆疊。
在一些實施例中，一或多個閘極側壁特徵(閘極間隔物(gate spacer))形成於偽閘極堆疊225的側壁上。閘極側壁特徵可用來隔離接下來形成的源極/汲極特徵和閘極堆疊；或用來補償源極/汲極特徵。閘極側壁特徵包含任何適當之介電材料，如氧化物半導體、氮化物半導體、碳化物半導體、氮氧化物半導體、其他適合之介電材質及/或其組合。在一些實施例中，閘極側壁特徵可包含多層，如第一層為氧化矽，第二層為氮化矽。在一例子中，閘極側壁特徵是藉由沉積和非等向性蝕刻來形成，非等向性蝕刻例如為乾式蝕刻。另一例子中，閘極側壁特徵的第一層是利用原子層沉積 所形成，並且第二層是利用沉積和乾式蝕刻所形成。
仍參照第1圖以及4A至4E圖，方法100包含操作110，其為形成源極/汲極(S/D)特徵230於鰭片220上。在本實施例中，源極/汲極特徵230是在源極/汲極區域內的磊晶成長半導體特徵，且被定義在鰭片上，並介於通道228間。磊晶源極/汲極特徵230可藉由選擇性磊晶成長(selective epitaxial growth；SEG)形成，用於具提高載流子遷移率和裝置性能的應力效應。閘極堆疊225(包含閘極間隔物)限制選擇性磊晶成長製程，使源極/汲極特徵230在源極/汲極區域內自對準。在許多實施例中，源極/汲極特徵230的形成是由一或多次選擇性磊晶成長，藉此使矽特徵、矽鍺特徵、碳化矽特徵及/或其他適當材料在源極/汲極區域內的鰭狀構造上以結晶狀態生長。或在一實施例中，磊晶成長前，先利用蝕刻製程，使源極/汲極區域內的部分鰭片220凹陷。該蝕刻過程也可移除設置在源極/汲極區域上的任何介電材料，如在閘極側壁特徵形成期間形成之介電材料。適當的磊晶製程包含化學氣相沉積技術、分子束磊晶及/或其他適合之製程。
在磊晶成長製程中，源極/汲極特徵230可藉由引入摻雜物而被臨場摻雜，摻雜物包括P型摻雜物，如硼或二氟化硼；以及N型摻雜物，如磷或砷。若源極/汲極特徵230未被臨場摻雜，則會進行佈植製程(如接面佈植(junction implant)製程)以引進相應的摻雜物進入源極/汲極特徵230。在一實施例中，N型場效電晶體中的源極/汲極特徵230包含摻有磷的矽(SiP)或摻有磷的碳化矽(SiCP)，而P型場效電晶體之源極/汲 極特徵230包含摻有硼的矽鍺(SiGeB)、摻有硼的矽鍺錫(SiGeSnB)(錫可用來調整晶格常數)及/或摻有硼的鍺錫(GeSnB)。源極/汲極特徵230可包含多於一層的半導體材料層。舉例而言，一矽鍺層磊晶成長於源極/汲極區域內的基材上，以及一矽晶層磊晶成長於矽鍺層上。之後會進行一或多個退火製程，以活化源極/汲極特徵230。適當之退火過程包含快速熱退火(Rapid Thermal Annealing；RTA)、雷射退火製程、其他適當之退火技術或其結合。
在一些其他實施例中，源極/汲極特徵230可磊晶成長至較高的高度，使源極/汲極特徵230的頂面232垂直高於鰭片220之頂面，如第4D圖所繪示。那些源極/汲極特徵230稱為被提高的源極/汲極特徵。
在一些實施例中，不同鰭片220上的磊晶成長源極/汲極特徵230彼此分離，如第4C圖所繪示。或者，側向的磊晶成長可導致相鄰鰭片220上的源極/汲極特徵230合併，形成共享源極/汲極特徵230，如第4E圖所繪示。
參照第1和5A至5C圖，方法100包含操作112，其係在基材上形成層間介電質(inter-level dielectric；ILD)235，以覆蓋源極/汲極區域中的源極/汲極特徵230。第5A圖為在一些實施例中半導體結構200之俯視圖；第5B圖為半導體結構200沿虛線AA’之截面圖；以及第5C圖為半導體結構200沿虛線BB’之截面圖。在第5A圖的半導體結構200俯視圖中，層間介電質層235繪為透明的，使其他結構(如鰭片200)得以繪示。層間介電質235作為支撐和隔離導線之絕緣體。層間 介電質235可包含任何適合之介電材料，如氧化矽、低介電係數材料、多孔性介電材料、其他適當之介電材料或是其組合。或在一實施例中，形成層間介電質235之前，在基材上可沉積蝕刻停止層，以在蝕刻期間提供蝕刻停止，以於稍後的製造階段在層間介電質形成接點。此蝕刻停止層包含不同於層間介電質235的材料，以提供蝕刻選擇性。舉例而言，蝕刻停止層可包含利用化學氣相沉積或原子層沉積之氮化矽。在一些實施例中，層間介電質235的形成包含沉積和化學機械研磨以提供平坦化之頂面。用以圖案化閘極堆疊225的硬遮罩，可藉由化學機械研磨製程、蝕刻操作，或是其組合來移除。
參照第1和6A至6C圖，方法100包含操作114，其係形成金屬閘極堆疊240取代偽閘極堆疊225。第6A圖為在一些實施例中半導體結構200之俯視圖；第6B圖為半導體結構200沿虛線AA’之截面圖；以及第6C圖為半導體結構200沿虛線BB’之截面圖。金屬閘極堆疊240、源極/汲極特徵230和通道228被用以形成各種鰭式場效電晶體，如N型鰭式場效電晶體和P型鰭式場效電晶體。
操作114中，偽閘極堆疊225係經適當之選擇性蝕刻(如濕式蝕刻)移除，因而產生閘極溝槽。若更多物質存在時，此蝕刻過程可包含多個蝕刻步驟以移除偽閘極堆疊。移除偽閘極堆疊225後，金屬閘極材料沉積於閘極溝槽中，並且利用化學機械研磨來移除過多的閘極材料及平坦化頂面。
金屬閘極堆疊240之閘極材料包含閘極介電層和 閘極。在一些實施例中，閘極介電層包含高介電係數材料，並且閘極包含金屬或金屬合金。金屬閘極堆疊240係形成於半導體結構200上，覆蓋鰭片220的通道區域228。在一些例子中，閘極介電層和閘極各可包含數個子層。高介電係數材料層可包含金屬氧化物、金屬氮化物，如氧化鑭(LaO)、氧化鋁(AlO)、氧化鋯(ZrO)、氧化鈦(TiO)、五氧化二鉭(Ta2O5)、氧化釔(Y2O3)、鈦酸鍶(SrTiO3；STO)、鈦酸鋇(BaTiO3；BTO)、氧化鋯鋇(BaZrO)、氧化鋯鉿(HfZrO)、氧化鑭鉿(HfLaO)、矽氧化鉿(HfSiO)、矽氧化鑭(LaSiO)、矽氧化鋁(AlSiO)、氧化鉭鉿(HfTaO)、氧化鈦鉿(HfTiO)、鈦酸鍶鋇((Ba,Sr)TiO3；BST)、氧化鋁(Al2O3)、氮化矽(Si3N4)、氮氧化物(SiON)或其他適當之介電材料。
以適當之技術沉積高介電係數層，如原子層沉積、有機金屬化學氣相沉積(metal organic CVD；MOCVD)、物理氣相沉積、熱氧化及/或其他適當之技術。閘極介電層可額外包含介面層置於鰭片的頂面與高介電係數層之間。該介面層可包含可包含氧化矽、氮化矽、氮氧化矽及/或任何適當之材料，並藉由任何適當之方法，如原子層沉積、化學氣相沉積、臭氧氧化等沈積而成。
接著藉由適當的方法填入閘極材料於閘極溝槽中，如原子層沉積、物理氣相沉積、化學氣相沉積、電鍍、其他適當方法或其組合。閘極可包含單一或多層，如金屬層、襯墊層、潤濕層及/或黏著層。此閘極可包含鈦(Ti)、銀(Ag)、鋁(Al)、氮化鋁鈦(TiAlN)、碳化鉭(TaC)、碳氮 化鉭(TaCN)、氮矽化鉭(TaSiN)、錳(Mn)、鋯(Zr)、氮化鈦(TiN)、氮化鉭(TaN)、釕(Ru)、鉬(Mo)、鋁(Al)、氮化鎢(WN)、銅(Cu)、鎢(W)或任何其他適當材料。在一些實施例中，不同金屬材料會根據各自的功函數而應用在N型場效電晶體和P型場效電晶體裝置，功函數為4.2eV或以下者用於N型場效電晶體，功函數為5.2eV或以上者用於P型場效電晶體。在一些實施例中，N型功函數金屬包含鉭(Ta)。在其他實施例中，N型功函數金屬包含鋁鈦合金(TiAl)、氮化鋁鈦(TiAlN)或其組合。在其他實施例中，N型金屬包含鉭(Ta)、鋁鈦合金(TiAl)、氮化鋁鈦(TiAlN)、氮化鎢(WN)或其組合。N型功函數金屬可包含多種金屬基薄膜，作為使性能表現和製程能力最佳化的堆疊。在一些實施例中，P型功函數金屬包含氮化鈦(TiN)或氮化鉭(TaN)。在其他實施例中，P型金屬包含氮化鈦、氮化鉭、氮化鎢、鋁鈦合金或其組合。P型功函數金屬可包含各種金屬基薄膜，作為使性能表現和製程能力最佳化的堆疊。功函數金屬可藉由的適當方法沉積而成，如物理氣相沉積。在其他例子中，在填入金屬前，會形成阻障層，襯於閘極溝槽內。此阻障層可包含鈦、氮化鈦、鉭、氮化鉭或其組合，並利用適當之方法沉積而成，如物理氣相沉積。在一些例子中，閘極介電層包含介面層和高介電係數材料層。閘極包含覆蓋層、用以調整功函數的金屬層，以及填充金屬，如鋁、銅或鎢。
參照第1、6A至6E和7A至7E圖，方法100包含操作116。依據一些實施例，第7A圖為半導體結構200之俯視圖； 第7B和7C圖各自為半導體結構200沿虛線AA’和BB’之截面圖。依據一些替代的實施例，第6D和6E圖各自為第6A圖的半導體結構200沿虛線AA’和BB’之截面圖。依據一些替代的實施例，第7D和7E圖各自為第7A圖的半導體結構200沿虛線AA’和BB’之截面圖。
在本實施例中，操作116進一步包含多個子操作：操作118，形成第二層間介電質層245；操作120，形成圖案化遮罩層於層間介電質層(235和245)上，以定義接觸特徵260的區域；操作122，蝕刻層間介電質層以形成接觸溝槽250；操作124，形成黏著層於接觸溝槽中；操作126，用導電材料填充此接觸溝槽，以形成金屬插塞；操作128，在高溫下對該導電材料進行熱回焊製程；以及操作130，進行化學機械研磨製程，以移除過多的導電材料並平坦化半導體結構200的頂面。這些操作將詳述於下文。
在形成第二層間介電質層245之操作118中，介電材料沉積於半導體結構200上。此介電材料和用於第一層間介電質層235之材料相似。舉例而言，層間介電質245可包含任何適當之介電材料，如氧化矽、低介電係數材料、多孔性介電材料、其他適當之介電材料或是其組合。該低介電係數材料可包含例如摻氟化物之矽玻璃(fluorinated silica glass,FSG)、碳摻雜矽氧化物、黑鑽石(Black Diamond®，產自美國加州聖塔克拉拉的應用材料公司)、乾凝膠、氣凝膠、氟化非晶碳、聚對二甲苯、二苯基苯並環丁烯(bis-benzocyclobutenes；BCB)、SiLK(產自美國密 西根州米德蘭的陶氏化學公司)、聚醯亞胺、多孔聚合物及/或其他適當材料。在一些實施例中，層間介電質245的形成包含沉積和化學機械研磨，以提供平坦化之頂面。該介電層之沉積可利用化學氣相沉積、旋轉塗佈或任何其他沉積技術。
在操作120中，圖案化遮罩層形成於第二層間介電質層245上，以定義接觸特徵260之區域。在一些實施例中，此遮罩層為光阻層，其係藉由微影製程，包含旋轉塗佈、曝光和顯影而形成。在一些替代性實施例中，遮罩層包含硬遮罩材料，例如氮化矽、氧化矽或氮氧化矽。圖案化硬遮罩層的形成包含沉積和圖案化。遮罩材料層先沉積，接著藉由微影製程和蝕刻來圖案化。圖案化製程可進一步包含利用微影形成圖案化光阻層於硬遮罩上；以及利用圖案化光阻層作為蝕刻遮罩，透過圖案化光阻層之開口來蝕刻硬遮罩。圖案化硬遮罩形成後，圖案化光阻層可藉由電漿灰化或濕式剝除法來移除。
在操作122中，蝕刻製程可利用圖案化遮罩層作為蝕刻遮罩，選擇性蝕刻層間介電質層235和245，因此形成接觸溝槽250，以曝露對應的源極/汲極特徵230。此蝕刻製程可包含一或多個蝕刻步驟，並且可包含任何適當之蝕刻技術，如濕式蝕刻、乾式蝕刻或其具有適當蝕刻液之組合。舉例而言，蝕刻製程包含乾式蝕刻，以蝕刻穿透層間介電質層235和245。在一些實施例中，蝕刻層間介電質層之蝕刻製程包含利用含氟蝕刻劑的電漿蝕刻製程，如六氟丁二烯(C4F6)、氧氣(O2)和二氟甲烷(CH2F2)，並且可進一步包含攜帶氣體，如氬。
接觸溝槽250自對準於，並且因此曝露對應的源 極/汲極特徵230。尤其，接觸溝槽250(例如第6A圖虛線圓圈252中的接觸溝槽250)可具有細長的形狀如長方形，以從鰭片上的源極/汲極特徵，延伸至相鄰鰭片之另一源極/汲極特徵。在此例中，細長接觸特徵250垂直對齊二源極/汲極特徵230，並進一步延伸至兩個源極/汲極特徵之間的部分隔離特徵之上。蝕刻製程形成接觸溝槽，不僅曝露出源極/汲極特徵，而且露出源極/汲極特徵之間部分的隔離特徵。以下敘述將聚焦於虛線圓圈252中的細長接觸溝槽250。蝕刻製程被設計用來選擇性蝕刻層間介電質層235和245之材料，最小化對於源極/汲極特徵230的損害。由於層間介電質層235和245具有相似或相同之組成。蝕刻過程會蝕刻穿過層間介電質層235和245直到到達源極/汲極特徵230。在其他實施例中，存在蝕刻停止層時，蝕刻製程更進一步包含蝕刻(如濕式蝕刻以選擇性蝕刻此蝕刻停止層)以打開蝕刻停止層，使對應的源極/汲極特徵230在接觸溝槽250中露出。由於在隔離特徵215上的層間介電質層235厚得多，並到達隔離特徵215之下方，其隔離特徵具有低於鰭片220之頂面224的頂面222，蝕刻製程繼續蝕刻到層間介電質層235較低而覆蓋隔離特徵215的部分，因此形成溝槽尖端255，如第6B和第6C圖所繪示。此溝槽尖端255具有較小的寬度，並且垂直位於鰭片220的頂面224下方深度D處。
在第6D和6E圖所繪示的替代實施例中，由於層間介電質層235和隔離特徵215在組成上的相似性，以及低蝕刻選擇性，可控制蝕刻製程以繼續蝕刻至隔離特徵215，造成 溝槽尖端255穿透至隔離特徵215，如第6D和6E圖所繪示。溝槽尖端255至少部分被隔離特徵215以深度D圍繞。藉由設計層間介電質層(235和245)以及隔離特徵215的組成、蝕刻劑以及其他蝕刻參數(例如電漿射頻功率和壓力)，可控制深度D於適當範圍內。舉例而言，控制蝕刻製程為較低方向性，使接觸溝槽尖端部分的黏著層較少。在一些例子中，蝕刻製程具有介於10mT至50mT之壓力；並具有介於100至1000W之射頻功率。在其他例子中，蝕刻製程被設計為在層間介電質層(235和245)以及隔離特徵215之間具有較低蝕刻選擇性；溝槽尖端255可有增加的深度D，更深入到達隔離特徵215，因此，透過後續的操作會導致氣隙增加。
在操作124中，形成黏著層270於接觸溝槽250的側壁上。此黏著層270沉積於接觸溝槽的表面，以襯於溝槽中改善接觸特徵之形成，例如提升濕潤性、增加黏著以及防止擴散。在各種實施例中，此黏著層270包含鈦、氮化鈦、其他適當黏著層材料或其組合。舉例而言，黏著層可包含兩層，例如氮化鈦和鈦。在現例中，黏著層270包含氮化鈦。黏著層沉積至足夠的厚度使以提供預期之功能，(例如濕潤性、黏著性及/或防止擴散)，並且不會太厚以佔據接觸溝槽太多空間。在一些例子中，黏著層270具有介於nm至10nm的厚度。黏著層270的形成可包含原子層沉積或化學氣相沉積。在一些實施例中，黏著層270的沉積法包含以四(二甲胺基)鈦(tetrakis-dimethylamino titanium；TDMAT)和氮/氫氣所進行的原子層沉積法。在一些實施例中，黏著層270的沉積法 包含以前驅物四氯化鈦和氨氣所進行的原子層沉積法。可調整黏著層270的形成以控制黏著層270，並最終控制氣隙的形成以及此氣隙體積。在一些實施例中，黏著層270的形成包含對此黏著層進行氮化製程，以提升黏著層和金屬插塞之間的黏著性。黏著層270的沉積可包含在高溫下沉積，例如沉積溫度介於200℃至500℃。在一些例子中，氮化製程引進氮氣以處理黏著層270。氣隙的控制和調整包含減少氮化製程，例如減少氮化持續時間及/或減少氮氣壓力。在一些其他例子中，氣隙的控制和調整包含減少黏著層之厚度及/或其他製程參數，例如沉積溫度和沉積壓力。在一些替代實施例中，黏著層270可藉由物理氣相沉積法來沉積，例如在氮氣環境下利用鈦靶濺鍍沉積。
在操作126中，沉積導電材料，例如金屬或金屬合金，以填充接觸溝槽250，造出金屬插塞作為接觸特徵260。本實施例中，此金屬插塞為鈷插塞。替代地，金屬插塞可包含鈷、鎢、銅、其他適當金屬、合金或其組合。在一實施例中，為了使填充效果較佳，接觸特徵260的形成包含交替性循環多次物理氣相沉積法及化學氣相沉積法來沉積鈷，直到接觸溝槽250被填滿。在進一步的實施例中，鈷插塞的沉積包含交替性在高溫下利用物理氣相沉積法及化學氣相沉積法來沉積鈷。對於在細長接觸溝槽250中形成的接觸特徵260(如第7A圖虛線圓圈275內者)，延伸至溝槽尖端255的接觸特徵260，被稱為接觸尖端262。此接觸尖端262在垂直方向上低於源極/汲極特徵230，如第7B和7C圖所繪示。在一些實施例中，溝槽尖端262 進一步穿入對應的隔離特徵215，如第7D和7E圖所繪示。
在操作128中，沉積以形成金屬插塞之後，將熱回焊製程用於金屬插塞，以提供回焊並提高填充效果。本實施例中，此熱回焊製程包含回焊溫度介於300℃與500℃之間的熱退火。在進一步的實施例中，此熱回焊製程包含引進氫氣使熱回焊在氫氣環境下進行。為了控制和調整氣隙的形成，回焊溫度降為低於400℃之溫度，例如300℃和380℃。
熱回焊製程之後，半導體結構200冷卻至環境溫度，例如室溫。在冷卻期間以及冷卻之後，形成氣隙265，接觸特徵260延伸至隔離特徵215內，例如第7A圖所繪示的虛線圓圈275中的接觸特徵260。此氣隙265位於接觸特徵260之下方，尤其位於接觸尖端262下方。氣隙265被介電層包圍，並且接觸尖端262覆蓋氣隙265。在一些實施例中，氣隙265形成於層間介電質層235中，如第7B和7C圖所繪示。在一些實施例中，氣隙265形成於隔離特徵215中，並被隔離特徵215包圍，如第7D和7E圖所繪示。
在熱回焊過程後的冷卻階段期間，被沉積的鈷縮小，造成了位於溝槽尖端255中的氣隙265。不同因素會影響氣隙265的形成以及體積，例如操作122、124、126以及128。這些因素包含但不僅限於，形成接觸溝槽的蝕刻製程(包含蝕刻選擇性和蝕刻方向性)、黏著層的形成(包含黏著層沉積、氮化製程以及形成金屬插塞之導電材料的沉積)；以及熱回焊製程(包含回焊溫度)。適當控制和調整以上的操作可有效的提升氣隙的形成，以及氣隙體積的增加，如以上各個操作所 述。藉由形成足夠尺寸(或體積)的氣隙265，可有效的減少寄生電容，並且提升電路之性能。
在操作130中，利用化學機械研磨製程以移除沉積於層間介電質層245上過多的導電材料，並且平坦化半導體結構200之頂面。
方法100可包含上述操作之前、期間或之後的附加操作。舉例而言，其他導電特徵，如內連結構的金屬線和導孔特徵。可藉由適當的方法(如鑲嵌製程)形成以連結不同的裝置(包含場效電晶體)至功能電路。
本揭露提供一種積體電路結構以及其製造方法。尤其半導體結構包含具受控氣隙的鰭式場效電晶體。氣隙被介電材料層包圍，並且有接觸尖端覆蓋。在部分實施例中，氣隙延伸至隔離特徵中，並且被相對應的淺溝槽隔離特徵包圍。方法包含蝕刻以形成接觸溝槽；黏著層的沉積；氮化製程；沉積導電材料以形成金屬插塞；以及熱回焊製程。此方法也包含調整及控制以上的製程以提升氣隙的形成。這些調整和控制包含但不僅限於：降低回焊溫度至低於400℃；減少氮化製程；以及黏著層的沉積為較低方向性。在本揭露方法及半導體裝置中的部分實施例，會出現不同的優點。舉例而言，藉由形成氣隙至足夠尺寸，可有效的減少寄生電容，並提升電路之性能。
因此，本揭露依據一些實施例提供一種製造積體電路之方法。此方法包含：形成隔離特徵於半導體基材中；形成第一鰭片和第二鰭片於半導體基材上，其中這些第一和第二鰭片係藉由隔離特徵在側向上分離；以及形成細長接觸 特徵落在這些第一和第二鰭片上，其中細長接觸特徵進一步嵌入隔離特徵內，在垂直方向上封入氣隙於細長接觸特徵與隔離特徵之間。
本揭露也依據一些實施例提供一種製造積體電路之方法。此方法包含：形成隔離特徵於半導體基材中；形成第一鰭片和第二鰭片於半導體基材上，其中這些第一和第二鰭片係藉由隔離特徵在側向上分離；沉積介電材料層於隔離特徵以及這些第一和第二鰭片上；對介電材料層進行蝕刻製程，藉此在介電材料層中形成接觸溝槽，其中蝕刻製程進一步使隔離特徵凹陷；以及形成接觸特徵於接觸溝槽內，接觸特徵落在這些第一和第二鰭片上，其中接觸特徵進一步嵌入隔離特徵內，在垂直方向上封入氣隙於接觸特徵與隔離特徵之間。
本揭露依據一些實施例提供一種積體電路結構。該積體電路結構包含基材；第一鰭片和一第二鰭片形成於基材上，且彼此係藉由多個隔離特徵在側向上分離；以及接觸特徵落在這些第一與第二鰭片上，並嵌入隔離特徵內，在垂直方向上定義氣隙於隔離特徵與接觸特徵之間，其中接觸特徵包含鈷。
以上概述幾個實施例的特徵，以讓本技術領域之人員可以更好的理解以下的詳述。本領域的技術人員應該理解，他們可容易地以本揭露作為基礎，用於設計或修改其他製程和結構，以執行相同的目的及/或達到這裡介紹的實施例中相同的優點。本領域之技術人員也應理解這樣的等同構造不脫離本揭露的精神和範疇，並且在不脫離本揭露的精神和範疇之 下，可進行不同的改變、替換和變更。

Claims (20)

  1. 一種製造積體電路的方法，包含：形成一隔離特徵於一半導體基材中；形成一第一鰭片和一第二鰭片於該半導體基材上，其中該些第一和第二鰭片係藉由該隔離特徵在側向上分離；以及形成一細長接觸特徵落在該些第一和第二鰭片上，其中該細長接觸特徵進一步嵌入該隔離特徵內，在垂直方向上封入一氣隙於該細長接觸特徵與該隔離特徵之間。
  2. 如請求項1所述之方法，其中形成該隔離特徵包含：圖案化該半導體基材以形成一溝槽；填充一介電材料於該溝槽中；以及對於該介電材料進行一化學機械研磨製程。
  3. 如請求項2所述之方法，其中形成該些第一和第二鰭片包含選擇性磊晶成長一第一半導體材料於該半導體基材的一第二半導體材料上。
  4. 如請求項3所述之方法，其中該第一半導體材料為矽鍺，該第二半導體材料為矽。
  5. 如請求項1所述之方法，其中形成該細長接觸特徵包含： 沉積一介電材料層在該隔離特徵與該些第一和第二鰭片上；圖案化該介電材料層以形成一接觸溝槽，其中該些第一和第二鰭片曝露於該接觸溝槽中，其中該接觸溝槽中的該隔離特徵部分凹陷；形成一黏著層於該接觸溝槽的多個側壁上；以及形成一金屬插塞於該接觸溝槽內，其中該金屬插塞被該黏著層包圍。
  6. 如請求項5所述之方法，其中該介電材料層的圖案化包含對於該介電材料層進行一蝕刻製程；該黏著層的形成包含沉積該黏著層，以及對該黏著層進行一氮化製程；以及該金屬插塞的形成包含沉積一金屬層，以及在氫氣環境下對該金屬插塞進行一熱回焊製程。
  7. 如請求項6所述之方法，其中該黏著層的沉積包含沉積氮化鈦；以及該金屬層的沉積包含沉積鈷。
  8. 如請求項7所述之方法，其中該黏著層的沉積包含在介於300℃及400℃間的一沉積溫度下沉積氮化鈦。
  9. 如請求項7所述之方法，其中該金屬層的沉積包含藉由物理氣相沉積以及化學氣相沉積交替地沉積鈷。
  10. 如請求項6所述之方法，其中進行該蝕刻製程包括以一包含C 4F 6、O 2及CH 2F 2的蝕刻劑進行該蝕刻製程。
  11. 如請求項6所述之方法，其中形成該細長接觸特徵包含調整該蝕刻製程、該氮化製程，以及該熱回焊製程中的至少一個，以增加該氣隙的一體積以減少寄生電容。
  12. 如請求項11所述之方法，其中調整該蝕刻製程、該氮化製程，以及該熱回焊製程中的至少一個包含減少該熱回焊製程的一回焊溫度至400℃以下。
  13. 如請求項11所述之方法，其中調整該蝕刻製程、該氮化製程，以及該熱回焊製程中的至少一個包含藉由減少該氮化製程的一氮氣壓力及一氮化持續時間中的其中一者以減少該氮化製程。
  14. 一種製造積體電路的方法，包含：形成一隔離特徵於一半導體基材中；形成一第一鰭片和第二鰭片於該半導體基材上，其中該些第一和第二鰭片係藉由該隔離特徵在側向上分離； 沉積一介電材料層於該隔離特徵以及該些第一和第二鰭片上；對該介電材料層進行一蝕刻製程，藉此在該介電材料層中形成一接觸溝槽，其中該蝕刻製程進一步使該隔離特徵凹陷；以及形成一接觸特徵於該接觸溝槽內，該接觸特徵落在該些第一和第二鰭片上，其中該接觸特徵進一步嵌入該隔離特徵內，在垂直方向上封入一氣隙於該接觸特徵與該隔離特徵之間。
  15. 如請求項14所述之方法，其中該蝕刻製程的進行包含透過一圖案化遮罩層的一開口對該介電材料層進行該蝕刻製程；以及該接觸特徵的形成包含沉積一氮化鈦黏著層於該接觸溝槽的多個側壁上，以及沉積鈷於該接觸溝槽以形成一鈷插塞於位於該接觸溝槽內的該氮化鈦黏著層上。
  16. 如請求項15所述之方法，進一步包含對該氮化鈦阻障層進行一氮化製程，以及在低於400℃的一回焊溫度下對該鈷插塞進行一回焊製程。
  17. 如請求項16所述之方法，其中該接觸特徵的形成包含調整該氮化製程和該回焊製程以增加該氣隙的一體積以減少寄生電容。
  18. 如請求項15所述之方法，其中該金屬層的沉積包含藉由物理氣相沉積以及化學氣相沉積交替地沉積鈷。
  19. 一種積體電路構造，包含：一基材；一第一鰭片和一第二鰭片形成於該基材上，且彼此係藉由多個隔離特徵在側向上分離；以及一接觸特徵落在該些第一與第二鰭片上，並嵌入該隔離特徵內，在垂直方向上定義一氣隙於該隔離特徵與該接觸特徵之間，其中該接觸特徵包含鈷。
  20. 如請求項19所述之積體電路構造，其中該接觸特徵包含一氮化鈦層；以及一鈷插塞被該氮化鈦層包圍；該接觸特徵包含位於該隔離特徵中的一嵌入部分，以及位於該些第一和第二鰭片上的多個座落部分；該嵌入部分具有一第一底面於該氣隙上；以及該些座落部分具有多個第二底面於該些第一和第二鰭片上，該第一底面低於該些第二底面。
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