TW201914194A - High boost converter including a first and a second coupled inductors, a first and a second switches, a first and a second clamping diodes, a first and a second clamping capacitors, a first to a fourth diodes, and a first to a fourth capacitors - Google Patents

Abstract

A high boost converter includes a first and a second coupled inductors, a first and a second switches, a first and a second clamping diodes, a first and a second clamping capacitors, a first to a fourth diodes, and a first to a fourth capacitors. The first ends of primary windings of the first and the second coupled inductors are electrically connected together to receive a direct-current input voltage. An input parallel architecture may share the input current, and is therefore suitable for high input current applications. The first and the second switches adopt an interleaving operation, which may make the ripple currents of the primary sides of the coupled inductors be cancelled and may reduce an input current ripple. The third and the fourth diodes and the third and the fourth capacitors provide a voltage multiplication function, and are connected in series with the first and the second capacitors for superimposing outputs, so as to further increase the voltage gain.

Description

High boost converter

This invention relates to a converter, and more particularly to a high boost converter.

Referring to Figure 1, a conventional boost converter, the conventional boost converter operates at a very high turn-on ratio to achieve a higher voltage gain. The parameters V _O , V _in , and D are the output voltage, the input voltage, and the responsible conduction ratio of the switch, respectively. However, the effect is affected by the parasitic element. When the conduction ratio exceeds 0.9, the voltage gain is not increased or decreased, and the height is not high. The need for voltage gain, therefore, a high boost converter that does not require a very high turn-on ratio and at the same time meets the requirements of high voltage gain is the future research direction.

Accordingly, it is an object of the present invention to provide a high boost converter that solves the above problems.

Therefore, the high boost converter of the present invention includes: first and second coupled inductors, first and second switches, first and second clamp diodes, first and second clamp capacitors, first to first Quadrupole, first to fourth capacitors.

Each coupled inductor has a primary side winding and a secondary side winding, each side winding having a first end and a second end, the first ends of the primary windings of the first and second coupled inductors being electrically connected together To receive a DC input voltage, the second end of the secondary winding of the first coupled inductor is electrically coupled to the second end of the secondary winding of the second coupled inductor.

The first switch has a first end electrically connected to the second end of the primary side winding of the first coupled inductor and a grounded second end, and is controlled to be switched between conducting and non-conducting. The second switch has a first end electrically connected to the second end of the primary side winding of the second coupled inductor and a grounded second end, and is controlled to be switched between conducting and non-conducting.

The first clamp diode has an anode electrically connected to the second end of the primary side winding of the first coupled inductor, and a cathode. The first clamp capacitor is electrically connected between the cathode of the first clamp diode and the second end of the primary side winding of the second coupled inductor. The second clamp diode has a cathode electrically connected to the second end of the second switch, and an anode. The second clamp capacitor is electrically connected between the anode of the second clamp diode and the first end of the second switch.

The first diode has an anode and a cathode electrically connected to the anode of the second clamp diode. The second diode has an anode electrically connected to the cathode of the first clamp diode, and a cathode. The third diode has an anode electrically connected to the cathode of the second diode, and a cathode electrically connected to the first end of the secondary winding of the first coupled inductor. The fourth diode has an anode electrically connected to the cathode of the first end of the secondary winding of the first coupled inductor, and a cathode.

The first capacitor is electrically connected between the second end of the primary side winding of the first coupled inductor and the anode of the first diode. The second capacitor is electrically connected between the second end of the primary side winding of the first coupled inductor and the cathode of the second diode. The third capacitor is electrically connected between the first end of the secondary winding of the second coupled inductor and the cathode of the second diode. The fourth capacitor is electrically connected between the first end of the secondary winding of the second coupled inductor and the cathode of the fourth diode.

The effect of the invention is that the third and fourth diodes and the third and fourth capacitors provide a voltage multiplication function, and the first and second capacitors are connected in series to superimpose the output, thereby further increasing the voltage gain, so that the converter does not need High voltage gain can be achieved by operating at a very high turn-on ratio.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

Referring to FIG. 2, an embodiment of the high boost converter of the present invention includes a first coupled inductor 1 and a second coupled inductor 2, a first switch S ₁ , a second switch S ₂ , and a first clamp. The diode D _C1 , a first clamping capacitor C _C1 , a second clamping diode D _C2 , a second clamping capacitor C _C2 , a first diode D ₁ , and a second diode D ₂ , a third diode D ₃ , a fourth diode D ₄ , first to fourth capacitors C ₁ to C ₄ , and a control unit 3 .

Each coupled inductor of the first coupled inductor 1 and the second coupled inductor 2 has a primary side winding N _P1 , N _S1 and a secondary side winding N _P2 , N _S2 , each side winding having a first end and a first At the two ends, the first ends of the primary side windings N _P1 , N _P2 of the first and second coupled inductors 1 and 2 are electrically connected together to receive a DC input voltage, and the secondary winding of the first coupled inductor 1 The second end of the N _P2 is electrically connected to the second end of the secondary side winding N _S2 of the second coupled inductor 2 . The first end of each primary side winding N _P1 , N _S1 is a striking end, and the second end of each primary side winding N _P1 , N _{S1 is} a non-tapping end. The first end of each secondary winding N _P2 , N _S is a striking end, and the second end of each secondary winding N _P2 , N _{S is} a non-tapping end.

The first switch S ₁ is electrically second end having a first end and a second end connected to the ground of the first coupling inductor 1 of the primary winding N _P1, and is controlled by switching to a conducting and non-conducting between. The second switch S ₂ has a first end electrically connected to the second end of the primary side winding of the second coupled inductor 2 and a grounded second end, and is controlled to be switched between conducting and non-conducting. The first switch S ₁ is an N-type power semiconductor transistor, and a first terminal of the first switch S ₁ is the drain, the second terminal of the first switch S ₁ is the source. The second switch S ₂ is an N-type power semiconductor transistor, and a first end of the second switch S ₂ is a drain, the second terminal of the second switch S ₂ is the source.

The first clamp diode D _C1 has an anode electrically connected to the second end of the primary side winding N _P1 of the first coupled inductor 1 and a cathode. The first clamp capacitor C _{C1 is} electrically connected between the cathode of the first clamp diode D _C1 and the second end of the primary side winding N _S1 of the second coupled inductor 2 .

The second clamp diode D _C2 has a cathode electrically connected to the second end of the second switch S ₂ and an anode. The second clamping capacitor C _{C2 is} electrically connected between the anode of the second clamping diode D _C2 and the first end of the second switch S ₂ .

The first diode D ₁ has an anode and a cathode electrically connected to the anode of the second clamp diode D _C2 . The second diode D ₂ has an anode electrically connected to the cathode of the first clamp diode D _C1 , and a cathode. The third diode D ₃ has an anode electrically connected to the cathode of the second diode D _{2 and} a cathode electrically connected to the first end of the secondary winding N _P2 of the first coupled inductor 1. The fourth diode D ₄ has an anode electrically connected to the cathode of the first end of the secondary winding N _P2 of the first coupled inductor 1, and a cathode.

The first capacitor C _{1 is} electrically connected between the second end of the primary side winding NP1 of the first coupled inductor 1 and the anode of the first diode D ₁ . The second capacitor C _{2 is} electrically connected between the second end of the primary side winding N _P1 of the first coupled inductor 1 and the cathode of the second diode D2. The third capacitor C _{3 is} electrically connected between the first end of the secondary side winding N _S2 of the second coupled inductor 2 and the cathode of the second diode D ₂ . The fourth capacitor C _{4 is} electrically connected between the first end of the secondary side winding N _S2 of the second coupled inductor 2 and the cathode of the fourth diode D4.

The control unit 3 generates a first pulse wave signal for switching the first switch S _{1 and} a second pulse wave signal for switching the second switch S ₂ , the first pulse wave signal and the second pulse wave signal have the same Cycle time. A portion of the on-time of the first switch S ₁ is overlapped with a portion of the on-time of the second switch S ₂ . The switching timing chart of the first switch S ₁ and the second switch S ₂ will be further described below in six stages.

Referring to FIG. 3, an equivalent circuit diagram of the embodiment is used to illustrate the magnetizing inductances Lm1 and Lm2 and the leakage inductances Lk1 and Lk2 in the non-ideal equivalent circuit of the two coupled inductors. Wherein, the parameters v _D1 , v _D2 , v _D3 , and v _D4 represent the cross voltages of the first to fourth diodes D1 to D4 , respectively, and the parameters v _DC1 and v _DC2 represent the first to second clamp diodes D, respectively. The crossover voltage of _C1 ~ D _C2 , the parameters V _CC1 , V _CC2 , represent the cross voltage of the first clamp capacitor C1 and the second clamp capacitor C2 respectively, and the parameters V _C1 , V _C2 , V _C3 , V _C4 respectively represent the first The voltage across the capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4, the parameters i _LK1 and i _LK2 represent the leakage inductance current flowing through the two coupled inductors 1, 2, respectively, and the parameter i _in represents the input current. The parameters i _D1 to i _D4 represent currents flowing through the first to fourth diodes D1 to D4, respectively, and the parameter V _O represents the total output voltage.

Referring to FIG. 4, it is an operation timing diagram of the embodiment, wherein the parameters v _gs1 and v _gs2 respectively represent voltages of the first and second pulse signals that control whether the first and second switches S ₁ and S ₂ are turned on. The parameters v _ds1 and v _ds2 represent the two-terminal voltage across the first and second switches S ₁ and S ₂ , respectively, and the parameter T _S is the cycle time of the first pulse signal.

The following is a circuit diagram of the six stages of the present embodiment, in which the conductive elements are indicated by solid lines, and the non-conducting elements are indicated by broken lines, which are described below for each stage.

The first stage (time:):

Referring to FIG. 4 and FIG. 5, a first switch S ₁ is converted into a non-conducting is turned on and the second switch S ₂ is turned on, the first clamp diode D _C1 is not turned on, the second clamp diode D _C2 nonconducting The first diode D _{1 is} not turned on, the second diode D _{2 is} not turned on, the third diode D _{3 is} turned on, and the fourth diode D _{4 is} not turned on.

The first phase begins with Leakage inductor current Fast rise when Stored in magnetizing inductance The energy is still transmitted from the primary side winding N _{P1 of the} first coupled inductor 1 to the secondary side winding N _S1 , the third diode Keep in conduction and flow through the third diode Current Third capacitor Charging. First diode Second diode Fourth diode First clamp diode And the first clamp diode Both are in a non-conducting state due to reverse bias, flowing through the third diode Current Falling and leakage inductance with Controlled current Declining rate, mitigating the third diode Reverse recovery problem. First stage diode voltage , , , , Separately , , , , . when Leakage inductor current rise to Current Down to 0, the third diode When converted to non-conducting, the first phase ends.

second stage( ):

Referring to FIG. 4 and FIG. 6, the first switch S1 is turned on, and the second switch S2 is turned on, the first clamp diode D _{C1 is} not turned on, and the second clamp diode D _{C2 is} not turned on, the first diode D _{1 is} not turned on, the second diode D _{2 is} not turned on, the third diode D ₃ is turned from non-conducting to non-conducting, and the fourth diode D _{4 is} not turned on.

The second phase begins with Third diode Switching to non-conduction, the remaining diodes D _C1 ~ D _C2 , D ₁ ~ D ₄ are reverse biased and not conducting, the first switch And second switch All are in a conductive state. Input voltage Connecting to the primary winding of the first and second coupled inductors, that is, bridging the magnetizing inductance And leakage inductance as well as with Current at this time with In a linear rise, the primary side windings of the first and second coupled inductors are in the second stage of the energy storage operation. In the second phase , , , , . when Second switch When switching to non-conduction, the second phase ends.

The third phase( ):

Referring to FIG. 4 and FIG. 7, the first switch S ₁ is turned on, the second switch S ₂ is not turned on, the first clamp diode D _C1 is not turned on, the second clamp diode D _C2 is not turned on, the first two The polar body D _{1 is} not turned on, the second diode D _{2 is} turned on, the third diode D _{3 is} not turned on, and the fourth diode D _{4 is} turned on.

The third phase begins with The second switch S ₂ is switched from conductive to non-conductive, and the first switch S ₁ remains conductive. Stored in magnetizing inductance The energy is transmitted to the secondary side through the primary side of the second coupled inductor 2, so that the fourth diode Switching to conduction, current flowing through the fourth diode Fourth capacitor recharging current It decreases linearly. Leakage inductor current Release energy to make the second diode And second clamp diode Convert to on state, current Divided into two paths to release energy:

Path 1: Leakage current Flow through the first clamp capacitor Second diode Second capacitor First switch First clamp capacitance Discharge and second capacitor Charging.

Path 2: leakage current Flow through the second clamp capacitor And second clamp diode Leakage current Second clamp capacitance Charging. In the third phase , , . when Second switch Switch to non-conduction and the third phase ends.

Fourth stage ):

Referring to FIG. 4 and FIG. 8 , the first switch S _{1 is} turned on, and the second switch S ₂ is turned from non-conducting to conducting, the first clamping diode D _{C1 is} not conducting, and the second clamping diode D _{C2 is} not conducting. The first diode D _{1 is} not turned on, the second diode D _{2 is} not turned on, the third diode D _{3 is} not turned on, and the fourth diode D _{4 is} turned on.

The fourth stage begins Second switch The state is switched from non-conducting to conducting, and the first switch Still keep on, leakage current Fast rise when Stored in magnetizing inductance The energy is still transmitted to the secondary side, the fourth diode Keep in conduction and flow through the fourth diode Current Fourth capacitor Charging. The remaining diodes D _C1 ~D _C2 and D ₁ ~D ₃ are not conducting due to the reverse bias and flow through the fourth diode. Current Drop and leakage inductance with Controlling the flow through the fourth diode Current The rate of decline, mitigating the fourth diode Reverse recovery problem. In the fourth stage , , , , . when , rise to Flowing through the fourth diode Current Down to 0, fourth diode When converted to non-conducting, the fourth phase ends.

The fifth stage ( ):

Referring to FIG. 4 and FIG. 9, the first switch S1 is turned on, and the second switch S2 is turned on, the first clamp diode D _{C1 is} not turned on, and the second clamp diode D _{C2 is} not turned on, the first diode D _{1 is} not turned on, the second diode D _{2 is} not turned on, the third diode D _{3 is} not turned on, and the fourth diode D ₄ is turned from conductive to non-conductive.

The fifth phase begins All diodes D _C1 ~D _C2 and D ₁ ~D ₄ are reverse biased and not turned on, the first switch And second switch All are in a conductive state. Input voltage Connected to the primary side of the first and second coupled inductors 1, 2, that is, across the magnetizing inductance And leakage inductance as well as with Current at this time with The linear rise, from the energy point of view, the primary side of the first and second coupled inductors 1, 2 is in the process of storing energy. In the fifth stage , , , , . when First switch This phase ends when switching to non-conduction.

The sixth stage ( ):

Referring to FIG. 4 and FIG. 10, a first switch S ₁ is turned into a non-conducting, the second switch S ₂ is turned on, the first clamp diode D _C1 is turned on, the second clamp diode D _C2 is not turned on, The first diode D _{1 is} turned on, the second diode D _{2 is} not turned on, the third diode D _{3 is} turned on, and the fourth diode D _{4 is} not turned on. .

The sixth phase begins First switch Switch from conduction to non-conduction, at this time the second switch Keep on and store in magnetizing inductance The energy is transferred to the secondary side, making the third diode And the first clamp diode Switch to conduction, diode Capacitance recharging current Linear decrease, leakage inductance current Release energy to make the first diode And the first clamp diode Transition to conduction state, leakage inductor current Divided into two paths to release energy:

Path 1: Leakage inductor current Flow through the first clamp diode First capacitor And second switch , where leakage inductance current First capacitor Charging. Path 2: Leakage inductor current Flowing through the capacitor C ₁ , the first diode D ₁ , the second clamping capacitor C _{C2 ,} and the second switch S ₂ , wherein the second clamping capacitor Discharge and first capacitor Charging. And , , . when The first switch S _{1 is} switched to be on, and the sixth phase is ended, and the next switching cycle is entered.

<voltage gain analysis>

Since the first and fourth stage converters operate for a short period of time, only the second, third, fifth and sixth stages are discussed as the main stages of steady state analysis.

In the second and fifth stages, it can be obtained , .

In the third stage, it can be obtained , .

In the sixth stage, it can be obtained , . If the switching period is , the time of the above four stages is , , , .

Because of the steady state, the magnetizing inductance satisfies the volt-second equilibrium theorem, that is, the average voltage of the magnetizing inductance of a switching period is zero, that is, . Magnetizing inductance In terms of time, the total time of the second, third and fifth stages is , voltage is The sixth phase is , the voltage is , applying the volt-second balance theorem to : , finishing available ,Correct In terms of By the third stage, we know ,therefore, . From the sixth stage, we know therefore, .

In the third stage, the fourth capacitor Voltage, can use Khreshow voltage theorem ( ) as follows:

In the sixth stage, the third capacitor The voltage can be obtained as follows:

The output voltage Can be obtained as follows:

Therefore the voltage gain of the converter can be expressed as .

As shown in Figure 11, the relationship between the voltage gain and the turn-on ratio under different coupling coefficients, when the coupled inductor turns ratio , the converter is in three different coupling coefficients , , with In the case of the voltage gain and the conduction ratio curve, it can be seen from the figure that the coupling coefficient has little effect on the voltage gain. If the leakage inductance of the coupled inductor is ignored, The ideal voltage gain M of the converter is as follows:

(when the coupling coefficient )

From the formula of the ideal voltage gain M, there are two design degrees of freedom for the voltage gain of the converter: the coupled inductor turns ratio And conduction ratio . By adjusting the coupling inductance turns ratio of the converter , the high boost can be achieved, and the converter does not need to operate at the maximum turn-on ratio.

As shown in Figure 12, it is the voltage gain and the turn-on ratio. And coupled inductor turns ratio The graph, as shown in the figure: When and When the voltage gain is 15 times, when and At the time, the voltage gain is 25 times.

<Switching voltage stress analysis>

If the capacitor chopping voltage and the leakage inductance of the coupled inductor are ignored (coupling coefficient) ), the switching element is considered ideal, ie the voltage drop is zero. From the third stage and the sixth stage, the first switch And second switch The voltage stresses are as follows:

Switching voltage stress is only available for output voltage Double, so you can choose to use a lower rated voltage of the metal oxide half field effect transistor (MOSFET), this component has a low on-resistance, which can reduce the on-power loss of the switch.

From the third and sixth stages, it can be found that the voltage stresses of the diodes D _C1 ~D _C2 and D ₁ ~D ₄ can be expressed as follows:

As shown in FIG. 13 , which is a graph of the power switch and the diode voltage stress and the coupled inductor turns ratio, the voltage stress of the power switch and the diode is normalized and the coupled inductor turns. Compared with the curve, the first switching voltage stress can be seen from the figure. And second switching voltage stress And diode voltage stress , , with Number of turns Increase and decrease. Diode voltage stress with Number of turns Increase and rise, but the voltage stress is still lower than the output voltage. Taking the turns ratio n=1 as an example, the first switch And the first switch And second clamp diode The voltage stress is 1/6 of the output voltage. First diode Second diode And the first clamp diode The voltage stress is 1/3 of the output voltage; the third diode And fourth diode The voltage stress is 1/3 of the output voltage.

In summary, the above embodiment has the following advantages:

1. The input parallel architecture of the converter can share the input current, so it is suitable for high input current applications.

2. The first switch S ₁ and the second switch S ₂ are interleaved, so that the chopping current on the primary side of the coupled inductor has a cancellation effect, which can reduce the input current ripple.

3. The third and fourth diodes D ₃ to D ₄ and the third and fourth capacitors C ₃ to C ₄ provide a voltage multiplication function, and are superimposed and outputted in series with the first and second capacitors C ₁ to C ₂ . The voltage gain is further increased, so that the converter can achieve high voltage gain without operating at a maximum turn-on ratio.

4. The voltage stress of the first switch S ₁ and the second switch S ₂ is much smaller than the output voltage, and a transistor with a lower rated withstand voltage and a smaller on-resistance can be used to reduce the conduction loss.

5. The leakage inductance of the coupled inductor mitigates the reverse recovery problem of the diode and also avoids the voltage surge problem of the switch. Therefore, it is suitable for high boost and high efficiency applications, and the object of the present invention can be achieved.

However, the above is only the embodiment of the present invention, and the scope of the invention is not limited thereto, and all the equivalent equivalent changes and modifications according to the scope of the patent application and the patent specification of the present invention are still The scope of the invention is covered.

1‧‧‧First coupled inductor

2‧‧‧Second coupled inductor

D _C1 ‧‧‧First Clamping Dipole

D _C2 ‧‧‧Second clamp diode

C _C1 ‧‧‧First Clamp Capacitor

C _C2 ‧‧‧Second clamp capacitor

D ₁ ‧‧‧First Diode

D ₂ ‧‧‧Secondary

D ₃ ‧‧‧third diode

D ₄ ‧‧‧fourth dipole

C ₁ ‧‧‧first capacitor

C ₂ ‧‧‧second capacitor

C ₃ ‧‧‧third capacitor

C ₄ ‧‧‧fourth capacitor

3‧‧‧Control unit

N _P1 ‧‧‧ primary winding

N _S1 ‧‧‧ primary winding

N _P2 ‧‧‧ secondary winding

N _S2 ‧‧‧ secondary winding

Vin‧‧‧Input voltage

Vo‧‧‧ output voltage

v _D1 ~v _D4 ‧‧‧cross pressure of the first to fourth diodes

v _DC1 ~v _DC2 ‧‧‧cross pressure of the first to second clamp diodes

V _C1 ‧‧‧cross pressure of the first capacitor

V _C2 ‧‧‧cross-voltage of the second capacitor

V _C3 ‧‧‧cross-voltage of the third capacitor

V _C4 ‧‧‧cross capacitance of the fourth capacitor

i _D1 ‧‧‧current flowing through the first diode

i _D2 ‧‧‧current flowing through the second diode

i _D3 ‧‧‧current flowing through the third diode

i _D4 ‧‧‧current flowing through the fourth diode

Other features and effects of the present invention will be apparent from the following description of the drawings, wherein: Figure 1 is a circuit diagram of a conventional boost converter; Figure 2 is a high boost converter of the present invention. FIG. 3 is an equivalent circuit diagram of the embodiment; FIG. 4 is an operational timing diagram of the embodiment; FIG. 5 is a circuit diagram of the operation of the embodiment in the first stage; The embodiment is a circuit diagram of the second stage; FIG. 7 is a circuit diagram of the embodiment operating in the third stage; FIG. 8 is a circuit diagram of the embodiment operating in the fourth stage; FIG. 10 is a circuit diagram of the sixth stage of the embodiment; FIG. 11 is a relationship diagram of different coupling coefficients and voltage gains of the embodiment; FIG. 12 is a coupled inductor of the embodiment. A voltage gain graph of the ratio and the turn-on ratio; and FIG. 13 is a graph of the switch-to-diode voltage stress and the coupled inductor turns ratio of the embodiment.

Claims (7)

A high boost converter includes: a first coupled inductor and a second coupled inductor, each coupled inductor having a primary side winding and a secondary side winding, each side winding having a first end and a second side The first ends of the primary windings of the first and second coupled inductors are electrically connected together to receive a DC input voltage, and the second end of the secondary winding of the first coupled inductor is electrically connected to the second coupling a second end of the secondary winding of the inductor; a first switch having a first end electrically connected to the second end of the first side winding of the first coupled inductor and a grounded second end, and controlled to be switched on And a second switch having a first end electrically connected to the second end of the second side of the second coupled inductor and a grounded second end, and controlled to be switched between conducting and non-conducting; a first clamping diode having an anode electrically connected to the second end of the primary winding of the first coupled inductor, and a cathode; a first clamping capacitor electrically connected to the first clamping diode Cathode and the second coupled electric a second clamping terminal of the primary winding; a second clamping diode having a cathode electrically connected to the second end of the second switch; and an anode; a second clamping capacitor electrically connected to the second a cathode of the clamp diode and a first end of the second switch; a first diode having an anode; and a cathode electrically connected to the anode of the second clamp diode; a pole having an anode electrically connected to the cathode of the first clamp diode and a cathode; a third diode having an anode electrically connected to the cathode of the second diode, and an electrical connection a cathode of the first end of the secondary winding of the first coupled inductor; a fourth diode having an anode electrically connected to the cathode of the first end of the secondary winding of the first coupled inductor, and a cathode a first capacitor electrically connected between the second end of the primary winding of the first coupled inductor and the anode of the first diode; a second capacitor electrically connected to the primary side of the first coupled inductor a second end of the winding and a cathode of the second diode; a third capacitor electrically connected to a first end of the second side winding of the second coupled inductor and a cathode of the second diode; and a fourth capacitor electrically connected to the first end of the second side winding of the second coupled inductor Between the cathodes of the fourth diode. The high boost converter of claim 1, wherein the first end of each primary side winding is a striking end, and the second end of each primary side winding is a non-tapping end. The high boost converter of claim 1, wherein the first end of each secondary winding is a striking end, and the second end of each secondary winding is a non-tapping end. The high-boost converter of claim 1, wherein the first switch is an N-type power semiconductor transistor, and the first end of the first switch is a drain, and the second end of the first switch is Source. The high-boost converter of claim 1, wherein the second switch is an N-type power semiconductor transistor, and the first end of the second switch is a drain, and the second end of the second switch is Source. The high boost converter of claim 1, further comprising a control unit, wherein the control unit generates a first pulse signal for switching the first switch and a second pulse signal for switching the second switch, The first pulse signal has the same cycle time as the second pulse signal. The high-boost converter of claim 1, wherein a portion of the on-time of the first switch overlaps a portion of an on-time of the second switch.