TWI580166B - Interleaved boost converter - Google Patents
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Description
本發明是有關於一種轉換器,特別是指一種交錯式升壓轉換器。This invention relates to a converter, and more particularly to an interleaved boost converter.
習知的升壓轉換器操作在極高導通比才能達到較高電壓增益,但是實務上受到寄生元件的影響,其電壓轉換比受限在約5倍以下,因此為符合電壓增益超過5倍的需求時,須研發具有高升壓的電壓轉換器。The conventional boost converter operates at a very high turn-on ratio to achieve a higher voltage gain, but is practically affected by parasitic components, and its voltage conversion ratio is limited to less than about 5 times, so that the voltage gain is more than 5 times. When needed, a voltage converter with a high boost must be developed.
因此,本發明之目的,即在提供一種具有高升壓的交錯式升壓轉換器。Accordingly, it is an object of the present invention to provide an interleaved boost converter having a high boost.
於是,本發明交錯式升壓轉換器,包含第一至第二變壓器、第一至第二輸入電容、第一至第六二極體、第一至第二開關,及第一至第三輸出電容。Accordingly, the interleaved boost converter of the present invention includes first to second transformers, first to second input capacitors, first to sixth diodes, first to second switches, and first to third outputs capacitance.
每一個變壓器具有一個一次側繞組、一個二次側繞組及一個三次側繞組,每一個側繞組具有一第一端及一第二端,該第一及第二變壓器的一次側繞組的第一端電連接一起以接收一呈直流的輸入電壓。該第一變壓器的三次側繞組的第二端電連接該該第二變壓器的三次側繞組的第二端Each transformer has a primary side winding, a secondary side winding and a tertiary side winding, each side winding having a first end and a second end, the first end of the primary winding of the first and second transformers Electrically connected together to receive a DC input voltage. a second end of the tertiary winding of the first transformer is electrically connected to a second end of the tertiary winding of the second transformer
第一輸入電容電連接於該第一變壓器的一次側繞組的第二端與該第一變壓器的二次側繞組的第一端之間。第二輸入電容電連接於該第二變壓器的一次側繞組的第一端與該第二變壓器的二次側繞組的第一端之間。The first input capacitor is electrically connected between the second end of the primary side winding of the first transformer and the first end of the secondary winding of the first transformer. The second input capacitor is electrically coupled between the first end of the primary side winding of the second transformer and the first end of the secondary winding of the second transformer.
第一二極體具有一電連接該第二變壓器的一次側繞組的第二端的陽極及一電連接該第一變壓器的二次側繞組的第一端的陰極。第二二極體具有一電連接該第一變壓器的一次側繞組的第二端的陽極及一電連接該第二變壓器的二次側繞組的第一端的陰極。The first diode has an anode electrically connected to the second end of the primary winding of the second transformer and a cathode electrically connected to the first end of the secondary winding of the first transformer. The second diode has an anode electrically connected to the second end of the primary winding of the first transformer and a cathode electrically connected to the first end of the secondary winding of the second transformer.
第一開關具有一電連接於該第一變壓器的一次側繞組的第二端的第一端,及一接地的第二端,且該第一開關受控制以切換於導通狀態和不導通狀態間。第二開關具有一電連接於該第二變壓器的一次側繞組的第二端的第一端,及一接地的第二端,且該第二開關受控制以切換於導通狀態和不導通狀態間。The first switch has a first end electrically connected to the second end of the primary side winding of the first transformer, and a grounded second end, and the first switch is controlled to switch between the conducting state and the non-conducting state. The second switch has a first end electrically connected to the second end of the primary side winding of the second transformer, and a grounded second end, and the second switch is controlled to switch between the conducting state and the non-conducting state.
第三二極體具有一電連接該第一變壓器的二次側繞組的第二端的陽極及一陰極。第四二極體具有一電連接該第二變壓器的二次側繞組的第二端的陽極及一電連接該第三二極體的陰極的陰極。The third diode has an anode electrically connected to the second end of the secondary winding of the first transformer and a cathode. The fourth diode has an anode electrically connected to the second end of the secondary winding of the second transformer and a cathode electrically connected to the cathode of the third diode.
第一輸出電容具有一電連接該第三二極體的陰極的第一端及一接地的第二端。第二輸出電容具有一電連接該第二變壓器的三次側繞組的第一端及一電連接該第三二極體的陰極的的第二端。第三輸出電容具有一第一端及一電連接該第二輸出電容的第一端的第二端。The first output capacitor has a first end electrically connected to the cathode of the third diode and a grounded second end. The second output capacitor has a first end electrically connected to the tertiary side winding of the second transformer and a second end electrically connected to the cathode of the third diode. The third output capacitor has a first end and a second end electrically connected to the first end of the second output capacitor.
第五二極體具有一個電連接該第三輸出電容的第一端的陰極,及一電連接該第一變壓器的三次側繞組的第一端的陽極。第六二極體具有一個電連接該第一變壓器的三次側繞組的第一端的陰極,及一電連接該第二輸出電容的第二端的陽極。The fifth diode has a cathode electrically connected to the first end of the third output capacitor, and an anode electrically connected to the first end of the tertiary winding of the first transformer. The sixth diode has a cathode electrically connected to the first end of the tertiary winding of the first transformer, and an anode electrically connected to the second end of the second output capacitor.
本發明之功效在於:不必操作在極大的責任導通比,即可達成高電壓增益,以符合現今高電壓增益的應用。The effect of the present invention is that high voltage gain can be achieved without having to operate at a great duty-conductance ratio to meet today's high voltage gain applications.
在本發明被詳細描述之前,應當注意在以下的說明內容中,類似的元件是以相同的編號來表示。Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.
參閱圖1,本發明交錯式升壓轉換器之一實施例,包含一個第一變壓器T1、一個第二變壓器T2、一個第一輸入電容CI1、一個第二輸入電容CI2、一個第一二極體D1、一個第二二極體D2、一個第三二極體D3、一個第四二極體D4、一個第五二極體D5、一個第六二極體D6、一個第一開關S1、一個第二開關S2、一個第一輸出電容C1、一個第二輸出電容C2、一個第三輸出電容C3,及一控制單元2。Referring to FIG. 1, an embodiment of an interleaved boost converter of the present invention includes a first transformer T1, a second transformer T2, a first input capacitor CI1, a second input capacitor CI2, and a first diode. D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a first switch S1, a first The second switch S2, a first output capacitor C1, a second output capacitor C2, a third output capacitor C3, and a control unit 2.
第一變壓器T1具有一個一次側繞組NP1及一個二次側繞組NP2及一個三次側繞組NP3,第二變壓器T2具有一個一次側繞組NS1及一個二次側繞組NS2及一個三次側繞組NS3,每一個側繞組NP1~NP3、NS1~NS3具有一第一端及一第二端,該第一及第二變壓器T1、T2的一次側繞組NP1、NS1的第一端電連接一起以接收一呈直流的輸入電壓Vin及一輸入電流Iin,該第一變壓器T3的三次側繞組NP3的第二端電連接該該第二變壓器T2的三次側繞組NS3的第二端。每一個一次側繞組NP1、NS1的第一端是極性點端,每一個一次側繞組NP1、NS1的第二端是非極性點端。每一個二次側繞組NP2、NS2的第一端是極性點端,每一個二次側繞組NP2、NS2的第二端是非極性點端。每一個三次側繞組NP3、NS3的第一端是極性點端,每一個三次側繞組NP3、NS3的第二端是非極性點端。該第一及第二變壓器T1、T2的匝數比相等。The first transformer T1 has a primary side winding NP1 and a secondary side winding NP2 and a tertiary side winding NP3. The second transformer T2 has a primary side winding NS1 and a secondary side winding NS2 and a tertiary side winding NS3, each of which The side windings NP1~NP3, NS1~NS3 have a first end and a second end, and the first ends of the primary windings NP1, NS1 of the first and second transformers T1, T2 are electrically connected together to receive a direct current The input voltage Vin and an input current Iin, the second end of the tertiary side winding NP3 of the first transformer T3 is electrically connected to the second end of the tertiary side winding NS3 of the second transformer T2. The first end of each of the primary side windings NP1, NS1 is a polarity point end, and the second end of each of the primary side windings NP1, NS1 is a non-polar point end. The first end of each of the secondary windings NP2, NS2 is a polarity point end, and the second end of each of the secondary side windings NP2, NS2 is a non-polar point end. The first end of each of the tertiary side windings NP3, NS3 is a polarity point end, and the second end of each of the tertiary side windings NP3, NS3 is a non-polar point end. The turns ratios of the first and second transformers T1, T2 are equal.
第一輸入電容CI1電連接於該第一變壓器T1的一次側繞組NP1的第二端與該第一變壓器T1的二次側繞組NP2的第一端之間。第二輸入電容CI2電連接於該第二變壓器T2的一次側繞組NS1的第一端與該第二變壓器T2的二次側繞組NS2的第一端之間。The first input capacitor CI1 is electrically connected between the second end of the primary side winding NP1 of the first transformer T1 and the first end of the secondary winding NP2 of the first transformer T1. The second input capacitor CI2 is electrically connected between the first end of the primary side winding NS1 of the second transformer T2 and the first end of the secondary side winding NS2 of the second transformer T2.
第一二極體D1具有一電連接該第二變壓器T2的一次側繞組NS1的第二端的陽極及一電連接該第一變壓器T1的二次側繞組NP2的第一端的陰極。第二二極體D2具有一電連接該第一變壓器T1的一次側繞組NP1的第二端的陽極及一電連接該第二變壓器T2的二次側繞組NS2的第一端的陰極。The first diode D1 has an anode electrically connected to the second end of the primary winding NS1 of the second transformer T2 and a cathode electrically connected to the first end of the secondary winding NP2 of the first transformer T1. The second diode D2 has an anode electrically connected to the second end of the primary winding NP1 of the first transformer T1 and a cathode electrically connected to the first end of the secondary winding NS2 of the second transformer T2.
第一開關S1具有一電連接於該第一變壓器T1的一次側繞組NP1的第二端的第一端,及一接地的第二端,且該第一開關S1受控制以切換於導通狀態和不導通狀態間。該第一開關S1是一N型功率半導體電晶體,且該第一開關S1的第一端是汲極,該第一開關S1的第二端是源極。第二開關S2具有一電連接於該第二變壓器T2的一次側繞組NS1的第二端的第一端,及一接地的第二端,且該第二開關S2受控制以切換於導通狀態和不導通狀態間。該第二開關S2是一N型功率半導體電晶體,且該第二開關S2的第一端是汲極,該第二開關S2的第二端是源極。The first switch S1 has a first end electrically connected to the second end of the primary winding NP1 of the first transformer T1, and a grounded second end, and the first switch S1 is controlled to switch to the conducting state and not Between on state. The first switch S1 is an N-type power semiconductor transistor, and the first end of the first switch S1 is a drain, and the second end of the first switch S1 is a source. The second switch S2 has a first end electrically connected to the second end of the primary winding NS1 of the second transformer T2, and a grounded second end, and the second switch S2 is controlled to switch to the conducting state and not Between on state. The second switch S2 is an N-type power semiconductor transistor, and the first end of the second switch S2 is a drain, and the second end of the second switch S2 is a source.
第三二極體D3具有一電連接該第一變壓器T1的二次側繞組NP2的第二端的陽極及一陰極。第四二極體D4具有一電連接該第二變壓器T2的二次側繞組NS2的第二端的陽極及一電連接該第三二極體D3的陰極的陰極。The third diode D3 has an anode electrically connected to the second end of the secondary winding NP2 of the first transformer T1 and a cathode. The fourth diode D4 has an anode electrically connected to the second end of the secondary winding NS2 of the second transformer T2 and a cathode electrically connected to the cathode of the third diode D3.
第一輸出電容C1具有一電連接該第三二極體D3的陰極的第一端及一接地的第二端。第二輸出電容C2具有一電連接該第二變壓器T2的三次側繞組NS3的第一端的第一端及一電連接該第三二極體D3的陰極的的第二端。第三輸出電容C3具有一第一端及一電連接該第二輸出電容C2的第一端的第二端。The first output capacitor C1 has a first end electrically connected to the cathode of the third diode D3 and a grounded second end. The second output capacitor C2 has a first end electrically connected to the first end of the tertiary side winding NS3 of the second transformer T2 and a second end electrically connected to the cathode of the third diode D3. The third output capacitor C3 has a first end and a second end electrically connected to the first end of the second output capacitor C2.
第五二極體D5具有一個電連接該第三輸出電容C3的第一端的陰極,及一電連接該第一變壓器T1的三次側繞組NP3的第一端的陽極。第六二極體D6具有一個電連接該第一變壓器T1的三次側繞組NP3的第一端的陰極,及一電連接該第二輸出電容C2的第二端的陽極。The fifth diode D5 has a cathode electrically connected to the first end of the third output capacitor C3, and an anode electrically connected to the first end of the tertiary side winding NP3 of the first transformer T1. The sixth diode D6 has a cathode electrically connected to the first end of the tertiary side winding NP3 of the first transformer T1, and an anode electrically connected to the second end of the second output capacitor C2.
該控制單元2產生一切換該第一開關S1的第一脈波調變信號及一切換該第二開關S2的第二脈波調變信號,該第一脈波調變信號與該第二脈波調變信號具有相同的周期時間。該第一及第二脈波調變信號的相位差為周期時間的二分之一。The control unit 2 generates a first pulse modulation signal for switching the first switch S1 and a second pulse modulation signal for switching the second switch S2, the first pulse modulation signal and the second pulse Wave modulation signals have the same cycle time. The phase difference between the first and second pulse modulation signals is one-half of the cycle time.
參閱圖2,為本實施例的操作時序圖,其中,參數 V gs1、V gs2分別代表控制該第一及第二開關S1、S2是否導通的第一及第二脈波調變信號的電壓,參數T S為第一脈波調變信號的週期時間,參數D為第一及第二開關S1、S2的責任導通週期,參數I1表示流經該第一變壓器T1的一次側繞組NP1的電流,參數I2分別表示流經該第二變壓器T2的一次側繞組NS1的電流,參數i D1~i D6分別代表流過第一至第六二極體D1~D6的電流,參數i LS代表第一及第二變壓器T1、T2的三次側繞組的漏電感電流,參數 表示流過漏電感電流i LS的最大值,參數 表示漏電感電流i LS的最小值,參數I O代表輸出電流,參數i C2代表第二電容C2提供的電流,參數i C3代表第三電容C3提供的電流,參數T 2的定義將在以下再作說明。 Referring to FIG. 2, an operation timing diagram of the embodiment, wherein the parameters V gs1 and V gs2 respectively represent voltages of the first and second pulse modulation signals that control whether the first and second switches S1 and S2 are turned on. The parameter T S is the cycle time of the first pulse modulation signal, the parameter D is the duty conduction period of the first and second switches S1 and S2, and the parameter I1 represents the current flowing through the primary winding NP1 of the first transformer T1. The parameter I2 represents the current flowing through the primary winding NS1 of the second transformer T2, respectively, and the parameters i D1 to i D6 represent the currents flowing through the first to sixth diodes D1 to D6, respectively, and the parameter i LS represents the first and Leakage inductance current of the third side winding of the second transformer T1, T2, parameters Indicates the maximum value of the leakage inductor current i LS flowing through the parameter Indicates the minimum value of the leakage inductor current i LS , the parameter I O represents the output current, the parameter i C2 represents the current supplied by the second capacitor C2, and the parameter i C3 represents the current supplied by the third capacitor C3. The definition of the parameter T 2 will be Give instructions.
以下為本實施例操作於十階段的各電路圖,其中,導通的元件以實線表示,不導通的元件以虛線表示,且更說明該第一至第二變壓器T1~T2的一次側繞組NP1、NS1的非理想等效電路中的磁化電感Lm1、Lm2,及該第一至第二變壓器T2的三次側繞組NP3、NS3的非理想等效電路中的漏電感LS,以下將在下列假設下:成圖2中本專利提出之嶄新能量回饋型交錯式高升壓轉換器的電路拓樸,接下來先對嶄新能量回饋型交錯式高升壓轉換器之電路動作原理作詳細的分析,以確定轉換器之高升壓性能,及確認電路動作的正確性。在分析前,會先做下列說明與假設:(1)第一開關S1與第二開關S2以180°的相位差交錯驅動。(2)操作在連續導通模式(CCM)。(3)已達到穩態。(4)電路中所有開關S1~S2及二極體D1~D6皆為理想元件。(5)電路中所有電感以及電容皆為理想元件,不具有寄生阻抗。(6)第一至第三輸出電容C1~C3與第一至第二輸入電容CI1~CI2相當大,可忽略電壓漣波,使得電容電壓為常數,而使電容電壓可視為電壓源,輸出電壓Vo視為常數。(7)第一及第二變壓器的磁化電感值皆相等。且第一至第二變壓器T1、T2的匝數比皆相同。以下分別針對每一階段進行說明。The following is a circuit diagram of the ten stages of the present embodiment, wherein the conductive elements are indicated by solid lines, the non-conducting elements are indicated by broken lines, and the primary windings NP1 of the first to second transformers T1 to T2 are further illustrated. The magnetizing inductances Lm1, Lm2 in the non-ideal equivalent circuit of NS1, and the leakage inductance LS in the non-ideal equivalent circuit of the tertiary side windings NP3, NS3 of the first to second transformers T2, will be as follows: In the circuit topology of the new energy feedback type interleaved high-boost converter proposed in this patent in Fig. 2, the circuit operation principle of the new energy feedback type interleaved high-boost converter is analyzed in detail to determine The high boost performance of the converter and the correctness of the circuit operation. Before the analysis, the following explanations and assumptions will be made: (1) The first switch S1 and the second switch S2 are alternately driven with a phase difference of 180°. (2) Operation in continuous conduction mode (CCM). (3) The steady state has been reached. (4) All switches S1~S2 and diodes D1~D6 in the circuit are ideal components. (5) All inductors and capacitors in the circuit are ideal components and do not have parasitic impedance. (6) The first to third output capacitors C1 to C3 are relatively large with the first to second input capacitors CI1 to CI2, and the voltage chopping can be ignored, so that the capacitor voltage is constant, and the capacitor voltage can be regarded as a voltage source and an output voltage. Vo is considered a constant. (7) The magnetization inductance values of the first and second transformers are all equal. And the turns ratios of the first to second transformers T1 and T2 are the same. The following is a description of each stage.
預備階段(時間:t~t0 ):Preparatory phase (time: t~t0):
參閱圖2及圖3,第一開關S1導通,第二開關S2導通,第一二極體D1不導通,第二二極體S2不導通,第三二極體D3不導通,第四二極體D4不導通,第五二極體D5不導通,第六二極體D6不導通。Referring to FIG. 2 and FIG. 3, the first switch S1 is turned on, the second switch S2 is turned on, the first diode D1 is not turned on, the second diode S2 is not turned on, and the third diode D3 is not turned on, and the fourth diode is not turned on. The body D4 is not turned on, the fifth diode D5 is not turned on, and the sixth diode D6 is not turned on.
預備階段時,由於輸入電壓Vin跨於磁化電感Lm1、Lm2上,使其電流i Lm1、i Lm2皆以斜率 線性上升。當第一開關S1由導通切換至不導通時,則進入在第一階段。以下,參數L m1、L m2、L S分別表示磁化電感Lm1、Lm2、漏電感LS的電感值。參數V CI1、V CI2分別表示第一及第二輸入電容CI1、CI2的電壓值。參數n表示第一變壓器T1的一次側繞組NP1與二次側繞組NP2的匝數比。在本實施例中,參數L m1相同於參數L m2。 In the preliminary stage, since the input voltage Vin is across the magnetizing inductances Lm1 and Lm2, the currents i Lm1 and i Lm2 are both sloped. Linear rise. When the first switch S1 is switched from on to off, it enters the first stage. Hereinafter, the parameters L m1 , L m2 , and L S represent the inductance values of the magnetizing inductances Lm1 and Lm2 and the leakage inductance LS, respectively. The parameters V CI1 and V CI2 indicate the voltage values of the first and second input capacitors CI1 and CI2, respectively. The parameter n represents the turns ratio of the primary side winding NP1 of the first transformer T1 to the secondary side winding NP2. In the present embodiment, the parameter L m1 is the same as the parameter L m2 .
第一階段(時間:t0~t1 ):The first stage (time: t0~t1):
參閱圖2及圖4,第一開關S1不導通,第二開關S2導通,第一二極體D1不導通,第二二極體D2導通,第三二極體D3導通,第四二極體D4不導通,第五二極體D5不導通,第六二極體D6導通。Referring to FIG. 2 and FIG. 4, the first switch S1 is not turned on, the second switch S2 is turned on, the first diode D1 is not turned on, the second diode D2 is turned on, the third diode D3 is turned on, and the fourth diode is turned on. D4 is not conducting, the fifth diode D5 is not conducting, and the sixth diode D6 is conducting.
此時第二二極體D2因電感電流需保持連續而導通且第一開關S1的跨壓被第二輸入電容CI2的電壓箝位。第三二極體D3因電流連續而導通,且電流i D3流經第一變壓器T1的二次側繞組NS1而使電流能量反饋至第一變壓器T1的一次側繞組NP1的第一端,得以降低所接收的輸入電流Iin。此時磁化電感Lm1因跨固定電壓則電流i Lm1皆以斜率 線性下降,其中,參數V CI2為第二輸入電容CI2的電壓,而漏電感電流i LS則以斜率 線性上升。當漏電感電流i LS上升至等同輸出電流Io時,會使第二輸出電容C2的電流i C2換向,而進入第二階段。 At this time, the second diode D2 needs to be kept continuous due to the inductor current, and the voltage across the first switch S1 is clamped by the voltage of the second input capacitor CI2. The third diode D3 is turned on by the continuous current, and the current i D3 flows through the secondary winding NS1 of the first transformer T1 to feed back the current energy to the first end of the primary winding NP1 of the first transformer T1, thereby being reduced. The input current Iin received. At this time, the magnetizing inductance Lm1 has a slope of current i Lm1 due to a fixed voltage. Linear decrease, where the parameter V CI2 is the voltage of the second input capacitor CI2, and the leakage inductor current i LS is the slope Linear rise. When the leakage inductor current i LS rises to the equivalent output current Io, the current i C2 of the second output capacitor C2 is commutated to enter the second stage.
第二階段(時間:t1~t2 ):The second stage (time: t1~t2):
參閱圖2及圖5,第一開關S1不導通,第二開關S2導通,第一二極體D1不導通,第二二極體D2導通,第三二極體D3導通,第四二極體D4不導通,第五二極體D5不導通,第六二極體D6導通。Referring to FIG. 2 and FIG. 5, the first switch S1 is not turned on, the second switch S2 is turned on, the first diode D1 is not turned on, the second diode D2 is turned on, the third diode D3 is turned on, and the fourth diode is turned on. D4 is not conducting, the fifth diode D5 is not conducting, and the sixth diode D6 is conducting.
當第二輸出電容C2的電流i C2換向後,開始對第二輸出電容C2做充電。當第一開關S1由不導通切換至導通時,則進入第三階段。 After the current i C2 of the second output capacitor C2 is commutated, charging of the second output capacitor C2 begins. When the first switch S1 is switched from non-conducting to conducting, it enters the third stage.
第三階段(時間:t2~t3 ):The third stage (time: t2~t3):
參閱圖2及圖6,第一開關S1導通,第二開關S2導通,第一二極體D1不導通,第二二極體D2不導通,第三二極體D3不導通,第四二極體D4不導通,第五二極體D5不導通,第六二極體D6導通。Referring to FIG. 2 and FIG. 6, the first switch S1 is turned on, the second switch S2 is turned on, the first diode D1 is not turned on, the second diode D2 is not turned on, and the third diode D3 is not turned on, and the fourth diode is not turned on. The body D4 is not turned on, the fifth diode D5 is not turned on, and the sixth diode D6 is turned on.
本階段第一開關S1由不導通轉變為導通,第二開關S2保持為導通,此階段第二二極體D2與第三二極體D3因為逆偏而由導通轉變為不導通。因漏電感LS的電流i LS需保持連續,故第六二極體D6保持導通,此時磁化電感Lm1因跨固定電壓則電流i Lm1皆以斜率 線性上升,磁化電感Lm2跨固定電壓則電流i Lm2皆以斜率 線性下降,其中參數V C2為第二輸出電容C2的電壓,而呈負電壓的第二輸出電容C2的電壓而跨於漏電感LS上,使其電流i C2以斜率 線性下降。當漏電感LS的電流i LS下降至等同輸出電流Io,第二輸出電容C2的電流i C2換向,則進入第四階段。 At this stage, the first switch S1 is turned from non-conducting to conducting, and the second switch S2 is kept turned on. At this stage, the second diode D2 and the third diode D3 are turned on from the conduction to the non-conduction due to the reverse bias. Due to leakage inductance LS LS current I required to maintain a continuous, it remains the sixth diode D6 is turned on, then the magnetizing inductance Lm1 because the voltage across the fixed current I begin slope Lm1 Linear rise, magnetization inductance Lm2 across a fixed voltage, current i Lm2 is slope Linear decrease, wherein the parameter V C2 is the voltage of the second output capacitor C2, and the voltage of the second output capacitor C2, which is a negative voltage, straddles the leakage inductance LS, causing the current i C2 to have a slope Linear decline. When the current i LS of the leakage inductance LS falls to the equivalent output current Io, and the current i C2 of the second output capacitor C2 is commutated, the fourth stage is entered.
第四階段(時間:t3~t4 ):The fourth stage (time: t3~t4):
參閱圖2及圖7,第一開關S1導通,第二開關S2導通,第一二極體D1不導通,第二二極體D2不導通,第三二極體D3不導通,第四二極體D4不導通,第五二極體D5不導通,第六二極體D6導通。Referring to FIG. 2 and FIG. 7, the first switch S1 is turned on, the second switch S2 is turned on, the first diode D1 is not turned on, the second diode D2 is not turned on, and the third diode D3 is not turned on, and the fourth diode is not turned on. The body D4 is not turned on, the fifth diode D5 is not turned on, and the sixth diode D6 is turned on.
本階段第一及第二開關S1、S2保持為導通,此階段第一至第四二極體D1~D4因逆偏保持為不導通。在第二輸出電容C2的電流i C2換向後,則開始對負載釋放能量。 At this stage, the first and second switches S1 and S2 are kept in conduction, and at this stage, the first to fourth diodes D1 to D4 are kept non-conductive due to the reverse bias. After the current i C2 of the second output capacitor C2 is commutated, energy is released to the load.
當漏電感LS的電流i LS下降至0,會使第六二極體D6由導通轉變為不導通,而進入第五階段。 When the current i LS of the leakage inductance LS drops to 0, the sixth diode D6 is turned from conduction to non-conduction, and enters the fifth stage.
第五階段(時間:t4~t5 ):The fifth stage (time: t4~t5):
參閱圖2及圖8,第一開關S1導通、第二開關S2導通、第一二極體D1:不導通、第二二極體D2不導通、第三二極體D3不導通、第四二極體D4不導通、第五二極體D5不導通、第六二極體D6不導通。Referring to FIG. 2 and FIG. 8 , the first switch S1 is turned on, the second switch S2 is turned on, the first diode D1 is not turned on, the second diode D2 is not turned on, and the third diode D3 is not turned on, and the fourth two The polar body D4 is not turned on, the fifth diode D5 is not turned on, and the sixth diode D6 is not turned on.
本階段當第六二極體D6由導通轉變為不導通,則第一及第二開關S1、S2保持為導通,此時磁化電感Lm1、Lm2皆因跨輸入電壓Vin則電流i Lm1、i Lm2皆以斜率 線性上升。當第二開關S2由導通切換至不導通時,則進入第六階段。 At this stage, when the sixth diode D6 is turned from non-conducting to non-conducting, the first and second switches S1 and S2 remain conductive. At this time, the magnetizing inductances Lm1 and Lm2 are currents i Lm1 and i Lm2 due to the input voltage Vin. Slope Linear rise. When the second switch S2 is switched from on to non-conducting, the sixth stage is entered.
第六階段(時間:t5~t6 ):The sixth stage (time: t5~t6):
參閱圖2及圖9,第一開關S1導通、第二開關S2不導通、第一二極體D1導通、第二二極體D2不導通、第三二極體D3不導通、第四二極體D4導通、第五二極體D5導通、第六二極體D6不導通。Referring to FIG. 2 and FIG. 9, the first switch S1 is turned on, the second switch S2 is not turned on, the first diode D1 is turned on, the second diode D2 is not turned on, the third diode D3 is not turned on, and the fourth diode is turned on. The body D4 is turned on, the fifth diode D5 is turned on, and the sixth diode D6 is not turned on.
本階段,第一開關S1保持為導通,第二開關S2由導通轉變為不導通,此時第一二極體D1因電感電流需保持連續而導通且第二開關S2跨壓被第一輸入電容CI1的電壓V CI1箝位, 。第四二極體D4因電流i D4連續而導通,且電流i D4流經第二變壓器T2的二次側繞組NS2而使電流能量反饋至第二變壓器T2的一次側繞組NP2的第一端,得以降低所接收的輸入電流Iin。而 必須大於0,才能使第五二極體D5導通,此時磁化電感Lm2因跨固定電壓則電流i Lm2以斜率 線性下降,漏電感電流i LS則因為跨固定負電壓而以斜率 線性下降。當漏電感電流i LS下降至負的輸出電流-Io時,會使第三輸出電容C3的電流i C3換向,而進入第七階段。 At this stage, the first switch S1 is kept conductive, and the second switch S2 is turned from non-conducting. At this time, the first diode D1 needs to be kept continuous due to the inductor current and the second switch S2 is biased by the first input capacitor. CI1 voltage V CI1 clamp, . The fourth diode D4 is continuously turned on by the current i D4 , and the current i D4 flows through the secondary winding NS2 of the second transformer T2 to feed back the current energy to the first end of the primary winding NP2 of the second transformer T2. The received input current Iin can be reduced. and Must be greater than 0 to make the fifth diode D5 turn on. At this time, the magnetizing inductance Lm2 has a slope of current i Lm2 due to a fixed voltage. Linear drop, leakage inductance current i LS is due to the slope across a fixed negative voltage Linear decline. When the leakage inductor current i LS drops to a negative output current -Io, the current i C3 of the third output capacitor C3 is commutated to enter the seventh stage.
第七階段(時間:t6~t7 ):The seventh stage (time: t6~t7):
參閱圖2及圖10,第一開關S1:導通、第二開關S2:不導通、第一二極體D1:導通、第二二極體D2:不導通、第三二極體D3:不導通、第四二極體D4:導通、第五二極體D5:導通、第六二極體D6:不導通。Referring to FIG. 2 and FIG. 10, the first switch S1: conductive, the second switch S2: non-conducting, the first diode D1: conducting, the second diode D2: non-conducting, the third diode D3: non-conducting , the fourth diode D4: conduction, the fifth diode D5: conduction, the sixth diode D6: non-conduction.
本階段第一開關S1保持為導通,第二開關S2保持為不導通,在第三輸出電容C3的電流i C3電流換向後,開始對第三輸出電容C3做充電。當第二開關S2由不導通轉變為導通,則進入第八階段。 At this stage, the first switch S1 remains conductive, and the second switch S2 remains non-conductive. After the current i C3 current of the third output capacitor C3 is commutated, the third output capacitor C3 is charged. When the second switch S2 is turned from non-conducting to conducting, the eighth stage is entered.
第八階段(時間:t7~t8 ):The eighth stage (time: t7~t8):
參閱圖2及圖11,第一開關S1:導通、第二開關S2:導通、第一二極體D1:不導通、第二二極體D2:不導通、第三二極體D3:不導通、第四二極體D4:不導通、第五二極體D5:導通、第六二極體D6:不導通。Referring to FIG. 2 and FIG. 11, the first switch S1: the conduction, the second switch S2: the conduction, the first diode D1: the non-conduction, the second diode D2: the non-conduction, the third diode D3: the non-conduction 4th diode D4: non-conducting, fifth diode D5: conducting, sixth diode D6: non-conducting.
本階段第一開關S1保持為導通,第二開關S2由不導通轉變為導通,此階段因漏電感電流i Ls需保持連續,故第五二極體D5保持導通,此時磁化電感Lm1因跨固定電壓則電流i Lm1以斜率 線性下降,磁化電感Lm2跨固定電壓則電流i Lm2以斜率 線性上升,而漏電感LS跨呈正電壓的第三輸出電容C3的電壓V C3而以斜率 線性上升。當漏電感電流i Ls上升至負的輸出電流-Io時,會使第三輸出電容C3的電流i C3電流換向,則進入第九階段。 At this stage, the first switch S1 is kept conductive, and the second switch S2 is turned from non-conducting to conducting. At this stage, the leakage inductor current i Ls needs to be kept continuous, so the fifth diode D5 remains conductive, and the magnetizing inductance Lm1 is crossed. Fixed voltage, current i Lm1 with slope Linear decline, magnetization inductance Lm2 across a fixed voltage, current i Lm2 slope Linear rise, while the leakage inductance LS spans the voltage V C3 of the third output capacitor C3 that is a positive voltage with a slope Linear rise. When the leakage inductor current i Ls rises to a negative output current -Io, the current i C3 current of the third output capacitor C3 is commutated, and the ninth stage is entered.
第九階段(時間:t8~t9 ):The ninth stage (time: t8~t9):
參閱圖2及圖12,第一開關S1:導通、第二開關S2:導通、第一二極體D1:不導通、第二二極體D2:不導通、第三二極體D3:不導通、第四二極體D4:不導通、第五二極體D5:導通、第六二極體D6:不導通。Referring to FIG. 2 and FIG. 12, the first switch S1: the conduction, the second switch S2: the conduction, the first diode D1: the non-conduction, the second diode D2: the non-conduction, the third diode D3: the non-conduction 4th diode D4: non-conducting, fifth diode D5: conducting, sixth diode D6: non-conducting.
本階段第一開關S1保持為導通,第二開關S2保持為導通,在第三輸出電容CI3的電流i C3電流換向後,第三輸出電容C3對負載釋放能量。當漏電感電流i Ls上升至0,會使第五二極體D5由導通轉變為不導通,則進入第十階段。 At this stage, the first switch S1 remains conductive, and the second switch S2 remains conductive. After the current i C3 current of the third output capacitor CI3 is commutated, the third output capacitor C3 releases energy to the load. When the leakage inductor current i Ls rises to zero, the fifth diode D5 is turned from non-conducting to non-conducting, and then enters the tenth stage.
第十階段(時間:t9~t10 ):The tenth stage (time: t9~t10):
參閱圖2及圖13,第一開關S1:導通、第二開關S2:導通、第一二極體D1:不導通、第二二極體D2:不導通、第三二極體D3:不導通、第四二極體D4:不導通、第五二極體D5:不導通、第六二極體D6:不導通。Referring to FIG. 2 and FIG. 13, the first switch S1 is turned on, the second switch S2 is turned on, the first diode D1 is not turned on, the second diode D2 is not turned on, and the third diode D3 is not turned on. 4th diode D4: non-conducting, fifth diode D5: non-conducting, sixth diode D6: non-conducting.
本階段當第五二極體D5由導通轉變為不導通之後,第一開關S1與第二開關S2保持為導通,此時磁化電感Lm1、Lm2皆因跨輸入電壓Vin則電流i Lm1、i Lm2皆以斜率 線性上升。第一至第六二極體D1~D6皆因逆向偏壓而不導通。 At this stage, after the fifth diode D5 is turned from non-conducting to non-conducting, the first switch S1 and the second switch S2 are kept conductive. At this time, the magnetizing inductances Lm1 and Lm2 are currents i Lm1 and i Lm2 due to the input voltage Vin. Slope Linear rise. The first to sixth diodes D1 to D6 are not turned on due to the reverse bias.
穩態分析:Steady state analysis:
由於磁化電感Lm1、Lm2需滿足磁通重置,可推導出電容CI1、CI2、C1的電壓公式: 、 、 。 Since the magnetizing inductances Lm1 and Lm2 need to satisfy the magnetic flux reset, the voltage formulas of the capacitors CI1, CI2, and C1 can be derived: , , .
從漏感Ls需滿足磁通重置,推導出第一及第二輸出電容C2、C2的電壓公式: 。 其中參數V NP3分別表示第一變壓器T1的三次側繞組電壓,參數V NS3分別表示第二變壓器T2的三次側繞組電壓,參數T 2的定義為第三階段與第四階段的時間和,若T 2非常的小則 。因此輸出電壓 。 From the leakage inductance Ls to meet the flux reset, the voltage formulas of the first and second output capacitors C2, C2 are derived: . Wherein the parameter V NP3 represents the tertiary side winding voltage of the first transformer T1, respectively, the parameter V NS3 represents the tertiary side winding voltage of the second transformer T2, respectively, and the parameter T 2 is defined as the time sum of the third stage and the fourth stage, if T 2 very small . Therefore output voltage .
實驗模擬:Experimental simulation:
參閱圖14,為本實施例的第一脈波調變信號的電壓Vgs1、輸入電壓Vin及輸出電壓Vo的一波形圖。可知當輸入電壓Vin=40 V、輸出電壓Vo=400 V時,責任導通比D的實際量測值為0.58,其數值比理想值大(當輸入電壓Vin=40 V、輸出電壓Vo=400 V之責任導通比的理論值為 D=0.55),因理想值忽略第一及第二開關S1、S2、第一至第六二極體D1~D6的導通壓降及寄生元件效應。 Referring to FIG. 14, a waveform diagram of the voltage Vgs1, the input voltage Vin, and the output voltage Vo of the first pulse-wave modulation signal of the embodiment is shown. It can be seen that when the input voltage Vin=40 V and the output voltage Vo=400 V, the actual measured value of the duty-conducting ratio D is 0.58, and its value is larger than the ideal value (when the input voltage Vin=40 V, the output voltage Vo=400 V) The theoretical value of the duty-conducting ratio is D = 0.55), and the conduction voltage drop and parasitic element effects of the first and second switches S1, S2, the first to sixth diodes D1 to D6 are ignored due to the ideal value.
參閱圖15,為本實施例的第一及第二變壓器T1、T2的一次側繞組電流I1、I2、及輸入電流Iin的波形圖,因為第一及一二開關S1、S2以差二分之一周期時間依序交錯導通,而使第一及第二變壓器T1~T2的一次側繞組電流I1、I2的漣波相差180度,又 ,因此一次側繞組電流I1、I2的漣波可以相消以降低輸入電流Iin之漣波,從圖15量測結果中可知,一次側繞組電流的漣波 和 約為15A,輸入電流Iin確實因交錯式操作,有漣波相消的性能。 Referring to FIG. 15, the waveforms of the primary side winding currents I1 and I2 and the input current Iin of the first and second transformers T1 and T2 of the present embodiment are shown, because the first and second switches S1 and S2 have a difference of two. One cycle time is sequentially staggered and turned on, and the chopping waves of the primary winding currents I1 and I2 of the first and second transformers T1 to T2 are 180 degrees apart, and Therefore, the chopping of the primary winding currents I1 and I2 can be canceled to reduce the chopping of the input current Iin. From the measurement results in Fig. 15, the chopping of the primary winding current is known. with Approximately 15A, the input current Iin is indeed interleaved and has the performance of chopping cancellation.
參閱圖16、17,分別為本實施例的第一脈波調變信號、第一開關S1的跨壓及第二輸入電容CI2的電壓的量測波形圖、本實施例的第二脈波調變信號、第二開關S2的跨壓及第一輸入電容CI1的電壓的量測波形圖,因為第一開關S1及第二開關S2跨壓V ds1、V ds2分別將會被第二輸入電容CI2的電壓及第一輸入電容CI1的電壓箝制:Vds1=VCI2、Vds2=VCI1,因此由圖15、16之量測結果,第一及第二輸入電容CI1、CI2的電壓約為100V,而第一及第二開關S1、S2的跨壓也約為100V,可知第一及第二開關S1、S2的電壓應力遠低於輸出電壓。 Referring to FIGS. 16 and 17, the measurement waveforms of the first pulse modulation signal, the voltage across the first switch S1, and the voltage of the second input capacitor CI2 are respectively measured in the embodiment, and the second pulse modulation in this embodiment. The measured waveform of the variable signal, the voltage across the second switch S2 and the voltage of the first input capacitor CI1, because the first switch S1 and the second switch S2 are respectively connected to the second input capacitor CI2 by the voltages V ds1 and V ds2 The voltage and the voltage of the first input capacitor CI1 are clamped: V ds1 =V CI2 , V ds2 =V CI1 , so the voltages of the first and second input capacitors CI1, CI2 are about 100V as measured by the measurements of Figures 15 and 16. The voltage across the first and second switches S1 and S2 is also about 100V. It can be seen that the voltage stress of the first and second switches S1 and S2 is much lower than the output voltage.
參閱圖18~20,分別為本實施例的第一及第二二極體D1~D2、第三及第四二極體D3~D4、第五及第六二極體D5~D6的電壓及電流的量測波形圖,由圖中可以看到第一及第二二極體D1、D2的電流和第五及第六二極體D5、D6的電流先降至零,第一及第二二極體D1、D2和第五及第六二極體D5、D6才轉態為不導通,所以無反向恢復問題,而第三及第四二極體D3、D4則是只有輕微的反向恢復問題,也因二極體沒有反向恢復問題,如此在轉態時就不會有切換時的雜訊影響,因此能夠減緩二極體反向恢復問題及EMI雜訊干擾。 18 to 20, the voltages of the first and second diodes D1 to D2, the third and fourth diodes D3 to D4, the fifth and sixth diodes D5 to D6 of the present embodiment, respectively. The measurement waveform of the current, it can be seen that the currents of the first and second diodes D1 and D2 and the currents of the fifth and sixth diodes D5 and D6 first drop to zero, first and second The diodes D1, D2 and the fifth and sixth diodes D5 and D6 are not turned on, so there is no reverse recovery problem, and the third and fourth diodes D3 and D4 are only slightly reversed. To the recovery problem, because the diode does not have a reverse recovery problem, there will be no noise influence during the switching, so the diode reverse recovery problem and EMI noise interference can be slowed down.
綜上所述,上述實施例具有以下優點: In summary, the above embodiment has the following advantages:
1.高功率應用,由於第一及第二變壓器T1~T2的的一次側繞組NP1、NP2的第一端電連接一起以接收輸入電流Iin及輸入電壓Vin,故可分擔輸入電流Iin,能有效降低電路中第一及第二輸入電容CI1、CI2、第一及第二開關S1、S2之電流應力,適合應用於高功率的場合。 1. For high-power applications, since the first ends of the primary windings NP1 and NP2 of the first and second transformers T1 to T2 are electrically connected together to receive the input current Iin and the input voltage Vin, the input current Iin can be shared, which is effective. The current stress of the first and second input capacitors CI1, CI2, the first and second switches S1, S2 in the circuit is reduced, and is suitable for high power applications.
2.高電力密度,第一及第二開關S1、S2係以180°的相位差交錯工作,可降低輸入電流Iin的漣波,因此,可在輸入電壓Vin與第一變壓器T1的一次側繞組NP1的第一端之間,使用電感值較小之濾波電感(圖未示)以濾除輸入電流Iin的漣波,由於電感值越小濾波電感的體積也越小,而提高電力密度。 2. High power density, the first and second switches S1 and S2 are interleaved with a phase difference of 180°, which can reduce the chopping of the input current Iin. Therefore, the input voltage Vin and the primary winding of the first transformer T1 can be used. Between the first ends of NP1, a filter inductor with a small inductance value (not shown) is used to filter out the chopping of the input current Iin. The smaller the inductance value, the smaller the volume of the filter inductor, and the higher the power density.
3.低電壓應力及低導通損失,第一及第二開關S1、S2具有低於輸出電壓的電壓應力,故可使用導通電阻較小的低額定耐壓功率電晶體,而更可降低導通損失,提升整體效率。 3. Low voltage stress and low conduction loss, the first and second switches S1, S2 have a voltage stress lower than the output voltage, so a low rated withstand voltage power transistor with a small on-resistance can be used, and the conduction loss can be further reduced. To improve overall efficiency.
4.高升壓增益,由於第一及第二變壓器T1、T2的三次側繞組NP3、NS3與串接的第一至第三輸出電容C1~C3,增加了電壓增益的設計自由度,而使本實施例不必操作在極大的責任導通比,即可達成高電壓增益。 4. High boost gain, because the third side windings NP3, NS3 of the first and second transformers T1, T2 and the first to third output capacitors C1~C3 connected in series increase the design freedom of voltage gain, This embodiment does not have to operate at a very large duty-conductance ratio to achieve a high voltage gain.
5.高轉換效率,從上述可知,本實施例能將輸入電流Iin分流、可選用低導通電阻的功率電晶體作為第一及第二開關S1~S2、與減緩第一至第六二極體D1~D6的反向恢復問題,可有效降低元件導通時所產生的功率損失。故確實能達成本發明之目的。 5. High conversion efficiency. As can be seen from the above, this embodiment can split the input current Iin, and the power transistor with low on-resistance can be used as the first and second switches S1~S2, and the first to sixth diodes are slowed down. The reverse recovery problem of D1~D6 can effectively reduce the power loss generated when the component is turned on. Therefore, the object of the present invention can be achieved.
惟以上所述者,僅為本發明之實施例而已,當不能以此限定本發明實施之範圍,凡是依本發明申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾,皆仍屬本發明專利涵蓋之範圍內。However, the above is only the embodiment of the present invention, and the scope of the invention is not limited thereto, and all the equivalent equivalent changes and modifications according to the scope of the patent application and the patent specification of the present invention are still The scope of the invention is covered.
T1‧‧‧第一變壓器 T1‧‧‧ first transformer
T2‧‧‧第二變壓器 T2‧‧‧second transformer
NP1‧‧‧一次側繞組 NP1‧‧‧ primary winding
NS1‧‧‧一次側繞組 NS1‧‧‧ primary winding
NP2‧‧‧二次側繞組 NP2‧‧‧ secondary winding
NS2‧‧‧二次側繞組 NS2‧‧‧ secondary winding
NP3‧‧‧三次側繞組 NP3‧‧‧ tertiary winding
NS3‧‧‧三次側繞組 NS3‧‧‧3rd side winding
CI1‧‧‧第一輸入電容 CI1‧‧‧first input capacitor
CI2‧‧‧第二輸入電容 CI2‧‧‧Second input capacitor
D1‧‧‧第一二極體 D1‧‧‧First Diode
D2‧‧‧第二二極體 D2‧‧‧ second diode
D3‧‧‧第三二極體 D3‧‧‧ third diode
D4‧‧‧第四二極體 D4‧‧‧ fourth diode
D5‧‧‧第五二極體 D5‧‧‧ fifth diode
D6‧‧‧第六二極體 D6‧‧‧ sixth diode
S1‧‧‧第一開關 S1‧‧‧ first switch
S2‧‧‧第二開關 S2‧‧‧ second switch
C1‧‧‧第一輸出電容 C1‧‧‧First output capacitor
C2‧‧‧第二輸出電容 C2‧‧‧second output capacitor
C3‧‧‧第三輸出電容 C3‧‧‧ third output capacitor
2‧‧‧控制單元 2‧‧‧Control unit
Vin‧‧‧輸入電壓 Vin‧‧‧Input voltage
Iin‧‧‧輸入電流 Iin‧‧‧ input current
Io‧‧‧輸出電流 Io‧‧‧ output current
Vo‧‧‧輸出電壓 Vo‧‧‧ output voltage
Lm1‧‧‧第一變壓器的磁化電感 Lm1‧‧‧ Magnetizing inductance of the first transformer
Lm2‧‧‧第二變壓器的磁化電感 Magnetization inductance of Lm2‧‧‧second transformer
iLS‧‧‧第一及第二變壓器的三次側繞阻的漏電感電流 i LS ‧‧‧Leakage inductance current of the third side winding of the first and second transformers
iLm1‧‧‧第一變壓器的磁化電感電流 i Lm1 ‧‧‧ Magnetizing inductor current of the first transformer
iLm2‧‧‧第二變壓器的磁化電感電流 i Lm2 ‧‧‧ Magnetizing inductor current of the second transformer
I1‧‧‧第一變壓器的一次側電流 I1‧‧‧ primary current of the first transformer
I2‧‧‧第二變壓器的一次側電流 I2‧‧‧ primary current of the second transformer
iD1‧‧‧流過第一二極體的電流 i D1 ‧‧‧current flowing through the first diode
iD2‧‧‧流過第二二極體的電流 i D2 ‧‧‧current flowing through the second diode
iD3‧‧‧流過第三二極體的電流 i D3 ‧‧‧current flowing through the third diode
iD4‧‧‧流過第四二極體的電流 i D4 ‧‧‧current flowing through the fourth diode
iD5‧‧‧流過第五二極體的電流 i D5 ‧‧‧current flowing through the fifth diode
iD6‧‧‧流過第六二極體的電流 i D6 ‧‧‧current flowing through the sixth diode
iS1‧‧‧流過第一開關的電流 i S1 ‧‧‧current flowing through the first switch
iS2‧‧‧流過第二開關的電流 i S2 ‧‧‧current flowing through the second switch
本發明之其他的特徵及功效,將於參照圖式的實施方式中清楚地呈現,其中: 圖1是本發明交錯式升壓轉換器的一實施例的一電路圖; 圖2是該實施例的一操作時序圖; 圖3是該實施例操作於預備階段的一電路圖; 圖4是該實施例操作於第一階段的一電路圖; 圖5是該實施例操作於第二階段的一電路圖; 圖6是該實施例操作於第三階段的一電路圖; 圖7是該實施例操作於第四階段的一電路圖; 圖8是該實施例操作於第五階段的一電路圖; 圖9是該實施例操作於第六階段的一電路圖; 圖10是該實施例操作於第七階段的一電路圖; 圖11是該實施例操作於第八階段的一電路圖; 圖12是該實施例操作於第九階段的一電路圖; 圖13是該實施例操作於第十階段的一電路圖; 圖14是該實施例的第一開關的脈波調變信號、輸入電壓及輸出電壓的一波形圖; 圖15是該實施例的第一及第二變壓器的漏電感電流、及輸入電流的一波形圖; 圖16是該實施例的第一脈波調變信號、第一開關的跨壓及第二輸入電容的電壓的一量測波形圖; 圖17是該實施例的第二脈波調變信號、第二開關的跨壓及第一輸入電容的電壓的一量測波形圖; 圖18是該實施例的第一及第二二極體的電壓及電流的一量測波形圖; 圖19是該實施例的第三及第四二極體的電壓及電流的一量測波形圖;及 圖20是該實施例的第五及第六二極體的電壓及電流的一量測波形圖。Other features and advantages of the present invention will be apparent from the embodiments of the present invention, wherein: Figure 1 is a circuit diagram of an embodiment of an interleaved boost converter of the present invention; Figure 3 is a circuit diagram of the operation of the embodiment in the preliminary stage; Figure 4 is a circuit diagram of the operation of the embodiment in the first stage; Figure 5 is a circuit diagram of the operation of the embodiment in the second stage; 6 is a circuit diagram of the operation of the embodiment in the third stage; FIG. 7 is a circuit diagram of the operation of the embodiment in the fourth stage; FIG. 8 is a circuit diagram of the operation of the embodiment in the fifth stage; Figure 10 is a circuit diagram of the operation of the embodiment in the seventh stage; Figure 11 is a circuit diagram of the embodiment operating in the eighth stage; Figure 12 is the operation of the embodiment in the ninth stage. FIG. 13 is a circuit diagram of the tenth stage of the operation of the embodiment; FIG. 14 is a waveform diagram of the pulse modulation signal, the input voltage, and the output voltage of the first switch of the embodiment; Example FIG. 16 is a waveform diagram of leakage inductance current and input current of the first and second transformers; FIG. 16 is a first pulse modulation signal, a voltage across the first switch, and a voltage of the second input capacitor of the embodiment. FIG. 17 is a measurement waveform diagram of the second pulse modulation signal, the voltage across the second switch, and the voltage of the first input capacitor of the embodiment; FIG. 18 is the first and the first embodiment of the embodiment. FIG. 19 is a waveform diagram of voltage and current of the third and fourth diodes of the embodiment; and FIG. 20 is a measurement waveform of the embodiment. A measurement waveform of the voltage and current of the fifth and sixth diodes.
T1‧‧‧第一變壓器 T1‧‧‧ first transformer
T2‧‧‧第二變壓器 T2‧‧‧second transformer
NP1‧‧‧一次側繞組 NP1‧‧‧ primary winding
NS1‧‧‧一次側繞組 NS1‧‧‧ primary winding
NP2‧‧‧二次側繞組 NP2‧‧‧ secondary winding
NS2‧‧‧二次側繞組 NS2‧‧‧ secondary winding
NP3‧‧‧三次側繞組 NP3‧‧‧ tertiary winding
NS3‧‧‧三次側繞組 NS3‧‧‧3rd side winding
CI1‧‧‧第一輸入電容 CI1‧‧‧first input capacitor
CI2‧‧‧第二輸入電容 CI2‧‧‧Second input capacitor
D1‧‧‧第一二極體 D1‧‧‧First Diode
D2‧‧‧第二二極體 D2‧‧‧ second diode
D3‧‧‧第三二極體 D3‧‧‧ third diode
D4‧‧‧第四二極體 D4‧‧‧ fourth diode
D5‧‧‧第五二極體 D5‧‧‧ fifth diode
D6‧‧‧第六二極體 D6‧‧‧ sixth diode
S1‧‧‧第一開關 S1‧‧‧ first switch
S2‧‧‧第二開關 S2‧‧‧ second switch
C1‧‧‧第一輸出電容 C1‧‧‧First output capacitor
C2‧‧‧第二輸出電容 C2‧‧‧second output capacitor
C3‧‧‧第三輸出電容 C3‧‧‧ third output capacitor
2‧‧‧控制單元 2‧‧‧Control unit
Vin‧‧‧輸入電壓 Vin‧‧‧Input voltage
Iin‧‧‧輸入電流 Iin‧‧‧ input current
Io‧‧‧輸出電流 Io‧‧‧ output current
Vo‧‧‧輸出電壓 Vo‧‧‧ output voltage
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TWI682617B (en) * | 2018-06-28 | 2020-01-11 | 崑山科技大學 | Interleaved ultra-high boost converter |
TWI687036B (en) * | 2018-06-29 | 2020-03-01 | 崑山科技大學 | Ultra-high boosting converter |
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TWI664797B (en) * | 2018-04-27 | 2019-07-01 | 崑山科技大學 | Dc power converter with high voltage gain |
TWI663816B (en) * | 2018-04-27 | 2019-06-21 | 崑山科技大學 | Interleaved high step-up dc-dc converter |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6445599B1 (en) * | 2001-03-29 | 2002-09-03 | Maxim Integrated Products, Inc. | Ripple canceling, soft switching isolated DC/DC converters with reduced voltage stress synchronous rectification |
US20110110132A1 (en) * | 2009-11-12 | 2011-05-12 | Polar Semiconductor, Inc. | Time-limiting mode (tlm) for an interleaved power factor correction (pfc) converter |
TWM438760U (en) * | 2012-04-09 | 2012-10-01 | Sinpro Electronics Co Ltd | Power conversion device with control switch |
TW201315119A (en) * | 2011-09-16 | 2013-04-01 | Univ Hungkuang | High efficient interleaved boosting converter |
TW201415777A (en) * | 2012-10-12 | 2014-04-16 | Nat Univ Tsing Hua | Isolated interleaved DC converter |
-
2016
- 2016-04-11 TW TW105111181A patent/TWI580166B/en not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6445599B1 (en) * | 2001-03-29 | 2002-09-03 | Maxim Integrated Products, Inc. | Ripple canceling, soft switching isolated DC/DC converters with reduced voltage stress synchronous rectification |
US20110110132A1 (en) * | 2009-11-12 | 2011-05-12 | Polar Semiconductor, Inc. | Time-limiting mode (tlm) for an interleaved power factor correction (pfc) converter |
TW201315119A (en) * | 2011-09-16 | 2013-04-01 | Univ Hungkuang | High efficient interleaved boosting converter |
TWM438760U (en) * | 2012-04-09 | 2012-10-01 | Sinpro Electronics Co Ltd | Power conversion device with control switch |
TW201415777A (en) * | 2012-10-12 | 2014-04-16 | Nat Univ Tsing Hua | Isolated interleaved DC converter |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI682617B (en) * | 2018-06-28 | 2020-01-11 | 崑山科技大學 | Interleaved ultra-high boost converter |
TWI687036B (en) * | 2018-06-29 | 2020-03-01 | 崑山科技大學 | Ultra-high boosting converter |
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