TWI441435B - Low voltage stress DC converter - Google Patents

Description

Low voltage stress DC converter

This invention relates to a converter, and more particularly to a low voltage stress DC converter.

In the paper "BRLin and HKChiang, "Analysis and Implementation of a Soft Switching Interleaved Forward Converter with Current Double Rectifier," IET Electr. Power Appl., Vol. 1, No. 5, pp. 697-704, 2007." A conventional power converter is proposed.

However, the disadvantages of conventional power converters are:

1. The switching stress used is v _in /1-D, where v _in is the input voltage and D is the power switch duty ratio. When D = 0.5, the switching stress is 2v _in , which is not suitable for high input voltage applications.

2. Use four switches to increase hardware cost.

Accordingly, it is an object of the present invention to provide a low voltage stress DC converter.

The low voltage stress DC converter comprises: first and second transformers, each transformer having a primary side winding and a secondary side winding, and each side winding has a first end and a second end, wherein a first end of the primary winding of the second transformer is electrically connected to a second end of the primary winding of the first transformer, and a second end of the secondary winding of the second transformer is electrically connected to the first transformer Secondary winding a second end; a first capacitor having a first end receiving a DC input voltage and a second end; a second capacitor having a first electrical connection to the second end of the first capacitor And a second end of the negative electrode receiving the input voltage; a resonant inductor electrically connected between the second end of the first capacitor and the second end of the primary winding of the first transformer; a first switch a first end electrically connected to the first end of the first capacitor, and a second end electrically connected to the first end of the primary side winding of the first transformer, and the first switch is controlled to switch a second switch having a first end electrically connected to the second end of the primary winding of the second transformer, and a second electrically connected to the second end of the second capacitor And the second switch is controlled to switch between the conducting state and the non-conducting state; a primary side diode having an anode electrically connected to the second end of the primary winding of the second transformer and an electrical connection First end of the primary winding of the first transformer a cathode; a first diode having a cathode electrically connected to the first end of the secondary winding of the first transformer; and an anode; a second diode having an electrical connection to the second transformer a cathode of the first end of the secondary winding, and an anode electrically connected to the anode of the first diode; a first output inductor having an electrical connection to the cathode of the first diode a first end of the pole, and a second end; a second output inductor having a first end electrically connected to the cathode of the second diode, and a second end; and an output capacitor electrically connected The second end of the first output inductor is coupled to the anode of the first diode for providing an output voltage.

The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments.

As shown in FIG. 1, a preferred embodiment of the low voltage stress DC converter of the present invention comprises: first and second transformers T ₁ , T ₂ , first and second capacitors C ₁ , C ₂ , and a resonant inductor L _r , first and second switches Q ₁ , Q ₂ , a primary side diode D _r , first and second diodes D ₁ , D ₂ , first and second output inductors L ₁ , L ₂ , And an output capacitor C _O .

Each of the transformers T ₁ and T ₂ has a primary side winding L _p1 , L _p2 and a secondary side winding L _s1 , L _s2 , and each of the side windings L _s1 , L _s2 , L _p1 , L _p2 has a first One end and a second end, wherein the first end of the primary side winding L _p2 of the second transformer T ₂ is electrically connected to the second end of the primary side winding L _p1 of the first transformer T ₁ , the second transformer The second end of the secondary winding L _s2 of T ₂ is electrically connected to the second end of the secondary winding L _s1 of the first transformer T ₁ . The first and second transformers T _1, T ₂ ratio is equal to the number of turns, and each of the primary winding L _p1, L _p2 of the dot end is the first end, each of the primary winding L _p1, L _p2 of the second The end is the non-dip end. The first end of each of the secondary side windings L _s1 , L _s2 is a striking end, and the second end of each of the secondary side windings L _s1 , L _{s2 is} a non-tapping end.

The first capacitor C ₁ has a first end that receives a positive input voltage and a second end.

The second capacitor C ₂ has a first end electrically connected to the second end of the first capacitor C ₁ and a second end receiving the input voltage v _in the negative pole.

The resonant inductor L _{r is} electrically connected between the second end of the first capacitor C _{1 and} the second end of the primary side winding L _p1 of the first transformer T ₁ .

The first switch Q ₁ has a first end electrically connected to the first end of the first capacitor C ₁ and a second end electrically connected to the first end of the primary side winding L _p1 of the first transformer T ₁ And the first switch Q ₁ is controlled to switch between a conducting state and a non-conducting state. The first switch Q ₁ is an N-type power semiconductor transistor, and a first terminal of the first switch Q ₁ is a drain, the second terminal of the first switch Q ₁ is a source electrode.

The second switch Q ₂ has a first end electrically connected to the second end of the primary side winding L _p2 of the second transformer T ₂ , and a second end electrically connected to the second end of the second capacitor C ₂ , and The second switch Q ₂ is controlled to switch between a conducting state and a non-conducting state. The second switch Q ₂ is an N-type power semiconductor transistor, and a first end of the second switch Q ₂ is a drain, the second terminal of the second switch Q ₂ is a source electrode.

The primary side diode D _r has an anode electrically connected to the second end of the primary side winding L _p2 of the second transformer T _{2 and} a first end electrically connected to the primary side winding L _p1 of the first transformer T ₁ Cathode.

The first diode D ₁ has a cathode electrically connected to the first end of the secondary winding L _s1 of the first transformer T ₁ , and an anode.

The second diode D ₂ has a cathode electrically connected to the first end of the secondary winding L _s2 of the second transformer T ₂ , and an anode electrically connected to the anode of the first diode D ₁ .

The first output inductor L ₁ has a first end electrically connected to the cathode of the first diode D ₁ and a second end.

The second output inductor L ₂ has a first end electrically connected to the cathode of the second diode D ₂ and a second end.

The output capacitor C _{O is} electrically connected between the second end of the first output inductor L ₁ and the anode of the first diode D ₁ for providing an output voltage V _O .

Referring to FIG. 2, it is an operation timing diagram of the embodiment, wherein the parameters v _g1 and v _g2 respectively represent voltages for controlling whether the first and second switches Q ₁ and Q ₂ are turned on, and the parameters v _Cr1 and v _Cr2 respectively represent the The voltages of the parasitic capacitances C _r1 and C _r2 of the first and second switches Q ₁ and Q ₂ , the parameters i _Lm1 and i _Lm2 respectively represent the magnetizing inductances L _m1 and L _m2 flowing through the two transformers T ₁ and T ₂ . Current, the parameter i _Lr represents the current flowing through the resonant inductor L _r , and the parameters i _D1 ~i _D2 represent the current flowing through the first to second diodes D ₁ -D ₂ , respectively, and the parameters i _L1 and i _L2 respectively represent output current of the first inductor of L ₁ flows, flows through the output inductor L current second parameter representative of the output current i _{O 2.} According to the switching of the two switches Q ₁ and Q ₂ , the present embodiment operates in eight modes, and in the following modes, the magnetizing inductances L _m1 and L _{m2 of} the two transformers T ₁ and T ₂ are drawn in the figure. The components that are turned on are indicated by solid lines, and the components that are not turned on are indicated by broken lines. Hereinafter, each mode is described for each mode and the duty-on period D<0.5 of the two switches Q ₁ and Q ₂ is made.

And the following analysis, the assumptions are:

1. The first and second transformers T ₁ and T ₂ have equal turns ratios and equal magnetization inductance values (L _{m 1} = L _{m 2} = L _m ), and their leakage inductances are equal.

2. The magnetizing inductance L _{m is} much larger than the resonant inductor L _r and the leakage inductance.

3. The capacitance values of the first and second capacitors C ₁ and C ₂ are much larger than the parasitic capacitances C _r1 and C _{r2 of the} first and second switches Q ₁ and Q ₂ .

4. The inductance values of the first and second output inductors L ₁ and L ₂ are equal, that is, L ₁ = L ₂ .

5. The output capacitor C _{O is} large, and the output voltage v _o can be regarded as a constant.

6. Operate in continuous conduction mode (CCM).

7. The energy stored in the resonant inductor L _r and the leakage inductance is greater than the energy of the parasitic capacitances C _{r 1} , C _{r 2} to achieve a zero voltage switching (ZVS) operation.

Mode one (time: t ₀ ~t ₁ ):

Referring to Figures 2 and 3a, the first switch Q _{1 is} turned on and the second switch Q ₂ is turned off.

The first switch Q _{1 is} in an on state, so that the energy stored in the first capacitor C ₁ is transmitted to the load through the first transformer T ₁ , and the detailed operation is as follows: the first switch Q ₁ crosses the voltage v _Cr1 =0, the first transformer Primary side voltage of V ₁ v _P1 v _C1 >0, the magnetizing inductor current i _Lm1 rises linearly, and the secondary side voltage of the transformer T ₁ And the second switch Q ₂ crosses the voltage v _Cr2 =v _in , and the second transformer T ₂ is demagnetized reset via the primary side diode D _r , so v _P2 -v _P1 <0, and the second diode D _{2 is} turned on and the first diode D ₁ is non-conducting, the first output inductor voltage v _L1 =2nv _C1 -v _o >0, and the current i _{L 1 is} linear Ascending, the energy stored in the first capacitor C ₁ is transferred to the load by the first transformer T ₁ . And the second output inductor voltage v _L2 = -v _o <0, the current i _L2 linearly decreases, so the total output current i ₀ = i _L1 + i _L2 will have the effect of chopping cancellation

Mode two (time: t ₁ ~t ₂ ):

Referring to FIG. 2 and FIG. 3b, the first and second switches Q ₁ and Q ₂ are not turned on.

Current flowing through the first switch Q ₁ i _Q1 and its positive charge parasitic capacitance C _R1, the stray capacitance of the voltage v C _{r1 Cr1} rises, the primary-side diode D _r is turned on, the two parasitic capacitance C The voltages v _Cr1 and v _{Cr2 of r1} and C _r2 satisfy v _Cr1 +v _Cr2 =v _in , so the parasitic capacitance C _{r2 is} discharged, and the voltage v _{Cr 2 thereof is} lowered. Since the two parasitic capacitances C _r1 and C _r2 are very small, v _Cr1 rises and v _Cr2 drops very fast, so mode 2 lasts for a short time, and magnetizing inductor current i _Lm can be regarded as a constant At the same time, i _Q1 =ni _L1 , so the parasitic capacitance C _r1 is quickly charged by the current i _Q1 .

When t = t ₂ , when the first switch voltage v _Cr1 rises to v _C1 , at this time v _Cr2 also drops to v _C2 , the primary side voltage v _P1 =0 of the first transformer T ₁ , the second transformer T ₂ The primary side voltage v _P2 =0, so v _S1 =0, and v _S2 =0, causes the first diode D _{1 to} start conducting, enters current commutation, and enters mode three.

Mode three (time: t ₂ ~t ₃ ):

Referring to FIG. 2 and FIG. 3c, the first and second switches Q ₁ and Q ₂ are not turned on.

The voltage across the first and second switches Q ₁ , Q ₂ is v _Cr1 = v _C1 , v _Cr2 = v _C2 , and the primary side voltages of the first and second transformers T ₁ and T ₂ are clamped at zero, i _Lm1 and i _{Lm2 is} kept constant, and the secondary side voltages V _S1 =v _S2 =0 of the first and second transformers T ₁ and T ₂ are subjected to a commutation process.

The resonant inductor L _r and the parasitic capacitances C _r1 and C _r2 form a resonant circuit. The first switch Q ₁ continues to rise across the voltage v _Cr1 , the second switch Q ₂ continues to fall across the voltage v _Cr2 , and the resonant inductor L _r crosses the negative voltage. i _Lr drops, causing the second diode current i _{D2 to} decrease, and the first diode current i _{D1 to} increase.

The initial energy storage of the resonant inductor L _r of mode 3 must be greater than the initial energy storage of the parasitic capacitances C _r1 and C _r2 to enable the second switch Q _{2 to} fall to zero across the voltage v _Cr2 to achieve zero voltage switching (ZVS) conditions. .

When the second switch Q ₂ falls to zero across the voltage v _Cr2 , the body diode of the second switch Q ₂ is turned on, and the mode three ends.

Mode four (time: t ₃ ~ T ₄ ):

Referring to Figures 2 and 3d, the first and second switches Q ₁ and Q ₂ are not turned on.

The second switch Q _{2 is} clamped at 0 across voltage v _Cr2 and v _Cr1 = v _in . Before the second switch Q ₂ of the body diode is turned on, the voltage across the second switch Q ₂ is zero, the current flowing through the second switch i _Q2 becomes positive, the second switch Q ₂ must be switched on, to achieve ZVS operating.

The primary side voltage v _P1 =0 of the first transformer T ₁ and v _P2 =0, the resonant inductor voltage v _Lr -v _C2 , the resonant inductor current i _Lr decreases linearly.

When the first diode current i _D1 rises to i _L1 and the second diode current i _D2 rises to 0, the commutation is completed, the second diode D _{2 is} not turned on, and the mode four ends.

Mode five (time: t ₄ ~t ₅ ):

Referring to FIG. 2 and FIG. 3E, a first switch Q ₁ is not turned on, the second switch Q ₂ is turned on.

The first diode current i _D1 =i _L2 , and the second diode current i _D2 =0, v _P2 =v _C2 , i _Lm2 linearly rises, the slope is v _C2 /L _m , and the second transformer T ₂ The secondary side voltage v _S2 =nv _p2 >0, at which time the energy stored in the second capacitor C ₂ is transferred to the output load side via the second transformer T ₂ . At this time, the first transformer T ₁ is flux resetted via the primary side diode D _r , and v _P1 =−v _P2 , so the magnetizing current i _Lm1 linearly decreases. In terms of output inductor current, since v _L2 = 2nv _C2 - v _o > 0, i _L2 rises linearly; v _L1 = -v _o , i _L1 decreases linearly, so the total output current i _O = i _L1 + i _L2 will be 涟The effect of wave cancellation.

Mode six (time: t ₅ ~t ₆ ):

Referring to Figures 2 and 3f, the first switch Q _{1 is} not conducting, and the second switch Q _{2 is} not conducting.

The current i _Q2 flowing through the second switch Q ₂ is positive and charges the parasitic capacitance C _r2 , and the voltage v _Cr2 rises. Since the primary side diode D _{r is} turned on, the voltages v _Cr1 and v _Cr2 satisfy v _in = v _{Cr1 .} +v _Cr2 , so the capacitor C _r1 discharges and the voltage v _Cr1 drops. Since the parasitic capacitances C _r1 and C _{r2 of the} first and second switches Q ₁ , Q ₂ are very small, v _Cr2 rises and v _Cr1 drops very fast, so the mode 6 has a very short time.

When the second switch Q ₂ rises to v _C2 across the voltage v _Cr2 , v _Cr1 drops to v _C1 at this time, and the primary side voltage v _P2 =0 of the second transformer T ₂ and v _P1 =0. When the second diode D ₂ begins to conduct, mode six ends.

Mode seven (time: t ₆ ~ T ₇ ):

Referring to FIG. 2 and FIG. 3g, the first and second switches Q ₁ and Q ₂ are not turned on.

The primary side voltages v _P1 and v _{P2 of the} first and second transformers T ₁ and T ₂ are clamped at zero, the first and second diodes D ₁ and D ₂ are commutated, and the mode seven is similar to the mode three, the magnetizing inductance The voltage clamp is at zero and i _Lm1 and i _Lm2 remain constant. The resonant inductor L _r , the parasitic capacitances C _r1 and C _r2 form a resonant circuit, v _Cr2 continues to rise (v _Cr2 >v _C2 ), and v _Cr1 continues to decrease (v _Cr2 <v _C1 ). The resonant inductor L _r crosses the positive voltage, the resonant current i _Lr rises, the current i _D2 increases, and i _D1 decreases.

The initial energy storage of the resonant inductor L _r and the leakage inductance of mode 7 must be greater than the initial energy storage of the two parasitic capacitances C _r1 and C _r2 in order to reduce the first switching voltage v _Cr1 to zero and achieve zero voltage switching (ZVS). )conditions of.

When the first switching voltage v _Cr1 drops to zero, the body diode of the first switch Q ₁ is turned on, and the mode seven ends.

Mode eight (time: t ₇ ~T _S +t ₀ ):

Referring to FIG. 2 and FIG. 3h, the first and second switches Q ₁ and Q ₂ are not turned on.

A current flowing through the first switch Q ₁ of the body diode, the first switch Q ₁ is zero voltage across the first switch voltage across v _Cr1 clamped to zero, and v _Cr2 = v _in. Since v _Cr1 =0, before the first switching current i _Q1 flows to a positive value, the first switch Q ₁ must be switched to be turned on to achieve a ZVS operation.

Resonant inductor voltage v _Lr v _C1 , the resonant inductor current i _Lr rises linearly, and the _dipoles D ₁ , D ₂ continue to perform the commutation process.

When the second diode current i _D2 =i _L1 and the first diode current i _D1 falls to 0, the first diode D ₁ turns non-conductive and the commutation is completed, and enters the next switching period.

Experimental simulation

When seen from the rear in FIG. 4, the v _in = 400V, the voltage across the first switch Q v _{Q1, ds} of ₁ has fallen to zero, the drive signal v _g1 was switched on to achieve ZVS performance, the second switch Q ₂ After the voltage v _{Q2, d} drops to zero, the drive signal v _g2 is switched to conduct to achieve ZVS performance. It can be seen from the figure that the voltage stress is v _in , and the measurement result is consistent with the first and second switches Q ₁ , Q ₂ having low voltage stress.

Figure 5 shows the waveform measurement of the output inductor currents i _L1 , i _L2 and the total output current i _O . It can be seen from the analog waveform that under steady state operation, i _L1 and i _{L2 are} chopped in opposite directions, which indeed makes the ripple △ i _O (=0.3A) is reduced a lot (△i _L1 △i _L2 3.9A), a smaller output filter capacitor can be used to reduce the converter's size and increase the power density. In addition, i _L1 =i _L2 =7.5A does share the total output current (15A), disperses the power loss and thermal stress of the magnetic element, and has high output current and low output current chopping performance.

6 is a current measurement diagram of the first and second diodes D ₁ to D ₂ , and the driving signals v _g1 and v _{g2 of} the two switches Q ₁ and Q ₂ can be seen from the figure. The current commutation waveform of the diodes D ₁ to D ₂ .

In summary, the above embodiment has the following advantages:

1. Each switch Q ₁ , Q ₂ has a lower voltage stress, and its switching stress is equivalent to the input voltage v _in , which is suitable for high input voltage applications.

2. Only two switches Q ₁ and Q _{2 are included} , which can reduce the hardware cost.

3. The first and second switches Q ₁ and Q ₂ can achieve zero voltage switching (ZVS) operation, reduce switching losses, and improve power conversion efficiency.

4. The first and second output inductors L ₁ and L _{2 are} used to share the output current, which is suitable for high output current applications.

5. The chopping of the current flowing through the first and second output inductors L ₁ and L ₂ is inverted, and the chopping canceling action can be performed, so that the output current is chopped with low output current.

6. The operating frequency of the output capacitor C _O is twice the switching frequency of the switches Q ₁ and Q ₂ . Under the same output chopping specification, a smaller filter component can be selected.

However, the above is only the preferred embodiment of the present invention, and the scope of the present invention cannot be limited thereto, that is, the patent application according to the present invention The scope of the invention and the equivalent equivalents and modifications of the invention are still within the scope of the invention.

T ₁ ‧‧‧First Transformer

D ₂ ‧‧‧Secondary

T ₂ ‧‧‧second transformer

L ₁ ‧‧‧first output inductor

C ₁ ‧‧‧first capacitor

L ₂ ‧‧‧second output inductor

C ₂ ‧‧‧second capacitor

C _O ‧‧‧ output capacitor

L _r ‧‧‧Resonance inductance

L _p1 , L _p2 ‧‧‧ primary winding

Q ₁ ‧‧‧First switch

L _s1 , L _s2 ‧‧‧ secondary winding

Q ₂ ‧‧‧Second switch

L _m1 ~L _m2 ‧‧‧ Magnetizing inductance

D _r ‧‧‧Primary side diode

v _in ‧‧‧Input voltage

D ₁ ‧‧‧First Diode

V _O ‧‧‧Output voltage

1 is a circuit diagram of a preferred embodiment of a low voltage stress DC converter of the present invention; FIG. 2 is a timing diagram of the preferred embodiment; FIG. 3a is a circuit diagram of the preferred embodiment in mode one; Figure 3c is a circuit diagram of the preferred embodiment in mode three; Figure 3d is a circuit diagram of the preferred embodiment in mode four; Figure 3e is a preferred embodiment of the preferred embodiment Figure 3f is a circuit diagram of the preferred embodiment in mode six; Figure 3g is a circuit diagram of the preferred embodiment in mode seven; Figure 3h is a preferred embodiment of mode eight FIG. 4 is a first measurement diagram of the preferred embodiment; FIG. 5 is a second measurement diagram of the preferred embodiment; and FIG. 6 is a third measurement of the preferred embodiment. Figure.

T ₁ ‧‧‧First Transformer

L ₁ ‧‧‧first output inductor

T ₂ ‧‧‧second transformer

L ₂ ‧‧‧second output inductor

C ₁ ‧‧‧first capacitor

C _O ‧‧‧ output capacitor

C ₂ ‧‧‧second capacitor

L _p1 , L _p2 ‧‧‧ primary winding

L _r ‧‧‧Resonance inductance

L _s1 , L _s2 ‧‧‧ secondary winding

Q ₁ ‧‧‧First switch

v _in ‧‧‧Input voltage

Q ₂ ‧‧‧Second switch

V _O ‧‧‧Output voltage

D _r ‧‧‧Primary side diode

D ₁ ‧‧‧First Diode

D ₂ ‧‧‧Secondary

Claims (8)

A low voltage stress DC converter comprising: first and second transformers, each transformer having a primary side winding and a secondary side winding, and each side winding has a first end and a second end, wherein a first end of the primary winding of the second transformer is electrically connected to a second end of the primary winding of the first transformer, and a second end of the secondary winding of the second transformer is electrically connected to the first transformer a second end of the secondary winding; a first capacitor having a first end receiving a DC input voltage, and a second end; a second capacitor having an electrical connection to the first capacitor a first end of the two ends, and a second end of the negative pole receiving the input voltage; a resonant inductor electrically connected between the second end of the first capacitor and the second end of the primary side winding of the first transformer; a first switch having a first end electrically connected to the first end of the first capacitor, and a second end electrically connected to the first end of the primary side winding of the first transformer, and the first switch Controlled to switch to conduction and non-conduction a second switch having a first end electrically connected to the second end of the primary winding of the second transformer, and a second end electrically connected to the second end of the second capacitor, and the second The switch is controlled to switch between a conducting state and a non-conducting state; a primary side diode having an anode electrically connected to the second end of the primary winding of the second transformer and an electrical connection to the first transformer a cathode of the first end of the primary winding; a first diode having a cathode electrically connected to the first end of the secondary winding of the first transformer; and an anode; a second diode a cathode having a first end electrically connected to the secondary winding of the second transformer, and an anode electrically connected to the anode of the first diode; a first output inductor having an electrical connection to the first a first end of the cathode of the diode and a second end; a second output inductor having a first end electrically connected to the cathode of the second diode, and a second end; and an output A capacitor is electrically connected between the second end of the first output inductor and the anode of the first diode to provide an output voltage. The low voltage stress DC converter of claim 1, wherein the first and second transformers have equal turns ratios. The low voltage stress DC converter of claim 1, wherein the first end of each of the secondary windings is a striking end, and the second end of each of the secondary windings is a non-tapping end. The low voltage stress DC converter of claim 1, wherein the first end of each of the primary windings is a striking end, and the second end of each of the primary windings is a non-tapping end. The low voltage stress DC converter of claim 1, wherein the first switch is an N-type power semiconductor transistor, and the first end of the first switch is a drain, the first switch The second end is the source. The low voltage stress DC converter of claim 1, wherein the second switch is an N-type power semiconductor transistor, and the first end of the second switch is a drain, the second switch The second end is the source. The low voltage stress DC converter of claim 1, wherein the switching of the first and second switches is zero voltage switching. The low voltage stress DC converter of claim 1, wherein the first and second output inductors have equal inductance values.