TWI694667B - High boost converter - Google Patents

Abstract

A high-boost converter includes first and second coupling inductors, first and second switches, a zero-voltage switching auxiliary unit, a clamping capacitor, a first clamping diode, a voltage multiplying unit, and an output unit, the first And the second coupling inductor are used to receive the DC input voltage. Both the first and second switches are controlled to switch between conducting and non-conducting. The zero-voltage switching auxiliary unit is electrically connected to the first and second switches, respectively, and the clamp The capacitor is used to make the first and second switches reach zero-voltage switching. The two ends of the voltage multiplying unit are electrically connected to the first clamping diode and the output unit, respectively, to raise the output voltage of the output unit.

Description

High boost converter

The invention relates to a converter, in particular to a high boost converter.

Referring to FIG. 1, a conventional boost converter, if the parasitic resistance is not considered, that is, the parasitic resistance r _{L is} equal to zero, its voltage gain is proportional to an output voltage V2, an input voltage V1, and a switch duty cycle. The relationship of D is as follows, where the conduction ratio D is a real number greater than 0 and less than 1.

In theory, to obtain a high voltage gain, the converter must operate at a very large conduction ratio, but in practice, due to the presence of parasitic elements, such as parasitic resistance r _{L is} not equal to zero, when the conduction ratio D is greater than 0.9, the traditional boost converter will have The following questions:

1. The voltage gain M does not increase and decrease and the conversion efficiency η is not good; 2. It is easy to produce a large input current ripple and reduce the life of the fuel cell; 3. The output diode has serious reverse recovery Loss and electromagnetic interference (EMI) noise issues.

On the other hand, the power switch of the traditional boost converter is a hard switch (Hard switching), there will be a switching loss, which leads to the problem that higher efficiency cannot be achieved.

Therefore, an object of the present invention is to provide a high-boost converter that can achieve a high-boost converter without operating at an extremely high turn-on ratio.

Therefore, the present invention provides a high boost converter including a first coupled inductor, a second coupled inductor, a first switch, a second switch, a first clamp diode, and a second clamp two A polar body, a clamping capacitor, a zero-voltage switching auxiliary unit, a third diode, a fourth diode, a first capacitor, and an output unit.

The first and second coupled inductors respectively have a primary winding and a secondary winding. Each side winding has a first end and a second end. The primary windings of the first and second coupled inductors One end is electrically connected together to receive a DC input voltage, and the second end of the secondary winding of the first coupled inductor is electrically connected to the second end of the secondary winding of the second coupled inductor. The first and second switches respectively have a first end electrically connected to the second end of the primary winding of the first and second coupled inductors, and a second end connected to ground, and are controlled to switch between conducting and non-conducting, respectively between.

The first and second clamp diodes respectively have an anode electrically connecting the second end of the primary winding of the first and second coupling inductors, and a cathode. The zero-voltage switching auxiliary unit is electrically connected to the first end of the first switch and the first end of the second switch, and The first end of the clamping capacitor is used to enable the first switch and the second switch to achieve zero voltage switching. The third diode has an anode electrically connected to the cathode of the first clamp diode, and a cathode electrically connected to the first end of the secondary winding of the second coupled inductor. The fourth diode has an anode electrically connected to the first end of the secondary winding of the first coupled inductor, and a cathode.

The first capacitor has a first end electrically connected to the cathode of the fourth diode, and a second end electrically connected to the first end of the secondary winding of the second coupled inductor. The output unit is electrically connected to the cathode of the fourth diode to provide an output voltage.

The effect of the present invention is that a voltage multiplying unit formed by the secondary winding of the first and second coupled inductors, the first and second capacitors, and the third and fourth diodes, plus The zero-voltage switching auxiliary unit effectively improves the voltage gain but does not require the switching operation at a high conduction ratio, and effectively improves the conversion efficiency.

2: zero voltage switching auxiliary unit

3: voltage multiplication unit

4: output unit

5: control unit

M: voltage gain

η: conversion efficiency

N _p1 : primary winding of the first coupled inductor

N _p2 : primary winding of the second coupled inductor

N _s1 : secondary winding of the first coupled inductor

N _s2 : secondary winding of the second coupled inductor

S ₁ : first switch

V _in : input voltage

V _o : output voltage

V _Cc : voltage across the clamping capacitor

V _C1 : voltage across the first capacitor

V _C2 : voltage across the second capacitor

V _S1-stress : voltage stress of the first switch

V _S2-stress : voltage stress of the second switch

V _Sa-stress : voltage stress of auxiliary switch

v _La : Overvoltage of auxiliary inductance

v _ds1 : cross voltage of the first switch

v _ds2 : cross voltage of the second switch

v _gs1 : switching control voltage of the first switch

v _gs2 : switching control voltage of the second switch

v _Ns1 : voltage across the secondary winding of the first coupled inductor

S ₂ : Second switch

S _a: the auxiliary switch

C _c : clamping capacitance

_Co : output capacitance

C ₁ : the first capacitor

C ₂ : second capacitor

C _S1 : Parasitic capacitance of the first switch

_CS2 : Parasitic capacitance of the second switch

D: Turn-on ratio

D _o : output diode

D ₁ : First clamp diode

D ₂ : Second clamp diode

D ₃ : Third diode

D ₄ : Fourth diode

D _a1 : first auxiliary diode

D _a2 : Second auxiliary diode

D _a3 : third auxiliary diode

L _a : auxiliary inductance

L _m1 : the first magnetizing inductance

L _m2 : second magnetizing inductance

L _m : magnetizing inductance

L _k1 : first leakage inductance

L _k2 : second leakage inductance

L _k : leakage inductance

n: Coupling inductance turns ratio

R _o : output load

v _Ns2 : voltage across the secondary winding of the second coupled inductor

i _in : input current

i _S1 : current of the first switch

i _S2 : current of the second switch

i _D1 : current of the first clamp diode

i _D2 : current of the first clamp diode

i _D3 : current of the third diode

i _D3 : current of the fourth diode

i _Do : output diode current

i _Lm1 : current of the first inductor

i _Lm2 : current of the second inductor

i _Lk1 : current of the first leakage inductance

i _Lk2 : current of the second leakage inductance

i _La : current of auxiliary inductor

r _L : parasitic resistance

T _s : switching period

t: time

t0~t15: first start time~sixteenth start time

t16: Sixteenth end time

Other features and effects of the present invention will be clearly presented in the embodiment with reference to the drawings, in which: FIG. 1 is a circuit diagram of a conventional boost converter; FIG. 2 is a circuit diagram illustrating the high boost of the present invention One of the preferred embodiments of the converter; FIG. 3 is an equivalent circuit diagram illustrating a preferred embodiment of the high boost converter of the present invention; 4 is an operation timing diagram of the preferred embodiment; FIG. 5 is a circuit diagram of the preferred embodiment operating in the first stage; FIG. 6 is a circuit diagram of the preferred embodiment operating in the second stage; FIG. 7 Is a circuit diagram of the preferred embodiment operating in the third stage; FIG. 8 is a circuit diagram of the preferred embodiment operating in the fourth stage; FIG. 9 is a circuit diagram of the preferred embodiment operating in the fifth stage; 10 is a circuit diagram of the preferred embodiment operating in the sixth stage; FIG. 11 is a circuit diagram of the preferred embodiment operating in the seventh stage; FIG. 12 is a circuit diagram of the preferred embodiment operating in the eighth stage; 13 is a circuit diagram of the preferred embodiment operating at the ninth stage; FIG. 14 is a circuit diagram of the preferred embodiment operating at the tenth stage; FIG. 15 is a circuit diagram of the preferred embodiment operating at the eleventh stage Circuit diagram; FIG. 16 is a circuit diagram of the preferred embodiment operating at the twelfth stage; FIG. 17 is a circuit diagram of the preferred embodiment operating at the thirteenth stage; FIG. 18 is the preferred embodiment operating at the tenth stage A circuit diagram of four stages; FIG. 19 is a circuit diagram of the preferred embodiment operating at the fifteenth stage; FIG. 20 is a circuit diagram of the preferred embodiment operating at the sixteenth stage; FIG. 21 is a waveform diagram illustrating The relationship between a switch driving signal, an input voltage, and an output voltage of the preferred embodiment; FIG. 22 is a waveform diagram for verifying a steady-state characteristic of the preferred embodiment. Figure 23 is a waveform diagram used to verify the performance of a switching voltage stress of the preferred embodiment; Figure 24 is a waveform diagram illustrating the preferred embodiment at an output power of 1000 watt hours, a first Switching waveforms of the switch and a second switch; FIG. 25 is a waveform diagram illustrating the switching waveforms of the first switch and the second switch of the preferred embodiment when the output power is 200 watts; FIG. 26 is a waveform Figure, to verify the performance of a ripple current of the preferred embodiment; FIG. 27 is a waveform diagram illustrating the trans-electrical voltage of each capacitor of the preferred embodiment; FIG. 28 is a waveform diagram illustrating the Transverse (electric) voltage and current of a first and second clamp diode of the preferred embodiment; and FIG. 29 is a waveform diagram illustrating a third and fourth diode of the preferred embodiment, And the output voltage and current of the output diode.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same numbers.

Referring to FIG. 2, a preferred embodiment of the high-boost DC converter of the present invention includes a first coupled inductor, a second coupled inductor, a first switch S ₁ , a second switch S ₂ , and a first clamp A diode D ₁ , a second clamp diode D ₂ , a clamp capacitor C _c , a zero-voltage switching auxiliary unit 2, a voltage multiplying unit 3, an output unit 4, and a control unit 5. Among them, the first coupled inductor has a primary winding N _p1 and a secondary winding N _s1 , the second coupled inductor has a primary winding N _p2 and a secondary winding N _s2 , each side winding has a The first end and a second end. Wherein, the first clamping diode D ₁ and the second clamping diode D ₂ have an anode and a cathode, respectively.

The first end of the primary winding N _p1 of the first coupling inductor is electrically connected to the first end of the primary winding N _p2 of the second coupling inductor, and the DC input voltage source makes the primary winding of the first coupling inductor N _p1 and the primary winding N _{p2 of} the second coupled inductor respectively receive an input current i _In provided by an input voltage V _in .

The anode of the first clamping diode D ₁ is electrically connected to the second end of the primary winding N _p1 of the first coupling inductor, and the anode of the second clamping diode D ₂ is electrically connected to the second coupling inductor The second end of the primary winding N _p2 . The cathode of the second clamping diode D ₂ is electrically connected to the cathode of the first clamping diode D ₁ .

The zero-voltage switching auxiliary unit 2 includes a first auxiliary diode D _a1 , a second auxiliary diode D _a2 , an auxiliary inductance L _a , a third auxiliary diode D _a3 , and an auxiliary switch S _a .

The first auxiliary diode D _a1 has an anode electrically connected to the first end of the first switch S ₁ , and a cathode. The second auxiliary diode D _a2 has an anode electrically connected to the first end of the second switch S ₂ , and a cathode electrically connected to the cathode of the first auxiliary diode D _a1 . The auxiliary inductor L _a having a cathode electrically connected to the first auxiliary diode D _a1 of the first end and a second end. The third auxiliary diode D _A3 having an anode electrically connected to a second end of the inductance L _a of the auxiliary, and a cathode electrically connected to the cathode of the first diode D _1. The auxiliary switch S _a having a first terminal electrically connected to the auxiliary inductor L _a second end, a second ground terminal, and a control unit electrically connected to the third terminal 5. Therefore, the anode of the first auxiliary diode D _a1 forms a first end of the zero-voltage switching auxiliary unit 2, and the anode of the second auxiliary diode D _a2 forms a second of the zero-voltage switching auxiliary unit 2 At the end, the cathode of the third auxiliary diode D _a3 forms a third end of the zero-voltage switching auxiliary unit 2.

The voltage multiplying unit 3 includes the third diode D ₃ , the fourth diode D ₄ , the secondary winding N _s1 of the first coupled inductor, the secondary winding N _{s2 of} the second coupled inductor, The first capacitor C ₁ and the second capacitor C ₂ .

The second end of the secondary winding N _s1 of the first coupled inductor is electrically connected to the second end of the secondary winding N _s2 of the second coupled inductor, and the third diode D ₃ has an electrical connection to the first a first end of the secondary winding N _s2 cathode anode of the clamp diode D ₁ of the cathode, and an electrical connector coupled to the second inductor, the fourth diode D is electrically connected to _{the. 4} having a first The anode of the first end of the secondary winding N _s1 of the coupled inductor and a cathode. The first capacitor C ₁ has a first end electrically connected to the cathode of the fourth diode D ₄ , and a second end electrically connected to the cathode of the third diode D ₃ . The second capacitor C ₂ has a first end electrically connected to the first end of the secondary winding N _s1 of the first coupled inductor, and a second end electrically connected to the cathode of the first clamp diode D ₁ end. Therefore, the second terminal of the second capacitor C ₂ forms an input terminal of the voltage multiplying unit 3, and the first terminal of the first capacitor C ₁ forms an output terminal of the voltage multiplying unit 3.

The output unit 4 includes an output diode D _o, an output capacitor C _o, and an output resistor R _o. The output diode D _o having a first electrically connected to the first terminal of the capacitor C _1, an anode, a cathode, and providing the output voltage V _o of. The output capacitor C _o having a first output terminal electrically connected to the cathode of a diode D _o, and a second end grounded. The output resistance R _o having a first output terminal electrically connected to the cathode of a diode D _o, and a second end grounded.

The first switch S ₁ has a first end electrically connected to the second end of the primary winding N _p1 of the first coupled inductor, a second end grounded, and a third end electrically connected to the control unit 5, the The control unit 5 controls the first switch S _{1 to} switch between a conducting state (ie conducting) and a non-conducting state (ie non-conducting) by outputting a first pulse wave modulation signal. The second switch S ₂ has a first end electrically connected to the second end of the primary winding N _p2 of the second coupling inductor, a second end grounded, and a third end electrically connected to the control unit 5, the The control unit 5 controls the second switch S _{2 to} switch between a conducting state and a non-conducting state by outputting a second pulse modulation signal. Further, the control unit 5 also outputs a third pulse modulation signal, to control the auxiliary switch S _a switch between a conductive state and a nonconductive state.

It is worth mentioning that, in the present embodiment, the first switches S _1, the second switch S _2, and the auxiliary switch S _a are all N-type power semiconductor transistor, but is not limited thereto.

In addition, in this embodiment, the time period of the first pulse modulation signal and the second pulse modulation signal are the same, but the working phase differs by 180°, and a part of the on-time of the first switch S ₁ parts overlaps a portion of the second on-time of S _2. The conduction time of the third pulse modulation signal is very short.

The coupling points of the first coupling inductance and the second coupling inductance are indicated by "‧" and "*" respectively.

Referring to FIG. 3, it is a non-ideal equivalent circuit diagram of this embodiment to illustrate a first magnetizing inductance L _m1 and a first leakage inductance L _k1 induced by the first coupling inductance, and the second coupling A second magnetizing inductance L _m2 and a second leakage inductance L _k2 induced by the inductance, a first switch parasitic capacitance C _S1 related to the first switch S ₁ , and a second switch S ₂ related to the second switch S ₂ The second switch parasitic capacitance _CS2 .

According to the non-ideal equivalent circuit diagram, the control unit 5 generates the first pulse modulation signal, the second pulse modulation signal, and, respectively, to control the first switch S ₁ and the second switch S ₂ , And a conduction ratio D is greater than 0.5 (when the conduction ratio D is less than 0.5, the high boost converter of the present invention can also operate, but the voltage gain M is smaller), and the first switch S ₁ and the second switch S ₂ work to 180 degrees of phase staggered manner, the auxiliary switch S _a is turned on for a short time, the main purpose of helping the first switch S ₁ and the second switch S ₂ reaches zero voltage switching (ZVS). In the steady state, according to the states of the first switch S ₁ and the second switch S ₂ , a timing diagram of the high boost converter of the present invention will be further described in sixteen stages below.

The following are the circuit diagrams of the sixteen stages of operation of this embodiment, in which the conducting elements are indicated by solid lines and the non-conducting elements are indicated by dashed lines, and the following analysis is based on four conditions:

Condition 1: The conduction voltage drop between all power switches and diodes is zero.

Condition 2: The clamping capacitor C _c , the output capacitor C _o , the first capacitor C ₁ , and the second capacitor C ₂ are sufficiently large, and the capacitance of the first capacitor C ₁ is equal to the second capacitor C ₂ Capacitance, therefore, the voltage across the clamp capacitor C _c , the voltage across the output capacitor C _o , the voltage across the first capacitor C ₁ , and the voltage across the second capacitor C ₂ are in one It can be regarded as a constant during the switching cycle.

，且該第一磁化電感L_m1的電感值與該第二磁化電感L_m2的電感值同等於一磁化電感L_m的電感值，即L_m1=L_m2=L_m，該第一漏電感L_k1的電感值與該第二漏電感L_k2的電感值同等於一漏電感L_k1的電感值，即L_k1=L_k2=L_k，而該第一耦合電感及該第二耦合電感的耦合係數

。 Condition 3: the turns ratio of the first coupled inductor and the second coupled inductor is equal, that is, the turns ratio of a coupled inductor

, And the inductance value of the first magnetizing inductance L _{m1 and} the inductance value of the second magnetizing inductance L _m2 are equal to the inductance value of a magnetizing inductance L _m , that is, L _m1 =L _m2 =L _m , the first leakage inductance L The inductance value of _{k1 and} the inductance value of the second leakage inductance L _k2 are equal to the inductance value of a leakage inductance L _k1 , that is, L _k1 =L _k2 =L _k , and the coupling of the first coupling inductance and the second coupling inductance coefficient

.

Condition 4: The magnetizing inductor current i _{Lm of} the coupled inductor operates in continuous conduction mode (CCM).

Each stage is described in the following content, where the time t corresponds to the start time of each stage is a first start time t0 to a sixteenth start time t15, when the time t reaches a sixteenth end At time t16, the entire converter completes sixteen stages of a cycle.

The first stage [t: t0~t1]:

Referring to FIGS. 4 and 5, the time t at which the first stage starts is equal to the first start time t0, the first switch S ₁ and the second switch S _{2 are both} in the conducting state, and all diodes are reversed The bias voltage is not turned on. The primary winding N _p1 of the first coupled inductor and the primary winding N _p2 of the second coupled inductor are equal to the input voltage V _in , that is, the first magnetizing inductance L _m1 , The crossover voltage of the second magnetizing inductance L _m2 , the first leakage inductance L _k1 , and the second leakage inductance L _k2 are all the input voltage V _in , and their currents rise linearly with the same slope,

When the time t is equal to the second start time t1 and the second switch S _{2 is} switched to the non-conducting state, this stage ends.

The second stage [t: t1~t2]:

4 and 6, the time t at which the second stage starts is equal to the second start time t1, and the second switch S _{2 is} switched to the non-conducting state. The current i _{Lk2 of} a second leakage inductance _{charges the} second switch parasitic capacitance C _S2 , the voltage across the second switch v _ds2 starts to rise from zero voltage, the voltage of the secondary winding of the first and second coupling inductors The difference can be expressed as,

When the time t is equal to the third start time t2 and the voltage across the second switch v _ds2 is equal to the voltage V _{Cc of} a clamping capacitor, the second clamping diode D ₂ and the third diode D ₃ , And the fourth diode D _{4 is} turned on, this stage is over. Because the capacitance value of the second switch parasitic capacitance C _S2 is very small, the time in this stage is very short.

The third stage [t: t2~t3]:

4 and 7, the time t at which the third stage starts is equal to the third start time t2, the second clamp diode D ₂ , the third diode D ₃ , and the fourth diode D _{4 is} turned on, the cross-voltage of the secondary winding of the second coupled inductor is less than zero, that is, V _in -V _Cc <0, the current i _{Lk2 of} the second leakage inductor decreases, and passes through the second clamp diode The body D ₂ charges the clamping capacitor C _c , and the energy stored in the second magnetizing inductance L _m2 is transferred to the secondary winding N _{s2 of} the second coupled inductance through the primary winding N _{p2 of} the second coupled inductance Through the third diode D ₃ and the fourth diode D ₄ , the first capacitor C ₁ and the second capacitor C _{2 are} charged. On the other hand, the current of the secondary windings (N _s1 , N _s2 ) of the first and second coupled inductors is induced to the primary windings (N _p1 , N _p2 ) of the first coupled inductor, so that the first leakage The induced current i _{Lk1 increases} with the current i _{Lm1 of} a first inductor, the current i _{D3 of} a third diode, and the current i _{D4 of} a fourth diode, i _Lk1 = i _Lm1 + n (i _D3 +i _D4 )…Form 3

When the time t is equal to the fourth start time t3, and the current i _{Lk2 of} the second leakage inductance drops to zero, the second clamp diode D ₂ becomes non-conducting with zero current switching (ZCS), this stage End. Because the second clamp diode D ₂ switches to non-conduction with zero current, there is no reverse recovery loss problem.

The fourth stage [t: t3~t4]:

Referring to FIGS. 4 and 8, the time t at which the fourth stage starts is equal to the fourth start time t3, the second clamp diode D ₂ is non-conductive, and the second magnetizing inductance L _{m2 is} completely determined by the first and The primary winding (N _p1 , N _p2 ) of the second coupled inductor senses the secondary winding (N _s1 , N _s2 ) of the first and second coupled inductors to continue to the first capacitor C ₁ and the first The second capacitor C _{2 is} charged, and the charging current from the third diode D ₃ and the fourth diode D ₄ is related to the current i _{Lm2 of} a second inductor and is expressed as, i _D3 + i _D4 = ( i _Lm2 / n )…Equation 4

The current i _{S1 of} the first switch can be expressed as i _S1 =(i _Lm1 +i _Lm2 )... Formula 5

When the time t is equal to the fifth start time t4, the switching of the auxiliary switch S _a, the end of the stage for the conductive state from the non-conductive state.

The fifth stage [t: t4~t5]:

Referring to FIGS. 4 and 9, the time t at which the fifth stage starts is equal to the fifth start time t4, the auxiliary switch S _{a is} in the conductive state, and the second auxiliary diode D _{a2 is} never turned to conductive, because this auxiliary inductance L _a, and its current initial value is zero, so that the auxiliary switches S _a and the second auxiliary diode D _a2 can be switched to zero current is turned on. At this time, the auxiliary inductance L _a , the second switch parasitic capacitance C _S2 , and the second leakage inductance L _k2 resonate, the auxiliary inductance current i _La rises in the form of resonance, and the voltage across the second switch v _ds2 The resonance form drops, and the current i _{Lk2 of} the second leakage inductance _rises from zero, causing the currents of the secondary windings (N _s1 and N _s2 ) of the first and second coupling inductances to start to fall, thereby causing the third and second The current i _D3 of the polar body and the current i _{D4 of} the fourth diode decrease.

When the time t is equal to the start of the sixth time t5, the leakage inductance of the second current i _Lk2 the second inductor current is equal to the i _Lm2, at this time, the current i _D3 of the third diode and the fourth diode The current i _{D4 of the} body drops to zero, and the third diode D ₃ and the fourth diode D ₄ are naturally switched to non-conduction with zero current switching, and this stage ends.

The sixth stage [t: t5~t6]:

Referring to FIGS. 4 and 10, the time t at which the sixth stage starts is equal to the sixth start time t5, the third diode D ₃ and the fourth diode D ₄ are both non-conductive, and the second switch voltage across v _ds2 continued to decline due to resonance, v _ds2 when the voltage across the second switch drops to zero, the second switch S _2, the body diode conduction, the second switch S ₂ zero-voltage switching condition Established.

When the time t is equal to the seventh start time t6, the second switch S ₂ switches from the non-conducting state to the conducting state, reaches zero voltage switching performance, and this stage ends.

The seventh stage [t: t6~t7]:

Referring to FIGS. 4 and 11, the time t at the beginning of the seventh stage is equal to the seventh start time t6, and the second switch S ₂ switches to the on state with zero voltage. At this time, the cross-voltage v _La of an auxiliary inductor is At zero, the current i _{La of} the auxiliary inductor remains constant.

When the eighth time t equal to the start time T7, of the auxiliary switch S _a is controlled by the third pulse modulation signal, switching from the conducting state for the non-conductive state, the end of the stage.

The eighth stage [t: t7~t8]:

Referring to FIG. 4 and FIG. 12, the beginning of the present time t is equal to an eighth of the eighth stage of the start time T7, of the auxiliary switch S _a in the non-conducting state, since the current i _La of the auxiliary inductor continuity, so that the third The auxiliary diode D _{a3 is} turned on, and the magnitude of the cross-voltage v _La of the auxiliary inductor is equal to the negative voltage V _Cc of the clamping capacitor, that is (v _La =-V _Cc ), and the current i _{La of} the auxiliary inductor drops demonstrably The energy stored in the auxiliary inductor L _a is transferred to the clamping capacitor C _c .

When the time t is equal to the ninth start time t8, the current i _{La of} the auxiliary inductor drops to zero, and the second auxiliary diode D _a2 and the third auxiliary diode D _a3 are naturally switched to non-conducting with zero current switching , This stage is over.

Referring to FIGS. 4 and 13, then, in the eight stages of the second half of the switching cycle, the energy stored in the first magnetizing inductance L _m1 is transmitted to the load formed by the output unit 4 through coupling induction, and the auxiliary switch S is controlled _a Bring the first switch S ₁ to zero voltage switching. Since the operating principles of the ninth and tenth stages are similar to those of the first and second stages of the first half of the switching cycle, detailed analysis is omitted here, and FIG. 13 shows the circuit in the ninth stage.

Referring to FIGS. 4 and 14, it should be noted that the difference between the circuit in the tenth stage and the circuit in the ninth stage is that in the circuit in the tenth stage, the first switch parasitic capacitance C _S1 is turned on due to the start of charging.

The eleventh stage [t: t10~t11]:

Referring to FIGS. 4 and 15, the time t at which the eleventh stage starts is equal to the eleventh starting time t10, the first switch S _{1 is} switched in the non-conduction state and the first clamp diode D _{1 is} turned on, The current i _{Lk1 of} a first leakage inductance _charges the voltage V _{Cc of the} clamping capacitor, and the current i _{Lk1 of} the first leakage inductance starts to decrease. The energy stored in the first magnetizing inductance L _m1 is transmitted to the output unit 4 by coupling induction, and the current i _{Do of} the output diode rises, the rate of increase is controlled by the first leakage inductance L _k1 , the first and The secondary winding (N _s1 , N _s2 ) of the second coupled inductor, the first capacitor C ₁ , and the second capacitor C ₂ serve as voltage sources to increase the voltage gain M.

When the time t is equal to the twelfth start time t11, the current i _{Lk1 of} the first leakage inductance drops to zero, and the first clamp diode D ₁ is naturally switched to non-conducting with zero current switching, and this stage ends.

The twelfth stage [t: t11~t12]:

Referring to FIGS. 4 and 16, the time t at the beginning of the twelfth stage is equal to the twelfth starting time t11, the first clamp diode D _{1 is} switched off, and the current i _{Lm1 of} the first inductor is completely From the coupled induction to the output unit 4 through the secondary windings (N _s1 , N _s2 ) of the first and second coupled inductors, the current i _{Do of} the output diode can be expressed as, i _Do = (i _Lm2 / n )…Formula 6

Voltage V _Cc to the output unit 4 of the clamp capacitor is discharged, wherein the second switch current i _S2 equal to the first coupled inductor current i _Lm1 of the second inductor current i _Lm2, i.e. i _S2 = ( i _Lm1 +i _Lm2 ).

When the thirteenth time t equal to the start time T12, when the auxiliary switch S _a conducting state for switching from the non-conductive state, the end of this phase.

The thirteenth stage [t: t12~t13]:

Referring to FIGS. 4 and 17, the time t at the beginning of the thirteenth phase is equal to the thirteenth starting time t12, the auxiliary switch S _{a is} in the on state, and the first auxiliary diode D _{a1 is} switched on, because the the initial value of the current i _La of the auxiliary inductor is zero, so that the auxiliary switch S _a and the first auxiliary diode D _a1 is switched to zero current switching the conducting state. The current i _{Lk1 of} the first leakage inductance _rises from zero, and the current i _{Do of} the output diode decreases.

When the time t is equal to the fourteenth time T13 starts, the output current is i _Do diode drops to zero, the output diode D _o to zero current switching is switched to the natural non-conducting state, the end of this phase.

The fourteenth stage [t: t13~t14]:

Referring to FIGS. 18, 19, and 20, since the operations of the fourteenth, fifteenth, and sixteenth phases correspond to the operations of the sixth, seventh, and eighth phases corresponding to the first half of the switching period, respectively The principle is similar, except that the second auxiliary diode D _a2 is turned on in the first half of the switching period, and the first auxiliary diode D _a1 is turned on in the second half of the switching period, so detailed analysis is omitted here.

After the above-mentioned sixteen stages are completed, the next switching period T _{s is} entered, and the circuit operation of the first stage is restarted.

From the above-mentioned analysis of the sixteen stages, it can be seen that both the first switch S ₁ and the second switch S _{2 of the} high boost converter of the present invention can achieve zero voltage switching performance, although the auxiliary switch S _a does not have zero voltage handover performance, but it can reach the auxiliary switch S _a zero current switching to the conducting state, switching losses decrease. In addition, because the first leakage inductance L _k1 and the second leakage inductance L _k2 enable all diodes to naturally switch to the non-conducting state with zero current switching, the reverse recovery loss is improved.

Before doing the steady-state voltage gain analysis, in order to simplify the analysis, it needs to be based on the following conditions:

Condition 1: Ignore the extremely short flexible switching stage, and only consider the first, third, fourth, ninth, eleventh, and twelfth stages.

Condition 2: ignore the first leakage inductance L _k1 and the second leakage inductance L _k2 .

Condition 3: The clamping capacitor C _c , the output capacitor C _o , the first capacitor C ₁ , and the second capacitor C ₂ are large enough to ignore the voltage ripple of the capacitor, so that the voltage across the capacitor is regarded as a constant.

Voltage gain:

Since the cross-voltage V _{Cc of} the clamp capacitor C _c can be regarded as the output voltage of the conventional boost converter, the cross-voltage V _{Cc of} the clamp capacitor can be derived as shown in Equation 7,

A voltage across the first capacitor _C1 of V C ₁ and a second voltage V across the capacitor C ₂ of _C2, may be the primary winding by the first and second stages of a third inductor coupled to the secondary winding of the induction The voltage is expressed by the turns ratio n of the coupled inductor, that is, v _Ns1 =nV _in , v _Ns2 =n(V _in -V _Cc ), so the voltage V _{C1 of} the first capacitor C ₁ can be derived as Equation 8,

In the eleventh stage, the primary winding of the first and second coupled inductors induces the voltage of the secondary winding, that is, v _Ns1 =n(V _in -V _Cc ), v _Ns2 =nV _in , so the output voltage V _o can be derived as in formula 9,

Therefore, the voltage gain of this converter can be expressed as

From Equation 10, it can be seen that the voltage gain has two design degrees of freedom: the coupled inductor turns ratio n and the conduction ratio D. The high-boost converter of the present invention can achieve a high voltage gain by appropriately designing the coupled inductor turns ratio n, without having to operate at a very large conduction ratio. Correct The voltage gain curve corresponding to the turns ratio n of the coupled inductor and the conduction ratio D is shown in FIG. 21. It can be seen from FIG. 20 that when the conduction ratio D=0.6 and the turns ratio n of the coupled inductor is 1, the voltage gain is 10 times.

Voltage stress of switch and diode:

According to the operating principle of the high-boost converter, the voltage stress of the first switch S ₁ , the second switch S ₂ , and the auxiliary switch S _a is equal to the cross-voltage V _{C1 of} the first capacitor C ₁ , which is expressed as One

The first clamp diode D ₁ , the second clamp diode D ₂ , the third diode D ₃ , the fourth diode D ₄ , the output diode D _o , the first The voltage stress of an auxiliary diode D _a1 , the second auxiliary diode D _a2 , and the third auxiliary diode D _a3 can be derived from each stage as Equation 12, Equation 13, Equation 14, and Formula fifteen,

Voltage of the conventional switching interleaved power converter and a boost diode output voltage stress, and the stress of the present invention, the high voltage switch of the boost converter output voltage V _o is only a 1 / (3n + 1) times , And the maximum voltage stress of the diode is only 2n/(3n+1) times of _Vo , if the coupling inductance turns ratio n is 1, it is only 1/2 times. In high output voltage applications, a metal oxide semiconductor field effect transistor (MOSFET) with a low rated withstand voltage and a low on-resistance (R _DS(ON) ) can be used to reduce the switching conduction loss. In addition, the Schottky diode can be used for the diode with lower voltage stress, and its conduction voltage drop is lower than that of a general power diode, which can reduce conduction loss.

Using IsSpice software to make preliminary circuit simulation and verification of the high boost converter of the present invention:

According to the circuit operation analysis results, IsSpice software is used for preliminary simulation. The specifications of the high boost converter are: input voltage 40V, output voltage 400V, maximum output power 1000W, switching frequency 50KHz (50KHz), and the The turns ratio n of the coupled inductor is 1, verifying the characteristics of the high boost converter, the simulation results and analysis are as follows,

(1) Verify the steady-state characteristics:

1000 watts at full load, the first switches S _1, the second switch S _2, and the auxiliary switch S _a drive signal, the input voltage and the output voltage waveform shown in Figure 22, wherein the auxiliary switch S _a ON time 1 microsecond, it can be seen from FIG. 21 of the input voltage V _in is equal to 40 volts, the output voltage V _o is equal to 400 V, the conduction ratio D is 0.61, the theoretical ratio of conduction is very close to 0.6, in line with the voltage gain The analysis result of (Formula 10). It is verified that the voltage gain is 10 times, but the converter does not have to operate at a very large turn-on ratio.

(2) Verify the switching voltage stress:

Referring to FIG. 23, it is the drive signal of each switch and the waveform of the voltage across each switch. From the figure, it can be seen that the maximum voltage across each switch is about 100 volts, so the voltage stress It is a quarter of the output voltage of 400 volts, which is in accordance with the derivation result of Equation 11, which verifies that each switch of the high boost converter has the advantage of low voltage stress.

(3) Verify that both switches can achieve zero voltage switching operation:

At a full load of 1000 watt-hours, the driving signals of the first switch S ₁ and the second switch S ₂ and the waveforms of the voltage across the first switch v _ds1 and the voltage across the second switch v _ds2 are shown in FIG. 24. From the waveform at the moment of switching, it can be seen that before the switch is switched to the on state, the cross-over voltage v _ds1 of the first switch and the cross-over voltage v _{ds2 of} the second switch have both dropped to zero first, so the operation of zero-voltage switching is reached.

When the load is 200 watts at light load, the driving signals of the first switch S ₁ and the second switch S ₂ and the waveforms of the voltage across the first switch v _ds1 and the voltage across the second switch v _ds2 are as shown in the figure As shown in 25, it can be seen that the first switch S ₁ and the second switch S ₂ still reach zero voltage switching operation.

(4) Verify that the interleaved operation has low input ripple current performance:

Referring to Figure 26, when loaded with 1000 watts, the leakage inductance of the first current i _Lk1, the leakage inductance of the second current i _Lk2, and the waveform of the input current i _in, the current of the leakage inductance of the first 26 seen from FIG. The ripple current of i _Lk1 and the current of the second leakage inductance i _Lk2 are both about 28 amperes (A), while the ripple current of the input current i _in is only about 1.77 amperes, verifying that the interleaved operation has the effect of reducing the input ripple current performance.

(5) Verify the capacitor voltage:

Referring to FIG. 27, the cross-voltage waveforms of the clamping capacitor C _c , the first capacitor C ₁ , the second capacitor C ₂ , and the output capacitor C _o are presented. The voltage across the clamping capacitor V _{Cc is} slightly greater than 100 volts, the voltage across the first capacitor C V _{C1 1,} the capacitor C and a second cross voltage V _{C2 2} is approximately equal to 100 volts, the output voltage across capacitor C _o is equal to 400 volts, are in compliance with the principle of formula The derivation results of formula 7, formula 8, and formula 9.

(6) Verify the reverse recovery problem and voltage stress of the clamp diode:

Referring to FIG. 28, the waveforms of the current i _D1 and the voltage (v _D1 ) of the first clamp diode, and the current i _D2 and the voltage (v _D2 ) of the second clamp diode are known from FIG. 28 The current i _D1 of the first clamp diode and the current i _{D2 of} the second clamp diode both drop to zero first, the cross-voltage of the first clamp diode and the second clamp two The voltage across the polar body is switched from conducting to non-conducting. Therefore, no reverse recovery current is generated, thus reducing the reverse recovery loss and electromagnetic interference (EMI) noise. On the other hand, the voltage stress of the first clamp diode D ₁ and the second clamp diode D ₂ is about 100 volts, which is only 1/4 of the output voltage V _o , which is in accordance with Equation 12 Derive the results.

(7) Verify reverse recovery problems and voltage stress of switching diodes and output diodes:

Referring to FIG. 29, the waveforms of the current i _D3 and voltage (v _D3 ) of the third diode, and the current i _D4 and voltage (v _D4 ) of the fourth diode, as shown in FIG. 28, there is no reverse recovery The generation of current can reduce the noise of reverse recovery loss and electromagnetic interference. On the other hand, the voltage stress of the third diode D ₃ and the fourth diode D ₄ is about 200 volts, which is only The 1/2 of the output voltage V _o conforms to the derivation result of Equation 13.

In summary, the above embodiments have the following advantages:

(1) Since the voltage multiplying unit 3 having the first coupling inductor and the second coupling inductor is introduced, the turn ratio of the first coupling inductor and the second coupling inductor increases the design freedom of the voltage gain.

(2) Since the zero voltage switching is added to the auxiliary unit 2, may utilize the first switch parasitic capacitances C _S1 and the second switch parasitic capacitance C _S2 respectively of the auxiliary inductor L _a resonance technology, such that the first switch S ₁ is Both the second switch S ₂ can achieve zero voltage switching, and the auxiliary switch S _a can achieve the soft cut performance of zero current switching, so as to reduce switching losses and improve efficiency.

(3) Since the switching voltage stress is much lower than the output voltage V _o , a metal oxide semiconductor field effect transistor (MOSFET) with a low rated withstand voltage and a low on-resistance (R _DS(ON) ) can be used to reduce Switch conduction loss.

(4) The first leakage inductance L _k1 and the second leakage inductance L _{k2 on the} input side are of a parallel architecture and interleaved operation, and have the effect of sharing input current and reducing input current ripple.

(5) The first leakage inductance L _k1 and the second leakage inductance L _k2 can alleviate the first clamping diode D ₁ , the second clamping diode D ₂ , and the third diode D ₃ , And the reverse recovery problem of the fourth diode D ₄ and reduce the reverse recovery loss. The energy of the first leakage inductance L _k1 and the second leakage inductance L _k2 can be recovered and reused, which can not only avoid voltage surge of the main switch, but also improve efficiency.

The above advantages (1) to (5) can indeed solve the shortcomings of the conventional boost converter, and indeed achieve the purpose of the present invention.

However, the above are only examples of the present invention, and the scope of implementation of the present invention cannot be limited by this, any simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still classified as Within the scope of the invention patent.

2: zero voltage switching auxiliary unit

3: voltage multiplication unit

4: output unit

5: control unit

N _p1 : primary winding of the first coupled inductor

N _p2 : primary winding of the second coupled inductor

N _s1 : secondary winding of the first coupled inductor

C _S1 : Parasitic capacitance of the first switch

_CS2 : Parasitic capacitance of the second switch

D _o : output diode

D ₁ : First clamp diode

D ₂ : Second clamp diode

D ₃ : Third diode

D ₄ : Fourth diode

D _a1 : first auxiliary diode

D _a2 : Second auxiliary diode

D _a3 : third auxiliary diode

N _s2 : secondary winding of the second coupled inductor

S ₁ : first switch

S ₂ : Second switch

S _a: the auxiliary switch

C _c : clamping capacitance

_Co : output capacitance

C ₁ : the first capacitor

C ₂ : second capacitor

L _a : auxiliary inductance

R _o : output load

V _in : input voltage

V _o : output voltage

Claims (9)

A high boost converter includes: a first coupled inductor and a second coupled inductor, the first and second coupled inductors have a primary winding and a secondary winding, each side winding has a first And a second end, the first ends of the primary windings of the first and second coupled inductors are electrically connected together to receive a DC input voltage, and the second ends of the secondary windings of the first coupled inductor are electrically connected A second terminal of the secondary winding of the second coupled inductor; a first switch having a first terminal electrically connected to the second terminal of the primary winding of the first coupled inductor and a second terminal grounded, and Controlled switching between conducting and non-conducting; a second switch having a first end electrically connected to the second end of the primary winding of the second coupled inductor and a second end connected to ground, and controlled to switch on And non-conducting; a first clamp diode with an anode electrically connected to the second end of the primary winding of the first coupling inductor, and a cathode; a second clamp diode with an electrical connection An anode at the second end of the primary winding of the second coupling inductor, and a cathode electrically connected to the cathode of the first clamping diode; a clamping capacitor has an electrical connection to the first clamping diode A first end of the cathode of the body and a second end connected to the ground; a zero-voltage switching auxiliary unit electrically connecting the first end of the first switch, the first end of the second switch, and the first of the clamping capacitor Terminal for the first switch and the second switch to achieve zero voltage switching; A third diode with an anode electrically connected to the cathode of the first clamp diode, and a cathode electrically connected to the first end of the secondary winding of the second coupled inductor; a fourth diode The body has an anode electrically connected to the first end of the secondary winding of the first coupled inductor, and a cathode; a first capacitor has a first end electrically connected to the cathode of the fourth diode, and A second end electrically connected to the first end of the secondary winding of the second coupled inductor; a second capacitor having a first end electrically connected to the first end of the secondary winding of the first coupled inductor, And a second end electrically connected to the cathode of the first clamp diode; and an output unit electrically connected to the cathode of the fourth diode to provide an output voltage; the zero-voltage switching auxiliary unit includes a A first auxiliary diode, a second auxiliary diode, an auxiliary inductor, a third auxiliary diode and an auxiliary switch; the first auxiliary diode has a first end electrically connected to the first switch Anode and cathode; the second auxiliary diode has an anode electrically connected to the first end of the second switch, and a cathode electrically connected to the cathode of the first auxiliary diode; the auxiliary inductor has an electric A first end connected to the cathode of the first auxiliary diode and a second end; the third auxiliary diode has an anode electrically connected to the second end of the auxiliary inductor, and an electrically connected to the first diode Cathode of body cathode; The auxiliary switch has a first terminal electrically connected to the second terminal of the auxiliary inductor, and a second terminal grounded. The high boost converter according to claim 1, wherein the output unit includes an output diode, an anode electrically connected to the first end of the first capacitor, and a cathode providing the output voltage; The output capacitor has a first end electrically connected to the cathode of the output diode and a second end grounded; and an output resistor has a first end electrically connected to the cathode of the output diode, and a The second end of the ground. The high-boost converter according to claim 1, wherein the first end of each primary winding is a dotted end, and the second end of each primary winding is a non-dotted end. The high boost converter according to claim 1, wherein the first end of each secondary winding is a dotted end, and the second end of each secondary winding is a non-dotted end. The high-boost converter according to claim 1, wherein the first switch is an N-type power semiconductor transistor, and the first end of the first switch is a drain, and the second end of the first switch is Source. The high-boost converter according to claim 1, wherein the second switch is an N-type power semiconductor transistor, and the first end of the second switch is a drain, and the second end of the second switch is Source. The high-boost converter according to claim 1, further includes a control unit that generates a first pulse signal that switches the first switch, and everything For the second pulse signal of the second switch, the first pulse signal and the second pulse signal have the same cycle time. The high boost converter according to claim 7, wherein the control unit further generates a third pulse signal for controlling the zero-voltage switching auxiliary unit. The high boost converter according to claim 1, wherein a part of the on-time of the first switch overlaps with a part of the on-time of the second switch.

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