TW201541829A - DC power boost circuit with high-efficiency and large-range output voltage - Google Patents

Abstract

Provided is a DC power boost circuit with high-efficiency and large-range output voltage, which includes: an inductor; a transformer having primary, secondary, tertiary and quaternary windings; a first switch having a first terminal electrically connected to the primary winding and a second terminal connected to the ground; a second switch having a first terminal electrically connected to the tertiary winding and a second terminal connected to the ground; a first clamp circuit for clamping the voltage cross over the first switch; a second clamp circuit for clamping the voltage cross over the second switch; an output capacitor having a first terminal for providing an output voltage and a second terminal connected to the ground; a first output diode; a second output diode; a first boost diode having an anode connected to the ground and a cathode electrically connected to the secondary winding; and a second boost diode having an anode connected to the ground and a cathode electrically connected to the quaternary winding.

Description

High efficiency and wide range output voltage DC power supply boost circuit

The present invention relates to a booster circuit, and more particularly to a DC power boost circuit having a high efficiency and a wide range of output voltages.

Generally, the voltage of a single battery is extremely low, and multiple batteries must be connected in series to provide higher voltage and power. However, when power is generated in series, if one of the batteries has a power supply output problem, the output power will be reduced and the overall loss will be accelerated, resulting in Reduced service life. Therefore, the current application uses less series and multiple parallels to reduce the single battery capacity matching failure problem, and with a boost converter to increase the voltage level to supply the load.

Referring to Figure 1, in the literature "PWLee, YSLee, DK Cheng, and XCLiu, "Steady-state analysis of an interleaved boost converter with coupled inductors," IEEE Trans. Ind. Electron., vol. 47, no. 4 A conventional interleaved boost converter is proposed in pp. 787-795, Aug. 2000. It is suitable for electrical connection to an external power supply that provides an input voltage Vi (eg, a fuel cell, a solar cell, or a lead acid). a battery) receives the input voltage Vi and is stepped up to obtain an output voltage Vo, and the interleaved boost converter includes: primary and secondary windings L1, L2, first and second diodes SD1 , SD2 First and second switches SW1, SW2, and an output capacitor Cf.

The primary and secondary side windings L ₁ , L ₂ each have a first end and a second end electrically coupled to the external power source to receive the input voltage.

The first diode SD1 has an anode electrically connected to the second end of the primary winding L1 and a cathode.

The second diode SD2 has an anode electrically connected to the second end of the secondary winding L2 and a cathode electrically connected to the cathode of the first diode SD1.

The output capacitor Cf has a first end electrically connected to the cathode of the first diode SD1 and providing the output voltage, and a grounded second end.

The first switch SW1 has a first end electrically connected to the second end of the primary side winding L1, a grounded second end, and the first switch is controlled to switch between the conductive state and the non-conductive state.

The second switch SW2 has a first end electrically connected to the second end of the secondary side winding L2, a grounded second end, and the second switch is controlled to switch between the conducting state and the non-conducting state.

Referring to Figure 2, when the first switch is turned on and the second switch is not turned on: the external power source is provided with a charging current through the primary excitation winding L _1, a first switch to ground to the primary winding L ₁ is generated A voltage. However, since the voltage of the primary winding L ₁ is small at the initial stage of charging, the reverse bias of the first diode is severe, and the reverse recovery current consumption power is generated, resulting in a decrease in power conversion efficiency.

Should the secondary winding L ₂ depending on its winding turns of the primary side L ₁ ratio of an induced voltage, and thus the external power source input voltage V _i of the series of the secondary winding L ₂ of the induced voltage so that the second The diode SD2 is turned on, and supplies current to the output capacitor Cf via the secondary side winding L ₂ and the second diode SD2 to obtain the output voltage V _o . At this time, if the voltage drop of the second diode SD2 is ignored, the two-terminal voltage across the second switch SW2 is equivalent to the output voltage V _o . For the safety of the circuit operation, high-voltage power with high withstand voltage must be selected. The crystal not only increases the cost, but also has a high conduction loss due to the high crossover voltage when the second switch SW2 is turned on.

Referring to FIG. 3, when the second switch SW2 is turned on and the first switch SW1 is not turned on: the external power source is turned to supply current through the secondary side winding L ₂ and the second switch SW2 to the ground to the secondary winding L ₂ is excited and charged to generate a voltage. At this time, the second diode SD2 also has a problem of reverse recovery current.

Should the primary winding L ₁ in accordance with the turns of the secondary winding L ₂ ratio of an induced voltage, and thus the external power source input voltage V _i of the series of the primary winding L ₁ of the induced voltage so that the first two diode SD1 is turned on, and current is supplied through the primary winding L _1, a first diode SD1 flows to the output capacitor Cf to obtain the output voltage V _o. At this time, if the voltage drop of the first diode SD1 is ignored, the two-terminal voltage across the first switch SW1 is equivalent to the output voltage V _o and has the same problem as the second switch SW2.

Further description of a conventional interleaved boost converter Please refer to this document, so it will not be repeated.

In summary, the conventional interleaved boost converter has the following disadvantages:

1. The first and second switches SW1, SW2 have a higher lead The loss is achieved, and it is required to use a high-cost power transistor with a higher cost.

2. The first and second diodes SD1, SD2 have a problem of reverse recovery current, which will result in a decrease in power conversion efficiency.

Accordingly, a first object of the present invention is to provide a DC power supply boosting circuit having a high efficiency and a wide range of output voltages for solving the above problems.

Therefore, the DC power supply boosting circuit of the high efficiency and large range output voltage of the present invention comprises: an inductor having a first end receiving an input voltage and a second end; and a transformer having one to four side windings, And each winding has a positive end point and a non-polar point end, the positive end point of the primary side winding and the non-polar point end of the tertiary side winding are electrically connected to the second end of the inductor; a first switch Having a first end electrically connected to the non-polar point end of the primary side winding and a grounded second end, and the first switch is controlled to switch between the conducting state and the non-conducting state; a second switch having a Electrically connecting the first end of the positive side end of the tertiary side winding and the second end of the ground, and the second switch is controlled to switch between the conducting state and the non-conducting state; a first clamping circuit electrically connecting the first Between the first end and the second end of a switch, for clamping the two end voltages of the first switch, and electrically connecting the non-polar point end of the secondary side winding; a second clamping circuit electrically connecting the first First end of the second switch Between the second end and the second end, the second end of the second switch is clamped and electrically connected to the positive end of the fourth-side winding; an output capacitor having a first end for providing an output voltage, and a grounded second end; a first output diode having an anode electrically connected to the positive terminal of the secondary winding, and a cathode electrically connected to the first end of the output capacitor; a second output a pole body having an anode electrically connected to a non-polar point end of the fourth-order winding, and a cathode electrically connected to a cathode of the first output diode; a first step-up diode having a grounded anode And a cathode electrically connected to the positive terminal of the secondary winding; and a second boosting diode having a grounded anode and a cathode electrically connected to the non-polar point of the fourth winding.

A second object of the present invention is to provide a solution to the above problem The problem is the high efficiency of a large range of output voltage DC power boost circuit.

Thus, the present invention has high efficiency and large range output voltage DC power The source boosting circuit is adapted to be electrically connected to an external low-voltage power supply that provides an input voltage to receive the input voltage, and is accordingly boosted to obtain an output voltage, and the high-efficiency and large-range output voltage of the DC power supply is boosted. The circuit comprises: an inductor having a first end receiving an input voltage, and a second end; a transformer having one to four side windings, each winding having a positive end point and a non-polar point End, the positive side winding The polarity end and the non-polar end of the tertiary winding are electrically connected to the second end of the inductor; a first switch having a first end electrically connected to the non-polar end of the primary winding and a second grounded And the first switch is controlled to switch between the conductive state and the non-conductive state; a second switch has a first end electrically connected to the positive side end of the tertiary side winding and a grounded second end, and The second switch is controlled to be switched between a conducting state and a non-conducting state; a first clamping circuit is electrically connected between the first end and the second end of the first switch for clamping the two ends of the first switch a second clamping circuit electrically connected between the first end and the second end of the second switch for clamping the two ends of the second switch Translating and electrically connecting the positive polarity end of the fourth-order side winding; an output capacitor having a first end providing an output voltage and a grounded second end; and a first output diode having a first output diode An anode electrically connected to the positive terminal of the secondary winding, and a cathode electrically connected to the first end of the output capacitor; a second output diode having an anode electrically connected to the non-polar point end of the fourth-order winding, and a cathode electrically connected to the first output diode a cathode; a first step-up diode having a grounded anode; and a cathode electrically connected to the positive terminal of the secondary winding; A second boosting diode has a grounded anode and a cathode electrically connected to the non-polar point end of the fourth-order winding.

V _IN ‧‧‧ input voltage

Output voltage V _H ‧‧‧

L _d ‧‧‧Inductance

T _r ‧‧‧Transformer

L ₁ ‧‧‧ primary winding

L ₂ ‧‧‧ secondary winding

L ₃ ‧‧‧3rd side winding

L ₄ ‧‧‧four-side winding

Q ₁ ‧‧‧First switch

Q ₂ ‧‧‧Second switch

1‧‧‧First clamp circuit

2‧‧‧Second clamp circuit

C ₁ ‧‧‧First Clamp Capacitor

C ₂ ‧‧‧Second clamp capacitor

C ₃ ‧‧‧ output capacitor

D ₁ ‧‧‧First clamped diode

D ₂ ‧‧‧Second clamped diode

D ₃ ‧‧‧first output diode

D ₄ ‧‧‧second output diode

D ₅ ‧‧‧First booster diode

D ₆ ‧‧‧second booster diode

Other features and effects of the present invention will be apparent from the following description of the drawings, wherein: FIG. 1 is a circuit diagram illustrating a conventional interleaved boost converter; FIG. 2 is a circuit diagram illustrating The interleaved boost converter performs boosting; FIG. 3 is a circuit diagram illustrating the interleaved boost converter performing another boost; FIG. 4 is a circuit diagram illustrating the high efficiency and wide range output voltage of the present invention. A preferred embodiment of the circuit; FIG. 5 is a timing diagram illustrating the conduction duty cycle of a first switch and a second switch of the preferred embodiment in an overlap region; FIG. 6(a) is a circuit diagram FIG. 6(b) is a circuit diagram illustrating the mode 2 of the two switches in the overlap region of the preferred embodiment; FIG. 6 is a schematic diagram of the mode 2 of the preferred embodiment of the present invention; FIG. (c) is a circuit diagram illustrating mode 3 of the dual switch operation of the preferred embodiment in the overlap region; FIG. 6(d) is a circuit diagram illustrating the two switch operations of the preferred embodiment in the overlap region Mode 4; Figure 6(e) is a circuit diagram illustrating the comparison The two switches of the preferred embodiment operate in mode 5 of the overlap region; Figure 6 (f) is a circuit diagram illustrating the mode 6 of the dual switch operation of the preferred embodiment in the overlap region; Figure 6 (i) is a circuit diagram illustrating the two switch operations of the preferred embodiment Mode 7 of the overlap region; FIG. 6(j) is a circuit diagram illustrating mode 8 of the dual switch operation of the preferred embodiment in the overlap region; FIG. 7(a) is a circuit diagram illustrating the preferred embodiment A transformer operates in mode 1 of an active area; FIG. 7(b) is a circuit diagram illustrating mode 2 of the transformer operating in the active region; FIG. 7(c) is a circuit diagram illustrating the comparison The transformer of the preferred embodiment operates in mode 3 of the active region; FIG. 7(d) is a circuit diagram illustrating mode 4 of the preferred embodiment of the transformer operating in the active region; FIG. 7(e) is a circuit diagram FIG. 7(f) is a circuit diagram illustrating the operation of the transformer of the preferred embodiment in mode 6 of the active area; FIG. 8 is a moment The sequence diagram illustrates that the transformer of the preferred embodiment operates in a failure zone; Figure 9(a) is a Road map described the operation of the preferred embodiment of the transformer in the embodiment mode of the failure of a region; FIG. 9 (b) is a circuit diagram illustrating the operation of the preferred embodiment of the transformer in the embodiment mode of the failure of the two regions; Figure 9 (c) is a circuit diagram showing the mode of operation of the transformer of the preferred embodiment in the failure zone; Figure 9 (d) is a circuit diagram illustrating the operation of the transformer of the preferred embodiment in the failure zone Figure 4 (e) is a circuit diagram illustrating mode 5 of the preferred embodiment of the transformer operating in the fail zone; Figure 9 (f) is a circuit diagram illustrating the transformer operation of the preferred embodiment Mode 6 in the failure zone; FIG. 10(a) is a graph illustrating the relationship between a voltage gain of the preferred embodiment and the conduction duty cycle of the two switches; FIG. 10(b) is a graph illustrating The relationship between the turns ratio of the transformer of the preferred embodiment is 2 and the coupling coefficient; FIG. 11(a) is a simulation diagram illustrating the first simulation when an output voltage of the preferred embodiment is 48V; Figure 11 (b) is a simulation diagram showing the second simulation when the output voltage of the preferred embodiment is 48 V; Figure 11 (c) is a simulation diagram showing the output voltage of the preferred embodiment is The third simulation at 48V; Figure 11(d) is a simulation diagram showing that the output voltage of the preferred embodiment is 48V. The fourth simulation; FIG. 11(e) is a simulation diagram illustrating a fifth simulation when the output voltage of the preferred embodiment is 48V; and FIG. 11(f) is a simulation diagram illustrating the preferred embodiment. The sixth simulation when the output voltage is 48V; Figure 11 (g) is a simulation diagram illustrating a seventh simulation when the output voltage of the preferred embodiment is 48 V; Figure 11 (h) is a simulation diagram illustrating the output voltage of the preferred embodiment. The eighth simulation at 48V; FIG. 11(i) is a simulation diagram illustrating the ninth simulation when the output voltage of the preferred embodiment is 48V; FIG. 11(j) is a simulation diagram illustrating the comparison. The tenth simulation when the output voltage of the preferred embodiment is 48V; FIG. 12(a) is a simulation diagram illustrating the first simulation when the output voltage of the preferred embodiment is 110V, FIG. 12(b) Is a simulation diagram illustrating the second simulation when the output voltage of the preferred embodiment is 110V; and FIG. 12(c) is a simulation diagram illustrating the third embodiment of the output voltage of the preferred embodiment at 110V. Figure 12(d) is a simulation diagram illustrating a fourth simulation when the output voltage of the preferred embodiment is 110V; Figure 12(e) is a simulation diagram illustrating the preferred embodiment of the preferred embodiment The fifth simulation when the output voltage is 110V, and FIG. 12(f) is a simulation diagram illustrating the sixth simulation when the output voltage of the preferred embodiment is 110V, and FIG. 12(g) is a The simulation diagram illustrates the seventh simulation when the output voltage of the preferred embodiment is 110V; and FIG. 12(h) is a simulation diagram illustrating the eighth simulation when the output voltage of the preferred embodiment is 110V. ; Figure 12 (i) is a simulation diagram illustrating the ninth simulation when the output voltage of the preferred embodiment is 110 V; Figure 12 (j) is a simulation diagram illustrating the output voltage of the preferred embodiment. The tenth simulation at 110V; FIG. 13(a) is a simulation diagram illustrating the first simulation when the output voltage of the preferred embodiment is 240V; and FIG. 13(b) is a simulation diagram illustrating the comparison. The second simulation of the output voltage of the preferred embodiment is 240V; FIG. 13(c) is a simulation diagram illustrating the third simulation when the output voltage of the preferred embodiment is 240V; FIG. 13(d) Is a simulation diagram illustrating a fourth simulation when the output voltage of the preferred embodiment is 240V; and FIG. 13(e) is a simulation diagram illustrating the fifth of the output voltage of the preferred embodiment at 240V. FIG. 13(f) is a simulation diagram illustrating a sixth simulation when the output voltage of the preferred embodiment is 240V; FIG. 13(g) is a simulation diagram illustrating the preferred embodiment. The seventh simulation when the output voltage is 240V; FIG. 13(h) is a simulation diagram illustrating the eighth simulation when the output voltage of the preferred embodiment is 240V; FIG. 13(i) A simulation diagram illustrating the ninth simulation when the output voltage of the preferred embodiment is 240V; and FIG. 13(j) is a simulation diagram illustrating the tenth of the output voltage of the preferred embodiment at 240V. simulation; Figure 14 is a schematic view showing a conversion efficiency of the preferred embodiment; Figure 15 (a) is a measurement diagram showing the first embodiment of the output voltage of 48 V and an output power of 400 W. Figure 15(b) is a measurement diagram illustrating the second actual measurement when the output voltage of the preferred embodiment is 48V and the output power is 400W; Figure 15(c) is an amount The figure shows the third actual measurement when the output voltage of the preferred embodiment is 48V and the output power is 400W; FIG. 15(d) is a measurement diagram illustrating the output voltage of the preferred embodiment. The fourth actual measurement is 48V and the output power is 400W; FIG. 15(e) is a measurement diagram illustrating the fifth practical example when the output voltage is 48V and the output power is 400W. Figure 15 (f) is a measurement diagram illustrating the sixth actual measurement of the output voltage of the preferred embodiment at 48 V and an output power of 400 W; Figure 15 (g) is a measurement The seventh actual measurement when the output voltage of the preferred embodiment is 48V and the output power is 400W is illustrated; FIG. 15(h) is a measurement diagram illustrating the better The eighth actual measurement when the output voltage of the embodiment is 48V and the output power is 400W; FIG. 15(i) is a measurement diagram illustrating that the output voltage of the preferred embodiment is 48V and the output power is 400W. The ninth actual measurement of the time; FIG. 15(j) is a measurement diagram illustrating the tenth actual measurement when the output voltage of the preferred embodiment is 48V and the output power is 400W; FIG. 16(a) Is a first measurement showing the first actual measurement when the output voltage of the preferred embodiment is 48V and the output power is 800W; Figure 16 (b) is a measurement diagram illustrating the second actual measurement when the output voltage of the preferred embodiment is 48 V and the output power is 800 W; Figure 16 (c) is a measurement diagram illustrating The third embodiment of the preferred embodiment has an output voltage of 48 V and an output power of 800 W. Figure 16 (d) is a measurement diagram illustrating the output voltage of the preferred embodiment being 48 V and output power. The fourth actual measurement is 800W; FIG. 16(e) is a measurement diagram illustrating the fifth actual measurement when the output voltage of the preferred embodiment is 48V and the output power is 800W; FIG. (f) is a measurement diagram illustrating the sixth actual measurement when the output voltage of the preferred embodiment is 48 V and the output power is 800 W; FIG. 16(g) is a measurement diagram indicating that the measurement is preferred. The seventh actual measurement of the output voltage of the embodiment is 48V and the output power is 800W; FIG. 16(h) is a measurement diagram illustrating that the output voltage of the preferred embodiment is 48V and the output power is 800W. The eighth actual measurement at the time; FIG. 16(i) is a measurement diagram illustrating the ninth practical case when the output voltage of the preferred embodiment is 48V and the output power is 800W. Figure 16 (j) is a measurement diagram illustrating the tenth actual measurement when the output voltage of the preferred embodiment is 48 V and the output power is 800 W; Figure 17 (a) is a measurement map, The first actual measurement when the output voltage of the preferred embodiment is 110V and the output power is 600W is illustrated; FIG. 17(b) is a measurement diagram illustrating that the output voltage of the preferred embodiment is 110V and The second actual measurement when the output power is 600W; FIG. 17(c) is a measurement diagram illustrating the third actual measurement when the output voltage of the preferred embodiment is 110V and the output power is 600W; Figure 17 (d) is a measurement diagram illustrating the fourth actual measurement when the output voltage of the preferred embodiment is 110 V and the output power is 600 W; Figure 17 (e) is a measurement diagram illustrating The fifth actual measurement when the output voltage is 110V and the output power is 600W; FIG. 17(f) is a measurement diagram showing that the output voltage of the preferred embodiment is 110V and the output power is The sixth actual measurement is 600W; FIG. 17(g) is a measurement diagram illustrating the seventh actual measurement when the output voltage of the preferred embodiment is 110V and the output power is 600W; (h) is a measurement diagram showing the eighth actual measurement when the output voltage of the preferred embodiment is 110 V and the output power is 600 W; FIG. 17(i) is a measurement diagram indicating that the measurement is preferred. The ninth actual measurement of the output voltage of the embodiment is 110V and the output power is 600W; FIG. 17(j) is a measurement diagram illustrating that the output voltage of the preferred embodiment is 110V and the output power is 600W. The tenth actual measurement in time; FIG. 18(a) is a measurement diagram illustrating the first output voltage of the preferred embodiment when the output voltage is 110V and the output power is 1700W. Actual measurement; FIG. 18(b) is a measurement diagram illustrating the second actual measurement when the output voltage of the preferred embodiment is 110 V and the output power is 1700 W; FIG. 18(c) is a measurement. The figure shows a third actual measurement when the output voltage of the preferred embodiment is 110 V and the output power is 1700 W. FIG. 18(d) is a measurement diagram illustrating the output voltage of the preferred embodiment. The fourth actual measurement when 110V and the output power is 1700W; FIG. 18(e) is a measurement diagram illustrating the fifth actual amount when the output voltage of the preferred embodiment is 110V and the output power is 1700W. Measurement; Figure 18 (f) is a measurement diagram illustrating the sixth actual measurement when the output voltage of the preferred embodiment is 110 V and the output power is 1700 W; Figure 18 (g) is a measurement diagram illustrating The seventh actual measurement when the output voltage is 110V and the output power is 1700W in the preferred embodiment; FIG. 18(h) is a measurement diagram showing that the output voltage of the preferred embodiment is 110V and the output power is The eighth actual measurement is 1700W; FIG. 18(i) is a measurement diagram illustrating the ninth actual measurement when the output voltage of the preferred embodiment is 110V and the output power is 1700W; FIG. (j) is a measurement diagram illustrating the tenth actual measurement when the output voltage of the preferred embodiment is 110 V and the output power is 1700 W; FIG. 19(a) is a measurement diagram illustrating the preferred measurement. The first actual measurement when the output voltage of the embodiment is 240V and the output power is 626W; FIG. 19(b) is a measurement diagram showing that the output voltage of the preferred embodiment is 240V and the output power is 626W. The second actual measurement at the time; FIG. 19(c) is a measurement diagram illustrating the output voltage of the preferred embodiment being 240V and the output power being 626W. Three actual measurements; Fig. 19(d) is a measurement diagram illustrating the fourth actual measurement when the output voltage of the preferred embodiment is 240V and the output power is 626W; Fig. 19(e) is an amount The figure shows the fifth actual measurement when the output voltage of the preferred embodiment is 240V and the output power is 626W; FIG. 19(f) is a measurement diagram illustrating the output voltage of the preferred embodiment. The sixth actual measurement is 240V and the output power is 626W; FIG. 19(g) is a measurement diagram illustrating the seventh practical situation when the output voltage of the preferred embodiment is 240V and the output power is 626W. Measure; Figure 19 (h) is a measurement diagram illustrating the eighth actual measurement when the output voltage of the preferred embodiment is 240 V and the output power is 626 W; Figure 19 (i) is a measurement diagram illustrating The ninth actual measurement of the output voltage of the preferred embodiment is 240V and the output power is 626W; FIG. 19(j) is a measurement diagram illustrating that the output voltage of the preferred embodiment is 240V and the output power is The tenth actual measurement is 626W; FIG. 20(a) is a measurement diagram illustrating the first actual measurement when the output voltage of the preferred embodiment is 240V and the output power is 1700W; (b) is a measurement diagram illustrating the second actual measurement when the output voltage of the preferred embodiment is 240 V and the output power is 1700 W; FIG. 20(c) is a measurement diagram indicating that the measurement is preferred. The third actual measurement when the output voltage is 240V and the output power is 1700W; FIG. 20(d) is a measurement diagram showing that the output voltage of the preferred embodiment is 240V and the output power is 1700W. The fourth actual measurement in time; FIG. 20(e) is a measurement diagram illustrating the output voltage of the preferred embodiment being 240V and the output power being 1700W. Five actual measurements; FIG. 20(f) is a measurement diagram illustrating the sixth actual measurement when the output voltage of the preferred embodiment is 240V and the output power is 1700W; FIG. 20(g) is a The measurement chart illustrates the seventh actual measurement when the output voltage of the preferred embodiment is 240 V and the output power is 1700 W; FIG. 20(h) is a measurement diagram illustrating the output of the preferred embodiment. The eighth actual measurement when the voltage is 240V and the output power is 1700W; FIG. 20(i) is a measurement diagram illustrating the ninth type when the output voltage of the preferred embodiment is 240V and the output power is 1700W. Actual measurement Figure 20 (j) is a measurement diagram illustrating the tenth actual measurement when the output voltage of the preferred embodiment is 240 V and the output power is 1700 W; and Figure 21 is a schematic diagram illustrating the actual measurement of the comparison A conversion efficiency of a preferred embodiment.

Referring to FIG. 4, a preferred embodiment of the high efficiency wide range output voltage DC power boost circuit of the present invention is suitable for electrical connection to an external low voltage power supply (eg, fuel cell, solar cell, lead) that provides an input voltage V _IN . An acid battery or the like receives the input voltage V _IN and is stepped up to obtain an output voltage V _H , and the high-efficiency and large-range output voltage DC power supply boosting circuit comprises: an inductor L _d , a transformer T _r , a first switch Q ₁ , a second switch Q ₂ , a first clamping circuit 1 , a second clamping circuit 2 , an output capacitor C ₃ , a first output diode D ₃ , a second output The diode D ₄ , a first boost diode D ₅ , and a second boost diode D ₆ .

The inductor L _d has a first end electrically connected to the external low voltage power supply to receive the input voltage V _IN , and a second end.

The transformer T _r has primary to fourth secondary windings L ₁ -L ₄ , and each winding L ₁ -L ₄ has a positive terminal and a non-polar terminal, and the positive terminal of the primary winding L ₁ And the non-polar point end of the tertiary side winding L ₃ is electrically connected to the second end of the inductor L _d . And let the turns ratio of the transformer T _r be N=N ₂ /N ₁ =N ₄ /N ₃ , and N ₁ =N ₃ , wherein the parameters N ₁ to N ₄ are the primary to fourth-order side windings L, respectively. The number of ₁ ~ L ₄ .

The first switch Q ₁ has a first end electrically connected to the non-polar point end of the primary side winding L ₁ and a grounded second end, and the first switch Q ₁ is controlled to be switched between a conducting state and a non-conducting state. between. In the present embodiment, the first switch Q ₁ is an N-type power semiconductor transistor, and a first terminal of the first switch Q ₁ is a drain, the second terminal of the first switch Q ₁ is a source.

The second switch Q ₂ has a first end electrically connected to the positive terminal of the tertiary side winding L ₃ and a grounded second end, and the second switch Q ₂ is controlled to be switched between the conducting state and the non-conducting state. between. In the present embodiment, the second switch Q ₂ is an N-type power semiconductor transistor, and the first terminal of the second switch Q ₂ is a drain, the second terminal of the second switch Q ₂ is a source.

The first clamping circuit 1 is electrically connected between the first switch Q ₁ of the first and second ends, and when the first switch Q ₁ is not turned on, the first clamping circuit 1 is used to clamp the first switch Q the voltage across the two ends _1, and electrically connected to the non-polar end point of the secondary winding L _2, and thus, the first switch Q ₁ may be selected with low breakdown voltage specifications of the power semiconductor transistor element in order to reduce cost, the first The clamping circuit 1 includes a first clamping diode D ₁ and a first clamping capacitor C ₁ .

The first clamp diode D ₁ has an anode electrically connected to the first end of the first switch Q ₁ and a cathode electrically connected to the non-polar point end of the secondary side winding L ₂ .

The first clamp capacitor C ₁ has a first end electrically connected to the non-polar point end of the secondary side winding L ₂ and a grounded second end.

The second clamping circuit 2 is electrically connected between the second switch Q ₂ of the first and second ends, and when the second switch Q ₂ is not turned on, the second clamp circuit 2 for clamping the second switch Q the voltage across the two ends _2, and is electrically connected with the positive terminal of the fourth point of winding L _4, and therefore, the second switch Q ₂ may be selected low voltage specifications of the power semiconductor transistor element to reduce cost, the second The clamping circuit 2 includes a second clamping diode D ₂ and a second clamping capacitor C ₂ .

The second clamp diode D ₂ has an anode electrically connected to the first end of the second switch Q ₂ and a cathode electrically connected to the positive terminal of the fourth-order winding L ₄ .

The second clamp capacitor C ₂ has a first end electrically connected to the positive terminal of the fourth-order winding L ₄ and a grounded second end.

The output capacitor C ₃ having a first end, a second end and a ground providing the output voltage of the V _H.

The first output diode D ₃ has an anode electrically connected to the positive terminal of the secondary winding L ₂ and a cathode electrically connected to the first end of the output capacitor C ₃ .

The second output diode D ₄ has an anode electrically connected to the non-polar point end of the fourth-order side winding L ₄ and a cathode electrically connected to the cathode of the first output diode D ₃ .

The first boosting diode D ₅ has a grounded anode and a cathode electrically connected to the positive terminal of the secondary winding L ₂ .

The second step-up diode D ₆ has a grounded anode and a cathode electrically connected to the non-polar point end of the fourth-order side winding L ₄ .

Referring to FIG. 5 and FIG. 6 , the parameters D and Δd are respectively the conduction duty cycle of the two switches Q ₁ and Q ₂ and the overlapping conduction duty cycle, and d ₁ and d2 are respectively the conduction responsibility of the first switch Q ₁ . The non-overlapping conduction duty cycle obtained by the period D deducting the overlapping conduction duty cycle Δd, the conduction duty cycle D of the second switch Q ₂ minus the overlapping conduction duty cycle Δd, the non-overlapping conduction responsibility cycle, parameter V _g1, V _g2 respectively, representing the control of the first and second switches Q _1, Q ₂ is turned on if the voltage, i _LM parameter represents the magnetizing current of the transformer T _r, i _Ld parameter represents the current flowing through the inductor L _d, i _L1 , i _L2 , i _L3 , and i _L4 represent a current flowing through the primary side winding L _{1 ,} a current flowing through the secondary side winding L _{2 ,} a current flowing through the tertiary side winding L ₃ , and flows through the fourth ₄ L of the primary winding current, i _Q1, V _Q1 parameter representing the current flowing through the first switch Q _1, and Q of _a voltage across the first switch, i _Q2, V _Q2 represent the parameters of flow through the second switch Q ₂ of the current, the voltage across Q ₂ of the second switch, the parameter i _D1 ~ i _D6 Representative of such a current flowing through diode D ₁ ~ D _6, V _D1 ~ V _D6 parameters representing these diodes D ₁ ~ D ₆ of the voltage across. According to the switching of the two switches Q ₁ and Q ₂ , the embodiment operates in the overlap region, so that the conduction duty cycle D is between 0.5 and 1 (0.5 ≦ D < 1), wherein there are eight modes; the effective region of the transformer, Let the duty cycle D be between 1/3 and 0.5 (1/3≦D≦0.5), of which there are six modes; the transformer failure zone, the conduction duty cycle D is between 0 and 1/3 (0 ≦D≦1/3), there are six modes, the following describes each zone and mode separately.

Wherein, the coupling coefficient k of the transformer T _r is defined as shown in the formula (1): k=L _M /(L _K1 +L _M ). (1)

The parameter L _M represents the magnetizing inductance of the primary side winding L ₁ or the tertiary side winding L ₃ , and the parameter L _K1 represents the leakage inductance of the primary side winding L ₁ .

<Principle analysis>

<overlap area 0.5≦D<1>

Mode One (Time: t ₀ ~ t ₁ ): Referring to FIG. 5 and FIG. 6a, the first switch Q _{1 is} continuously turned on, and the second switch Q _{2 is} not turned on.

The external power source is connected in series with the inductor L _{d to} supply current through the primary side winding L ₁ , and the first switch Q ₁ flows to the ground to excite the primary side winding L ₁ , and is similar to the input voltage V _{IN of} the external power source and the inductance L The voltage of the voltage V _Ld of _{d is} the same as the voltage across the two ends of the primary side winding L ₁ , so that the voltage V _{L1 of} the primary side winding L ₁ can be derived as shown in the formula (2): V _L1 =V _IN +V _Ld ........(2)

At the same time, the voltage V _{L1 of the} primary side winding L ₁ is induced to the positive polarity end of the other three windings L ₂ to L ₄ according to the turns ratio, so that the secondary to fourth secondary windings L ₂ to L ₄ each generate an induced voltage. Passing energy through a two-part path, respectively, a first partial path and a second partial path, as follows: a first partial path: the tertiary side winding L ₃ is turned on via the second clamped diode D ₂ The second clamp capacitor C ₂ is charged, and the voltage sum of the induced voltage of the tertiary side winding L _{3 and} the voltage of the primary side winding L ₁ via the equation (2) is equal to the voltage across the second clamp capacitor C ₂ . The two ends, so the voltage V _C2 of the second clamp capacitor C ₂ of mode one is as shown in the formula (3): V _c2 = kV _L1 + V _L1 . . . formula (3)

The voltages V _L2 and V _{L4 of the} secondary and fourth-order side windings L ₂ and L _{4 are} as shown in the formula (4): V _L2 = kNV _L1 = V _L4 . (4)

It can be proved from the subsequent mode that the current flowing through the primary side winding L ₁ leakage inductance L _K1 and the tertiary side winding leakage inductance L _K3 is respectively absorbed by the first clamping capacitor C ₁ and the second clamping capacitor C ₂ , and The first clamp capacitor C ₁ and the second clamp capacitor C ₂ clamp the withstand voltage of the two switches Q ₁ and Q ₂ .

a second partial path: a voltage sum of the induced voltage of the secondary side winding L _{2 and} the voltage of the first clamping capacitor C ₁ is turned on via the first output diode D ₃ to the output capacitor C ₃ as a formula ( 5), let the output voltage of mode 1 be represented by V _H1 : V _H1 = V _C1 + V _L2 = V _C1 + NkV _L1 . . . Equation (5)

Before the present mode is turned off, the charging current i ₃ L winding _L3 of the second clamp capacitor C ₂ from the tertiary side is nearing completion, so that the three winding currents i _{L3 3} L is very small, close to zero.

Mode 2 (time: t ₁ ~ t ₂ ): Referring to FIG. 5 and FIG. 6b, the first switch Q _{1 is} continuously turned on, and the second switch Q ₂ starts to be turned on.

When the second switch Q _{2 is} turned on, the current i _L3 of the tertiary side winding L ₃ is close to zero, and the second clamp diode D ₂ is a Schottky Diode of low reverse recovery current. Therefore, the second switch Q ₂ forms a characteristic of low current conduction or zero current switching. Since the first switch Q ₁ is turned on continuously, the primary _{winding. 1} L three-side winding and the excitation and L ₃ has inductive characteristics simultaneously, so that the four voltage winding L V ₁ ~ L ₄ is _L1 ~ V _L4 zero The four windings L ₁ to L _{4 can} be regarded as equivalent short circuits, and the transformer T _r stops all energy transfer, and the currents i _L1 to i _{L4 of} the four windings L ₁ to L ₄ are zero.

The inductance L _d receiving the input voltage V _IN, the inductance L _d of the voltage and the same input voltage V _IN, the current of the inductor L _d i _Ld continuously raised to increase the energy storage, and the average shunt to the second switch Q ₁ , Q ₂ . According to the Voltage-Second Balance theorem, it can be calculated that the voltage of the inductor L _d in mode one is as shown in equation (6): V _Ld(1) = V _IN (Δd/d ₁ )... ..........式(6)

Substituting the equation (6) into the equation (2), the voltage V _L1 of the primary side winding L ₁ during the mode one is obtained as shown in the equation (7): V _L1 = (1 + Δd / d ₁ ) V _IN .............Formula (7)

Mode 3 (time: t ₂ ~ t ₃ ): Referring to FIG. 5 and FIG. 6 c , the first switch Q _{1 is} turned off, and the second switch Q _{2 is} continuously turned on.

When the first switch Q ₁ is turned off, the transformer T _r is changed to L ₃ of the three excitation winding, the exciting current i _LM tertiary windings L ₃ generated is negative, and L ₁ continued from the primary winding Flow, the current i _{L3 of} the tertiary side winding L ₃ maintains the conduction path of the second switch Q ₂ when the mode is second, and the current i _{L3 of} the tertiary side winding L ₃ starts to receive the inductance L _d current i _Ld and is transmitted through Magnetic energy conversion is induced to the other three windings L ₁ , L ₂ , L ₄ . The tertiary windings L induced current i _{L3 3} of because of the tertiary windings L leakage inductance L _{k3 3} limiting its rise, the primary winding L leakage inductance of ₁ L _k1 need to release its stored energy, causing the inductor L _D Now a current i _Ld can not flow to the tertiary windings L _3, so that the leakage inductance of the primary winding L ₁ of a first current i _Lk1 charge the parasitic capacitance of the switch Q _1, and thus the first switching voltage V _{Q1 1} to Q He begins to rise, forcing the first clamping diode D ₁ and discharge parasitic capacitance of the first reduction clamping diode D ₁ is reverse bias voltage. The fourth winding L ₄ and the capacitor C ₂ of the second clamping force to the second output diode D ₄ of discharge parasitic capacitance, the second diode D output voltage V _{D4 4} starts decreasing. Similarly, the voltage V _{L2 of} the secondary side winding L ₂ also forces the first step-up diode D _{5 to} reduce the reverse bias.

Mode 4 (time: t ₃ ~ t ₄ ): Referring to FIG. 5 and FIG. 6d, the first clamp diode D ₁ , the second output diode D ₄ , and the first boost diode D _{5 are} turned on. And the second switch Q _{2 is} continuously turned on.

When the voltage V _{Q1 of} the first switch Q ₁ is higher than the voltage V _{C1 of} the first clamp capacitor C ₁ , the first clamp diode D _{1 is} turned on, and the secondary side winding L ₂ and the fourth side are The winding L ₄ also electrically conducts the first step-up diode D ₅ and the second output diode D _{4 ,} respectively. The input voltage V _IN charges the first clamp capacitor C ₁ via the inductor L _d , the primary side winding L ₁ and the path of the first clamp diode D ₁ , and then derives the mode according to the volt-second theorem. The voltage V _Ld(2) of the inductance L _d is as shown in the formula (8): V _Ld(2) = V _IN (Δd/d2). )

The voltage of the tertiary side winding L _{3 is the combination} of the input voltage V _IN and the voltage of the inductor L _d as shown in the formula (9): V _L3 =V _IN (1+Δd/d2)...... .......式(9)

The voltage V _{C1 of} the first clamp capacitor C ₁ is equal to the voltage V _{Q1 of} the first switch Q ₁ , and the first clamp capacitor C ₁ can suppress the surge voltage of the first switch Q ₁ to achieve the function of clamping voltage. The voltage V _{Q1 of the} first switch Q ₁ is as shown in the formula (10): V _Q1 = V _C1 = V _IN + V _{Ld (2)} + V _L1 = V _IN (1 + Δd / d2) + kV ₃ 10)

Substituting equation (9) into equation (10) is simplified to equation (11): V _Q1 = V _C1 = (1 + k) (1 + Δd / d2) V _IN .......... ...(11)

The voltage V _{L2 of} the secondary winding L ₂ is induced to the first clamping capacitor C ₁ via the first boosting diode D ₅ . Since the circuit is a symmetric balanced structure, the first clamping capacitor C ₁ operates in a mode the same second clamp capacitor C _2, and therefore by the formula (9) can be derived the second switch Q ₂ and the second voltage V _Q2 clamp capacitor voltage V _{C2 2} C as the formula (12) as shown: V _Q2 = V _C2 =(1+k)(1+Δd/d ₁ )V _IN .............(12)

Mode 5 (time: t ₄ ~ t ₅ ): Referring to FIG. 5 and FIG. 6e, the first switch Q _{1 is} turned off, and the second switch Q _{2 is} continuously turned on.

When the primary winding of the transformer T _r of the excitation current i _LM of L ₁ zero, the leakage energy is fully released, thus producing an exciting current i _LM excitation winding L ₃ of the tertiary side circuit. The voltage of the secondary side winding L ₂ charges the first clamp capacitor C ₁ . Let the output voltage of this mode be V _H2 as the voltage of the output capacitor C ₃ , which is equal to the voltage of the fourth clamp capacitor C ₂ connected in series with the fourth-side winding L ₄ , as shown in the formula (13): V _H2 = V _C2 +V _L4 =V _C2 +NkV _L3 .............Formula (13)

Since the second clamp capacitor C ₂ has been charged once in mode 1, the discharge current provided by the output capacitor C ₃ is effectively reduced.

Mode six (time: t ₅ ~ t ₆ ): Referring to FIG. 5 and FIG. 6f, the first switch Q ₁ starts to conduct, and the second switch Q _{2 is} continuously turned on.

When the first switch Q _{1 is} turned on again, and the second switch Q _{2 is} continuously turned on, the state at this time is the same as that of the mode 2, and the four windings L ₁ to L ₄ form a short-circuit state, and only the inductor L _{d is} stored to store electric energy.

Mode seven (time: t ₆ ~ t ₇ ): Referring to FIG. 5 and FIG. 6i, the first switch Q _{1 is} continuously turned on, and the second switch Q _{2 is} turned off.

The current i _{L3 of} the tertiary side winding L ₃ continues to flow, and begins to release its leakage current i _LK3 to charge the parasitic capacitance of the second switch Q ₂ , and release the second clamp diode D ₂ , the first The parasitic capacitance charge of the output diode D ₃ and the second boost diode D ₆ is substantially the same as that of the mode 3. In this case the transformer T _r from the primary winding L ₁ energized and its six o'clock maintaining mode current i _{L 1} of the first conduction path switch Q _1, the primary winding current i L of the inductor _{Ll 1} receives the current i _{Ld is} induced to the other three windings L ₂ , L ₃ , L _{4 by} magnetic energy conversion.

Mode VIII (time: t ₇ ~ t ₈ ): Referring to FIG. 5 and FIG. 6j, the second clamp diode D ₂ , the first output diode D ₃ , and the second boost diode D _{6 are} turned on. And the first switch Q _{1 is} continuously turned on.

The second clamp capacitor C ₂ absorbs the leakage current i _{LK3 of} the tertiary side winding L ₃ and clamps the voltage of the second switch Q ₂ . The principle of the mode is similar to that of the mode 4, when the excitation current of the transformer T _r is _LM zero, and by the time the primary excitation winding L _1, a back mode.

The complete formula of the output voltage V _H1 can be obtained by substituting equations (11) and (7) into equation (5) as shown in equation (14): V _H1 = (1 + k) V _IN (1 + Δd / d ₂ )+kNV _IN (1+△d/d ₁ ) Equation (14)

Similarly, the complete formula of the output voltage V _H can be obtained by substituting equations (12), (3) and (9) into equation (13) as shown in equation (15): V _H2 = (1 + k) V _IN ( 1+Δd/d ₁ )+kNV _IN (1+Δd/d ₂ ) Equation (15)

If the equations (14) and (15) are not equal, the symmetrical circuit is unbalanced, and the power is all shifted to one of the higher conduction duty cycles, so that the transformer T _{r is} saturated and overheated, causing the boost function to fail. Therefore, if equations (14) and (15) are equal, the symmetrical circuit will naturally balance, and the condition is simplified as shown in equation (16): N=1+(1/k)............ . (16)

Since the coupling coefficient k of the transformer T _r approaches 1, the turns ratio N is almost close to 2. If the transformer T _r turns ratio N is equal to 2, and the coupling coefficient k is close to 1, substituting into equations (14) and (15), when the two switches Q ₁ , Q ₂ do not overlap the conduction duty periods d ₁ and d ₂ We are different, the output voltage V _H in different modes remain the same, such as when no overlapping conduction duty cycle of the first switch Q ₁ 'd ₁ is larger than the second switch does not overlap the guide Q ₂ through duty cycle d ₂ (d _1> d ₂ ), it can be known that the voltage V _{C2 of} the second clamp capacitor C ₂ is less than the voltage V _{C1 of} the first clamp capacitor C ₁ , but the voltage V _{L4 of the} fourth-order winding L ₄ is greater than the voltage of the secondary side winding L ₂ V _L2 , then the relationship V _C1 +V _L2 =V _C2 +V _{L4 is} thus balanced. To simplify the theoretical analysis, the non-overlapping conduction duty period d ₁ of the first switch Q ₁ is defined to be equal to the second switch Q ₂ . The overlap conduction duty cycle d ₂ is represented by the non-overlapping conduction duty cycle d ₁ of the first switch Q ₁ , and the final output output voltage V _H can be expressed as shown in the equation (17): V _H = 4kV _IN ( 1+△d/d ₁ ).............(17)

Then, the boosting magnification G _{V is} as shown in the formula (18): G _V = V _H /V _IN = 4k (1 + Δd / d ₁ ).

Therefore, in the overlap region, the voltage gain is from 4 times to 20 times, and the boost ratio Gv is reduced without the turns ratio N of the transformer T _r being 2. In addition, the transformer T _{r has} a turns ratio N of 2 and a coupling coefficient k of 1 is substituted into the equation (4) to obtain a current i _{c1 of} the first clamp capacitor C ₁ , which can be simultaneously derived from the equation (19). Four windings L ₁ ~ L ₄ .

V _L2 =2V _L1 =V _C1 .............Formula (19)

<Transformer effective area 1/3<=D<=0.5>

When the conduction duty cycle D of the two switches Q ₁ , Q ₂ is between 1/3 and 0.5, the conduction duty cycle D of the two switches Q ₁ , Q ₂ is the non-overlapping conduction duty cycle of the first switch Q _{1 1,} because the first switch Q is turned overlapping the duty cycle is equal to ₁ d ₁ of the second switch Q is turned overlapping the duty cycle D _{2 2,} places not overlapped conduction duty cycle of the first switch Q ₁ is d ₁ of representative.

Referring to Figure 7a, a pattern for the first switch Q ₁ turns on, and the second switch Q ₂ is turned off.

Referring to FIG. 7b, mode 2 is that the two switches Q ₁ and Q _{2 are} turned off.

Referring to Figure 7c, the first model three clamping diode D _1, the first boost diode D _5, the second output diode D ₄ is turned on for the rendering.

Referring to Figures 7d to 7f, mode four to mode six are symmetrically exchanged with the first three modes, respectively.

When any one of the two switch Q _1, Q ₂ is turned on, the energy storage inductance L _d and the step-up transformer T _{R &lt;} otherwise the second switch Q _1, Q ₂ is turned off the same, the inductance L _d and discharging of the transformer T _r has no boost function.

When the first switch Q _{1 is} turned on, the inductor L _d voltage V _Ld is 0.5V _C1 , and when the first switch Q ₁ is turned off, the voltage V _{Q1 is} higher than the voltage V _{C1 of} the first clamp capacitor C ₁ , Therefore, the first clamp diode D _{1 is} turned on, and the first clamp capacitor C ₁ and the second clamp capacitor C ₂ are both charged, and the first switch Q ₁ voltage V _{Q1 is} clamped to be the first The voltage V _{C1 of the} capacitor C ₁ is clamped, and the transformer T _{r is} not boosted and presents a short circuit state. According to the volt-second balance theorem, the voltage V _{Ld of} the inductor L _d when the conduction state is known is as shown in the formula (20): V _Ld =V _IN ((1-2d ₁ )/2(1-d ₁ )).............(20)

The voltage V _{L1 of} the primary side winding L ₁ is _{expressed by the} formula (21): V _L1 =V _IN /2(1-d ₁ ). (...)

Then, the voltage V _{Q1 of} the first switch Q ₁ is as shown in the formula (22): V _Q1 = V _C1 = V _IN / (1 - d ₁ ). )

When the first switch Q _{1 is} turned on, the output voltage V _{H is} the voltage V _{L2 of} the secondary winding L ₂ in series with the voltage V _{c1 of} the first clamping capacitor C ₁ , and the voltage V of the secondary winding L _{2 L2 is} as shown in equation (23): V _L2 = kNV _L3 = kNV _IN /2 (1-d ₁ ).

Since the balance mechanism is derived as described above, the output voltage V _H can be expressed as in equation (24): V _H = V _C1 + V _L2 = (2+N) kV _IN /2 (1-d ₁ ).... ......... (24)

If the coupling coefficient k of the transformer T _r is 1, the boosting magnification G _V is as shown in the equation (25): G _V = (2+N)/2 (1-d ₁ )... .......式(25)

The above-mentioned transformer T _{r has} a turns ratio N of 2 to achieve a balancing effect, so the above equation can be simplified as shown in the equation (26): G _V = 2 / (1 - d ₁ )........ .....式(26)

<Transformer failure zone 0<=D<=1/3>

Mode One (Time: t ₀ ~ t ₁ ): Referring to FIG. 8 and FIG. 9a, the first switch Q _{1 is} turned on for a period of time, and the second switch Q _{2 is} turned off.

Q via the first switch conduction path _1, the series inductance L _d of the primary winding L ₁ of the withstand voltage of the input voltage V _IN, due to the failure of the transformer T _r, so that the voltage of the four windings of the L ₁ ~ L ₄ V _L1 ~ V _L4 approaches zero, the inductor L _d i _Ld current rises to store electrical energy, does not overlap the guide through the first switch Q ₁ 'd ₁ duty cycle conduction period for storage, the inductance L _d of The voltage V _{Ld is} as shown in equation (27): V _Ld =V _IN =L(di _{Ld /dt).............(27} )

At the same time, the first clamp capacitor C ₁ is discharged to the output capacitor C ₃ via the secondary winding L ₂ . Since the voltages V _L1 VV _{L4 of} the four windings L ₁ -L ₄ approach zero, the tertiary side The winding L ₃ and the fourth-order side winding L ₄ have no induced current i _L3 ~i _L4 .

Mode 2 (time: t ₁ ~ t ₂ ): Referring to FIG. 8 and FIG. 9b, the first switch Q _{1 is} turned off, and the second switch Q _{2 is} continuously turned off.

When the first switch Q ₁ is turned off, the current i _{Ld of} the inductor L _d cannot be changed instantaneously, so the first clamp diode D ₁ and the second clamp diode D ₂ become forward biased, providing two The path continually flows the current i _{Ld of} the inductor L _d while charging the first clamp capacitor C ₁ , the second clamp capacitor C ₂ , and the output capacitor C ₃ , and the voltage V _{Ld of} the inductor L _d is (28): V _Ld =V _c1 -V _IN =L(di _{Ld /dt).............(28} )

Since the four windings L ₁ to L ₄ have no induced current, the leakage inductance can be neglected, and the voltage of the first clamp capacitor C ₁ is derived from equations (27), (28) and the volt-second theorem as shown in equation (29): V _C1 =V _IN /(1-2d ₁ )=V _C2 .............(29)

Mode 3 (time: t ₂ ~ t ₃ ): Referring to FIG. 8 and FIG. 9 _c , the first switch Q _{1 is} continuously turned off, and the second switch Q _{2 is} turned on instantaneously.

When the second switch Q _{2 is} turned on instantaneously, the second clamp diode D _{2 is} turned off, and since the second clamp diode D ₂ is a low-back recovery current of the Schottky diode, there is almost no reverse recovery current. problem. The first output diode D ₃ starts to be turned off, and the first output diode D ₃ has a low reverse recovery current characteristic due to the secondary side winding L ₂ and its leakage inductance limitation. The second output diode D ₄ begins to release its parasitic capacitance energy, and the mode ends when the second output diode D _{4 is} turned on.

Mode 4 (time: t ₃ ~ t ₄ ): Referring to FIG. 8 and FIG. 9d, the second switch Q ₂ and the second output diode D _{4 are} continuously turned on.

The second clamp capacitor C _{2 is} connected in series to the fourth-order side winding L _{4 to} release energy to the output capacitor C ₃ via the second output diode D ₄ , because the voltage V _L4 of the fourth-order side winding L ₄ is low. Then, the output voltage V _H is the voltage of the second clamp capacitor C ₂ as shown in the formula (30): V _H =V _IN /(1-2d ₁ )=V _C2 ........... ..式(30)

The voltage gain G _V can be obtained from the above equation as shown in the equation (31): G _V =1/(1-2d ₁ )............. (31)

The second switch Q _{2 is} continuously turned on, so that the input voltage V _IN continues to store energy for the inductor L _d and the secondary side winding L ₂ .

Mode 5 (time: t ₄ ~ t ₅ ): Referring to FIG. 8 and FIG. 9e, the first switch Q _{1 is} continuously turned off, the second switch Q _{2 is} turned off, and all energy is transmitted in the same manner as mode 2. The four windings L ₁ ~L _{4 is} in a failed state.

Mode 6 (time: t ₅ ~ t ₀ ): Referring to FIG. 8 and FIG. 9 f , the first switch Q _{1 is} turned on instantaneously, the second clamp diode D ₂ , the first output diode D ₃ , and the The second output diode D _{4 is} turned on.

The first switch Q _{1 is} turned on, so that the input voltage V _IN stores energy to the inductor L _d and the primary winding L ₁ , and the current i _{Ld of} the inductor L _d and the current i _{L1 of} the primary winding L ₁ pass through the first The switch Q ₁ rises sharply after receiving the input current i _IN , and the principle of this mode is similar to that of mode three, and then returns to mode one.

It can be known from mode 1 to mode 6 that although the on-period of the two switches Q ₁ and Q ₂ is small, any mode has a current delivered to the output capacitor C ₃ , and the input voltage V _IN is connected in series with the inductor L _{d .} Therefore, the input voltage V _IN and the output voltage V _{H both} have a current continuous characteristic. In addition, under the change of the conduction duty cycle D, the output voltage V _H must be continuous, so the equations (31) and (26) must be equal at the demarcation point, and the equation is as shown in the equation (32): G _V = 2 / ( 1-d ₁ )=1/(1-2d ₁ ).............Formula (32)

It can be found that the conduction duty cycle of the two switches Q ₁ and Q ₂ is as shown in the formula (33): d ₁ = 1/3.

When the transformer T _{r is} in the active area and the dead zone, the non-overlapping conduction duty period d ₁ of the two switches Q ₁ , Q ₂ is 1/3. When the non-overlapping conduction duty cycle d _{1 is} less than 1/3, the representative output voltage V _H does not require a high boosting ratio, and only the inductance L _d is sufficient to complete, so the transformer T _r loses the boosting function and is formed with In the traditional single-inductor chopper function of the interleaving function, when the transformer T _{r is} in the dead zone, the voltage gain G _V can be adjusted from 3 times down to the same as the input voltage V _IN . If the conduction duty cycle d _{1 is} greater than 1/3, the transformer T _r has a boost function, and the inductance L _d becomes a buffer component without a boost function. When the duty cycle of conduction overlap if d ₁ is larger than 1/2, the inductance L _d T _r while the transformer has a step-up function, a higher voltage gain G _V. Therefore, the two switches Q ₁ and Q ₂ operate in different non-overlapping conduction duty cycles d ₁ , but have three kinds of boosting circuit characteristics, and have the characteristics of high output period, high voltage gain and low reverse recovery current.

<simulation and measurement results>

Referring to FIG. 10(a), in equation (16), the turns ratio N of the transformer T _r is limited to 2 and the coupling coefficient k is 1, and the conduction duty cycle D of the two switches Q ₁ and Q _{2 is} different. Equation (18), equation (26), and equation (32) yield a curve of the voltage gain G _V of the transformer T _r in three regions. The control cycle D of the two switches Q ₁ and Q ₂ is very wide. Therefore, when the transformer T _r turns ratio N is fixed at 2, the voltage gain G _V can be controlled to operate 1 to 20 times.

Referring to FIG. 10(b), when the turns ratio N of the transformer T _r is 2, a different coupling coefficient k, the curve of the conduction duty cycle D and the voltage gain G _V , when the voltage gain G _V is 10 times, The coupling coefficient k is a phenomenon in which the voltage gain G _V between 0.995 and 0.985 does not change significantly. However, when the coupling coefficient k drops to 0.97, the leakage inductance of the transformer T _r will start to affect the voltage gain G _V , but the present embodiment The conduction duty cycle D gives a wide range of the two switches Q ₁ and Q ₂ , which is sufficient to compensate for the influence of the leakage inductance of the transformer T _r at the time of high voltage output.

Referring to FIG. 11 (a) to 11 (j), respectively, the simulation is that the output power is equal to 800 W, the input voltage is 24 V, the output voltage is 48 V, the turns ratio N of the transformer T _r is 2, and the two switches Q _1. The voltage and current waveforms of each component when the switching frequency of Q ₂ is 40 kHz.

Referring to Figure 11 (a) and 11 (b), respectively, the first switch Q ₁ for the current analog voltage waveform diagram of the first clamping diode D _1, the first switch Q ₁ and the first clamp diode body D the voltage across the output voltage V _{H 1} is the same as the 48V, because of the inductance L _d and the primary winding L ₁ to accept the current i from the input voltage V _{iN iN,} the turn-on duty D is smaller than 0.33 design, the first A switch Q ₁ current exhibits a low effective current value in a square wave shape, the first clamp diode D ₁ provides the inductor L _d energy freewheeling path, and the voltage V _{D1 of} the first clamp diode D ₁ is The voltage V _{C1 of the} first clamp capacitor C ₁ is also equal to the voltage V _{Q1 of} the first switch Q ₁ .

Referring to Figures 11(c) and 11(d), the primary and secondary windings L ₁ and L ₂ and the currents i _L1 to i _{L4 of} the tertiary and fourth-order windings L ₃ and L _{4 are respectively} simulated waveforms. The waveform can be observed, and the currents i _L1 ~i _L4 of the four-side windings L ₁ -L ₄ are equal to the inductance L _d current i _Ld , and fully utilize the shunting and complementary characteristics of the four-side windings L ₁ -L ₄ .

Referring to Figures 11(e) and 11(f), the voltages and currents of the first and second output diodes D ₃ and D ₄ respectively are due to the current waveforms of the currents i _D3 and i _D4 and the second and fourth The secondary windings L ₂ and L _{4 have the same} current i _L2 and i _L4 , and the output current is the sum of the currents i _D3 and i _D4 of the first and second output diodes D ₃ and D ₄ , so the output current frequency is not only It is twice the frequency (80 kHz) of the first and second switches Q ₁ and Q ₂ and is almost a continuous current waveform, which effectively reduces the output current ripple.

Referring to FIGS. 11(g) and 11(h), the voltages and currents of the first and second step-up diodes D ₅ and D _{6 respectively} , the first and second step-up diodes D ₅ and D ₆ main function is to clamp the voltage of the first and second output diodes D ₃ , D ₄ connected in series, so the currents i _D5 , i _{D6 of} the first and second step-up diodes D ₅ , D ₆ Very low, observed by the analog waveform, the voltage across the quadrupole D ₃ ~ D ₆ is clamped to the same output voltage V _H .

Referring to Fig. 12, when the output power is 1700 W and the output voltage V _H is 110 V, the waveforms of the components are simulated. The two switches Q ₁ , Q ₂ operate in an overlap region.

See FIG. 12 (a), 12 (b ), respectively, for the first switch Q ₁ and the first clamping diode D ₁ of the voltage and current, the first switch Q ₁ and the first clamping diode D ₁ voltage clamping half the output voltage is about 55V V _H, V _H is far lower than the output voltage, since the current of the transformer T _r i _Ld accepted from the inductance L _d, and a conduction duty cycle D exceeds 0.5 design of the first low effective current value conducting current switch Q ₁ exhibits the shape of a square wave, so that the first switch Q ₁ are flexible Ju switching effect of near-zero current, the first clamping diode D ₁ without reverse recovery current shortcomings, the handover Losses and conduction losses can be effectively reduced. As the first clamp diode D ₁ provides the transformer T _r leakage inductance i _Lk1 and the magnetizing inductance L _m energy freewheeling path, the first clamp diode D ₁ cross-voltage is the first clamp capacitor C ₁ The voltage V _C1 is equal to the voltage across the first switch Q ₁ across the voltage V _Q1 , so that the surge voltage of the first switch Q ₁ can be suppressed to achieve the voltage clamping function.

Referring to Figures 12(c) and 12(d), the primary and secondary windings L ₁ and L ₂ and the currents i _L1 to i _{L4 of} the tertiary and quadratic windings L ₃ and L _{4 respectively} observe the analog waveform. The current i _{L1 of} the primary side winding L ₁ is much higher than the secondary side winding L ₂ current i _L2 multiplied by the value of the transformer T _r turns ratio N, because the current i _L1 of the primary side winding L ₁ includes a transfer induction The currents i _L3 and i _L4 to the third and fourth side windings L ₃ and L _{4 are} sufficient to exhibit the shunting and complementary characteristics of the four side windings L ₁ to L ₄ .

Referring to FIGS. 12(e) and 12(f), the voltages and currents of the first and second output diodes D ₃ and D ₄ are respectively observed, and the analog waveform is observed when the first switch Q ₁ or the second switch When Q ₂ is turned off, the second clamp capacitor C ₂ or the first clamp capacitor C ₁ from the other side is connected in series to the first output diode D via the secondary side winding L ₂ or the fourth side winding L ₄ . ₃ or the second output diode D _{4 is} output to the output capacitor C ₃ , and the output current is the current sum of the first output diode D ₃ and the second output diode D ₄ , and the output current frequency is obtained. For the two times of the two switches Q ₁ and Q ₂ (80 kHz), the output current ripple can be effectively reduced, and the first output diode D ₃ and the second output diode D ₄ are 110V across the voltage. Since the first output diode D ₃ a current i _D3 is equal to the second output diode D the current i _{D4 4,} this circuit can be inferred with the balance of properties.

Referring to FIGS. 12(g) and 12(h), the voltage and current of the first step-up diode D ₅ and the second step-up diode D ₆ are respectively the first and second boosters. The voltage across the poles D ₅ and D ₆ is 110V. When the two switches Q ₁ and Q _{2 are} simultaneously turned on, the leakage inductance of the transformer T _r and the diode D ₁ when the transformer T _{r is} in a failure state. The parasitic capacitance of ~D ₆ resonates, so the two switches Q ₁ , Q ₂ and the diodes D ₁ -D ₆ all have free oscillation.

See FIG. 12 (i) and 12 (j), the current through the inductor L _d i _Ld, a, tertiary windings L _1, L of the current i _{L1 3,} i _L3, that can be observed in FIG respectively for the inductance L _d The current i _Ld is a continuous waveform, and the inductor L _d stores energy in the iron core when the two switches Q ₁ and Q _{2 are} overlapped, so that the boosting characteristic is itself and the input power source V _IN can be greatly reduced. Current chopping.

Referring to Figures 13(a) to 13(j), when the output voltage V _H is 240V and the output voltage V _H is 240V, the analog waveforms of the components are respectively operated, and the two switches Q ₁ and Q ₂ operate in the overlap region. The analysis principle is roughly similar to that of Figs. 13(a) to 13(j), and therefore the description will not be repeated.

Referring to Figure 14, a schematic diagram of an analog converter without loss in consideration of the efficiency of the transformer T _r of the present embodiment, it can be seen from the figure the highest conversion efficiency of about 98%, even when the output power of 2000W, the conversion efficiency There are still 94%.

Referring to Figures 15(a)~15(j), the actual measurement of this embodiment is respectively When the output power is 400W, the input voltage is 24V and the output voltage is 48V. The voltage and current waveforms of the various components are compared with the simulation results of Figures 12(a) to 12(j). The graphs are approximately similar and conform to the theoretical analysis, so they are not repeated.

Referring to Figures 16(a) to 16(j), the actual measurement of this embodiment is respectively When the output power is 800W, the input voltage is 24V, the output voltage is 48V, and the voltage and current waveforms of each component are similar to the above-mentioned light-load implementation waveforms 15(a)~15(j), so they are not repeated. Description.

Referring to FIGS. 17(a) to 17(j), respectively, the actual measurement is performed when the output power is 600 W, the input voltage is 24 V, the output voltage is 110 V, the voltage and current waveforms of the components, and the two switches are Q ₁ and Q ₂ operate in the overlap region.

Referring to Figure 17 (a) and 17 (b), respectively, for the first switch Q ₁ and the first clamping diode D ₁ of the voltage and current waveforms, the first switch Q ₁ and the first clamp diode D The voltage of ₁ is clamped at half of the output voltage V _H , which is 55V, which is much lower than the output voltage V _H . Therefore, the highest clamp voltage of the first switch Q ₁ is consistent with the above theoretical analysis and simulation results, and has ZCS characteristics. Can reduce switching losses.

Referring to Figures 17(c) and 17(d), the current waveforms of the primary and secondary windings L ₁ and L ₂ and the tertiary and fourth-order windings L ₃ and L _{4 are respectively} compared. Fu, it can be seen that the currents i _L1 and i _{L3 of the} primary and tertiary side windings L ₁ and L ₃ have low-voltage and large-current characteristics, while the currents i _L2 and i _{L4 of} the secondary and fourth-order side windings L ₂ and L ₄ are High voltage and low current characteristics, and consistent with the simulation of Figures 13 (c), 13 (d).

Referring to FIG. 17(e), 17(f), and 17(i), respectively, voltage and current waveform patterns of the first output diode D ₃ and the second output diode D _{4 are} obtained from the figure. It is known that the reverse recovery currents of these diodes D ₃ and D ₄ are very small, and they are clamped at 110V, which is consistent with the simulation of Figs. 13(e), 13(f), and 13(i). Again, this embodiment demonstrates that it has balanced characteristics.

Referring to FIGS. 17(g) and 17(h), the voltage and current of the first step-up diode D ₅ and the second step-up diode D _{6 are respectively} , and the diodes D ₅ and D _{6 are respectively} The voltage across the 110V is equal to the output voltage V _H , and its waveform matches the simulation of Figures 13(g) and 13(h).

Refer to FIG. 17 (j), and for the primary inductance L _d and tertiary windings L _1, L ₃ of the current i _L1, i _L3, i _Ld waveform, due to the interleaving trigger design, the operating frequency for the inductor L _d When the frequency of the two switches Q ₁ and Q ₂ is twice 80 kHz, the inductance L _d can effectively assist the boosting and suppress the current rise, and reduce the line conduction loss caused by the large current.

Referring to Figures 19(a) to 19(j), the actual measurement is performed at the output power of 626W, the input voltage is 24V, the output voltage is 240V, and the voltage and current waveforms of the components are respectively measured. Q ₁ and Q ₂ operate in the overlap region, which is similar to the above-mentioned light-load implementation waveforms 17(a) to 17(j), and therefore will not be repeated.

Referring to FIG. 18(a) to FIG. 18(j), respectively, the actual measurement is performed when the output power is 1700 W, the input voltage is 24 V, the output voltage is 110 V, the voltage and current waveforms of the components, and the two switches Q ₁ and Q ₂ operate in the overlap region, which is similar to the above-mentioned light-load implementation waveforms 17(a) to 17(j), and therefore will not be repeated.

Referring to Figures 20(a) to 20(j), respectively, the actual measurement is performed when the output power is 1700W, the input voltage is 24V, the output voltage is 240V, and the voltage and current waveforms of the components are, and the two switches are Q ₁ and Q ₂ operate in the overlap region, which is similar to the above-mentioned light-load implementation waveforms 17(a) to 17(j), and therefore will not be repeated.

Referring to FIG. 21, the conversion efficiency of the actual measurement of the embodiment is shown. The figure shows that the highest conversion efficiency is about 97%. Even when the output power is 2000W, the corresponding conversion efficiency is still 93%. Therefore, this embodiment uses an interleaved architecture to complete the boost function, and the overall conversion efficiency is better. Prior art, and solve the problem of insufficient conventional boost ratio.

In summary, the above embodiment has the following advantages:

1. The first clamping circuit 1 and the second clamping circuit 2 are respectively used to clamp the first switch Q ₁ and the second switch Q ₂ so that the first switch Q ₁ and the second switch Q ₂ can be zero current Switching between conduction and non-conduction has a lower conduction loss and a lower cost low voltage power transistor can be used.

2. Restricting the reverse recovery current of the first output diode D ₃ by using the secondary winding L ₂ and the first step-up diode D ₅ ; using the fourth-order winding L ₄ and the second boost The diode D ₆ limits the reverse recovery current of the second output diode D ₄ to improve power conversion efficiency.

3. It can be seen from the equations (18), (26), and (31) that the present embodiment provides a 1-20 times boost ratio, and when the equation (18) shows a high voltage gain, the transformer T can be broken. The turns ratio of _r .

However, the above is only the preferred embodiment of the present invention. When it is not possible to limit the scope of the implementation of the present invention, that is, according to the present invention The simple equivalent changes and modifications made by the patent scope and the contents of the patent specification are still within the scope of the invention.

V _IN ‧‧‧ input voltage

Output voltage V _H ‧‧‧

L _d ‧‧‧Inductance

T _r ‧‧‧Transformer

L ₁ ‧‧‧ primary winding

L ₂ ‧‧‧ secondary winding

L ₃ ‧‧‧3rd side winding

L ₄ ‧‧‧four-side winding

Q ₁ ‧‧‧First switch

Q ₂ ‧‧‧Second switch

1‧‧‧First clamp circuit

2‧‧‧Second clamp circuit

C ₁ ‧‧‧First Clamp Capacitor

C ₂ ‧‧‧Second clamp capacitor

C ₃ ‧‧‧ output capacitor

D ₁ ‧‧‧First clamped diode

D ₂ ‧‧‧Second clamped diode

D ₃ ‧‧‧first output diode

D ₄ ‧‧‧second output diode

D ₅ ‧‧‧First booster diode

D ₆ ‧‧‧second booster diode

Claims (10)

A DC power boost circuit includes: an inductor having a first end receiving an input voltage, and a second end; a transformer having one to four side windings, each having a positive polarity point And a non-polar point end, the positive polarity end of the primary side winding and the non-polar point end of the tertiary side winding are electrically connected to the second end of the inductor; a first switch having an electrical connection to the primary side winding a first end of the non-polar point end and a grounded second end, and the first switch is controlled to switch between a conducting state and a non-conducting state; a second switch having a positive polarity electrically connecting the tertiary side winding a first end of the point end and a second end of the ground, and the second switch is controlled to switch between the conductive state and the non-conductive state; a first clamping circuit electrically connecting the first end and the second end of the first switch Between the ends, for clamping the two ends of the first switch, and electrically connecting the non-polar point ends of the secondary winding; a second clamping circuit electrically connecting the first end and the second end of the second switch Between the ends, for clamping the second switch The end is transposed and electrically connected to the positive polarity end of the fourth-order winding; an output capacitor having a first end providing an output voltage and a grounded second end; and a first output diode having An anode electrically connected to the positive terminal of the secondary winding, and an electrically connected first end of the output capacitor a cathode; a second output diode having an anode electrically connected to the non-polar point end of the fourth-order winding, and a cathode electrically connected to the cathode of the first output diode; a first boosting diode a cathode having a ground, and a cathode electrically connected to the positive terminal of the secondary winding; and a second boosting diode having a grounded anode and a non-electrical connection to the fourth winding The cathode at the end of the polarity. The DC power supply boosting circuit of claim 1, wherein the first clamping circuit comprises: a first clamping diode having an anode electrically connected to the first end of the first switch, and an electrical connection a cathode of the non-polar point end of the secondary winding; and a first clamping capacitor having a first end electrically connected to the non-polar point end of the secondary winding and a grounded second end. The DC power supply boosting circuit of claim 1, wherein the second clamping circuit comprises: a second clamping diode having an anode electrically connected to the first end of the second switch, and an electrical connection a cathode of the positive side end of the fourth-order winding; and a second clamp capacitor having a first end electrically connected to the positive terminal of the fourth-side winding and a grounded second end. The DC power supply boosting circuit of claim 1, wherein the first switch is an N-type power semiconductor transistor, and the first end of the first switch It is a drain, and the second end of the first switch is a source. The DC power boosting circuit of claim 1, wherein the second switch is an N-type power semiconductor transistor, and the first end of the second switch is a drain, and the second end of the second switch It is the source. The DC power boosting circuit of claim 1, wherein when the duty cycle of the two switches is between 0.5 and 1, the ratio of the output voltage to the input voltage is as follows: G _V = 4k (1+Δd/d ₁ ) wherein the parameter k is the coupling coefficient of the transformer, the parameter Δd is the overlapping duty cycle of the two switches, and the parameter d ₁ is the conduction duty cycle of the first switch minus the overlap The non-overlapping conduction responsibility cycle obtained by the continuity of responsibility cycle. The DC power boosting circuit of claim 1, wherein when the duty cycle of the two switches is between 1/3 and 0.5, the ratio of the output voltage to the input voltage is as follows: G _V =(2+N)k/2(1-d ₁ ) where the parameter N is the turns ratio of the transformer, the parameter k is the coupling coefficient of the transformer, and the parameter d ₁ is the conduction duty cycle of the first switch minus the The overlapped conduction responsibility cycle results in a non-overlapping conduction responsibility cycle. The DC power boosting circuit of claim 1, wherein when the duty cycle of the two switches is between 0 and 1/3, the ratio of the output voltage to the input voltage is as follows: G _V =1/(1-2d ₁ ) wherein the parameter d ₁ is a non-overlapping conduction duty cycle obtained by subtracting the overlapping conduction duty cycle of the first switch. A DC power supply boosting circuit is adapted to be electrically connected to an external low voltage power supply that provides an input voltage to receive the input voltage, and is accordingly boosted to obtain an output voltage, and the high efficiency large range output voltage DC power supply The boosting circuit comprises: an inductor having a first end receiving an input voltage, and a second end; a transformer having one to four secondary windings, each winding having a positive terminal and a non- a polarity point end, the positive polarity end of the primary side winding and the non-polar point end of the tertiary side winding are electrically connected to the second end of the inductor; a first switch having a non-polar point electrically connected to the primary side winding a first end of the end and a grounded second end, and the first switch is controlled to switch between a conducting state and a non-conducting state; a second switch having a first electrically connected end of the third side winding And a second terminal connected to the ground, wherein the second switch is controlled to switch between the conductive state and the non-conductive state; a first clamping circuit electrically connected between the first end and the second end of the first switch For pliers The second end of the first switch is electrically connected to the non-polar point end of the secondary side winding; a second clamping circuit is electrically connected between the first end and the second end of the second switch for clamping The second end of the second switch crosses the voltage and is electrically connected to the positive polarity end of the fourth-order winding; An output capacitor having a first end for providing an output voltage and a grounded second end; a first output diode having an anode electrically connected to a positive terminal of the secondary winding, and an electric a cathode connected to the first end of the output capacitor; a second output diode having an anode electrically connected to the non-polar point end of the fourth-order winding, and a cathode electrically connected to the cathode of the first output diode a first boosting diode having a grounded anode and a cathode electrically connected to a positive terminal of the secondary winding; and a second boosting diode having a grounded anode and a The cathode of the non-polar point end of the fourth-order side winding is electrically connected. The DC power boosting circuit of claim 9, wherein when the duty cycle of the two switches is between 0.5 and 1, the ratio of the output voltage to the input voltage is as follows: G _V = 4k (1+Δd/d ₁ ) wherein the parameter k is the coupling coefficient of the transformer, the parameter Δd is the overlapping duty cycle of the two switches, and the parameter d ₁ is the conduction duty cycle of the first switch minus the overlap The non-overlapping conduction responsibility cycle obtained by the continuity of responsibility cycle.