TWI452815B - High performance staggered boost converter - Google Patents

Description

High performance interleaved boost converter

The present invention relates to a converter, and more particularly to a high efficiency interleaved boost converter.

With the high price of oil per barrel and the increasingly serious environmental pollution, the effective use of energy is a policy direction that countries attach importance to. The carbon dioxide, sulfur dioxide and ash particles produced by burning cars and locomotives seriously cause air and environmental pollution. In order to improve the gradual reduction of non-renewable energy capacity and the greenhouse effect, we began to promote electric vehicles to promote energy conservation and carbon reduction. .

As shown in Fig. 1, in the literature "PWLee, YSLee, DK Cheng, and XCLiu, "Steady-state analysis of an interleaved boost converter with coupled inductors," IEEE Trans. Ind. Electron., vol. 47, no A conventional interleaved boost converter is proposed in .4, pp. 787-795, Aug. 2000., applied to an electric motor vehicle and electrically connected to an external power source (for example, a solar cell) that supplies an input voltage Vi. Or a lithium iron battery) to receive the input voltage Vi, and accordingly to boost to obtain an output voltage Vo, and the interleaved boost converter comprises: primary and secondary windings L1, L2, first and second The pole body SD1, SD2, the first and second switches SW1, SW2, and an output capacitor Cf.

The primary and secondary side windings L1, L2 each have a first end and a second end electrically coupled to the external power source to receive the input voltage.

The first diode SD1 has an electrical connection to the primary winding L1. The anode of the second end and a cathode.

The second diode SD2 has an anode electrically connected to the second end of the secondary winding L2 and a cathode electrically connected to the cathode of the first diode SD1.

The output capacitor Cf has a first end electrically connected to the cathode of the first diode SD1 and providing the output voltage, and a grounded second end.

The first switch SW1 has a first end electrically connected to the second end of the primary side winding L1, a grounded second end, and the first switch is controlled to switch between the conductive state and the non-conductive state.

The second switch SW2 has a first end electrically connected to the second end of the secondary side winding L2, a grounded second end, and the second switch is controlled to switch between the conducting state and the non-conducting state.

As shown in FIG. 2, when the first switch is turned on and the second switch is not turned on: the external power source supplies current through the primary side winding L1, the first switch flows to the ground to excite and charge the primary side winding L1. A voltage. However, since the voltage of the primary side winding L1 is small at the initial stage of charging, the reverse bias of the first diode is severe, and the reverse recovery current consumption power is generated, resulting in a decrease in power conversion efficiency.

Further, the secondary winding L2 generates an induced voltage according to the turns ratio of the primary winding L1, and the input voltage Vi of the external power supply is connected in series with the induced voltage of the secondary winding L2 to make the second diode SD2 Turning on, and supplying current to the output capacitor Cf via the secondary side winding L2 and the second diode SD2 to obtain the output voltage Vo. At this time, if the second diode is ignored The voltage drop of the SD2 is equal to the output voltage Vo of the second switch SW2. For the safety of the circuit operation, a high-voltage power transistor with high withstand voltage must be selected, which not only increases the cost, but also when the second switch SW2 The turn-on instant also has a high conduction loss due to the high cross-over voltage.

As shown in FIG. 3, when the second switch SW2 is turned on and the first switch SW1 is not turned on: the external power source is turned to supply current through the secondary side winding L2 and the second switch SW2 to the ground to the secondary side. Winding L2 is energized and charged to generate a voltage. At this time, the second diode SD2 also has a problem of reverse recovery current.

Further, the primary side winding L1 generates an induced voltage according to the turns ratio of the secondary side winding L2, and the input voltage Vi of the external power supply is connected in series with the induced voltage of the primary side winding L1 to turn on the first diode SD1. And supplying current to the output capacitor Cf via the primary side winding L1 and the first diode SD1 to obtain the output voltage Vo. At this time, if the voltage drop of the first diode SD1 is ignored, the two-terminal voltage across the first switch SW1 is equivalent to the output voltage Vo, and has the same problem as the second switch SW2.

Further description of a conventional interleaved boost converter can be found in this document and will not be repeated.

In summary, the conventional interleaved boost converter has the following disadvantages:

1. The first and second switches SW1 and SW2 have a high conduction loss and are required to be implemented by using a high-cost power transistor having a relatively high cost.

2. The first and second diodes SD1, SD2 have a problem of reverse recovery current, which will result in a decrease in power conversion efficiency.

Accordingly, it is a first object of the present invention to provide a high efficiency interleaved boost converter that reduces conduction losses.

The high efficiency interleaved boost converter is electrically connected to an external power supply that provides an input voltage, and includes: an inductor, a transformer circuit, a first boost capacitor, a second boost capacitor, and a first A switch, a second switch, a voltage clamping circuit, an output capacitor, and an output switching circuit.

The inductor has a first end electrically coupled to the external power source to receive the input voltage, and a second end. The transformer circuit has one to four secondary windings, and each winding has a positive end point and a non-polar point end, and the positive side end of the primary side winding and the non-polar point end of the secondary side winding are both Electrically connected to the second end of the inductor, and the non-polar point end of the primary side winding is electrically connected to the positive polarity end of the tertiary side winding, and the positive polarity end of the secondary side winding is electrically connected to the fourth side The non-polar point of the winding. The first boosting capacitor has a first end electrically connected to the non-polar dot end of the tertiary side winding, and a second end. The second boosting capacitor has a first end electrically connected to the positive terminal of the fourth-order winding, and a second end. The first switch has a first end electrically connected to the non-polar point end of the primary side winding and a grounded second end, and the first switch is controlled to switch between the conducting state and the non-conducting state. The second switch has a first end electrically connected to the positive terminal of the secondary winding and a grounded second end, and the second switch is controlled to switch between the conducting state and the non-conducting state. The voltage clamping circuit is electrically connected to the first ends of the first and second switches, and is electrically connected to the second ends of the first and second boosting capacitors, and is controlled to switch the first opening Passing the first terminal voltage to the second end of the second boosting capacitor or transmitting the first terminal voltage of the second switch to the second end of the first boosting capacitor to clamp the first and second ends The cross pressure of the switch. The output capacitor has a first end that provides an output voltage and a second end that is grounded. The output switching circuit is electrically connected between the second end of the first and second boosting capacitors and the first end of the output capacitor, and is controlled to switch the second terminal voltage of the first capacitor to The first end of the output capacitor or the second terminal of the second capacitor is passed to the first end of the output capacitor as the output voltage.

Preferably, the voltage clamping circuit comprises: a third switch and a fourth switch. The third switch has a first end electrically connected to the second end of the second boosting capacitor, and a second end electrically connected to the first end of the first switch, and the third switch is controlled to switch Between the on state and the non-conduction state. The fourth switch has a first end electrically connected to the second end of the first boosting capacitor, and a second end electrically connected to the first end of the second switch, and the fourth switch is controlled to switch Between the on state and the non-conduction state.

Preferably, the third and fourth switches are all N-type power semiconductor transistors, the first end being a drain and the second end being a source.

Preferably, the output switching circuit comprises: a fifth switch and a sixth switch. The fifth switch has a first end electrically connected to the first end of the output capacitor, and a second end electrically connected to the second end of the first boost capacitor, and the fifth switch is controlled to switch to Between the on state and the non-conduction state. The sixth switch has a first end electrically connected to the first end of the output capacitor, and a second end electrically connected to the second end of the second boost capacitor, and the sixth switch is controlled to switch to Between the on state and the non-conduction state.

Preferably, the first and second switches are all N-type power semiconductor transistors, the first end being a drain and the second end being a source.

Preferably, the high efficiency interleaved boost converter further comprises a first damper circuit. The first damper circuit is electrically connected between the first end of the first switch and the second end of the first boost capacitor and the ground. When the first switch is not conducting, the first damper circuit is used for The two-terminal voltage across the first switch is clamped to forcibly suppress the surge voltage generation of the first switch.

Preferably, the first vibration-damping circuit comprises: a first clamp diode, a first charge diode, and a first clamp capacitor. The first clamp diode has an anode electrically connected to the first end of the first switch, and a cathode. The first charging diode has an anode electrically connected to the cathode of the first clamping diode, and a cathode electrically connected to the second end of the first boosting capacitor. The first clamp capacitor is electrically connected between the cathode of the first clamp diode and the ground. When the second switch is turned on and the first switch is not turned on, the first clamp diode is turned on to transfer current from the primary side winding to the first clamp capacitor for charging.

Preferably, the high efficiency interleaved boost converter further comprises: a second damper circuit. The second damper circuit is electrically connected between the first end of the second switch and the second end of the second boost capacitor and the ground. When the second switch is non-conductive, the second clamp circuit is used for clamping The second end of the second switch crosses the voltage to forcibly suppress the generation of the surge voltage of the second switch.

Preferably, the second vibration-damping circuit comprises: a second clamping diode, a second charging diode, and a second clamping capacitor. The second clamp diode has an anode electrically connected to the first end of the second switch, and a cathode pole. The second charging diode has an anode electrically connected to the cathode of the second clamping diode, and a cathode electrically connected to the second end of the second boosting capacitor. The second clamp capacitor is electrically connected between the cathode of the second clamp diode and the ground. When the first switch is turned on and the second switch is not turned on, the second clamp diode is turned on to transfer current from the secondary side winding to the second clamp capacitor for charging.

A second object of the present invention is to provide a high efficiency interleaved boost converter.

The high performance interleaved boost converter is applied to an electric motor vehicle and includes: an inductor, a transformer circuit, a first boost capacitor, a second boost capacitor, a first switch, a second switch, A voltage clamping circuit, an output capacitor, and an output switching circuit.

The inductor has a first end electrically coupled to a solar cell that provides an input voltage to receive the input voltage, and a second end. The transformer circuit has one to four secondary windings, and each winding has a positive end point and a non-polar point end, and the positive side end of the primary side winding and the non-polar point end of the secondary side winding are both Electrically connected to the second end of the inductor, and the non-polar point end of the primary side winding is electrically connected to the positive polarity end of the tertiary side winding, and the positive polarity end of the secondary side winding is electrically connected to the fourth side The non-polar point of the winding. The first boosting capacitor has a first end electrically connected to the non-polar dot end of the tertiary side winding, and a second end. The second boosting capacitor has a first end electrically connected to the positive terminal of the fourth-order winding, and a second end. The first switch has a first end electrically connected to the non-polar point end of the primary side winding and a grounded second end, and the first switch is controlled Switch between the on state and the non-conduction state. The second switch has a first end electrically connected to the positive terminal of the secondary winding and a grounded second end, and the second switch is controlled to switch between the conducting state and the non-conducting state. The voltage clamping circuit is electrically connected to the first ends of the first and second switches, and is electrically connected to the second ends of the first and second boosting capacitors, and is controlled to switch the first switch The first end of the second boosting capacitor is substantially equipotential or the first end of the second switch and the second end of the first boosting capacitor are substantially equipotential to clamp the first and the first The crossover of the two switches. The output capacitor has a first end that provides an output voltage and a second end that is grounded. The output switching circuit is electrically connected between the second end of the first and second boosting capacitors and the first end of the output capacitor, and is controlled to switch the second terminal voltage of the first capacitor to the The first end of the output capacitor or the second terminal of the second capacitor is passed to the first end of the output capacitor as the output voltage.

The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention.

4, the high efficiency of the present invention is interleaved boost converter of the first embodiment of the preferred embodiment, it is applied to a motor vehicle and electrically connected to an input voltage V _IN provide an external power supply (example: a solar cell or lithium-iron battery) to receive the input voltage V _iN, and accordingly to obtain a boosted output voltage V _H, and the high-performance interleaved boost converter comprising: an inductor L _X, a transformation circuit T _r, a The first boosting capacitor C ₁ , a second boosting capacitor C ₂ , an output capacitor C _H , a first switch Q ₁ , a second switch Q ₂ , a voltage clamping circuit 1 , and an output switching circuit 2 .

The inductor L _X has a first end electrically connected to the external power source to receive the input voltage V _IN , and a second end.

The transformer circuit T _r has primary to fourth secondary windings L ₁ - L ₄ , and each winding L ₁ - L ₄ has a positive terminal and a non-polar terminal, and the positive polarity of the primary winding L ₁ The non-polar point end of the point end and the secondary side winding L ₂ are electrically connected to the second end of the inductor L _X , and the non-polar point end of the primary side winding L ₁ is electrically connected to the tertiary side winding L ₃ At the positive polarity end, the positive polarity end of the secondary winding L ₂ is electrically connected to the non-polar dot end of the fourth-order winding L ₄ . And let the turns ratio of the transformer circuit T _r be N = N ₂ / N ₁ = N ₄ / N ₃ and N ₁ = N ₃ , wherein the parameters N ₁ ~ N ₄ are the primary to fourth-order side windings, respectively. The number of turns of L ₁ ~ L ₄ .

The first boost capacitor C ₁ having an electrical connection to a first end of the tertiary windings L _3-point non-polar end and a second end.

The second boosting capacitor C ₂ has a first end electrically connected to the positive terminal of the fourth-order winding L ₄ and a second end.

The first switch Q ₁ has a first end electrically connected to the non-polar point end of the primary side winding L ₁ and a second end connected to the ground, and the first switch Q ₁ is controlled to be switched between the conducting state and the non-conducting state. between.

The second switch Q ₂ has a first end electrically connected to the positive side end of the secondary side winding L ₂ and a second end connected to the ground, and the second switch Q ₂ is controlled to be switched between the conducting state and the non-conducting Between states.

The voltage clamping circuit 1 is electrically connected to the first ends of the first and second switches Q ₁ , Q ₂ , and is electrically connected to the second ends of the first and second boosting capacitors C ₁ , C ₂ and controlled Switching the first end of the first switch Q ₁ and the second end of the second boost capacitor C _{2 to} be substantially equipotential or to make the first end of the second switch Q ₂ and the first boost capacitor The second end of C ₁ is substantially equipotential to clamp the voltage across the first and second switches Q ₁ , Q ₂ , and therefore, a power semiconductor transistor having a lower withstand voltage specification than the prior art can be selected as the first and the The two switches Q ₁ and Q ₂ reduce the component cost, and when the first and second switches Q ₁ and Q _{2 are} turned on, they also have a low conduction loss due to the low crossover voltage. The voltage clamping circuit 1 includes a third switch Q ₃ and a fourth switch Q ₄ .

The third switch Q ₃ has a first end electrically connected to the second end of the second boosting capacitor C ₂ , and a second end electrically connected to the first end of the first switch Q ₁ , and the first end The three switches Q ₃ are controlled to switch between a conducting state and a non-conducting state.

The fourth switch Q ₄ has a first end electrically connected to the second end of the first boosting capacitor C ₁ , and a second end electrically connected to the first end of the second switch Q ₂ , and the first end The four switches Q ₄ are controlled to switch between a conducting state and a non-conducting state.

The output capacitor C _H has a first end that provides the output voltage V _H and a grounded second end.

The output switching circuit 2 is electrically connected between the second end of the first and second boosting capacitors C ₁ , C _{2 and} the first end of the output capacitor C _H , and is controlled to switch the first capacitor C The second terminal voltage of ₁ is transferred to the first terminal of the output capacitor C _H or the second terminal voltage of the second capacitor C ₂ is transferred to the first terminal of the output capacitor C _H as the output voltage V _H . The output switching circuit 2 includes a fifth switch Q ₅ and a sixth switch Q ₆ .

The fifth switch Q ₅ has a first end electrically connected to the first end of the output capacitor C _H , and a second end electrically connected to the second end of the first boost capacitor C ₁ , and the fifth Switch Q ₅ is controlled to switch between a conducting state and a non-conducting state.

The sixth switch Q ₆ has a first end electrically connected to the first end of the output capacitor C _H , and a second end electrically connected to the second end of the second boost capacitor C ₂ , and the sixth Switch Q ₆ is controlled to switch between a conducting state and a non-conducting state.

The first to sixth switches Q ₁ - Q _{6 are} all N-type power semiconductor transistors, the first end of which is a drain and the second end is a source.

Referring to FIG. 5, the parameter Δd is a duty conduction period in which the two switches Q ₁ and Q _{2 are} overlapped, and d ₁ and d ₂ are respectively the first switch Q _{1 is} turned on and does not overlap the duty conduction period, and the second switch Q _{2 is} turned on and does not overlap the duty-on period, and the parameters V _g1 V V _g6 respectively represent voltages for controlling whether the first to sixth switches Q ₁ - Q ₆ are turned on, and the parameter i _LX represents the current flowing through the inductor L _X , i _LM The parameter represents the exciting current of the transformer circuit T _r , and i _{L 1} , i _{L 2} , i _{L 3} , i _{L 4} represent the current flowing through the primary winding L ₁ and flow through the secondary winding L ₂ , respectively. a current, a current flowing through the tertiary side winding L _{3 ,} a current flowing through the fourth-side winding L ₄ , and parameters i _{Q 1} to i _{Q 6} representing flow through the first to sixth switches Q ₁ to Q ₆ , respectively The current, the parameters V _{Q 1} V V _{Q 6} represent the voltages across the first to sixth switches Q ₁ to Q ₆ , respectively. According to the switching of the six switches Q ₁ ~ Q ₆ , the present embodiment operates in eight modes, each of which is described below for each mode and the duty-on period D>0.5.

In the present embodiment, the coupling coefficient k is defined as shown in the formula (1): k = L _M / ( L _{k 1} + L _M ) (1)

Among them, the parameters L _M and L _k1 respectively represent the magnetizing inductance and the leakage inductance of the primary side winding L ₁ . The windings are sandwiched and have a good coupling effect, so that the coupling coefficient k is close to 1. The following is a simplified mathematical equation for theoretical analysis, and the coupling coefficient k can be defined as 1.

Mode one (time: t ₀ ~ t ₁ ):

Referring to FIG. 5 and FIG. 6(a), the first, fourth and sixth switches Q ₁ , Q ₄ and Q _{6 are} turned on, and the remaining switches are not turned on.

A first switch Q ₁ via the pilot period of time to provide a conductive path, the input voltage V _IN T _r of the primary circuit of the transformer of the excitation winding L _1, and each in accordance with the turns ratio of the induction coil to the other three points of positive polarity To generate an induced voltage, the energy is respectively transmitted through the two-part path, which is a first partial path and a second partial path, as follows: the first partial path is: external power supply, inductance L _X , second winding L ₂ and a third winding L ₃ provides a current of the fourth switch Q _4, a first capacitor C _1, the first switch Q ₁ to flow to charge the first capacitance C ₁ via.

The second part of the path: external power supply, the inductance L _X, and the fourth secondary winding L _2, L ₄ and the second capacitor C ₂ provides a current flows via the sixth switch Q ₆ output capacitor C _H is charged, therefore, The voltage of the input voltage V _IN , the voltage of the inductor L _X , the induced voltage of the second and fourth windings L ₂ , L ₄ , and the voltage of the second capacitor C _{2 are} equal to the output voltage V _H , and the third switch Q ₃ does not conduct and ignores the voltage drop of the first and sixth switches Q ₁ , Q ₆ , and it can be inferred that the voltage across the third switch Q ₃ , v _{Q 3 , is} equal to the output voltage V _H .

The relationship between the current i _{L1 of the} primary side winding L ₁ and the current i _{LX of the} inductor L _{X and} the current of other windings is as shown in the formula (4.2): i _{L 1} = i _{L 2} + N ( i _{L 3} + i _{L 4} )= i _LX - i _{L 2} (4.2)

Since the excitation current is much smaller than the induced current, it can be ignored. The current of the fourth switch Q ₄ is equal to the difference between i _{L 2} and i _{L 4} and is equal to the current i _{L 3} , so equation (4.2) can be simplified as in equation (4.3): i _{L 1} =( N +1) i _{L 2} =( N +1) i _LX /( N +2) (4.3)

As can be seen from the above equation, the first switch Q _{1 is} subjected to most of the inductor current i _LX , so the material of the low on-resistance must be used to reduce the conduction loss.

Mode 2 (time: t ₁ ~ t ₂ ):

Referring to FIG. 5 and FIG. 6(b), the second switch Q ₂ starts to conduct and the first switch Q _{1 is} continuously turned on, and the third to sixth switches Q ₃ - Q ₆ are not turned on.

Since the first and second switches Q ₁ and Q _{2 are both} turned on, the primary and secondary windings L ₁ and L ₂ have both excitation and inductive characteristics, forming a short circuit phenomenon, so that the voltages of the four windings L ₁ to L _{4 are} all zero, all the energy transfer is stopped, and therefore, the external power source to the charging inductor L _X, L _X so that the inductor current to generate an inductance i _LX according to the input voltage V _IN. Therefore, the voltage of the inductor L _X during this mode v _{LX is} as shown in equation (4.4):

And the currents i _{L 1} and i _{L 2 of} the two windings are equal to 1/2 times the current i _{LX of the} inductor.

Mode three (time: t ₂ ~ t ₃ ):

Referring to FIG. 5 and FIG. 6(c), only the second switch Q _{2 is} continuously turned on, and the other switches Q ₁ , Q ₃ ~ Q ₆ are not turned on.

When the first switch Q ₁ turns non-conducting, the current i _{LX of} the inductor L _X is turned to flow through the secondary side winding L ₂ so that the current i _{L 2 is} rapidly pulled up, and then the magnetic energy is converted to other windings. The second switch Q _{2 is} continuously turned on, and the fourth and sixth switches Q ₄ and Q ₆ continue to be non-conducting, so that the current i _{L 2 of} the secondary side winding L ₂ is maintained to rise before the mode conduction path is maintained.

At this time, the influence by the leakage inductance energy is released, the primary winding of the current i L _{1 L 1} freewheeling and began to decline, and the leakage inductance of the primary winding L ₁ of the path are transmitted via the two portions, namely a first portion and a path the second partial path, as follows: the first partial path: the leakage inductance of the primary winding L ₁ of the first switch to provide a current flows Q ₁ to both ends of the parasitic capacitance of the parasitic capacitance of the first switch Q ₁ is charged ends, The voltage across the first switch Q ₁ begins to rise.

The second part of the path: a primary winding of _a leakage inductance L to provide more current flows to the parasitic capacitance of the third switch Q ₃ of the second boost capacitor C ₂ to the second boost capacitor C ₂ is charged, so that the The two ends of the third switch Q ₃ are lowered across the voltage.

The voltage of the external power source, the inductor L _X , the primary side winding L ₁ , the tertiary side winding L ₃ and the first boosting capacitor C ₁ and the parasitic capacitance of the fifth switch Q ₅ provide current to the output capacitor C _H to the output capacitor C _H is charged so that the pressure drop across the two ends of the fifth switch of Q _5.

Mode four (time: t ₃ ~ t ₄ ):

Referring to FIG. 5 and FIG. 6(d), the second switch Q _{2 is} continuously turned on, and the remaining switches Q ₁ , Q ₃ to Q ₆ are not turned on.

When the voltage across the first switch Q ₁ rises across the voltage, the voltages of the first, third and fourth windings L ₁ , L ₃ and L ₄ increase simultaneously, and the base diodes of the third and fifth switches Q ₃ and Q ₅ are turned on. At this time, the leakage inductance L _{k 1} voltage of the primary winding L ₁ is divided into two partial paths to transmit the leakage inductance L _{k 1} current, which are the first partial path and the second partial path, respectively, as follows: the first partial path: external power supply, The inductance L _X , the leakage inductance L _{k 1 of the} primary winding L ₁ , and the fourth-order winding L ₄ provide a current flowing to the second capacitor C ₂ via the base diode of the third switch Q ₃ to the second capacitor C ₂ charging. At this time, the capacitor C ₂ can not only provide the leakage current freewheeling path of the primary winding L ₁ but also absorb the exciting current i _LM energy from the transformer circuit T _r .

The second partial path: the external power source, the inductance L _X , the leakage inductance L _{k 1 of the} primary winding L ₁ , the tertiary side winding L ₃ and the first capacitor C ₁ provide a current flowing through the base diode of the fifth switch Q ₅ output capacitor C _H to charge the capacitor C _H to the output.

Since the mode has a charging output capacitor C _H, and therefore the frequency of the output current is twice the _switching frequency of the first switch Q, the discharge current can effectively reduce the ripple of the capacitor C _H is provided. Let the output voltage of mode four be V _{H 1} , then the output voltage V _{H 1 is} as in equation (4.5):

From equation (4.4), the voltage V _{C 2 of the} capacitor C ₂ can be derived as in equation (4.6):

It can be seen from equation (4.6) that if the overlap conduction duty cycle Δd of the first switch Q ₁ is increased, the voltage V _{C 2 of the} second boost capacitor C _{2 is} raised, and the first step of the interleaving effect is turned on. When three and four side winding L _{3, L. 4} of the current i _{L 3,} i _{L 4} is equal to the sum of the primary winding of the current i L ₁ when _{L 1,} L is the leakage inductance of the primary winding of _an energy release over, so a first voltage across the switch Q ₁ v _{Q 1} clamped thereto and stops rising, by the formula (4.6) can be deduced across the first switch Q ₁ of voltage v _{Q 1} of formula (4.7):

Mode five (time: t ₄ ~ t ₅ ):

Referring to FIG. 5 and FIG. 6(e), the second, third, and fifth switches Q ₂ , Q ₃ , and Q _{5 are} turned on, and the remaining switches Q ₁ , Q ₄ , and Q _{6 are} not turned on.

Since the input voltage V _IN is a low voltage level with respect to the output voltage V _H and has a high current characteristic, when the base diodes of the third and fifth switches Q ₃ , Q ₅ are turned on, there is a high-value diode. The voltage drop forms a conduction loss. At this time, the triggering of the third and fifth switches Q ₃ and Q _{5 is} synchronous rectification, which can greatly improve the conduction voltage drop and the conduction loss. At this time, the exciting current i _LM has completely discharged and starts to turn, and the excitation is started by the secondary side winding L ₂ .

Mode six (time: t ₅ ~ t ₆ ):

Referring to Figures 5 and 6(f), the first and second switches Q ₁ , Q _{2 are} turned on, and the remaining switches Q ₃ - Q _{6 are} not turned on.

Since the first and second switches Q ₁ and Q _{2 are both} turned on, the primary and secondary windings L ₁ and L _{2 are} simultaneously excited, and the induced current forms a short circuit, so that the voltages of the four windings are all zero, and the working principle thereof It is the same as the operation mode and mode 2, so it will not be repeated.

Mode seven (time: t ₆ ~ t ₇ ):

Referring to FIG. 5 and FIG. 6 (g), the first switch Q ₁ is turned on continuously, while the remaining switches Q ₂ ~ Q ₆ nonconductive.

When the second switch Q ₂ turns non-conducting, the current i _{LX of} the inductor turns to flow through the primary side winding L ₁ so that the current i _{L 1 is} rapidly pulled up, and then the magnetic energy is converted to the other windings, because the first switch Q _{1 is} continuously turned on, and the fourth and sixth switches Q ₄ and Q ₆ continue to be non-conducting, so that the current i _{L 1 of} the primary side winding L ₁ is maintained as the mode six-conducting path starts to rise.

At this time, the influence by the leakage inductance energy is released, the secondary winding current i ₂ L _{2 L} of freewheeling and begins to decrease, so that the secondary winding L ₂ of the induced voltage are transmitted via the paths of three parts, namely a first portion of the path a second partial path and a third partial path are as follows: the first partial path: the secondary side winding L ₂ provides a current flow to the parasitic capacitance across the second switch Q _{2 to the} opposite ends of the second switch Q ₂ The parasitic capacitance is charged such that the voltage across the second switch Q ₂ begins to rise.

a second partial path: the secondary side winding L ₂ , the parasitic capacitance of the fourth switch Q ₄ , the first boosting capacitor C ₁ and the tertiary side winding L ₃ provide a current flowing to the ground via the first switch Q ₁ , such that the first The four ends of the four switches Q ₄ are lowered across the voltage.

The third part of the path: external power supply, the inductance L _X, the secondary winding L _2, four winding L _4, a second capacitor C _2, the sixth switch Q ₆ of a parasitic capacitance providing a current for the output capacitor C _H Charging causes the voltage across the sixth switch Q _{6 to} begin to drop.

Mode eight (time: t ₇ ~ t ₀ ):

Referring to FIG. 5 and FIG. 6 (h), the first switch Q ₁ is turned on continuously, while the remaining switches neither Q ₂ ~ Q ₆ is turned on.

When the voltage across the second switch Q ₂ rises across the voltage, the voltages of the second, third and fourth windings L ₂ , L ₃ and L ₄ increase simultaneously, and the base diodes of the fourth and sixth switches Q ₄ and Q ₆ are turned on. At this time, the leakage inductance L _{k 2} voltage of the secondary winding L ₁ is divided into two parts to transmit its leakage inductance L _{k 2} current, which are the first partial path and the second partial path, respectively, as follows: First partial path: external power supply The inductance L _X , the leakage inductance L _{k 2 of the} secondary winding L ₂ and the tertiary side winding L ₃ provide a current flowing to the first capacitor C ₁ via the base diode of the fourth switch Q ₄ for charging. At this time, the first capacitor C ₁ may be provided not only the leakage inductance of the secondary winding L ₂ L of _{K 2} freewheel path while absorbing energy from the exciting current i _LM T _r of the transformer circuit.

The second part of the path: the external power source, the inductance L _X , the leakage inductance L _{k 2 of the} secondary winding L ₂ , the fourth-order winding L ₄ , and the second capacitor C ₂ provide a current through the base diode of the sixth switch Q ₆ the flow body is charged output capacitor C _H.

At this time, the inductor voltage v _{LX is} related to the duty cycle d ₂ , as shown in equation (4.8):

Assuming that the output voltage of mode eight is V _{H 2} , the output voltage V _{H 2 is} as shown in equation (4.9):

From equation (4.4), it can be inferred that the voltage V _{C 1 of the} first capacitor C ₁ is as shown in the equation (4.10):

T _r When the exciting current i _LM transforming circuit and leakage inductance of the secondary winding L ₂ of the i _{LK 2} complete energy has been released, and re-receiving of the primary winding _{excitation. 1} L, the process returns to an operation mode.

It can be seen from mode 4 that if the overlap conduction duty cycle Δd of the first switch Q ₁ is increased, the second capacitor voltage V _{C 2} will be boosted, so that the non-overlapping conduction duty cycle d ₂ of the second switch in mode eight will be less than d _{1 .} So that the first capacitor voltage V _{C 1 is} lower than the second capacitor voltage V _{C 2} . Substituting equations (4.10) and (4.6) into equations (4.5) and (4.9), respectively, equations (4.11) and (4.12) can be obtained as follows:

Due to the staggered effect of the capacitor voltage, Equations (4.11) and (4.12) are identical, which proves that even if the two conduction duty cycles are different, the unbalanced energy can be guided to the first and second capacitors C ₁ and C ₂ . the output capacitor C _H and then discharged through the lower equalizer modes, and independent of temperature and component parameters to ensure that the output of mode 4 remains equal to the voltage V _{H 1} mode output voltage of eight V _{H 2.}

To simplify the theoretical analysis, the definition of the non-overlapping conduction duty cycle d _{1 is} equivalent to d ₂ and is represented by d ₁ . _2, the output voltage can be derived according to the formula V _H (4.6) and (4.10), the first and second capacitor that C _1, C ₂ of cross voltage V _C V _{C 1} is equivalent to the formula (4.13 ) shown:

The entire boosting ratio G _V can be simplified as shown in equation (4.14):

<simulation and measurement results>

As shown in FIG 7, is the coupling coefficient k = 1 and different numbers of turns when the boosting ratio Gv N and responsibilities conduction period overlaps a graph showing the ratio of △ d, can be seen that when the input voltage is 6.4V, the output voltage is 48V, boosting ratio of 7.5 times was observed on FIG substituting, if N = 1, overlapping responsibilities conduction period of 0.1 △ d.

As shown in FIGS. 8(a) to 8(j), respectively, when the output power is equal to 100 W, the input voltage is 6.4 V, the output voltage is 48 V, N=1, and d ₁ =d ₂ >50%, respectively, in this embodiment. , voltage and current waveforms of various components.

As shown in Figures 8(a) and 8(b), the analog waveforms of the voltage and current of the first and second switches Q ₁ and Q ₂ are respectively clamped at about 16V, which is much lower than the output voltage. The on-currents of the first and second switches Q ₁ and Q ₂ exhibit a low effective current value of a square wave shape, and have a zero current switching effect, so that switching loss and conduction loss can be effectively reduced.

8(c) and 8(d) are the voltage and current waveforms of the third and fourth switches Q ₃ and Q _{4 respectively} , which can be observed by the waveform. When the currents of the third and fourth switches Q ₃ and Q _{4 are} i _{Q 3} , i _{Q 4} occurs synchronous rectification technology, can reduce the voltage drop and conduction loss due to switch conduction, the third and fourth switches Q ₃ , Q ₄ across the voltage v _{Q 3} and v _{Q 4 are the} same as the output voltage value 48V, its switch specification can be used with a lower conduction loss switch.

FIG 8 (e) and 8 (f) are fifth and sixth switch Q _5, Q ₆ of the voltage and current waveforms, when the fifth and sixth switch Q _5, Q ₆ of the current i _{Q 5,} i _{Q 6} When the synchronous rectification technology is used, the conduction loss due to the conduction of the switch can be reduced, and the switching voltages v _{Q 5} and v _{Q 6} are both 32V.

8(g) and 8(h) are current waveforms of the primary and tertiary side windings L ₁ , L ₃ , the secondary and quadratic windings L ₂ , L ₄ , respectively, which can be observed by the waveform, and the primary side winding L ₁ much higher than the current i _{L 1} L tertiary windings of the current I _{L 3 3} multiplied by the turns ratio, since the primary winding of the current L ₁ i _{L 1} must contain four transfer induced to the secondary winding L ₂ and , L ₄ current.

Figure 8(i) shows the current waveform of the inductor L _X and the primary and secondary windings L ₁ , L ₂ . It can be seen that the inductor current i _LX is a continuous waveform at the first and second switches Q ₁ , Q . _{2 When the} overlap is turned on, the energy can be stored and released in the next stage, so that it has a boosting characteristic, and can greatly reduce the input current ripple from the external power source and accurately distribute the current to the primary and secondary side windings L ₁ , L ₂ .

8(j) _shows the output voltage V _H of the output capacitor C _H and the voltage values v _{C 1} , v _{C 2 of the} first and second boost capacitors C1 and C2.

FIG. 9 is a graph showing the analog conversion efficiency of the present embodiment. It can be seen that the highest conversion efficiency is about 97.8%, and even when the output power is 500 W, the corresponding conversion efficiency is still 94%.

As shown in Figures 10(a) to 10(j), the actual measurement for the present embodiment is that the output power is equal to 100 W, the input voltage is 6.4 V, the output voltage is 48 V, N = 1, d ₁ = d ₂ > Voltage and current waveforms of each component at 50%.

As shown in the switching voltage and current waveforms of Figures 10(a) to 10(f), the highest clamping voltage of each power switch is consistent with the above theoretical analysis and simulation results, and the third to sixth switches Q ₃ ~ Q ₆ has synchronous rectification technology, which can greatly reduce the switch-on voltage drop and conduction loss.

Figures 10(g) and 10(h) show the current waveforms of the primary and tertiary side windings L ₁ and L ₃ , and the secondary and quadratic windings L ₂ and L _{4 respectively} . The primary and secondary winding currents i can be seen. _{L 1} and i _{L 2} have low-voltage and high-current characteristics, while the tertiary and quadratic winding currents i _{L 3} and i _{L 4} are high-voltage and low-current characteristics, and are consistent with the simulations of Figs. 8(g) and 8(h).

Fig. 10(i) shows the current waveform of the inductor L _X and the primary and secondary windings L ₁ and L ₂ . It can be found that the currents of the primary and secondary windings L ₁ and L _{2 are} close to a square wave, and the inductance L _X can be effective. Reduce current peaks to mitigate line conduction losses caused by large currents.

Fig. 10(j) shows the waveforms of the output voltage V _H and the voltages V _{C 1} and v _{C 2 of} the two boost capacitors C1 and C2. As can be seen from the figure, the output voltage V _H is very low, which can effectively reduce The capacity of the output capacitor C _H .

Figure 11 is a graph showing the conversion efficiency of an interleaved balanced boost converter. The graph shows that the highest conversion efficiency is about 97%, and the efficiency is still 92.5% even at an output power of 500W.

As shown in FIG. 12, the second preferred embodiment of the high-performance interleaved boost converter of the present invention differs from the first preferred embodiment in that it further includes a first damper circuit 3 and a second Vibration damping circuit 4.

The first snubber circuit 3 is electrically connected to a first terminal of the first switch Q _1, and between the second end of the booster capacitor C1 of the first, non-conducting when the first switch Q _1, the first 3 for the clamp snubber circuit of the first switch Q ₁ bis end to force the voltage across the first switch Q suppress _a surge voltage is generated. The first damper circuit 3 includes a first clamp diode D ₁ , a first charge diode D ₃ , and a first clamp capacitor C ₃ .

The first clamp diode D ₁ has an anode electrically connected to the first end of the first switch Q ₁ and a cathode.

The first charging diode D ₃ has an anode electrically connected to the cathode of the first clamping diode D ₁ and a cathode electrically connected to the second end of the first boosting capacitor C ₁ .

The first clamp capacitor C _{3 is} electrically connected between the cathode of the first clamp diode D ₁ and the ground.

When the second switch Q _{2 is} turned on and the first switch Q _{1 is} not turned on, the first clamp diode D _{1 is} turned on to transfer current from the primary side winding L ₁ to the first clamp capacitor C. ₁ to charge.

The second slow-vibrating circuit 4 is electrically connected between the first end of the second switch Q _{2 and} the second end of the second boosting capacitor C ₂ and the ground. When the second switch Q _{2 is} not turned on, the first two clamping circuit 4 for clamping the second switch Q ₂ of the voltage across the two ends of the second switch forcibly suppress surge voltage generated Q _2. The second damper circuit 4 includes a second clamp diode D ₂ , a second charge diode D ₄ , and a second clamp capacitor C ₄ .

The second clamp diode D ₂ has an anode electrically connected to the first end of the second switch Q ₂ and a cathode.

The second charging diode D ₄ has an anode electrically connected to the cathode of the second clamping diode D ₂ and a cathode electrically connected to the second end of the second boosting capacitor C ₂ .

The second clamp capacitor C _{4 is} electrically connected between the cathode of the second clamp diode D ₂ and the ground.

When the first switch is turned on Q ₁ and the second switch Q _{2 is} not turned on, the second clamp diode D _{2 is} turned on to transfer current from the secondary side winding L ₂ to the second clamp capacitor. C ₄ to charge.

In summary, the above embodiment has the following advantages:

1 1. The voltage clamping circuit for clamping the first and second switches Q _1, Q ₂ of the voltage across the first and second embodiment of the present switch embodiment of Q _1, Q ₂ has compared to prior art having a relatively Low conduction losses and low cost power transistors with lower cost can be used.

2. Using the two switches Q ₆ , Q ₅ to replace the first and second diodes SD1 and SD2 of the prior art, the power recovery can be improved by reducing the diode reverse recovery current to almost zero compared to the prior art. effectiveness.

3. It can be known from the equation (4.13) that the present embodiment provides a high boosting magnification.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.

L _X ‧‧‧Inductance

T _r ‧‧‧Transformer circuit

L ₁ ‧‧‧ primary winding

L ₂ ‧‧‧ secondary winding

L ₃ ‧‧‧3rd side winding

L ₄ ‧‧‧four-side winding

C ₁ ‧‧‧First boost capacitor

C ₂ ‧‧‧second boost capacitor

Output capacitance C _H ‧‧‧

Q ₁ ‧‧‧First switch

Q ₂ ‧‧‧Second switch

1‧‧‧Voltage clamp circuit

Q ₃ ‧‧‧third switch

Q ₄ ‧‧‧fourth switch

2‧‧‧Output switching circuit

Q ₅ ‧‧‧ fifth switch

Q ₆ ‧‧‧ sixth switch

3‧‧‧First slow-vibration circuit

D ₁ ‧‧‧First clamped diode

D ₃ ‧‧‧First charging diode

C ₃ ‧‧‧First clamp capacitor

4‧‧‧Second slow-vibration circuit

D ₂ ‧‧‧Second clamped diode

D ₄ ‧‧‧Second charging diode

C ₄ ‧‧‧Second clamp capacitor

1 is a circuit diagram of a conventional interleaved boost converter; FIG. 2 is a circuit diagram of the conventional interleaved boost converter performing boosting; FIG. 3 is a conventional interleaved boost converter implementation. FIG. 4 is a circuit diagram of a first preferred embodiment of the high efficiency interleaved boost converter of the present invention; FIG. 5 is a timing diagram of the preferred embodiment; FIG. 6(a) is a circuit diagram The preferred embodiment operates in a circuit diagram of mode one; FIG. 6(b) is a circuit diagram of the preferred embodiment operating in mode two; and FIG. 6(c) is a circuit diagram of the preferred embodiment operating in mode three; FIG. (d) is a circuit diagram of the preferred embodiment operating in mode four; FIG. 6(e) is a circuit diagram of the preferred embodiment operating in mode five; and FIG. 6(f) is a preferred embodiment operating in mode six Figure 6(g) is a circuit diagram of the preferred embodiment operating in mode seven; Figure 6(h) is a circuit diagram of the preferred embodiment operating in mode eight; Figure 7 is a boosting override and overlapping duty-on period FIG. 8(a) is a first simulation diagram of the preferred embodiment at an output power of 100 W; Figure 8 (b) is a second simulation diagram of the preferred embodiment at an output power of 100 W; Figure 8 (c) is a third simulation diagram of the preferred embodiment at an output power of 100 W; Figure 8 (d) Is a fourth simulation diagram of the preferred embodiment at an output power of 100 W; FIG. 8(e) is a fifth simulation diagram of the preferred embodiment at an output power of 100 W; FIG. 8(f) is the comparison A preferred embodiment is a sixth simulation diagram with an output power of 100 W; FIG. 8(g) is a seventh simulation diagram of the preferred embodiment at an output power of 100 W; and FIG. 8(h) is a preferred embodiment of the preferred embodiment. An eighth simulation diagram with an output power of 100 W; FIG. 8(i) is a ninth simulation diagram of the preferred embodiment at an output power of 100 W; and FIG. 8(j) is a preferred embodiment of the output power of 100 W. The tenth simulation diagram; FIG. 9 is a schematic diagram of the conversion efficiency of the preferred embodiment; FIG. 10(a) is the first actual measurement diagram of the preferred embodiment at an output power of 100 W; b) is the second actual measurement map of the preferred embodiment at an output power of 100 W; and FIG. 10(c) is the third embodiment of the preferred embodiment with an output power of 100 W. Actual measurement chart; FIG. 10(d) is a fourth actual measurement chart of the preferred embodiment at an output power of 100 W; FIG. 10(e) is a fifth embodiment of the preferred embodiment with an output power of 100 W. Actual measurement chart; FIG. 10(f) is a sixth actual measurement chart of the preferred embodiment at an output power of 100 W; FIG. 10(g) is the seventh embodiment of the preferred embodiment with an output power of 100 W. Actual measurement chart; FIG. 10(h) is the eighth actual measurement chart of the preferred embodiment at an output power of 100 W; FIG. 10(i) is the ninth embodiment of the preferred embodiment with an output power of 100 W. Actual measurement chart; FIG. 10(j) is a tenth actual measurement chart of the preferred embodiment at an output power of 100 W; and FIG. 11 is a conversion efficiency diagram of the actual measurement of the preferred embodiment; 12 is a circuit diagram of a second preferred embodiment of the high efficiency interleaved boost converter of the present invention.

L _X ‧‧‧Inductance

T _r ‧‧‧Transformer circuit

L ₁ ‧‧‧ primary winding

L ₂ ‧‧‧ secondary winding

L ₃ ‧‧‧3rd side winding

L ₄ ‧‧‧four-side winding

C ₁ ‧‧‧First boost capacitor

C ₂ ‧‧‧second boost capacitor

Q ₁ ‧‧‧First switch

Q ₂ ‧‧‧Second switch

1‧‧‧Voltage clamp circuit

Q ₃ ‧‧‧third switch

Q ₄ ‧‧‧fourth switch

2‧‧‧Output switching circuit

Q ₅ ‧‧‧ fifth switch

Q ₆ ‧‧‧ sixth switch

Output capacitance C _H ‧‧‧

Claims (10)

A high efficiency interleaved boost converter electrically coupled to an external power supply that provides an input voltage, and comprising: an inductor having a first end electrically coupled to the external power source to receive the input voltage, and a second a transformer circuit having one to four secondary windings, each winding having a positive terminal and a non-polar terminal, a positive terminal of the primary winding and a non-polar of the secondary winding The non-polar point end of the primary side winding is electrically connected to the positive polarity end of the tertiary side winding, and the positive polarity end of the secondary side winding is electrically connected to the a non-polar point end of the fourth-order side winding; a first boosting capacitor having a first end electrically connected to the non-polar point end of the tertiary side winding, and a second end; a second boosting capacitor having a a first end electrically connected to the positive end of the fourth-side winding, and a second end; a first switch having a first end electrically connected to the non-polar end of the primary winding and a grounded first Two ends, and the first switch is controlled to switch to Between the on state and the non-conducting state; a second switch having a first end electrically connected to the positive side end of the secondary winding and a grounded second end, and the second switch is controlled to switch to conduction Between the state and the non-conducting state; a voltage clamping circuit electrically connected to the first ends of the first and second switches, and electrically connected to the second ends of the first and second boosting capacitors, and controlled to switch Grounding the first end of the first switch and the second boosting The second end of the capacitor is substantially equipotential or the first end of the second switch and the second end of the first boost capacitor are substantially equipotential to clamp the voltage across the first and second switches; The capacitor has a first end providing an output voltage and a grounded second end; and an output switching circuit electrically connected to the second end of the first and second boosting capacitors and the first of the output capacitors Between the terminals, and controlled to switch the second terminal voltage of the first capacitor to the first end of the output capacitor or to transmit the second terminal voltage of the second capacitor to the first end of the output capacitor As the output voltage. The high-performance interleaved boost converter of claim 1, wherein the voltage clamping circuit comprises: a third switch having a first end electrically connected to the second end of the second boosting capacitor And a second end electrically connected to the first end of the first switch, and the third switch is controlled to switch between a conducting state and a non-conducting state; and a fourth switch having an electrical connection to the first a first end of the second end of the boost capacitor, and a second end electrically coupled to the first end of the second switch, and the fourth switch is controlled to switch between a conducting state and a non-conducting state. The high-performance interleaved boost converter according to claim 2, wherein the third and fourth switches are N-type power semiconductor transistors, the first end is a drain, and the second end is Source. High-performance interleaved boost converter as described in item 1 of the patent application scope The output switching circuit includes: a fifth switch having a first end electrically connected to the first end of the output capacitor, and a second end electrically connected to the second end of the first boosting capacitor And the fifth switch is controlled to switch between the conductive state and the non-conductive state; and a sixth switch having a first end electrically connected to the first end of the output capacitor, and an electrical connection to the second a second end of the second end of the boost capacitor, and the sixth switch is controlled to switch between a conducting state and a non-conducting state. The high-performance interleaved boost converter according to claim 1, wherein the first and second switches are N-type power semiconductor transistors, the first end is a drain, and the second end is Source. The high-performance interleaved boost converter according to claim 1, further comprising: a first vibration-damping circuit electrically connected to the first end of the first switch and the second of the first boost capacitor Between the terminal and the ground, when the first switch is not conducting, the first damper circuit is configured to clamp the two-terminal voltage across the first switch to forcibly suppress the spur voltage generation of the first switch. The high efficiency interleaved boost converter of claim 6, wherein the first vibration-damping circuit comprises: a first clamp diode having a first end electrically connected to the first switch An anode, and a cathode; a first charging diode having an anode electrically connected to the cathode of the first clamping diode, and an electrical connection to the first boosting capacitor a cathode of the second end; and a first clamping capacitor electrically connected between the cathode of the first clamping diode and the ground; and when the second switch is turned on and the first switch is not conducting, the first clamping diode The body is guided to pass current from the primary side winding to the first clamp capacitor for charging. The high-performance interleaved boost converter according to claim 1, further comprising: a second damper circuit electrically connected to the first end of the second switch and the second second boost capacitor Between the terminal and the ground, when the second switch is not conducting, the second clamping circuit is configured to clamp the two-terminal voltage across the second switch to forcibly suppress the surge voltage generation of the second switch. The high efficiency interleaved boost converter of claim 8, wherein the second damper circuit comprises: a second clamp diode having a first end electrically connected to the second switch An anode, and a cathode; a second charging diode having an anode electrically connected to the cathode of the second clamping diode; and a cathode electrically connected to the second end of the second boosting capacitor; And a second clamping capacitor electrically connected between the cathode of the second clamping diode and the ground; when the first switch is turned on and the second switch is not conducting, the second clamping diode is turned on Current from the secondary winding is transferred to the second clamp capacitor for charging. A high efficiency interleaved boost converter for use in an electric motor vehicle, comprising: an inductor having a first end electrically connected to a solar cell providing an input voltage to receive the input voltage, and a second end a transformer circuit having one to four secondary windings, each winding having a positive terminal and a non-polar terminal, a positive terminal of the primary winding and a non-polar point of the secondary winding The terminal is electrically connected to the second end of the inductor, and the non-polar point end of the primary winding is electrically connected to the positive terminal of the tertiary winding, and the positive terminal of the secondary winding is electrically connected to the fourth a non-polar point end of the secondary winding; a first boosting capacitor having a first end electrically connected to the non-polar point end of the tertiary side winding, and a second end; a second boosting capacitor having an electric a first end connected to the positive polarity end of the fourth-order winding, and a second end; a first switch having a first end electrically connected to the non-polar point end of the primary side winding and a second grounded End, and the first switch is controlled to switch to Between the on state and the non-conducting state; a second switch having a first end electrically connected to the positive side end of the secondary winding and a grounded second end, and the second switch is controlled to switch to conduction Between the state and the non-conducting state; a voltage clamping circuit electrically connected to the first ends of the first and second switches, and electrically connected to the second ends of the first and second boosting capacitors, and controlled to switch The first end of the first switch and the second end of the second boost capacitor are substantially equipotential or the first end of the second switch and the The second end of the first boosting capacitor is substantially equipotential to clamp the voltage across the first and second switches; an output capacitor having a first end providing an output voltage and a grounded second end; And an output switching circuit electrically connected between the second end of the first and second boosting capacitors and the first end of the output capacitor, and controlled to switch the second terminal voltage of the first capacitor The first end of the output capacitor or the second terminal of the second capacitor is passed to the first end of the output capacitor as the output voltage.