KR20160053145A - Dual full-bridge converter - Google Patents

Abstract

The present invention relates to a dual full-bridge converter, which integrates two full-bridge inverters sharing one leg in a primary side, and integrates two distributing rectifying circuits sharing an inductor in a secondary side, thereby not only achieving a low duty cycle loss and a wide zero voltage switching (ZVS) range, but also reducing the production costs with a small number of composition elements.

Description

DUAL FULL-BRIDGE CONVERTER

The present invention relates to a dual full-bridge converter, and more particularly, to a dual-bridge converter in which two full-bridge inverters sharing one leg are integrated into a primary side, and two secondary-current rectifying circuits sharing an inductor are integrated To a dual full bridge converter that achieves low duty cycle losses, wide ZVS range, and fewer components.

Hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), and pure electric vehicles (EVs) have been increasing due to accelerated global warming, Electric vehicles, and FCVs (Fuel Cell Vehicles) are rapidly increasing sales of environmentally friendly electric powered vehicles. Moreover, due to the domestic target of the International Energy Association (IEA), an increasing trend of electric vehicle sales is becoming a trend in the automobile market.

These automobiles essentially require rechargeable batteries as the energy source of the electronic driving force system. Among them, plug-in hybrid electric vehicles and pure electric vehicles require a large-sized battery pack having a significantly higher capacity than other vehicles because the battery plays a main role in the energy source.

Batteries in electric vehicles are charged from an AC power grid through an AC-to-DC converter, commonly referred to as a battery charger. In order to achieve high conversion efficiency without low current distortion for AC networks and loss of charger capacity, most battery chargers require an AC-DC converter with a power factor correction (PFC) connected to an isolated DC-DC converter As shown in FIG.

There are several key requirements in developing such battery chargers. First, it is essential to reduce the size and weight of the battery charger to facilitate packaging and to emphasize the practical aspects of energy. Furthermore, high efficiency in the overall battery charging process is emphasized for size reduction and fuel economy. Reliable and reliable operation must also be met.

To meet these needs, recent battery chargers employ Bridgeless boost PFC technology for AC-DC converters to reduce conduction losses. Typically, the AC input voltage is rectified by a bridge diode connected to the back of the boost section.

Due to the voltage drop across each bridge diode, excessive conduction losses occur, especially at low line input voltages, which reduces overall efficiency and increases the size and weight of the heat sink excessively. Interleaving or a parallel approach may be considered due to degradation, especially to achieve high efficiency at high power levels.

For DC-DC converters in battery charger applications, phase-shifted full bridge (PSFB) is the most popular consideration. Phase transition full bridge converters are well studied topologies for high power applications at medium power requiring isolation. The main advantage of phase-shift full-bridge converters is that they have zero voltage switching (ZVS) characteristics without additional auxiliary components or complex control performance. The operation including ZVS has various advantages such as reduction of the switching loss of the primary side power supply device and noise-free environment of the control circuit. The more efficient operation of the phase-transition full-bridge converter allows significant reduction in required heat management in size and weight sensitive applications. However, as the allowable range of ZVS operation is narrow, a relatively small load makes the ZVS state worse. Accordingly, various studies have been conducted.

To extend the soft switching range, several approaches have been taken. First, the design of a transformer with large loss inductance and the addition of an external inductor were studied. However, these methods increase the duty cycle loss and the voltage spikes of the secondary side diodes and reduce the voltage conversion ratio. Another approach is to reduce the magnetization inductance of the transformer. Although this method increases the ZVS range, the RMS current stress and conduction losses on the primary side are significantly increased.

The present invention provides a low duty cycle loss, a wide ZVS range, and a low duty cycle by integrating two full bridge inverters sharing one leg on the primary side and integrating two inductor current sharing circuits sharing the inductor on the secondary side. We propose a dual full bridge converter to achieve fewer components.

The above object is achieved by a full bridge converter for operating two full bridge inverters in parallel, comprising: two transformers; A first full bridge inverter including one full bridge circuit and connected to the primary side of the first transformer; A second full bridge inverter including another full bridge circuit and connected to the primary side of the second transformer; And a second leg comprising a first output diode connected in series, a first leg comprising a first output inductor and a second output diode and a third output diode connected in series, a second leg comprising a second output inductor and a fourth output diode, Wherein the contacts of the first output inductor and the first output diode and the contacts of the second output inductor and the fourth output diode are connected to the secondary of the second transformer, And a rectification stage in which the contacts of the second output diode and the contacts of the second output inductor and the third output diode are connected to the secondary side of the first transformer.

The above object is achieved by a full bridge converter for operating two full bridge inverters in parallel, comprising: first and second transformers; A first leg, a second leg, and a third leg, each of the first leg, the second leg, and the first transformer being constituted by a pair of series-connected switches, constituting a first full bridge circuit, A first stage comprising a second full bridge circuit including the second leg, the third leg and the second transformer; And a fourth leg comprising a first output diode connected in series, a fourth leg comprising a first output inductor and a second output diode and a third output diode connected in series, a fifth leg comprising a second output inductor and a fourth output diode, Wherein the contacts of the first output inductor and the first output diode and the contacts of the second output inductor and the fourth output diode are connected to the secondary of the second transformer, And a second stage in which the contacts of the second output diode and the contacts of the second output inductor and the third output diode are connected to the secondary side of the first transformer.

The present invention relates to a soft-switching DC-DC converter for a built-in battery charger for a high output of an electric vehicle having a capacity of more than 6.6 kW, and has a structure in which two full bridge inverters are integrated on a primary side, Two shared current rectifier circuits are integrated. As a result, this dual full-bridge converter not only achieves low duty cycle losses, wide ZVS range, but also low cost with fewer components.

1 is a circuit diagram of a dual full bridge converter according to the present invention,
Figure 2 shows the battery charger profile of the dual full bridge converter of Figure 1,
FIG. 3 shows the main operating waveforms of the dual full bridge converter of FIG. 1,
4 (a) - (f) are operational circuit diagrams during the first half cycle of the dual full bridge converter of FIG. 1,
5 is an equivalent circuit diagram in mode 2,
6 shows voltage and current waveforms by VDT control,
7 is a circuit diagram of a mode added between mode 2 and mode 3,
8 is a graph showing the relationship between the ZVS condition and the primary current,
9 is a graph showing primary current and output inductor current at low input voltage and full load conditions,
10 is a graph showing the primary voltages of the two transformers corresponding to the minimum and maximum input voltages,
11 is a graph showing the gate-source voltage and the drain-source voltage of the third switch which is the center leg switch,
12 is a graph showing a gate-source voltage and a drain-source voltage of a sixth switch which is a lagging leg switch,
Figure 13 compares efficiency versus output power under a constant current mode and constant voltage mode at an output voltage of 13.5A.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. It should be noted that, in adding reference numerals to the constituent elements of the drawings, the same constituent elements are denoted by the same reference symbols as possible even if they are shown in different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the constituent elements from other constituent elements, and the terms do not limit the nature, order or order of the constituent elements. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected to or connected to the other component, It should be understood that an element may be "connected," "coupled," or "connected."

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following detailed description, circuit configurations, operating principles, and related analysis results of a dual full bridge converter according to the present invention will be described. To verify the effectiveness of this dual full bridge converter, we performed an experiment with a circular converter realized with a 6.6kW battery charger, and the experimental results described below show the efficiency of the proposed converter as a battery charger.

1 is a circuit diagram of a dual full bridge converter according to the present invention.

As shown in FIG. 1, the dual full-bridge converter according to the present invention may include first and second full-bridge inverters sharing one leg with the third and fourth switches Q3 and Q4 on the primary side.

The first full bridge inverter includes first through fourth switches Q1 through Q4 and a first transformer T1. The second full bridge inverter includes third through sixth switches Q3 through Q6 and a second transformer T2. do. And an additional external inductor L _ext connected in series with the second transformer T 2 is employed on the primary side.

The first stage of the first full bridge inverter and the second full bridge inverter includes a first leg, a second leg and a third leg composed of a pair of switches connected in series. The first full bridge inverter includes a first leg in which first and second switches Q1 and Q2 are disposed, a second leg in which third and fourth switches are disposed, and a primary side of the first transformer, The bridge inverter includes a second leg in which third and fourth switches are disposed, a third leg in which fifth and sixth switches are disposed, and a primary side of the second transformer.

The second stage or rectification stage, which is the secondary side of the first and second transformers T1, T2, comprises a fourth leg comprising a first output diode connected in series, a first output inductor and a second output diode, And a fifth leg comprising a third output diode, a second output inductor, and a fourth output diode. Here, the contacts of the first output inductor and the first output diode, the contacts of the second output inductor and the fourth output diode are connected to the secondary of the second transformer, and the contacts of the first output inductor and the second output diode, The contacts of the output inductor and the third output diode are connected to the secondary of the first transformer. Accordingly, the secondary side of the first and second transformers T1 and T2 and the first and second output inductors L _{o1 and} L _o2 are connected in series as a circle.

This rectification stage constitutes a pair of current doubler rectifier (CDR) circuits. The first CDR circuit consists of the second and third output diodes D _o2 , D _o3 , the first and second output inductors L _o1 , L _o2 , and the secondary of the second transformer T2. Here, the cathodes of the second and third output diodes and the first and second output inductors are connected to both ends of the first transformer T1. The second CDR circuit is constituted by the first and fourth output diodes D _o1 and D _o4 , the first and second output inductors L _o1 and L _o2 , and the secondary side of the second transformer T2. Here, the anode of the first and fourth output diodes and the first and second output inductors L _o1 and L _o2 are connected to both ends of the second transformer T2.

In the rectification stage, an RCD clamp circuit for fixing the voltage stress of the second and third output diodes D _o2 and D _o3 is provided. On the primary side, a rectifier circuit for the first and fourth output diodes D _o1 and Do ₄ 1 and second clamp diodes D _C1 and D _C2 are employed. The first and second clamp diodes D _C1 and D _C2 are paths through which the current formed by the difference between the current i _Lext flowing through the external inductor L _ext and the current i _pri2 flowing through the second full bridge inductor flows.

Hereinafter, the operation of the integrated dual PSFB with CDR according to the present invention will be analyzed. To perform the analysis, some assumptions are made as follows.

_{1) N p1 = N p2 =} N p, N s / N p = n

2) The main switches are ideal MOSFETs except for parasitic capacitors and internal diodes.

3) The output diode is ideal except for the junction capacitor. C _Do1 = C _Do2 = C _Do3 = C _Do4 = C _j

4) The capacitance of the parasitic capacitor C _oss of the switch is much larger than the junction capacitance of the diode.

5) The output capacitor is large enough to be regarded as a constant voltage source with output voltage V _o .

6) Output inductors have the same size. _{O1 o2} L = L _o = L, Δi = Δi _{Lo1 Lo2}

The converter of the present invention operates along a battery charger profile as shown in Fig. The worst case is a low-voltage, high-current output condition as shown at point a in Fig. The gate signal of this converter is based on the same phase transition method as the conventional PSFB converter.

Figure 3 shows the main operating waveforms of the converter of the present invention. 3, all the switches have constant duty ratios (D = 0.5), ignoring the dead time T _DT1 and T _DT2 between the third switch Q3 and the fourth switch Q4, the fifth switch Q5 and the sixth switch Q6, . The switches, which are odd-numbered 1,3,5 switch is driven by the control of the phase transition time T _Φ1 and _Φ2 T, are driven similarly the switches 2, 4, 6, which are even-numbered switch.

The 1,3,5 intervals are gate signals of the switch, that has a phase delay time T and T _{Φ1 Φ2.} Each phase delay time has the same size T _Φ , but under high voltage output conditions, the phase transition time T _Φ1 should be prevented from becoming smaller than the dead time T _DT to prevent voltage overshoot at the primary side switches. Further, the load is small in the CV mode, the sum of the phase transition time T _Φ1 and _Φ2 T less than 0.5Ts.

The switching cycle has twelve modes that can be divided into two half cycles, the first half cycle is from mode 1 to mode 6, and the second half cycle is from mode 7 to mode 12. Since the operation principle of two half cycles is symmetrical, only the first half cycle will be described in order to avoid repeated explanation. Figure 4 shows the operating circuit for the first half cycle.

Mode 1 [t0-t1]

Mode 1 begins when the first switch Q1 is turned on and ends when the fourth switch Q4 is turned off. During mode 1, the first, fourth and sixth switches Q1, Q4 and Q6 are in the ON state and the second, third and fourth output diodes D _o2 , D _o3 and D _o4 are in the conducting state. The difference between the primary output current is the second, the fourth output diode D flows through _o2 and D _o4, second current i _Lo2 flowing through the output inductor (t) and the current i flowing through the secondary side of the second transformer _sec1 (t) The current formed by the third output diode D _o3 flows through the third output diode _Do3 . This is because the current i _Lo2 (t) flowing through the second output inductor is reduced when it meets the current i _sec1 (t) flowing on the secondary side of the first transformer. As shown in FIG. 4 (a), the main current i _pri1 (t) flowing through the first full bridge inverter flows through the first and fourth switches Q1 and Q4 and therefore the current i _sec1 (t) has a constant value.

The power source is transmitted to the secondary side through the second transformer T2, and the following equation 1 can be obtained.

Mode 2 [t1-t2]

Mode 2 begins when the fourth switch Q4 is turned off, and ends when the current i _Do2 flowing along the second output diode reaches a zero level. During mode 2, since the commutation occurs between the second and third output diodes D _o2 , D _o3 , the main power supply current flows through the second, third, and fourth diodes D _o2 , D _o3 , and D _o4 . The difference between the current i _Lo1 (t) flowing in the first output inductor and the current i _sec2 (t) flowing in the secondary side of the second transformer flows through the first output diode _Do1 . Because of this, all the output diodes are conducted and the voltage across the secondary of the first transformers T1, T2 becomes zero. Further, the second clamping diode D _C2 is conducted, whereby the equivalent circuit is as shown in Fig. Based on the equivalent circuit, the following equations (2) and (3) are obtained.

here,

이다.

to be.

Mode 3 [t2-t3]

Mode 3 starts when the commutation between the output diodes employed on the secondary side is completed and ends when the sixth switch Q6 is turned off. For mode 3, the first, third, and sixth switches Q1, Q3, Q6 is in the ON state, the first, third, and fourth output diode D _o1, D _{o3, o4} D is conductive. The input power is transmitted to the secondary side by the first transformer T1 and the main current path is formed along the third and fourth output diodes D _o3 and D _o4 . The current formed by the difference between the secondary current i _sec2 (t) of the second transformer and the current i _Lo1 (t) flowing through the first output inductor flows through the first output diode _Do1 . This is because the secondary current i _sec2 (t) of the second transformer has a constant value as the main current i _pri2 (t) circulates through the third and sixth switches Q3 and Q6.

Mode 4 [t3-t4]

Mode 4 starts when the sixth switch Q6 is turned off, and ends when the current i _Do4 (t) flowing through the fourth output diode reaches zero. Mode for 4, first, third, fourth output diode D _o1, D _{o3, o4} D is conducting, the first and the commutation is generated between the fourth output diode D _o1, D _o4. Also, resonance occurs in the capacitors C _oss5 , C _oss6 , L _lk2 , and L _ext in the primary side. As a result, the voltage that flows through _COS5 and _COS6 is resonated and discharged, respectively.

이다. here,

to be.

The main current i _pri2 is as follows.

, here,

,

이다.

to be.

Because of the resonance operation, the fifth switch Q5 can be turned on by the ZVS characteristic.

Mode 5 [t4-t5]

Mode 5 is the main power supply mode. Mode 5 begins when the current i _Do4 (t) flowing through the fourth output diode reaches a zero level, and ends when the first switch Q1 is turned off. During mode 5, the first, third and fifth switches Q1, Q3 and Q5 are turned on and the first and third output diodes _Do1 and _Do3 are conducted. The input power is transmitted to the secondary side through the first transformer T1, T2.

Mode 6 [t5-t6]

Mode 6 starts when the first switch Q1 is turned off, and ends when the second switch Q2 is turned on. During mode 6, resonance occurs at C _oss1 , C _oss2 , and L _lk1 on the primary side. As a result, the voltage _across C _oss2 and C _oss1 is discharged and charged by resonance, respectively.

이다. here,

to be.

The main current i _pri2 is as follows.

, here,

,

이다.

to be.

Since the operation is the same as that of the conventional PSFB, the output current has the highest value, which is reflected on the primary side. As a result, the switch is easily turned on under ZVS conditions.

The DC conversion ratio of this converter can be derived by using the principle of voltage-time balance of the output inductor. The conversion rate equation can be expressed as follows.

,

이고, D_eff1 과 D_eff2는 효율적인 듀티 사이클이다. here,

,

, And D _eff1 and D _eff2 are efficient duty cycles.

Note that the output voltage of this converter can be regulated by adjusting the phase delay at a fixed switching frequency, as with conventional PSFB converters.

It is generally known that applying a large resonant inductor to extend the ZVS range increases duty cycle losses. Another method of using a large turn ratio transformer with a large number of secondary windings has the disadvantage of creating primary side conduction losses and increasing secondary voltage stress.

The output inductor current can be negative so that the current reflected from the secondary side in this converter can be used as the soft switching energy for the fifth and sixth switches Q5 and Q6 as the lagging leg switches. Thereby, the ZVS range can be extended by a small external inductor and has a low duty cycle loss T _DCL2 . Also, for the center leg, there is no external inductor that increases the duty cycle loss. The duty cycle loss T _DCL1 and T _DCL2 of this converter is expressed by the following equations (9) and (10).

이다. here,

to be.

Leading leg switches can easily be ZVS conditions because the current reflected from the output inductor has the highest value. This is the same as a conventional PSFB converter.

The ZVS condition of the center leg switch is achieved by the sum of the two primary currents flowing through the parasitic capacitors of the switches and the center leg switches are in the same state so that if the third switch Q3 achieves the ZVS condition, do.

Under high load conditions, the main current has a large value due to the reflected current. Thus, the drain-source voltage of the third switch Q3 drops below the zero voltage in the first valley, so that the third switch Q3 can be easily turned on without loss. However, under low load conditions, the ZVS energy is not sufficient to achieve the ZVS condition. After the first valley, the direction of the main current i _pri1 of the first transformer is changed and its voltage is increased. To achieve the ZVS condition, a method of controlling the dead time T _DT1 with the modified dead time (VDT) is implemented in the controller. Since the main current i _pri2 of the second transformer maintains a negative value as shown in Fig. 6, ZVS can be achieved under low load conditions if time is sufficient.

In this way there is an additional mode between mode 2 and mode 3. The circuit diagram for this additional mode is as shown in Fig. The resonant frequency is changed by the parasitic capacitor of the second rectifier diode as follows.

The current waveform is as shown in Fig. Each main current has the same magnitude at time t1-1 at which resonance starts at the new frequency. Since one has a sine wave and the other has a cosine wave, the drain-source voltage can reach zero levels.

The delay time should be controlled by the following equation (12). When Equation (12) is satisfied, the delay time must be large. Conversely, if the delay time is large, equation (12) is satisfied.

The ZVS condition of the lagging leg switches is affected by i _pri2 which is the sum of the magnetizing current of the second transformer T2 and the reflecting current of the secondary output inductor. This is the same as a conventional PSFB converter. However, in the converter of the present invention, the reflected ripple current of the output inductor extends at low load. In other words, the analysis in mode 4 is performed when the ZVS condition is achieved for fifth switch Q5. The current i _Lo2 (t) flowing through the second output inductor under a low load condition becomes a negative value. The current then circulates between the first and second output inductors and the secondary of the first and second transformers. Thereby, the reflection current becomes higher under a very low load condition, which increases the ZVS energy of the fifth switch Q5. As a result, a wide ZVS range can be achieved with a small external inductor.

Conventional interleaved PSFB converters require two external inductors for wide ZVS operation of the lagging leg switches in each FB inverter circuit. However, as described above, in the present invention, the soft switching energy is formed from one external inductor. Also, since the primary side is integrated, the number of switches can be reduced. Accordingly, fewer components are used in this converter. Table 1 shows the number of constituent elements in comparison. Table 1 shows that the converter of the present invention is a converter for processing a high power of 6.6 KW, and the conventional converter is a case of an interleaved PSFB converter.

The converter Single PSFB Converter Interleaved PSFB converter switch 6 4 4 diode 4 4 8 Transformers 2 One 2 Output inductor 2 One 2 Resonant inductor One One 2 system 15 11 22

The turn ratio required in a transformer can be designed in terms of DC conversion ratio and delay time. Based on these equations, the turn ratio can be expressed by the following equation (13).

이다. here,

to be.

The design of switches and diodes is based on voltage and current stress. In the case of the primary switch, a voltage stress is equal to the input voltage, the third and fourth switches Q3, Q4 of the current stress is nI _o, electric current stress of the other switch is half of this.

The diodes reduce the voltage ringing of the secondary side first and fourth output diodes _Do1 , _Do4 . Accordingly, the voltage clamp can be achieved only by the diode that regenerates the ringing energy. For the second and third output diodes, an RCD clamp circuit is used.

The output capacitors are typically designed in consideration of voltage ripple. However, current ripple is an important factor in designing the output capacitors of converters with high output currents. In this converter, the current ripple can be calculated by the following equation.

The output inductor can be designed by the following equation.

Current ripple is an important factor for optimal design.

Hereinafter, the ZVS condition of the fifth switch Q5 of the lagging leg analyzed in Mode 4 will be described. As described above, the reflection current increases at a very small load condition by the reflection current (Iref) expression of the following expression (16).

According to the design of the output inductor, the size of the ripple is determined by the inductance of the output inductor. Therefore, the reflection current can be determined by the circuit design.

When the reflection current becomes zero, that is, when the current ripple of the current i _Lo2 of the second output inductor becomes equal to the output current, the magnetizing current becomes a single source for achieving the ZVS condition. During mode 4, the magnetizing current has a peak value because it is proportional to the duty cycle.

As described above, the relationship between the ZVS condition and the primary current is as shown in Fig. In order to achieve the ZVS condition in all load ranges, the primary current i _Lm of the first or second transformer should be higher than the _required current i _{ZVS, required} to achieve the ZVS condition expressed by:

Based on the analysis of the magnetizing current and the reflection current, the primary current can be expressed by the following equation (18).

,

이다. here,

,

to be.

The relationship between the magnetizing current and the reflection current depends on the inductance of the transformer and the output inductor.

To verify the validity of this converter, a 6.6 kW round converter is realized with a battery charger with the following specifications.

Input voltage (V _IN ): 385V - 400V

Output voltage (V _o ): 250V - 420V

Maximum output current (I _{o, max} ): 16 A

Switching frequency: 100kHz

ZVS Range: Full Load - 25% Load

This circular converter is fabricated using the components listed in Table 2 below.

Main switch Q1 - Q6 IPP6074C6 The first to fourth output diodes D _O1 - D _O4 IDH15S120 (1200V, 15A, V _f = 2.5V) The first and second transformers (T1, T2) Core: EE7072
Turn ratio n: 1.33 (N _P : N _S = 24: 32) The first transformer T1 and the second transformer T2
L _ml : 2.35mH L _m2 : 2.35mH
L _{lk 1} : 7.6 μH L _{lk 2} : 7.6 μH The external inductor (L _ext ) 8.8 μH, MPP core The first and second output inductors (L _O1 , L _O2 ) 250 μH, HF core Output capacitor (C _O ) 270uF / 450V Controller TMS320F28069

The converter is designed with a small external inductor and a wide ZVS range. The turn ratio of the transformer and the filter inductors were designed according to the procedure described in Equations (13) to (18). Magnetizing inductance and external inductor are designed to have ZVS characteristics up to 25% load. To alleviate the voltage ringing problem of the rectifier diode, a clamp diode circuit and an RCD snubber circuit are employed on the secondary side (R = 100kΩ / 10W, C = 33nF, D = ES1M).

Conventional PSFB converters designed for comparison have a ZVS range at 50-100% of full load and require very large resonant inductors to ensure ZVS operation under low load conditions.

Figure 9 shows the primary side current and the output inductor current at low input voltage and full load conditions. According to the primary current waveform, it can be seen that this converter operates well according to the phase transfer method. In addition, it can be seen that load sharing is appropriately performed even if there is no other technique, depending on the output inductor current.

10 shows the primary voltages of the two transformers corresponding to the minimum and maximum input voltages. As shown in Fig. 10, in order to adjust the output voltage, the controller changes the phase delay. Also, the diode voltage is clamped below 830V as designed.

11 and 12 show the gate-source voltage and the drain-source voltage of the third switch, which is the center leg switch, and the sixth switch, which is the lagging leg switch, respectively. As shown, the drain voltage decreases to zero level before the gate voltage reaches the threshold, showing ZVS turn on. ZVS is easily achieved at high load conditions.

Figure 13 compares efficiency versus output power under a constant current mode and constant voltage mode at an output voltage of 13.5A. The peak efficiency of the constant current and voltage fields is 96.6% of full load and 97.3% of full load, respectively. This shows that the converter has more than 95% efficiency over a wide power and voltage range. The efficiency of this converter is higher than that of conventional converters.

The dual full bridge converter of the present invention is driven by the high current used in the EV charger and has a wide band ZVS characteristic. This dual full bridge converter is an integrated dual phase transition control full bridge converter and is implemented using only six switches and one external inductor, so the number of components can be reduced. In addition, a wide ZVS condition is achieved by the fluctuating dead time control scheme and the reflection current from the output inductor by integration of the current doubler. According to this converter, load breaking waveform can be obtained without special control. The operating principles and ZVS characteristics of this converter are analyzed for electric car charger applications. The experimental results obtained from the 5.7 kW circular converter demonstrate the effectiveness of this converter for electric car chargers.

These converters can easily reflect the trend of continuously increasing the power factor of the battery charger for the purpose of extending the drive range in the EV mode. This is because the power handling capacity of the proposed converter can be easily increased by the use of two power transformers and CDRs.

The standard content or standard documents referred to in the above-mentioned embodiments constitute a part of this specification, for the sake of simplicity of description of the specification. Therefore, it is to be understood that the content of the above standard content and portions of the standard documents are added to or contained in the scope of the present invention.

The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents thereof should be construed as falling within the scope of the present invention.

Claims (13)

In a full bridge converter for operating two full bridge inverters in parallel,
Two transformers;
A first full bridge inverter including one full bridge circuit and connected to the primary side of the first transformer;
A second full bridge inverter including another full bridge circuit and connected to the primary side of the second transformer; And
A second leg comprising a first output diode connected in series, a first leg comprising a first output inductor and a second output diode and a third output diode connected in series, a second output inductor and a fourth output diode, Wherein the contacts of the first output inductor and the first output diode and the contacts of the second output inductor and the fourth output diode are connected to the secondary side of the second transformer and the first output inductor and the first output inductor And a contact point of the second output inductor and a contact of the second output inductor and the third output diode are connected to the secondary of the first transformer. The method according to claim 1,
Wherein the first full bridge inverter includes first to fourth switches and a primary side of the first transformer. The method according to claim 1,
Wherein the second full bridge inverter includes third to sixth switches and a primary side of the second transformer. The method according to claim 1,
And an external inductor connected in series with the second transformer. The method according to claim 1,
Wherein the rectification stage comprises a first current doubler rectifier (CDR) circuit having the second and third output diodes, the first and second output inductors, and the secondary of the second transformer. The method according to claim 1,
Wherein the rectification stage comprises a second current-doubler rectifier (CDR) circuit having the first and fourth output diodes, the first and second output inductors, and the secondary of the second transformer. The method according to claim 1,
And the rectification stage includes a clamp circuit for fixing a voltage stress of the second output diode and the third output diode. The method according to claim 1,
Wherein the second full bridge inverter comprises first and second clamp diodes for fixing the voltage stress of the first output diode and the fourth output diode. 5. The method of claim 4,
The ZVS (zero voltage switching) range is extended by the external inductor. The method according to claim 2 or 3,
Further comprising a controller for adjusting a dead time between the first to sixth switch actuation to achieve zero voltage switching (ZVS) conditions. In a full bridge converter for operating two full bridge inverters in parallel,
First and second transformers;
A first leg, a second leg, and a third leg, each of the first leg, the second leg, and the first transformer being constituted by a pair of series-connected switches, constituting a first full bridge circuit, A first stage comprising a second full bridge circuit including the second leg, the third leg and the second transformer; And
A fourth leg comprising a first output diode connected in series, a fourth leg comprising a first output inductor and a second output diode and a third leg connected in series, a fifth leg comprising a second output inductor and a fourth output diode, Wherein the contacts of the first output inductor and the first output diode and the contacts of the second output inductor and the fourth output diode are connected to the secondary side of the second transformer and the first output inductor and the first output inductor And a second stage in which a contact of the second output inductor and a contact of the second output inductor and the third output diode are connected to a secondary of the first transformer. 12. The method of claim 11,
Wherein the two full bridge inverters comprise:
A first full bridge inverter having first to fourth switches disposed in the first and second legs and a primary side of the first transformer;
And a second full bridge inverter including third and sixth switches disposed in the second and third legs and a primary side of the second transformer. 12. The method of claim 11,
And an external inductor connected in series with the second transformer.

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