TW201842625A - Conductive substrate and method for producing conductive substrate - Google Patents
Conductive substrate and method for producing conductive substrate Download PDFInfo
- Publication number
- TW201842625A TW201842625A TW107112918A TW107112918A TW201842625A TW 201842625 A TW201842625 A TW 201842625A TW 107112918 A TW107112918 A TW 107112918A TW 107112918 A TW107112918 A TW 107112918A TW 201842625 A TW201842625 A TW 201842625A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- roughened
- conductive substrate
- metal layer
- plating
- Prior art date
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
- B32B15/08—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Laminated Bodies (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
Description
本發明涉及導電性基板、導電性基板的製造方法。 The present invention relates to a conductive substrate and a method for manufacturing a conductive substrate.
液晶顯示器、攜帶電話、數位相機等各種電子機器中,使用了安裝有各種電子零件並具有配線圖案的導電性基板。 In various electronic devices such as liquid crystal displays, mobile phones, and digital cameras, conductive substrates having various electronic components mounted thereon and having wiring patterns are used.
具有配線圖案的導電性基板藉由在絕緣性的基材上形成金屬層,並根據期望的配線圖案對該金屬層進行圖案化而形成。就具有配線圖案的導電性基板而言,一般藉由在金屬層上配置具有與所要形成的配線圖案相對應的形狀的阻劑(resist),並實施蝕刻而形成。 A conductive substrate having a wiring pattern is formed by forming a metal layer on an insulating substrate and patterning the metal layer in accordance with a desired wiring pattern. A conductive substrate having a wiring pattern is generally formed by disposing a resist having a shape corresponding to a wiring pattern to be formed on a metal layer and performing etching.
然而,在藉由蝕刻形成配線圖案的情況下,蝕刻不僅沿金屬層的厚度方向,而且還沿作為與厚度方向垂直的方向的面方向進行。沿面方向的蝕刻的進行會導致產生阻劑的下部也被蝕刻的所謂的側蝕(side etching)。 However, in the case where the wiring pattern is formed by etching, the etching is performed not only in the thickness direction of the metal layer but also in a plane direction which is a direction perpendicular to the thickness direction. The progress of the etching in the surface direction causes a so-called side etching in which the lower portion of the resist is also etched.
故,當在金屬層上形成阻劑圖案時,考慮到側蝕量,也預先實施了使阻劑圖案變粗的補正。但該補正卻阻礙了具有配線圖案的導電性基板的配線的微細化。 Therefore, when a resist pattern is formed on the metal layer, in consideration of the amount of side etching, correction for making the resist pattern thicker is also performed in advance. However, this correction hinders the miniaturization of the wiring of a conductive substrate having a wiring pattern.
此外,例如專利文獻1中公開了如下一種銅箔配線形成方法,包括在銅箔表面上形成密著層、在上述密著層之上形成感光性阻劑、按照期望的圖案對上述感光性阻劑進行曝光、對上述感光性阻劑進行顯影、除去從上述感光性阻劑所露出的上述密著層、及對上述銅箔進行蝕刻以形成配線的步驟。 In addition, for example, Patent Document 1 discloses a copper foil wiring forming method including forming an adhesive layer on a surface of a copper foil, forming a photosensitive resist on the adhesive layer, and resisting the photosensitive resist according to a desired pattern. A step of exposing the photoresist, developing the photosensitive resist, removing the adhesive layer exposed from the photosensitive resist, and etching the copper foil to form wiring.
〔專利文獻1〕 日本特開2005-039097號公報 [Patent Document 1] Japanese Patent Laid-Open No. 2005-039097
然而,即使採用專利文獻1所公開的銅箔配線形成方法也無法充分抑制側蝕的發生。 However, even if the copper foil wiring forming method disclosed in Patent Document 1 is used, the occurrence of side corrosion cannot be sufficiently suppressed.
鑑於上述先前技術的問題,於本發明的一方面,以提供一種可抑制側蝕的發生的導電性基板為目的。 In view of the foregoing problems in the prior art, it is an object of the present invention to provide a conductive substrate capable of suppressing the occurrence of side etching.
為了解決上述課題,於本發明的一方面,提供一種導電性基板,具有:絕緣性基材;形成在上述絕緣性基材的至少一個面上的金屬層;及形成在上述金屬層上的粗化鍍層,上述粗化鍍層含有平均晶粒尺寸為50nm以上且150nm以下的粒狀結晶。 In order to solve the above problems, in one aspect of the present invention, there is provided a conductive substrate including: an insulating substrate; a metal layer formed on at least one surface of the insulating substrate; and a roughened layer formed on the metal layer. An electroless plating layer, the roughened plating layer contains granular crystals having an average grain size of 50 nm or more and 150 nm or less.
根據本發明的一方面,能夠提供一種可抑制側蝕的發生的導電性基板。 According to one aspect of the present invention, it is possible to provide a conductive substrate capable of suppressing the occurrence of side etching.
10A、10B、20A、20B、30‧‧‧導電性基板 10A, 10B, 20A, 20B, 30‧‧‧ conductive substrate
11、51‧‧‧絕緣性基材 11, 51‧‧‧ insulating substrate
12、12A、12B、52‧‧‧金屬層 12, 12A, 12B, 52‧‧‧ metal layers
13、13A、13B、32A、32B、53‧‧‧粗化鍍層 13, 13A, 13B, 32A, 32B, 53‧‧‧ rough coating
〔第1A圖〕 本發明的實施方式的導電性基板的斷面圖。 [FIG. 1A] A cross-sectional view of a conductive substrate according to an embodiment of the present invention.
〔第1B圖〕 本發明的實施方式的導電性基板的斷面圖。 [FIG. 1B] A cross-sectional view of a conductive substrate according to an embodiment of the present invention.
〔第2A圖〕 本發明的實施方式的導電性基板的斷面圖。 [FIG. 2A] A cross-sectional view of a conductive substrate according to an embodiment of the present invention.
〔第2B圖〕 本發明的實施方式的導電性基板的斷面圖。 [FIG. 2B] A cross-sectional view of a conductive substrate according to an embodiment of the present invention.
〔第3圖〕 本發明的實施方式的具備網(mesh)狀配線的導電性基板的俯視圖。 [FIG. 3] A plan view of a conductive substrate including a mesh wiring according to an embodiment of the present invention.
〔第4A圖〕 沿圖3的A-A’線的斷面圖的一構成例。 [Fig. 4A] An example of the configuration of a cross-sectional view taken along the line A-A 'in Fig. 3.
〔第4B圖〕 沿圖3的A-A’線的斷面圖的另一構成例。 [Fig. 4B] Another configuration example of a sectional view taken along the line A-A 'in Fig. 3.
〔第5圖〕 側蝕量的說明圖。 [Fig. 5] An explanatory diagram of the amount of side etching.
以下,對本發明的導電性基板和導電性基板的製造方法的一實施方式進行說明。 Hereinafter, one embodiment of the conductive substrate and the manufacturing method of the conductive substrate of this invention is demonstrated.
(導電性基板) (Conductive substrate)
本實施方式的導電性基板可具有絕緣性基材、形成在絕緣性基材的至少一個面上的金屬層、及形成在金屬層上的粗化鍍層。 The conductive substrate of the present embodiment may include an insulating substrate, a metal layer formed on at least one surface of the insulating substrate, and a roughened plating layer formed on the metal layer.
另外,粗化鍍層可含有平均晶粒尺寸(size)為50nm以上且150nm以下的粒狀結晶。 In addition, the roughened plating layer may contain granular crystals having an average crystal grain size (size) of 50 nm or more and 150 nm or less.
此外,在其他形態中,粗化鍍層也可含有平均長度為100nm以上且300nm以下,平均寬度為30nm以上且80nm以下,並且平均縱橫比(aspect ratio)為2.0以上且4.5以下的針狀結晶。 In addition, in other forms, the roughened plating layer may include needle-like crystals having an average length of 100 nm to 300 nm, an average width of 30 nm to 80 nm, and an average aspect ratio of 2.0 to 4.5.
需要說明的是,本實施方式的導電性基板是指,包括對金屬層等進行圖案化前的在絕緣性基材的表面上具有金屬層和粗化鍍層的基板、及對金屬層等進行了圖案化的基板,即配線基板。 In addition, the conductive substrate of this embodiment means the board | substrate which has a metal layer and a roughening plating layer on the surface of an insulating base material before patterning a metal layer etc., and the metal layer etc. were performed. A patterned substrate, that is, a wiring substrate.
這裡,首先對本實施方式的導電性基板所包含的各構件在以下 進行說明。 Here, each member included in the conductive substrate of the present embodiment will be described below.
作為絕緣性基材的材料對其並無特別限定,但例如可優選使用從聚醯胺系樹脂、聚對酞酸乙二酯系樹脂、聚萘二甲酸乙二酯系樹脂、環烯系樹脂、聚醯亞胺系樹脂、聚碳酸酯系樹脂等中選出的一種以上的樹脂。特別地,作為絕緣性基材的材料,可較佳使用從聚醯胺、PET(聚對酞酸乙二酯)、PEN(聚萘二甲酸乙二酯)、COP(環烯聚合物)、聚醯亞胺、聚碳酸酯等中選出的一種以上的樹脂。 The material for the insulating base material is not particularly limited, but for example, a polyamide resin, a polyethylene terephthalate resin, a polyethylene naphthalate resin, or a cycloolefin resin can be preferably used. One or more resins selected from polyimide resins, polycarbonate resins, and the like. In particular, as the material of the insulating substrate, polyamine, PET (polyethylene terephthalate), PEN (polyethylene naphthalate), COP (cycloolefin polymer), and One or more resins selected from polyimide and polycarbonate.
對絕緣性基材的厚度並無特別限定,可根據作為導電性基板時所要求的強度、基於導電性基板的用途的規格、靜電容量等進行任意選擇。作為絕緣性基材的厚度,例如優選為10μm以上且200μm以下,較佳為12μm以上且120μm以下,更佳為12μm以上且100μm以下。 The thickness of the insulating base material is not particularly limited, and can be arbitrarily selected according to the strength required when used as a conductive substrate, specifications based on the use of the conductive substrate, capacitance, and the like. The thickness of the insulating base material is, for example, preferably 10 μm or more and 200 μm or less, preferably 12 μm or more and 120 μm or less, and more preferably 12 μm or more and 100 μm or less.
接下來對金屬層進行說明。 Next, the metal layer will be described.
對構成金屬層的材料並無特別限定,可選擇具有符合用途的電傳導率的材料,但從電氣特性較優且蝕刻處理較容易的觀點來看,作為構成金屬層的材料優選使用銅。即,金屬層優選含有銅。 The material constituting the metal layer is not particularly limited, and a material having an electrical conductivity suitable for the application may be selected. However, from the viewpoint of superior electrical characteristics and easier etching, copper is preferably used as the material constituting the metal layer. That is, the metal layer preferably contains copper.
在金屬層含有銅的情況下,構成金屬層的材料例如優選為Cu和從Ni、Mo、Ta、Ti、V、Cr、Fe、Mn、Co、及W的金屬群中選出的至少一種以上的金屬的銅合金、或包括銅和從上述金屬群中選出的一種以上的金屬的材料。此外,金屬層也可為由銅所構成的銅層。 When the metal layer contains copper, the material constituting the metal layer is preferably, for example, Cu and at least one selected from the group consisting of Ni, Mo, Ta, Ti, V, Cr, Fe, Mn, Co, and W. A copper alloy of a metal, or a material including copper and one or more metals selected from the above-mentioned metal group. The metal layer may be a copper layer made of copper.
即,在金屬層含有銅的情況下,金屬層可為從銅、含有銅的金屬、及銅合金中選出的一種以上的層。在金屬層含有銅的情況下,金屬層優選為銅或銅合金的層。其理由在於,就銅或銅合金的層而言,尤其是其電傳導率(導電性)較高,藉由蝕刻加工可容易形成配線。還在於,就銅或銅合金的層而言,尤其容易產生後述的側蝕,但在本實施方式的導電性基板中可對側蝕進 行抑制。 That is, when the metal layer contains copper, the metal layer may be one or more layers selected from copper, a copper-containing metal, and a copper alloy. When the metal layer contains copper, the metal layer is preferably a layer of copper or a copper alloy. The reason is that the copper or copper alloy layer has a particularly high electrical conductivity (conductivity), and wiring can be easily formed by etching. The copper or copper alloy layer is particularly susceptible to side etch, which will be described later. However, the conductive substrate of this embodiment can suppress side etch.
對形成金屬層的方法並無特別限定,但例如優選藉由在其他構件和金屬層之間不配置接著劑而形成。即,金屬層優選直接配置在其他構件的上表面。需要說明的是,金屬層例如可形成並配置在後述的密著層和/或絕緣性基材的上表面。為此,金屬層優選直接形成並配置在密著層或絕緣性基材的上表面。 The method for forming the metal layer is not particularly limited, but it is preferably formed, for example, by not placing an adhesive between another member and the metal layer. That is, the metal layer is preferably arranged directly on the upper surface of another member. In addition, a metal layer can be formed and arrange | positioned on the upper surface of the adhesion layer and / or an insulating base material mentioned later, for example. For this reason, the metal layer is preferably directly formed and disposed on the upper surface of the adhesion layer or the insulating base material.
為了在其他構件的上表面上直接形成金屬層,金屬層優選具有採用乾式鍍法而成膜的金屬薄膜層。作為乾式鍍法對其並無特別限定,但例如可使用蒸鍍法、濺射法、離子鍍法等。尤其從膜厚控制較容易的觀點來看,優選採用濺射法。 In order to form a metal layer directly on the upper surface of another member, the metal layer preferably has a metal thin film layer formed by a dry plating method. The dry plating method is not particularly limited, but for example, a vapor deposition method, a sputtering method, an ion plating method, or the like can be used. In particular, from the viewpoint of easier film thickness control, a sputtering method is preferably used.
此外,在使金屬層更厚的情況下,可在採用乾式鍍法形成金屬薄膜層之後再使用濕式鍍法對金屬鍍層進行積層。具體而言,例如可在絕緣性基材或密著層上採用乾式鍍法形成金屬薄膜層,再將該金屬薄膜層使用為供電層,並採用作為濕式鍍法的一種的電解鍍法形成金屬鍍層。 In addition, when the metal layer is made thicker, the metal plating layer may be laminated using a wet plating method after the metal thin film layer is formed by a dry plating method. Specifically, for example, a metal thin film layer may be formed on an insulating substrate or an adhesive layer by a dry plating method, and the metal thin film layer may be used as a power supply layer, and may be formed by an electrolytic plating method which is a type of wet plating Metal plating.
需要說明的是,在如上所述僅採用乾式鍍法使金屬層成膜的情況下,金屬層可由金屬薄膜層構成。此外,在藉由乾式鍍法和濕式鍍法的組合形成金屬層的情況下,金屬層可由金屬薄膜層和金屬鍍層構成。 In addition, in the case where the metal layer is formed into a film using only the dry plating method as described above, the metal layer may be composed of a metal thin film layer. When the metal layer is formed by a combination of a dry plating method and a wet plating method, the metal layer may be composed of a metal thin film layer and a metal plating layer.
藉由如上所述僅採用乾式鍍法、或採用乾式鍍法和濕式鍍法的組合來形成金屬層,可在絕緣性基材或密著層上不藉由接著劑而直接形成並配置金屬層。 By forming the metal layer using only the dry plating method or a combination of the dry plating method and the wet plating method as described above, the metal can be directly formed and arranged on the insulating base material or the adhesive layer without using an adhesive. Floor.
對金屬層的厚度並無特別限定,在將金屬層使用為配線的情況下,可根據供給至該配線的電流的大小、配線寬度等進行任意選擇。 The thickness of the metal layer is not particularly limited, and when the metal layer is used as a wiring, it can be arbitrarily selected according to the magnitude of the current supplied to the wiring, the wiring width, and the like.
然而,金屬層若過厚,則進行用於形成配線圖案的蝕刻時,蝕刻所需的時間較長,故存在產生容易發生側蝕、難以形成細線等問題的情況。 為此,金屬層的厚度優選為5μm以下,較佳為3μm以下。 However, if the metal layer is too thick, it takes a long time to perform the etching for forming a wiring pattern, so that problems such as easy occurrence of side etching and difficulty in forming thin lines may occur. For this reason, the thickness of the metal layer is preferably 5 μm or less, and more preferably 3 μm or less.
此外,尤其從降低導電性基板的電阻值以可充分提供電流的觀點來看,例如金屬層的厚度優選為50nm以上,較佳為60nm以上,更佳為150nm以上。 In addition, in particular, from the viewpoint of reducing the resistance value of the conductive substrate so that sufficient current can be supplied, for example, the thickness of the metal layer is preferably 50 nm or more, preferably 60 nm or more, and more preferably 150 nm or more.
需要說明的是,在金屬層如上所述具有金屬薄膜層和金屬鍍層的情況下,金屬薄膜層的厚度和金屬鍍層的厚度的合計優選位於上述範圍。 When the metal layer has the metal thin film layer and the metal plating layer as described above, the total of the thickness of the metal thin film layer and the thickness of the metal plating layer is preferably in the above range.
在金屬層由金屬薄膜層構成的情況、或由金屬薄膜層和金屬鍍層構成的情況的任一情況下,都對金屬薄膜層的厚度並無特別限定,但例如優選為50nm以上且700nm以下。 The thickness of the metal thin film layer is not particularly limited in the case where the metal layer is composed of a metal thin film layer, or in the case where it is composed of a metal thin film layer and a metal plating layer, but it is preferably 50 nm or more and 700 nm or less.
接下來對粗化鍍層進行說明。 Next, the roughened plating layer will be described.
本發明的發明人對在金屬層上配置阻劑並進行蝕刻的情況下無法充分抑制側蝕的原因進行了深入研究。其結果為,明確了存在金屬層和阻劑的密著性不足導致蝕刻液會浸入金屬層和阻劑之間並進行擴展的情況,其為無法充分抑制側蝕的原因。 The inventors of the present invention have conducted intensive studies on the reason why side etching cannot be sufficiently suppressed when a resist is disposed on a metal layer and etching is performed. As a result, it became clear that the insufficient adhesion between the metal layer and the resist caused the etchant to penetrate between the metal layer and the resist and spread, which was the reason why the side etching could not be sufficiently suppressed.
故,本發明的發明人進一步進行了研究並發現,當在金屬層上設置粗化鍍層,由此在導電性基板的表面、具體而言、粗化鍍層的表面上配置阻劑的情況下,可提高粗化鍍層和阻劑之間的密著性。據此,發現了藉由採用具有該粗化鍍層的導電性基板可抑制側蝕,並完成了本發明。 Therefore, the inventors of the present invention have conducted further research and found that when a roughened plating layer is provided on the metal layer, and thus a resist is disposed on the surface of the conductive substrate, specifically, the surface of the roughened plating layer, It can improve the adhesion between the roughened coating and the resist. Based on this, it was found that the use of a conductive substrate having the roughened plating layer can suppress side corrosion, and completed the present invention.
就本實施方式的導電性基板的粗化鍍層而言,其表面、具體而言、粗化鍍層的與絕緣性基材相對的面的相反側的面、即、如後所述進行圖案化時配置阻劑的面優選為粗化面。 The surface of the roughened plating layer of the conductive substrate of the present embodiment, specifically, the surface of the roughened plating layer opposite to the surface facing the insulating substrate, that is, when patterned as described later The surface on which the resist is disposed is preferably a roughened surface.
從尤其要抑制側蝕的發生的觀點來看,粗化鍍層優選含有從粒狀結晶和針狀結晶中選出的一種以上的結晶。 From the viewpoint of suppressing the occurrence of side corrosion in particular, the roughened plating layer preferably contains one or more crystals selected from granular crystals and needle crystals.
在粗化鍍層含有粒狀結晶的情況下,粗化鍍層優選含有平均晶 粒尺寸為50nm以上且150nm以下的粒狀結晶。 When the roughened plating layer contains granular crystals, the roughened plating layer preferably contains granular crystals having an average crystal grain size of 50 nm or more and 150 nm or less.
其原因在於,藉由使粗化鍍層含有粒狀結晶,並使其平均晶粒尺寸為50nm以上且150nm以下,可提高以粗化鍍層的表面為粗化面時的粗化鍍層和阻劑之間的密著性,並尤其可抑制側蝕的發生。 The reason for this is that the coarsened plating layer contains granular crystals and the average grain size is 50 nm or more and 150 nm or less, so that the roughened plating layer and the resist can be improved when the surface of the roughened plating layer is a roughened surface. It can prevent the occurrence of side erosion.
在粗化鍍層含有粒狀結晶的情況下,其平均晶粒尺寸優選為70nm以上且150nm以下。 When the roughened plating layer contains granular crystals, the average grain size is preferably 70 nm or more and 150 nm or less.
此外,在粗化鍍層含有粒狀結晶的情況下,粒狀結晶的晶粒尺寸的標準偏差σ優選為10nm以上,較佳為15nm以上。其理由在於,藉由使標準偏差σ為10nm以上,就粗化鍍層所含有的粒狀結晶而言,意味著具有一定程度以上的不均勻性,尤其可提高粗化鍍層和阻劑之間的密著性。對粒狀結晶的晶粒尺寸的標準偏差σ的上限值並無特別限定,但例如可為100nm以下。 When the roughened plating layer contains granular crystals, the standard deviation σ of the grain size of the granular crystals is preferably 10 nm or more, and more preferably 15 nm or more. The reason is that by setting the standard deviation σ to be 10 nm or more, the granular crystals contained in the roughened plating layer have a certain degree of non-uniformity, and in particular, can improve the roughness between the roughened plating layer and the resist. Adhesiveness. The upper limit value of the standard deviation σ of the grain size of the granular crystal is not particularly limited, but may be, for example, 100 nm or less.
需要說明的是,粒狀結晶的晶粒尺寸是指,在如後所述採用掃描式電子顯微鏡等對粗化鍍層的粗化面進行觀察的情況下,完全包攝(subsumption)進行測定的粒狀結晶的最小尺寸的圓的直徑。 It should be noted that the grain size of the granular crystal refers to a particle that is completely subsumption measured when the roughened surface of the roughened coating is observed with a scanning electron microscope or the like as described later. The diameter of a circle with the smallest size of a crystal.
此外,在粗化鍍層含有針狀結晶的情況下,粗化鍍層優選含有平均長度為100nm以上且300nm以下,平均寬度為30nm以上且80nm以下,並且平均縱橫比為2.0以上且4.5以下的針狀結晶。 In addition, when the roughened plating layer contains needle-like crystals, the roughened plating layer preferably contains needle-like shapes having an average length of 100 nm to 300 nm, an average width of 30 nm to 80 nm, and an average aspect ratio of 2.0 to 4.5. crystallization.
其原因在於,藉由使粗化鍍層含有針狀結晶,並使其平均長度為100nm以上且300nm以下,平均寬度為30nm以上且80nm以下,並且縱橫比為2.0以上且4.5以下,可提高將粗化鍍層的表面作為粗化面時的粗化鍍層和阻劑之間的密著性,尤其可抑制側蝕的發生。 The reason is that the roughened plating layer contains needle-like crystals, the average length is 100 nm or more and 300 nm or less, the average width is 30 nm or more and 80 nm or less, and the aspect ratio is 2.0 or more and 4.5 or less. The adhesion between the roughened plating layer and the resist when the surface of the roughened plating layer is used as the roughened surface can suppress the occurrence of side corrosion in particular.
在粗化鍍層含有針狀結晶的情況下,優選為,其平均長度為120nm以上且260nm以下,平均寬度為40nm以上且70nm以下,並且平均縱橫比為2.5以上且4.5以下。 When the roughened plating layer contains needle-like crystals, the average length is preferably 120 nm or more and 260 nm or less, the average width is 40 nm or more and 70 nm or less, and the average aspect ratio is 2.5 or more and 4.5 or less.
此外,在粗化鍍層含有針狀結晶的情況下,針狀結晶的長度、寬度、及縱橫比的標準偏差σ分別優選為40nm以上、5nm以上、及0.5以上。其理由在於,藉由使針狀結晶的長度、寬度、及縱橫比的標準偏差σ位於上述範圍,就粗化鍍層所含有的針狀結晶而言,意味著具有一定程度以上的不均勻性,尤其可提高粗化鍍層和阻劑之間的密著性。對針狀結晶的長度、寬度、及縱橫比的標準偏差σ的上限值並無特別限定,但例如可分別為75nm以下、50nm以下、及5以下。 When the roughened plating layer contains needle-like crystals, the standard deviations σ of the length, width, and aspect ratio of the needle-like crystals are preferably 40 nm or more, 5 nm or more, and 0.5 or more, respectively. The reason is that by setting the standard deviation σ of the length, width, and aspect ratio of the acicular crystals within the above range, it means that the acicular crystals contained in the roughened plating layer have a certain degree of non-uniformity, In particular, the adhesion between the roughened plating layer and the resist can be improved. The upper limits of the length, width, and standard deviation σ of the acicular crystal are not particularly limited, but may be, for example, 75 nm or less, 50 nm or less, and 5 or less.
需要說明的是,針狀結晶的長度和寬度是指,在如後所述採用掃描式電子顯微鏡等對粗化鍍層的粗化面進行觀察的情況時,各針狀結晶的長邊的長度和短邊的長度。另外,縱橫比為長度除以寬度後的值。 It should be noted that the length and width of the acicular crystals refer to the length and length of the long sides of each acicular crystal when the roughened surface of the roughened coating is observed using a scanning electron microscope or the like as described later. The length of the short side. The aspect ratio is a value obtained by dividing the length by the width.
就粗化鍍層所含有的結晶的平均晶粒尺寸、平均長度、平均寬度、平均縱橫比、及標準偏差σ而言,例如可根據使用掃描式電子顯微鏡(SEM:Scanning Electron Microscope)觀察粗化鍍層的粗化面時的觀察圖像進行測定和計算。 The average grain size, average length, average width, average aspect ratio, and standard deviation σ of the crystals included in the roughened plating layer can be observed, for example, by using a scanning electron microscope (SEM: Scanning Electron Microscope). The roughened surface is measured and calculated from the observation image.
對觀察粗化鍍層的粗化面時的具體條件並無特別限定,但例如優選在任意的位置擴大50000倍。另外,在粗化鍍層含有粒狀結晶的情況下,可對1個視野內任意選擇的20個粒狀結晶進行晶粒尺寸的測定,並將該20個粒狀結晶的晶粒尺寸的平均值作為平均晶粒尺寸。此外,還可根據20個粒狀結晶的晶粒尺寸的測定值和所算出的平均晶粒尺寸,計算晶粒尺寸的標準偏差。 The specific conditions for observing the roughened surface of the roughened plating layer are not particularly limited, but for example, it is preferable to enlarge it by 50,000 times at an arbitrary position. In addition, when the roughened plating layer contains granular crystals, the grain size of 20 granular crystals arbitrarily selected in one visual field can be measured, and the average value of the grain sizes of the 20 granular crystals can be measured. As the average grain size. In addition, the standard deviation of the grain size can also be calculated based on the measured grain size of the 20 granular crystals and the calculated average grain size.
在粗化鍍層含有針狀結晶的情況下,同樣可對1個視野內任意選擇的20個針狀結晶進行長度和寬度的測定,並計算縱橫比。另外,可將20個針狀結晶的長度、寬度、及縱橫比的平均值作為平均長度、平均寬度、及平均縱橫比。此外,還可根據20個針狀結晶的長度、寬度的測定值、縱橫比的計算值、及所算出的平均長度、平均寬度、平均縱橫比,計算各自的標準偏差。 In the case where the roughened plating layer contains needle-like crystals, the length and width of 20 needle-like crystals arbitrarily selected in one visual field can also be measured, and the aspect ratio can be calculated. In addition, the average value of the length, width, and aspect ratio of the 20 needle crystals can be used as the average length, average width, and average aspect ratio. In addition, the respective standard deviations can be calculated from the measured values of the length and width of the 20 needle-shaped crystals, the calculated values of the aspect ratio, and the calculated average length, average width, and average aspect ratio.
需要說明的是,就粒狀結晶或針狀結晶而言,優選以1個視野內包括20個以上的方式選擇觀察視野的位置,但在無法選擇包含20個以上的粒狀結晶或針狀結晶的視野的情況下,也可使用數量小於20個的粒狀結晶或針狀結晶來計算平均晶粒尺寸或平均長度、平均寬度、平均縱橫比。 It should be noted that, for granular crystals or acicular crystals, it is preferable to select the position of the observation field such that 20 or more are included in one field of view. In the case of a field of view, the average grain size or average length, average width, and average aspect ratio can also be calculated using granular crystals or acicular crystals with a number of less than 20 pieces.
如上所述,就粗化鍍層的粗化面而言,藉由掃描式電子顯微鏡等可算出粒狀結晶等的結晶的尺寸,故也可以說,上述的粒狀結晶和/或針狀結晶為粗化鍍層的粗化面所含有的結晶。 As described above, regarding the roughened surface of the roughened coating, the size of crystals such as granular crystals can be calculated by a scanning electron microscope or the like. Therefore, it can be said that the above-mentioned granular crystals and / or acicular crystals are Crystals contained in the roughened surface of the plating layer are roughened.
對本實施方式的導電性基板的粗化鍍層的材料並無特別限定,但例如可包括單質鎳、鎳氧化物、鎳氫氧化物、及銅。 The material of the rough-plated layer of the conductive substrate according to this embodiment is not particularly limited, but may include, for example, elemental nickel, nickel oxide, nickel hydroxide, and copper.
這裡,對粗化鍍層所含有的銅的狀態並物特別限定,但銅例如可包括從單質銅和銅的化合物中選出的一種以上。作為銅的化合物,例如可列舉出銅氧化物、銅氫氧化物等。 Here, the state of the copper contained in the roughened plating layer is particularly limited, but the copper may include, for example, one or more kinds selected from a simple copper and a copper compound. Examples of the copper compound include copper oxide and copper hydroxide.
為此,粗化鍍層例如可含有單質鎳、鎳氧化物、及鎳氫氧化物,另外還可含有從單質銅即金屬銅、銅氧化物、及銅氫氧化物中選出的一種以上。 For this reason, the roughened plating layer may contain, for example, elemental nickel, nickel oxide, and nickel hydroxide, and may further include one or more selected from the group consisting of metal copper, copper oxide, and copper hydroxide.
藉由使粗化鍍層含有從單質鎳、鎳氧化物、鎳氫氧化物、及銅、例如從單質銅和銅的化合物中選出的一種以上,可使粗化鍍層的對蝕刻液的反應性與金屬層相同。為此,在同時對金屬層和粗化鍍層進行蝕刻的情況下,可使兩個層變為目標形狀,並可在平面內進行均勻蝕刻,尤其可抑制尺寸不均勻性和/或側蝕的發生。 When the roughened plating layer contains at least one selected from elemental nickel, nickel oxide, nickel hydroxide, and copper, for example, from a compound of elemental copper and copper, the reactivity of the roughened plating layer to the etching solution and the metal can be made. The layers are the same. For this reason, when the metal layer and the roughened plating layer are etched at the same time, the two layers can be changed into a target shape, and uniform etching can be performed in a plane. In particular, dimensional unevenness and / or side etching can be suppressed. occur.
對粗化鍍層的形成方法並無特別限定,例如可採用濕式法形成。 The method for forming the roughened plating layer is not particularly limited, and for example, it can be formed by a wet method.
作為濕式法,尤其優選使用電解鍍法。 As the wet method, an electrolytic plating method is particularly preferably used.
對採用電解鍍法進行粗化鍍層的成膜時所使用的鍍液的組成成 分並無特別限定。例如,可優選使用含有鎳離子和銅離子的鍍液。 There are no particular restrictions on the composition of the plating solution used in forming the rough-plated layer by the electrolytic plating method. For example, a plating solution containing nickel ions and copper ions can be preferably used.
例如,鍍液中的鎳離子濃度優選為2.0g/L以上,較佳為3.0g/L以上。 For example, the nickel ion concentration in the plating solution is preferably 2.0 g / L or more, and more preferably 3.0 g / L or more.
對鍍液中的鎳離子濃度的上限值並無特別限定,但例如優選為20.0g/L以下,較佳為15.0g/L以下。 The upper limit value of the nickel ion concentration in the plating solution is not particularly limited, but it is preferably, for example, 20.0 g / L or less, and more preferably 15.0 g / L or less.
此外,鍍液中的銅離子濃度優選為0.005g/L以上,較佳為0.008g/L以上。 The copper ion concentration in the plating solution is preferably 0.005 g / L or more, and more preferably 0.008 g / L or more.
對鍍液中的銅離子濃度的上限值並無特別限定,但例如優選為4.0g/L以下,較佳為1.02g/L以下。 The upper limit value of the copper ion concentration in the plating solution is not particularly limited, but is preferably 4.0 g / L or less, and more preferably 1.02 g / L or less.
當調製鍍液時,對鎳離子和銅離子的供給方法並無特別限定,例如可在鹽的狀態下進行供給。例如,可優選使用胺磺酸鹽和/或硫酸鹽。需要說明的是,就鹽的種類而言,各金屬元素都可為相同種類的鹽,也可同時使用不同種類的鹽。具體而言,例如也可使用硫酸鎳和硫酸銅那樣的相同種類的鹽來調製鍍液。此外,例如還可同時使用硫酸鎳和胺磺酸銅那樣的不同種類的鹽來調製鍍液。 When the plating solution is prepared, the method for supplying nickel ions and copper ions is not particularly limited, and for example, the supply can be performed in a salt state. For example, sulfamates and / or sulfates may be preferably used. It should be noted that, in terms of the type of salt, each metal element may be the same type of salt, or different types of salts may be used simultaneously. Specifically, for example, the same kind of salt as nickel sulfate and copper sulfate may be used to prepare the plating solution. In addition, for example, different types of salts such as nickel sulfate and copper sulfamate can be used simultaneously to prepare a plating solution.
另外,作為pH調整劑,可優選使用鹼金屬氫氧化物。 In addition, as the pH adjuster, an alkali metal hydroxide can be preferably used.
就作為pH調整劑的鹼金屬氫氧化物而言,例如可使用從氫氧化鈉、氫氧化鉀、及氫氧化鋰中選出的一種以上。特別地,就作為pH調整劑的鹼金屬氫氧化物而言,較佳為從氫氧化鈉和氫氧化鉀中選出的一種以上。其原因在於,氫氧化鈉和氫氧化鉀很容易獲得,並且成本也較低。 As the alkali metal hydroxide as a pH adjuster, for example, one or more selected from sodium hydroxide, potassium hydroxide, and lithium hydroxide can be used. In particular, the alkali metal hydroxide as a pH adjuster is preferably one or more selected from sodium hydroxide and potassium hydroxide. The reason is that sodium hydroxide and potassium hydroxide are easily available and the cost is low.
對本實施方式的鍍液的pH值並無特別限定,但例如優選為3.0以上且5.2以下,較佳為3.5以上且5.0以下。 The pH of the plating solution of this embodiment is not particularly limited, but it is preferably, for example, 3.0 or more and 5.2 or less, and more preferably 3.5 or more and 5.0 or less.
此外,鍍液還可含有錯合劑。作為錯合劑,例如可優選使用醯胺硫酸。 The plating solution may further contain a complexing agent. As the complexing agent, for example, amidosulfuric acid can be preferably used.
對鍍液中的錯合劑的含量並無特別限定,可進行任意選擇。 The content of the complexing agent in the plating solution is not particularly limited, and can be arbitrarily selected.
例如,在作為錯合劑使用醯胺硫酸的情況下,對鍍液中的醯胺硫酸的濃度並無特別限定,但例如優選為1g/L以上且50g/L以下,較佳為5g/L以上且20g/L以下。 For example, when using ammonium sulfuric acid as a complexing agent, the concentration of ammonium sulfuric acid in the plating solution is not particularly limited, but it is preferably 1 g / L or more and 50 g / L or less, and more preferably 5 g / L or more And 20g / L or less.
需要說明的是,藉由對粗化鍍層成膜時的鍍液的pH值和/或電流密度進行調整,可對粗化鍍層所含有的結晶的形狀和/或大小進行選擇。例如,藉由使鍍液的pH值較高或使成膜時的電流密度較高,可容易生成針狀結晶,另外,藉由使鍍液的pH值較低或使成膜時的電流密度較低,可容易生成粒狀結晶。 It should be noted that the shape and / or size of crystals contained in the roughened plating layer can be selected by adjusting the pH and / or current density of the plating solution during the formation of the roughened plating layer. For example, when the pH of the plating solution is high or the current density during film formation is high, needle-like crystals can be easily formed. In addition, the pH of the plating solution is low or the current density during film formation is low. Lower, easy to form granular crystals.
為此,例如可進行預備試驗來選擇條件,以獲得具有期望的形狀和尺寸的結晶的粗化鍍層。 To this end, for example, preliminary tests may be performed to select conditions to obtain a roughened plating layer of crystals having a desired shape and size.
對粗化鍍層的厚度並無特別限定,可對其厚度進行選擇,以可充分提高與阻劑層之間的密著性。 The thickness of the roughened plating layer is not particularly limited, and its thickness can be selected so as to sufficiently improve the adhesion with the resist layer.
粗化鍍層的厚度例如優選為50nm以上,較佳為70nm以上。其原因在於,藉由使粗化鍍層的厚度為50nm以上,可充分地在表面上形成凹凸,由此可提高與阻劑層之間的密著性。 The thickness of the roughened plating layer is preferably 50 nm or more, and more preferably 70 nm or more. The reason for this is that by making the thickness of the roughened plating layer 50 nm or more, unevenness can be sufficiently formed on the surface, whereby the adhesion with the resist layer can be improved.
此外,對粗化鍍層的厚度的上限值並無特別限定,但如果過厚,則形成配線時的蝕刻所需的時間變長,會招致成本的上昇。為此,粗化鍍層的厚度優選為350nm以下,較佳為150nm以下,更佳為145nm以下。 In addition, the upper limit value of the thickness of the roughened plating layer is not particularly limited, but if it is too thick, the time required for the etching at the time of forming the wiring becomes long, which causes an increase in cost. For this reason, the thickness of the roughened plating layer is preferably 350 nm or less, preferably 150 nm or less, and more preferably 145 nm or less.
此外,導電性基板除了上述的絕緣性基材、金屬層、及粗化鍍層以外還可設置任意的層。例如,可設置密著層。 In addition, the conductive substrate may be provided with any layer other than the above-mentioned insulating base material, metal layer, and roughened plating layer. For example, an adhesion layer may be provided.
對密著層的構成例進行說明。 A configuration example of the adhesion layer will be described.
如上所述,金屬層可形成在絕緣性基材上,但在將金屬層直接形成在絕緣性基材上的情況下,存在絕緣性基材和金屬層的密著性不足的情 況。為此,在將金屬層直接形成在絕緣性基材的上表面的情況下、製造過程中、或使用時,存在金屬層會從絕緣性基材剝離的情況。 As described above, the metal layer may be formed on the insulating base material. However, when the metal layer is directly formed on the insulating base material, the adhesion between the insulating base material and the metal layer may be insufficient. For this reason, when the metal layer is directly formed on the upper surface of the insulating substrate, during the manufacturing process, or during use, the metal layer may be peeled from the insulating substrate.
故,在本實施方式的導電性基板中,為了提高絕緣性基材和金屬層之間的密著性,可在絕緣性基材上配置密著層。即,也可為在絕緣性基材和金屬層之間具有密著層的導電性基板。 Therefore, in the conductive substrate of this embodiment, in order to improve the adhesion between the insulating substrate and the metal layer, an adhesive layer may be disposed on the insulating substrate. That is, it may be a conductive substrate having an adhesive layer between the insulating base material and the metal layer.
藉由在絕緣性基材和金屬層之間配置密著層,可提高絕緣性基材和金屬層的密著性,並可更切實地對金屬層從絕緣性基材的剝離進行抑制。 By disposing an adhesive layer between the insulating substrate and the metal layer, the adhesiveness between the insulating substrate and the metal layer can be improved, and peeling of the metal layer from the insulating substrate can be more reliably suppressed.
對構成密著層的材料並無特別限定,可根據與絕緣性基材和金屬層之間的密著力、所要求的金屬層表面的光反射的抑制程度、對於導電性基板使用環境(例如,濕度和/或溫度)的穩定性程度等進行任意選擇。 The material constituting the adhesion layer is not particularly limited, and may be based on the adhesion force between the insulating substrate and the metal layer, the degree of suppression of light reflection on the surface of the metal layer, and the use environment of the conductive substrate (for example, The degree of stability such as humidity and / or temperature can be arbitrarily selected.
密著層例如優選含有從Ni、Zn、Mo、Ta、Ti、V、Cr、Fe、Co、W、Cu、Sn、及Mn中選出的至少一種以上的金屬。此外,密著層還可再含有從碳、氧、氫、及氮中選出的一種以上的元素。 The adhesion layer preferably contains, for example, at least one metal selected from Ni, Zn, Mo, Ta, Ti, V, Cr, Fe, Co, W, Cu, Sn, and Mn. In addition, the adhesion layer may further contain one or more elements selected from carbon, oxygen, hydrogen, and nitrogen.
需要說明的是,密著層也可含有金屬合金,該金屬合金包括從Ni、Zn、Mo、Ta、Ti、V、Cr、Fe、Co、W、Cu、Sn、及Mn中選出的至少兩種以上的金屬。此情況下,密著層也還可再含有從碳、氧、氫、及氮中選出的一種以上的元素。此時,作為含有從Ni、Zn、Mo、Ta、Ti、V、Cr、Fe、Co、W、Cu、Sn、及Mn中選出的至少兩種以上的金屬的金屬合金,可優選使用Cu-Ti-Fe合金、Cu-Ni-Fe合金、Ni-Cu合金、Ni-Zn合金、Ni-Ti合金、Ni-W合金、Ni-Cr合金、及/或、Ni-Cu-Cr合金。 It should be noted that the adhesion layer may also contain a metal alloy including at least two selected from Ni, Zn, Mo, Ta, Ti, V, Cr, Fe, Co, W, Cu, Sn, and Mn. More than one metal. In this case, the adhesion layer may further contain one or more elements selected from carbon, oxygen, hydrogen, and nitrogen. At this time, as a metal alloy containing at least two metals selected from Ni, Zn, Mo, Ta, Ti, V, Cr, Fe, Co, W, Cu, Sn, and Mn, Cu- Ti-Fe alloy, Cu-Ni-Fe alloy, Ni-Cu alloy, Ni-Zn alloy, Ni-Ti alloy, Ni-W alloy, Ni-Cr alloy, and / or Ni-Cu-Cr alloy.
對密著層的成膜方法並無特別限定,但優選採用乾式鍍法進行成膜。作為乾式鍍法,例如可優選使用濺射法、離子鍍法、蒸鍍法等。在採用乾式法使密著層成膜的情況下,從膜厚控制較容易的觀點來看,使用濺射法較佳。需要說明的是,密著層中如上所述也可添加從碳、氧、氫、及氮中選出的 一種以上的元素,此時可更佳地使用反應性濺射法。 The method for forming the adhesive layer is not particularly limited, but it is preferable to form the film by a dry plating method. As the dry plating method, for example, a sputtering method, an ion plating method, a vapor deposition method, or the like can be preferably used. When a dry method is used to form the adhesive layer, it is preferable to use a sputtering method from the viewpoint of easier film thickness control. In addition, as described above, one or more elements selected from carbon, oxygen, hydrogen, and nitrogen may be added to the adhesion layer. In this case, a reactive sputtering method can be more preferably used.
在密著層含有從碳、氧、氫、及氮中選出的一種以上的元素的情況下,藉由預先在密著層成膜時的環境中添加含有從碳、氧、氫、及氮中選出的一種以上的元素的氣體,可將其添加在密著層中。例如,在密著層中添加碳的情況下,可在進行乾式鍍時的環境中預先添加從一氧化碳氣體和二氧化碳氣體中選出的一種以上,在添加氧的情況下,可在進行乾式鍍時的環境中預先添加氧氣,在添加氫的情況下,可在進行乾式鍍時的環境中預先添加從氫氣和水中選出的一種以上,在添加氮的情況下,可在進行乾式鍍時的環境中預先添加氮氣。 When the adhesion layer contains one or more elements selected from carbon, oxygen, hydrogen, and nitrogen, the carbon, oxygen, hydrogen, and nitrogen are added to the environment in advance when the film is formed in the adhesion layer. The selected gas of one or more elements can be added to the adhesion layer. For example, when carbon is added to the adhesion layer, one or more kinds selected from carbon monoxide gas and carbon dioxide gas can be added in advance to the environment when performing dry plating, and when oxygen is added, it can be used during dry plating. Oxygen is added to the environment in advance, and when hydrogen is added, one or more selected from hydrogen and water may be added to the environment in the case of dry plating, and in the case of nitrogen, it may be added to the environment in the case of dry plating in advance. Add nitrogen.
就含有從碳、氧、氫、及氮中選出的一種以上的元素的氣體而言,優選添加非活性氣體,以作為乾式鍍時的環境氣體。作為非活性氣體,對其並無特別限定,但例如可優選使用氬。 For a gas containing one or more elements selected from carbon, oxygen, hydrogen, and nitrogen, it is preferable to add an inert gas as an ambient gas during dry plating. The inert gas is not particularly limited, but for example, argon can be preferably used.
藉由如上所述採用乾式鍍法使密著層成膜,可提高絕緣性基材和密著層之間的密著性。另外,密著層例如可含有金屬作為主成分,故與金屬層之間的密著性也較高。為此,藉由在絕緣性基材和金屬層之間配置密著層,可抑制金屬層的剝離。 By forming the adhesive layer using the dry plating method as described above, the adhesion between the insulating base material and the adhesive layer can be improved. In addition, since the adhesion layer may contain, for example, a metal as a main component, adhesion to the metal layer is also high. For this reason, by providing an adhesive layer between the insulating base material and the metal layer, peeling of the metal layer can be suppressed.
對密著層的厚度並無特別限定,但例如優選為3nm以上且50nm以下,較佳為3nm以上且35nm以下,更佳為3nm以上且33nm以下。 The thickness of the adhesion layer is not particularly limited, but it is preferably, for example, 3 nm or more and 50 nm or less, preferably 3 nm or more and 35 nm or less, and more preferably 3 nm or more and 33 nm or less.
接下來,對導電性基板的構成例進行說明。 Next, a configuration example of the conductive substrate will be described.
如上所述,本實施方式的導電性基板可具有絕緣性基材、金屬層、及粗化鍍層。此外,還可任意地設置密著層等的層。 As described above, the conductive substrate of the present embodiment may include an insulating substrate, a metal layer, and a roughened plating layer. In addition, layers such as an adhesion layer may be arbitrarily provided.
以下使用圖1A和圖1B對具體構成例進行說明。圖1A和圖1B示出了本實施方式的導電性基板的與絕緣性基材、金屬層、及粗化鍍層的積層方向平行的面的斷面圖的例子。 A specific configuration example will be described below using FIGS. 1A and 1B. FIGS. 1A and 1B show examples of cross-sectional views of a surface of a conductive substrate according to the present embodiment parallel to the lamination direction of the insulating base material, the metal layer, and the roughened plating layer.
就本實施方式的導電性基板而言,例如可在絕緣性基材的至少一個面上具有從絕緣性基材側開始依次積層有金屬層和粗化鍍層的結構。 The conductive substrate according to this embodiment may have a structure in which a metal layer and a roughened plating layer are sequentially laminated on at least one surface of the insulating substrate from the insulating substrate side, for example.
具體而言,例如,如圖1A所示的導電性基板10A,可在絕緣性基材11的一個面11a側依次對金屬層12和粗化鍍層13進行各為一層的積層。就粗化鍍層13而言,可使粗化鍍層13的與絕緣性基材11相對的面的相反側的面、即、表面A作為粗化面。此外,如圖1B所示的導電性基板10B,也可在絕緣性基材11的一個面11a側和另一個面(另一面)11b側分別依次對金屬層12A、12B和粗化鍍層13A、13B進行各為一層的積層。此情況下,就粗化鍍層13A、13B而言,也可使與絕緣性基材11相對的面的相反側的面、即、表面A和表面B作為粗化面。 Specifically, for example, as shown in FIG. 1A, in the conductive substrate 10A, the metal layer 12 and the roughened plating layer 13 may be laminated one by one on the one surface 11 a side of the insulating base material 11 in this order. As for the roughened plating layer 13, the surface A of the roughened plating layer 13 opposite to the surface opposing the insulating base material 11, that is, the surface A can be made into a roughened surface. In addition, as shown in FIG. 1B, the conductive substrate 10B may have the metal layers 12A, 12B, and the roughened plating layers 13A, 12A, 12B, and 13B performs lamination of each layer. In this case, as for the roughened plating layers 13A and 13B, the surfaces opposite to the surface facing the insulating base material 11, that is, the surface A and the surface B may be roughened surfaces.
此外,還可為再設置了作為任意的層的例如密著層的結構。此情況下,例如,可為在絕緣性基材的至少一個面上從絕緣性基材側開始依次形成了密著層、金屬層、及粗化鍍層的結構。 In addition, a structure such as an adhesion layer may be further provided as an arbitrary layer. In this case, for example, it is possible to have a structure in which an adhesion layer, a metal layer, and a roughened plating layer are sequentially formed on at least one surface of the insulating substrate from the insulating substrate side.
具體而言,例如,如圖2A所示的導電性基板20A,在絕緣性基材11的一個面11a側可依次對密著層14、金屬層12、及粗化鍍層13進行積層。 Specifically, for example, as shown in FIG. 2A, in the conductive substrate 20A, the adhesive layer 14, the metal layer 12, and the roughened plating layer 13 may be laminated in this order on one surface 11 a side of the insulating substrate 11.
此情況下,也可為在絕緣性基材11的兩個面上對密著層、金屬層、及粗化鍍層進行積層的結構。具體而言,如圖2B所示的導電性基板20B,可在絕緣性基材11的一個面11a側和另一個面11b側分別依次對密著層14A、14B、金屬層12A、12B、及粗化鍍層13A、13B進行積層。 In this case, a structure in which an adhesive layer, a metal layer, and a roughened plating layer are laminated on both surfaces of the insulating base material 11 may be used. Specifically, as shown in FIG. 2B, the conductive substrate 20B can sequentially face the adhesion layers 14A, 14B, the metal layers 12A, 12B on one surface 11 a side and the other surface 11 b side of the insulating substrate 11, respectively, and The rough plating layers 13A and 13B are laminated.
需要說明的是,圖1B和圖2B中示出了在絕緣性基材的兩個面上進行了金屬層、粗化鍍層等的積層的情況下,以絕緣性基材11為對稱面,絕緣性基材11的上下所積層的層呈對稱配置的例子,但並不限定於該形態。例如,還可使圖2B中的絕緣性基材11的一個面11a側的結構與圖1B中的結構同樣地為不設置密著層14A而僅依次積層了金屬層12A和粗化鍍層13A的形態,由此可使 絕緣性基材11的上下所積層的層為非對稱的結構。 In addition, FIG. 1B and FIG. 2B show a case where a metal layer, a roughened plating layer, or the like is laminated on both surfaces of the insulating base material, and the insulating base material 11 is used as a symmetrical surface to insulate the substrate. The example in which the layers stacked on top and bottom of the base material 11 are symmetrically arranged is not limited to this configuration. For example, the structure of the one surface 11a side of the insulating base material 11 in FIG. 2B may be the same as the structure in FIG. 1B in which the metal layer 12A and the rough plating layer 13A are laminated in this order without providing the adhesion layer 14A As a result, the layers stacked above and below the insulating base material 11 can have an asymmetric structure.
就本實施方式的導電性基板而言,可優選作為對各種電子零件進行安裝而使用的導電性基板來使用。對導電性基板的配線形狀並無特別限定,可具有任意的形狀和圖案。這裡,以具備網狀配線的導電性基板為例進行說明。 The conductive substrate according to this embodiment can be preferably used as a conductive substrate used for mounting various electronic components. The wiring shape of the conductive substrate is not particularly limited, and may have any shape and pattern. Here, a conductive substrate provided with a mesh wiring will be described as an example.
具備網狀配線的導電性基板可藉由對至此說明的本實施方式的導電性基板的金屬層和粗化鍍層、根據情況還包括密著層進行蝕刻而獲得。 The conductive substrate provided with the mesh wiring can be obtained by etching the metal layer and the roughened plating layer of the conductive substrate according to the present embodiment described above, and optionally including an adhesion layer.
例如,可藉由兩層配線作為(獲得)網狀配線。具體構成例示於圖3。圖3示出了對具備網狀配線的導電性基板30從金屬層等的積層方向的上表面側進行觀察的圖,為了易於理解配線圖案,絕緣性基材和藉由對金屬層進行圖案化而形成的配線31A、31B以外的層的記載(圖示)被進行了省略。此外,還示出了經由絕緣性基材11可看到的配線31B。 For example, two layers of wiring can be used as (obtained) the mesh wiring. A specific configuration example is shown in FIG. 3. FIG. 3 is a diagram showing a conductive substrate 30 having mesh wiring viewed from the upper surface side in the lamination direction of a metal layer or the like. In order to easily understand the wiring pattern, an insulating substrate and a metal layer are patterned. The description (illustration) of the layers other than the formed wirings 31A and 31B is omitted. Moreover, the wiring 31B which can be seen through the insulating base material 11 is also shown.
圖3所示的導電性基板30具有絕緣性基材11、與圖中Y軸方向平行的複數個配線31A、及與X軸方向平行的配線31B。需要說明的是,配線31A、31B藉由對金屬層進行蝕刻而形成,該配線31A、31B的上表面或下表面上形成了圖中未示的粗化鍍層。此外,粗化鍍層被蝕刻為與配線31A、31B相同的形狀。 The conductive substrate 30 shown in FIG. 3 includes an insulating substrate 11, a plurality of wirings 31A parallel to the Y-axis direction in the figure, and wirings 31B parallel to the X-axis direction. It should be noted that the wirings 31A and 31B are formed by etching a metal layer, and rough surfaces (not shown) are formed on the upper or lower surfaces of the wirings 31A and 31B. The roughened plating is etched into the same shape as the wirings 31A and 31B.
對絕緣性基材11和配線31A、31B的配置並無特別限定。圖4A和圖4B中示出了絕緣性基材11和配線的配置的構成例。圖4A和圖4B相當於沿圖3的A-A’線的斷面圖。 The arrangement of the insulating base material 11 and the wirings 31A and 31B is not particularly limited. 4A and 4B show a configuration example of the arrangement of the insulating base material 11 and the wiring. 4A and 4B are cross-sectional views taken along line A-A 'in FIG. 3.
首先,如圖4A所示,絕緣性基材11的上、下表面上可分別配置配線31A、31B。需要說明的是,圖4A中,配線31A的上表面和配線31B的下表面上還配置了形狀被蝕刻為與配線相同的粗化鍍層32A、32B。 First, as shown in FIG. 4A, wirings 31A and 31B may be arranged on the upper and lower surfaces of the insulating base material 11, respectively. In addition, in FIG. 4A, the upper surface of the wiring 31A and the lower surface of the wiring 31B are also provided with the roughened plating layers 32A and 32B having the same shape as the wiring.
此外,如圖4B所示,也可使用一組絕緣性基材11,以夾著一個 絕緣性基材11的方式在上、下表面上配置配線31A、31B,並且,將一個配線31B配置在絕緣性基材11之間。此情況下,配線31A、31B的上表面上也可配置形狀被蝕刻為與配線相同的粗化鍍層32A、32B。需要說明的是,如上所述,除了金屬層和粗化鍍層以外還可設置密著層。為此,在圖4A和圖4B的任一情況下,例如都可在配線31A和配線31B中的任意一個或兩個與絕緣性基材11之間設置密著層。在設置密著層的情況下,密著層也優選被蝕刻為形狀與配線31A、31B相同。 In addition, as shown in FIG. 4B, a group of insulating substrates 11 may be used to arrange wirings 31A and 31B on the upper and lower surfaces so as to sandwich one insulating substrate 11, and one wiring 31B may be arranged on Between the insulating base materials 11. In this case, the roughened plating layers 32A and 32B having the same shape as that of the wirings may be arranged on the upper surfaces of the wirings 31A and 31B. It should be noted that, as described above, an adhesion layer may be provided in addition to the metal layer and the roughened plating layer. For this reason, in any of the cases of FIGS. 4A and 4B, for example, an adhesive layer may be provided between any one or both of the wiring 31A and 31B and the insulating base material 11. When the adhesion layer is provided, the adhesion layer is also preferably etched to have the same shape as the wirings 31A and 31B.
就圖3和圖4A所示的具有網狀配線的導電性基板而言,例如,可基於圖1B那樣在絕緣性基材11的兩個面上具備金屬層12A、12B和粗化鍍層13A、13B的導電性基板來形成。 The conductive substrate with mesh wiring shown in FIG. 3 and FIG. 4A may be provided with metal layers 12A, 12B and a roughened plating layer 13A, on both surfaces of the insulating base material 11 as shown in FIG. 1B, for example. 13B is formed of a conductive substrate.
若以使用圖1B的導電性基板來形成的情況為例進行說明,則首先對絕緣性基材11的一個面11a側的金屬層12A和粗化鍍層13A實施蝕刻,以使與圖1B中Y軸方向平行的複數個線狀的圖案沿X軸方向隔開預定間隔而配置。需要說明的是,圖1B中的X軸方向是指與各層的寬度方向平行的方向。此外,圖1B中的Y軸方向是指與圖1B中的紙面垂直的方向。 In the case of using the conductive substrate of FIG. 1B as an example, the metal layer 12A and the roughened plating layer 13A on the one surface 11a side of the insulating base material 11 are etched so that they are the same as Y in FIG. 1B. A plurality of linear patterns parallel to the axial direction are arranged at predetermined intervals in the X-axis direction. It should be noted that the X-axis direction in FIG. 1B refers to a direction parallel to the width direction of each layer. In addition, the Y-axis direction in FIG. 1B refers to a direction perpendicular to the paper surface in FIG. 1B.
接下來,對絕緣性基材11的另一個面11b側的金屬層12B和粗化鍍層13B進行蝕刻,以使與圖1B中X軸方向平行的複數個線狀的圖案沿Y軸方向隔開預定間隔而配置。 Next, the metal layer 12B and the roughened plating layer 13B on the other surface 11b side of the insulating base material 11 are etched so that a plurality of linear patterns parallel to the X-axis direction in FIG. 1B are spaced along the Y-axis direction. Arranged at predetermined intervals.
藉由以上的操作,可形成圖3和圖4A所示的具有網狀配線的導電性基板。需要說明的是,也可同時實施絕緣性基材11的兩個面的蝕刻。即,金屬層12A、12B和粗化鍍層13A、13B的蝕刻也可同時進行。此外,就圖4A中的配線31A、31B和絕緣性基材11之間還具有形狀被圖案化為與配線31A、31B相同的密著層的導電性基板而言,可藉由使用圖2B所示的導電性基板並同樣地進行蝕刻而製作。 Through the above operations, a conductive substrate having mesh wiring as shown in FIGS. 3 and 4A can be formed. In addition, you may perform the etching of both surfaces of the insulating base material 11 simultaneously. That is, the metal layers 12A and 12B and the rough plating layers 13A and 13B may be etched simultaneously. In addition, for a conductive substrate having a shape patterned into the same adhesion layer as that of the wirings 31A and 31B between the wirings 31A and 31B and the insulating base material 11 in FIG. 4A, it can be achieved by using FIG. 2B. The conductive substrate shown below was fabricated by similarly etching.
圖3所示的具有網狀配線的導電性基板還可使用兩個圖1A或圖2A所示的導電性基板來形成。若以使用兩個圖1A的導電性基板來形成的情況為例進行說明,則針對兩個圖1A所示的導電性基板分別蝕刻金屬層12和粗化鍍層13,以使與X軸方向平行的複數個線狀的圖案沿Y軸方向隔開預定間隔而配置。然後,以使藉由上述蝕刻處理在各導電性基板上所形成的線狀的圖案互相交叉的方式調整方向並使兩個導電性基板貼合,由此可製成具備網狀配線的導電性基板。對兩個導電性基板貼合時的貼合面並無特別限定。例如,藉由使積層了金屬層12等的圖1A中的表面A和沒有積層金屬層12等的圖1A中的另一個面11b貼合,也可成為圖4B所示的結構。 The conductive substrate with mesh wiring shown in FIG. 3 can also be formed using two conductive substrates shown in FIG. 1A or 2A. Taking the case where two conductive substrates shown in FIG. 1A are used as an example for description, the metal layer 12 and the roughened plating layer 13 are etched for the two conductive substrates shown in FIG. 1A so as to be parallel to the X-axis direction. A plurality of linear patterns are arranged at predetermined intervals in the Y-axis direction. Then, by adjusting the directions so that the linear patterns formed on the respective conductive substrates by the above-mentioned etching process intersect with each other and bonding the two conductive substrates together, it is possible to produce conductivity having mesh wiring. Substrate. The bonding surface when two conductive substrates are bonded is not particularly limited. For example, the structure shown in FIG. 4B may be formed by bonding the surface A in FIG. 1A in which the metal layer 12 and the like are laminated and the other surface 11 b in FIG. 1A in which the metal layer 12 and the like are not laminated.
此外,例如藉由使絕緣性基材11的沒有積層金屬層12等的圖1A中的另一個面11b彼此貼合,還可成為斷面示於圖4A的結構。 In addition, for example, by bonding the other surfaces 11 b in FIG. 1A without the laminated metal layer 12 and the like of the insulating base material 11 to each other, a structure having a cross section shown in FIG. 4A may be used.
需要說明的是,就圖4A和圖4B中的配線31A、31B和絕緣性基材11之間還具有形狀被圖案化為與配線31A、31B相同的密著層的導電性基板而言,可藉由使用圖2A所示的導電性基板以取代圖1A所示的導電性基板來進行製作。 It should be noted that, for a conductive substrate having a shape in which the wiring 31A, 31B and the insulating base material 11 in FIG. 4A and FIG. 4B are patterned into the same adhesion layer as the wiring 31A, 31B, It is manufactured by using the conductive substrate shown in FIG. 2A instead of the conductive substrate shown in FIG. 1A.
對圖3、圖4A、及圖4B所示的具有網狀配線的導電性基板中的配線的寬度和/或配線間的距離並無特別限定,例如,可根據配線中所流動的電流量等進行選擇。 The width of the wiring and / or the distance between the wirings in the conductive substrate with mesh wiring shown in FIGS. 3, 4A, and 4B is not particularly limited. For example, it can be based on the amount of current flowing in the wiring. Make your selection.
然而,根據本實施方式的導電性基板,即使在具有粗化鍍層,並對粗化鍍層和金屬層進行了蝕刻和圖案化的情況下,也可抑制側蝕的發生,並可將粗化鍍層和金屬層圖案化為期望形狀。具體而言,例如可形成配線寬度為10μm以下的配線。為此,本實施方式的導電性基板優選包含配線寬度為10μm以下的配線。對配線寬度的下限值並無特別限定,但例如可為3μm以上。 However, according to the conductive substrate of this embodiment, even when the roughened plating layer and the roughened plating layer and the metal layer are etched and patterned, the occurrence of side corrosion can be suppressed, and the roughened plating layer can be formed. And the metal layer is patterned into a desired shape. Specifically, for example, a wiring having a wiring width of 10 μm or less can be formed. For this reason, it is preferable that the conductive substrate of this embodiment includes wiring having a wiring width of 10 μm or less. The lower limit value of the wiring width is not particularly limited, but may be, for example, 3 μm or more.
圖3、圖4A、及圖4B中示出了藉由組合直線形狀的配線以形成 網狀配線(配線圖案)的例子,但並不限定於該形態,配線圖案的形狀和/或構成配線圖案的配線可為任意形狀。 3, 4A, and 4B show examples of forming a net-like wiring (wiring pattern) by combining linear wirings, but the present invention is not limited to this configuration. The shape of the wiring pattern and / or the configuration of the wiring pattern are shown. The wiring can be any shape.
此外,圖4A和圖4B中示出了殘留有粗化鍍層且具有配線圖案的導電性基板的例子,但粗化鍍層是為了提高與阻劑之間的密著性而設置的層,故形成配線圖案之後也可將其除去。在進行除去的情況下,例如可藉由一般的硫酸/過氧化氫水類的微蝕刻液除去粗化鍍層。 In addition, FIG. 4A and FIG. 4B show an example of a conductive substrate having a roughened plating layer remaining and having a wiring pattern. However, the roughened plating layer is a layer provided to improve adhesion to a resist, and is therefore formed. The wiring pattern can also be removed afterwards. In the case of removal, for example, the rough plating layer can be removed by a general micro-etching solution of sulfuric acid / hydrogen peroxide water.
根據以上的本實施方式的導電性基板,在形成於絕緣性基材的至少一個面的金屬層上具有積層了粗化鍍層的結構。為此,與阻劑之間的密著性較高,可抑制側蝕的發生。 According to the conductive substrate of this embodiment described above, the roughened layer is laminated on the metal layer formed on at least one surface of the insulating base material. For this reason, the adhesiveness with the resist is high, and the occurrence of side corrosion can be suppressed.
(導電性基板的製造方法) (Manufacturing method of conductive substrate)
接著,對本實施方式的導電性基板的製造方法的一構成例進行說明。 Next, a configuration example of a method for manufacturing a conductive substrate according to this embodiment will be described.
本實施方式的導電性基板的製造方法可具有以下的步驟。 The method for manufacturing a conductive substrate according to this embodiment may include the following steps.
在絕緣性基材的至少一個面上形成金屬層的金屬層形成步驟。 A metal layer forming step of forming a metal layer on at least one surface of the insulating base material.
在金屬層上形成粗化鍍層的粗化鍍層形成步驟。 A rough plating layer forming step of forming a rough plating layer on a metal layer.
另外,在粗化鍍層形成步驟中,可使用含有鎳離子和銅離子的鍍液並採用電解法進行粗化鍍層的成膜。 In the roughening plating layer forming step, a roughening plating layer can be formed by an electrolytic method using a plating solution containing nickel ions and copper ions.
以下,對本實施方式的導電性基板的製造方法進行具體說明。 Hereinafter, the manufacturing method of the conductive substrate of this embodiment is demonstrated concretely.
需要說明的是,藉由本實施方式的導電性基板的製造方法可優選製造上述的導電性基板。為此,就以下所說明的部分以外的部分而言,可為與上述的導電性基板的情形同樣的結構,故省略一部分說明。 In addition, the above-mentioned conductive substrate can be preferably manufactured by the manufacturing method of the conductive substrate of this embodiment. For this reason, parts other than those described below may have the same structure as in the case of the above-mentioned conductive substrate, and a part of the description is omitted.
可預先準備供金屬層形成步驟中使用的絕緣性基材。另外,根據需要還可預先進行將絕緣性基材切斷為任意尺寸等的處理。 An insulating substrate to be used in the metal layer forming step may be prepared in advance. In addition, if necessary, a process such as cutting the insulating base material to an arbitrary size may be performed in advance.
另外,金屬層如上所述優選具有金屬薄膜層。此外,金屬層還可具有金屬薄膜層和金屬鍍層。為此,金屬層形成步驟例如可具有採用乾式鍍 法形成金屬薄膜層的步驟。此外,金屬層形成步驟也可具有採用乾式鍍法形成金屬薄膜層的步驟、及將該金屬薄膜層作為供電層並採用作為濕式鍍法的一種的電鍍法形成金屬鍍層的步驟。 The metal layer preferably has a metal thin film layer as described above. The metal layer may further include a metal thin film layer and a metal plating layer. For this purpose, the metal layer forming step may include, for example, a step of forming a metal thin film layer by a dry plating method. In addition, the metal layer forming step may include a step of forming a metal thin film layer by a dry plating method, and a step of forming a metal plating layer by using the metal thin film layer as a power supply layer and using a plating method which is a type of wet plating method.
作為金屬薄膜層形成步驟中採用的乾式鍍法,對其並無特別限定,例如可使用蒸鍍法、濺射法、或離子鍍法等。需要說明的是,作為蒸鍍法,可優選使用真空蒸鍍法。作為金屬薄膜層形成步驟中採用的乾式鍍法,尤其從膜厚控制較容易的觀點來看,較佳使用濺射法。 The dry plating method used in the step of forming the metal thin film layer is not particularly limited, and for example, a vapor deposition method, a sputtering method, or an ion plating method can be used. In addition, as a vapor deposition method, a vacuum vapor deposition method can be used preferably. As the dry plating method used in the step of forming the metal thin film layer, a sputtering method is preferably used from the viewpoint that the film thickness control is relatively easy.
接下來,對金屬鍍層形成步驟進行說明。對採用濕式鍍法形成金屬鍍層的步驟中的條件、即、電鍍處理的條件並無特別限定,可使用常規方法中的諸條件。例如,將形成了金屬薄膜層的基材供給至具有金屬鍍液的鍍槽內,並對電流密度和/或基材的搬送速度進行控制,據此可形成金屬鍍層。 Next, a metal plating layer forming process is demonstrated. The conditions in the step of forming the metal plating layer by the wet plating method, that is, the conditions of the plating treatment are not particularly limited, and various conditions in the conventional method can be used. For example, the base material on which the metal thin film layer is formed is supplied into a plating tank having a metal plating solution, and the current density and / or the transfer speed of the base material is controlled, thereby forming a metal plating layer.
接下來,對粗化鍍層形成步驟進行說明。 Next, a roughened plating layer forming step will be described.
在粗化鍍層形成步驟中,例如可形成含有單質鎳、鎳氧化物、鎳氫氧化物、及銅的粗化鍍層。 In the rough plating layer forming step, for example, a rough plating layer containing elemental nickel, nickel oxide, nickel hydroxide, and copper can be formed.
粗化鍍層可藉由濕式法形成。具體而言,例如,將金屬層作為供電層來使用,由此在具有上述的鍍液的鍍槽內可在金屬層上藉由電解法、例如、電解鍍法形成粗化鍍層。藉由這樣地將金屬層作為供電層,並採用電解鍍法形成粗化鍍層,可在金屬層的與絕緣性基材相對的面的相反側的面的整面上形成粗化鍍層。 The roughened plating layer can be formed by a wet method. Specifically, for example, by using a metal layer as a power supply layer, a roughened plating layer can be formed on a metal layer by an electrolytic method, for example, an electrolytic plating method, in a plating tank having the above-mentioned plating solution. By using the metal layer as a power supply layer and forming the roughened plating layer by the electrolytic plating method in this manner, the roughened plating layer can be formed on the entire surface of the metal layer on the side opposite to the surface facing the insulating base material.
使粗化鍍層成膜時,藉由調整鍍液的pH值和/或電流密度,可選擇粗化鍍層所含有的結晶的形狀和/或尺寸。例如,藉由使鍍液的pH值較高或使成膜時的電流密度較高,可容易生成針狀結晶,另外,藉由使鍍液的pH值較低或使成膜時的電流密度較低,可容易生成粒狀結晶。 When the roughened plating layer is formed into a film, the shape and / or size of the crystals contained in the roughened plating layer can be selected by adjusting the pH and / or current density of the plating solution. For example, when the pH of the plating solution is high or the current density during film formation is high, needle-like crystals can be easily formed. In addition, the pH of the plating solution is low or the current density during film formation is low. Lower, easy to form granular crystals.
為此,例如可進行預備試驗來選擇條件,以成為具有期望的形 狀和尺寸的結晶的粗化鍍層。 For this purpose, for example, a preliminary test may be performed to select conditions so as to obtain a roughened plated layer of crystals having a desired shape and size.
鍍液如上所述,故省略其說明。 Since the plating solution is as described above, its explanation is omitted.
在本實施方式的導電性基板的製造方法中,除了上述步驟以外,還可實施任意的步驟。 In the manufacturing method of the conductive substrate of this embodiment, in addition to the above-mentioned steps, arbitrary steps can be performed.
例如,在絕緣性基材和金屬層之間形成密著層的情況下,可實施在絕緣性基材的形成金屬層的面上形成密著層的密著層形成步驟。在實施密著層形成步驟的情況下,金屬層形成步驟可在密著層形成步驟之後實施,在金屬層形成步驟中,可在本步驟中於絕緣性基材上形成了密著層的基材上形成金屬薄膜層。 For example, when an adhesion layer is formed between the insulating base material and the metal layer, an adhesion layer forming step of forming an adhesion layer on the metal layer-forming surface of the insulating base material may be performed. When the adhesion layer formation step is performed, the metal layer formation step may be performed after the adhesion layer formation step. In the metal layer formation step, the base of the adhesion layer may be formed on the insulating substrate in this step. A metal thin film layer is formed on the material.
在密著層形成步驟中,密著層的成膜方法並無特別限定,但優選採用乾式鍍法進行成膜。作為乾式鍍法,例如可優選使用濺射法、離子鍍法、蒸鍍法等。在採用乾式法使密著層成膜的情況下,從膜厚控制較容易的觀點來看,較佳採用濺射法。需要說明的是,密著層中如上所述還可添加從碳、氧、氫、及氮中選出的一種以上的元素,此時可更佳地採用反應性濺射法。 In the adhesion layer forming step, the method for forming the adhesion layer is not particularly limited, but it is preferable to form the film by a dry plating method. As the dry plating method, for example, a sputtering method, an ion plating method, a vapor deposition method, or the like can be preferably used. When a dry method is used to form the adhesion layer, a sputtering method is preferably used from the viewpoint of easier film thickness control. In addition, as described above, one or more elements selected from carbon, oxygen, hydrogen, and nitrogen may be added to the adhesion layer. In this case, a reactive sputtering method may be more preferably used.
就藉由本實施方式的導電性基板的製造方法所獲得的導電性基板而言,例如可應用於對各種電子零件進行安裝而使用的導電性基板等的各種用途。另外,在應用於各種用途的情況下,優選對本實施方式的導電性基板中所含的金屬層和粗化鍍層進行了圖案化。需要說明的是,在設置密著層的情況下,優選對密著層也進行了圖案化。就金屬層和粗化鍍層、根據情況還包括密著層而言,例如可按照期望的配線圖案進行圖案化,另外,就金屬層和粗化鍍層、根據情況還包括密著層而言,優選被圖案化為相同的形狀。 The conductive substrate obtained by the method for manufacturing a conductive substrate according to the present embodiment can be applied to various applications such as a conductive substrate used for mounting various electronic components. When applied to various applications, it is preferable to pattern the metal layer and the roughened plating layer included in the conductive substrate of the present embodiment. In addition, when an adhesion layer is provided, it is preferable to pattern also an adhesion layer. The metal layer, the roughened plating layer, and the adhesion layer may be patterned according to the situation, for example, and the metal layer, the roughened plating layer, and the adhesion layer may be patterned according to the situation. Are patterned into the same shape.
為此,本實施方式的導電性基板的製造方法可具有對金屬層和粗化鍍層進行圖案化的圖案化步驟。需要說明的是,在形成了密著層的情況下,圖案化步驟可為對密著層、金屬層、及粗化鍍層進行圖案化的步驟。 Therefore, the method for manufacturing a conductive substrate according to this embodiment may include a patterning step of patterning a metal layer and a roughened plating layer. It should be noted that, when the adhesion layer is formed, the patterning step may be a step of patterning the adhesion layer, the metal layer, and the roughened plating layer.
對圖案化步驟的工序並無特別限定,可按照任意的工序進行實施。例如,在圖1A那樣於絕緣性基材11上進行了金屬層12和粗化鍍層13的積層的導電性基板10A的情況下,首先可實施在粗化鍍層13的表面A上配置具有期望圖案的阻劑的阻劑配置工序。然後可實施向粗化鍍層13的表面A、即、配置了阻劑的表面側供給蝕刻液的蝕刻工序。 The process of the patterning step is not particularly limited, and can be carried out in accordance with an arbitrary process. For example, in the case of a conductive substrate 10A in which a metal layer 12 and a roughened plating layer 13 are laminated on an insulating base material 11 as shown in FIG. Resistor placement process for the resist. Then, an etching step of supplying an etchant to the surface A of the roughened plating layer 13, that is, the surface on which the resist is disposed, may be performed.
對蝕刻工序中使用的蝕刻液並無特別限定,可根據金屬層、粗化鍍層的組成成分等進行任意選擇。例如,在金屬層和粗化鍍層對於蝕刻液的反應性大致相同的情況下,可優選採用一般的金屬層的蝕刻時所使用的蝕刻液。 The etching solution used in the etching step is not particularly limited, and can be arbitrarily selected according to the composition of the metal layer, the roughened plating layer, and the like. For example, when the reactivity of the metal layer and the roughened plating layer with respect to the etchant is substantially the same, an etchant used in the etching of a general metal layer can be preferably used.
作為蝕刻液,例如可優選使用含有從硫酸、過氧化氫(過氧化氫水)、鹽酸、氯化銅(II)、及氯化鐵(III)中選出的一種以上的混合水溶液。對蝕刻液中的各組成成分的含量並無特別限定。 As the etching solution, for example, a mixed aqueous solution containing one or more kinds selected from sulfuric acid, hydrogen peroxide (hydrogen peroxide water), hydrochloric acid, copper (II) chloride, and iron (III) chloride can be preferably used. The content of each component in the etching solution is not particularly limited.
蝕刻液也可在室溫下使用,但為了提高反應性,還可加溫後再使用,例如可加熱至40℃以上且50℃以下後再進行使用。 The etchant may be used at room temperature, but in order to improve the reactivity, it may be used after being heated. For example, the etchant may be used after being heated to 40 ° C or higher and 50 ° C or lower.
此外,就圖1B那樣在絕緣性基材11的一個面11a和另一個面11b上積層了金屬層12A、12B和粗化鍍層13A、13B的導電性基板10B而言,也可實施進行圖案化的圖案化步驟。此情況下,例如可實施在粗化鍍層13A、13B的表面A和表面B上配置具有期望圖案的阻劑的阻劑配置工序。之後,可實施向粗化鍍層13A、13B的表面A和表面B、即、配置了阻劑的表面側供給蝕刻液的蝕刻工序。 In addition, the conductive substrate 10B in which the metal layers 12A and 12B and the roughened plating layers 13A and 13B are laminated on one surface 11a and the other surface 11b of the insulating base material 11 as shown in FIG. 1B may be patterned. Patterning steps. In this case, for example, a resist disposing step of disposing a resist having a desired pattern on the surfaces A and B of the rough plating layers 13A and 13B can be performed. After that, an etching step of supplying an etching solution to the surface A and the surface B of the rough plating layers 13A and 13B, that is, the surface on which the resist is disposed, may be performed.
對蝕刻工序中形成的圖案並無特別限定,可為任意的形狀。例如,在圖1A所示的導電性基板10A的情況下,如上所述,也可使金屬層12和粗化鍍層13以含有複數條直線和/或彎曲成鋸齒狀的線(之字形直線)的方式形成圖案。 The pattern formed in the etching step is not particularly limited, and may be any shape. For example, in the case of the conductive substrate 10A shown in FIG. 1A, as described above, the metal layer 12 and the roughened plating layer 13 may be formed to include a plurality of straight lines and / or a zigzag line (a zigzag straight line). Way to form a pattern.
此外,在圖1B所示的導電性基板10B的情況下,還可採用使金屬層12A和金屬層12B成為網狀配線的方式形成圖案。此情況下,粗化鍍層13A優選被圖案化為與金屬層12A相同的形狀,粗化鍍層13B優選被圖案化為與金屬層12B相同的形狀。 In addition, in the case of the conductive substrate 10B shown in FIG. 1B, a pattern may be formed so that the metal layer 12A and the metal layer 12B are meshed wirings. In this case, the rough plating layer 13A is preferably patterned into the same shape as the metal layer 12A, and the rough plating layer 13B is preferably patterned into the same shape as the metal layer 12B.
此外,例如在圖案化步驟中對上述導電性基板10A的金屬層12等進行了圖案化之後,也可實施使圖案化了的兩個以上的導電性基板進行積層的積層步驟。積層時,例如藉由使各導電性基板的金屬層的圖案交叉積層,也可獲得具備網狀配線的積層導電性基板。 In addition, for example, after the metal layer 12 and the like of the conductive substrate 10A are patterned in the patterning step, a lamination step of laminating two or more patterned conductive substrates may be performed. At the time of lamination, for example, by laminating the patterns of the metal layers of the respective conductive substrates, it is also possible to obtain a laminated conductive substrate including a mesh wiring.
對使積層了的兩個以上的導電性基板固定的方法並無特別限定,例如可藉由接著劑等進行固定。 The method of fixing two or more laminated conductive substrates is not particularly limited, and for example, it can be fixed by an adhesive or the like.
就藉由以上的本實施方式的導電性基板的製造方法所獲得的導電性基板而言,在形成於絕緣性基材的至少一個面的金屬層上具有積層了粗化鍍層的結構。另外,就粗化鍍層而言,變為了與絕緣性基材相對的面的相反側的面為粗化面的粗化鍍層。為此,與阻劑之間的密著性較高,可抑制側蝕的發生。 The conductive substrate obtained by the method for manufacturing a conductive substrate according to the present embodiment has a structure in which a roughened plating layer is laminated on a metal layer formed on at least one surface of an insulating base material. In addition, the roughened plating layer is a roughened plating layer in which a surface on the opposite side to a surface facing the insulating base material is a roughened surface. For this reason, the adhesiveness with the resist is high, and the occurrence of side corrosion can be suppressed.
實施例 Examples
以下基於具體實施例和比較例進行說明,但本發明並不限定於該些實施例。 The following description is based on specific examples and comparative examples, but the present invention is not limited to these examples.
(評價方法) (Evaluation method)
對以下的實施例和比較例中所製作的試料採用下述方法進行了評價。 The samples produced in the following examples and comparative examples were evaluated by the following methods.
(1)粗化鍍層的成分分析 (1) Composition analysis of roughened coating
粗化鍍層的成分分析藉由X射線光電子分光裝置(PHI社製,型號:QuantaSXM)進行。需要說明的是,X射線源使用了單色化Al(1486.6eV)。 The component analysis of the roughened coating was performed by an X-ray photoelectron spectrometer (manufactured by PHI, model: QuantaSXM). It should be noted that the X-ray source used monochromatic Al (1486.6 eV).
如後所述,在以下的各實施例和比較例中,製作了具有圖1A的 結構的導電性基板。故,對圖1A中從粗化鍍層13的外部所露出的表面A進行Ar離子蝕刻,並對從最表面開始的10nm深的內部的Ni 2P光譜和Cu LMM光譜進行了測定。 As described later, in each of the following Examples and Comparative Examples, a conductive substrate having a structure of FIG. 1A was produced. Therefore, the surface A exposed from the outside of the roughened plating layer 13 in FIG. 1A was subjected to Ar ion etching, and the internal Ni 2P spectrum and Cu LMM spectrum at a depth of 10 nm from the outermost surface were measured.
由此可確認到,實施例1~實施例10和比較例1~比較例4的任意一個例子中都含有單質鎳、鎳氧化物、鎳氫氧化物、及銅。 From this, it was confirmed that elemental nickel, nickel oxide, nickel hydroxide, and copper were contained in any of Examples 1 to 10 and Comparative Examples 1 to 4.
(2)粗化鍍層所含有的結晶的形狀和尺寸 (2) the shape and size of crystals contained in the roughened coating
對作為粗化鍍層的粗化面的與絕緣性基材相對的面的相反側的面、具體而言、圖1A的表面A藉由掃描式電子顯微鏡進行了觀察,並對粗化鍍層所含有的結晶的形狀和尺寸進行了評價。 The surface opposite to the surface facing the insulating substrate, which is the roughened surface of the roughened coating layer, specifically, the surface A in FIG. 1A was observed with a scanning electron microscope. The shape and size of the crystals were evaluated.
評價時,首先在粗化鍍層的粗化面的任意位置處將觀察區域放大了50000倍。然後對該觀察區域內所存在的結晶的形狀進行了觀察。當觀察到了粒狀結晶時,在表1的結晶形狀的欄中表示為粒狀,當觀察到了針狀結晶時,在表1的結晶形狀的欄中表示為針狀。 At the time of evaluation, the observation area was enlarged 50,000 times at any position on the roughened surface of the roughened plating layer. Then, the shape of crystals present in the observation area was observed. When granular crystals are observed, they are shown as grains in the column of crystal shape in Table 1, and when needle-like crystals are observed, they are shown as needles in the column of crystal shape in Table 1.
另外,在觀察到了粒狀結晶的情況下,選擇20個作為評價對象的粒狀結晶,並對平均晶粒尺寸和標準偏差σ進行了測定和計算。需要說明的是,粒狀結晶的晶粒尺寸是指,完全包攝進行粒狀結晶的測定的粒狀結晶的最小尺寸的的圓的直徑。此外,在觀察到針狀結晶的情況下,選擇20個作為評價對象的針狀結晶,並對平均長度、平均寬度、平均縱橫比、及標準偏差σ進行了測定和計算。 In addition, when granular crystals were observed, 20 granular crystals were selected as evaluation targets, and the average crystal grain size and standard deviation σ were measured and calculated. In addition, the grain size of a granular crystal means the diameter of the circle | round | yen which fully encompasses the minimum size of the granular crystal which measured the granular crystal. In addition, when acicular crystals were observed, 20 acicular crystals were selected as evaluation objects, and the average length, average width, average aspect ratio, and standard deviation σ were measured and calculated.
在評價粒狀結晶的情況下,將其平均晶粒尺寸和標準偏差記載於表1中的「晶粒尺寸/長度」欄。 When evaluating granular crystals, the average crystal grain size and standard deviation are described in the "Crystal size / length" column in Table 1.
在評價針狀結晶的情況下,將其長度平均值和標準偏差記載於表1中的「晶粒尺寸/長度」欄,並將寬度和縱橫比的平均值分別記載於表1中的「寬度」欄和「縱橫比」欄。 In the case of evaluating needle-like crystals, the average length and standard deviation of the length are described in the "Grain Size / Length" column in Table 1, and the average values of width and aspect ratio are described in "Width" "And" Aspect Ratio "columns.
各參數已經在上面進行了說明,故這裡省略其說明。 Each parameter has been described above, so its description is omitted here.
(3)側蝕量 (3) Side erosion
首先,在以下的實施例和比較例中所獲得的導電性基板的粗化鍍層表面上藉由層壓(laminate)法貼附乾膜阻劑(日立化成RY3310)。然後,經由光掩膜進行紫外線曝光,再藉由1%的碳酸鈉水溶液對阻劑進行溶解並進行了顯影。據此,製作了在粗化鍍層上具有相互平行的複數條直線狀的圖案的阻劑的樣品。 First, a dry film resist (Hitachi Chemical Co., Ltd. RY3310) was affixed to the roughened plating surface of the conductive substrates obtained in the following Examples and Comparative Examples by a laminate method. Then, UV exposure was performed through a photomask, and the resist was dissolved and developed with a 1% sodium carbonate aqueous solution. Based on this, a sample of a resist having a plurality of linear patterns parallel to each other on the roughened plating layer was prepared.
接下來,將樣品浸漬於由10重量%的硫酸和3重量%的過氧化氫所組成的30℃的蝕刻液。 Next, the sample was immersed in an etching solution at 30 ° C. consisting of 10% by weight sulfuric acid and 3% by weight hydrogen peroxide.
針對所獲得的樣品,不剝離阻劑,並對與導電性基板的各層的積層方向平行且與阻劑的直線狀的圖案垂直的斷面進行了觀察。此情況下,如圖5所示,觀察到了在絕緣性基材51上積層有圖案化了的金屬層52、圖案化了的粗化鍍層53、及阻劑54的斷面形狀。之後,測定了阻劑的寬度方向的端部54a和圖案化了的金屬層52的寬度方向的端部52a之間的距離L,並將其作為側蝕量。 Regarding the obtained sample, the resist was not peeled off, and a cross section parallel to the lamination direction of each layer of the conductive substrate and perpendicular to the linear pattern of the resist was observed. In this case, as shown in FIG. 5, the cross-sectional shapes of the patterned metal layer 52, the patterned roughened plating layer 53, and the resist 54 were laminated on the insulating base material 51. Then, the distance L between the widthwise end portion 54a of the resist and the patterned metal layer 52 in the width direction was measured as the side etching amount.
需要說明的是,在從浸漬至蝕刻液開始的60秒後、120秒後、及180秒後的時點分別從蝕刻液中取出導電性基板並清洗後,如上所述進行了側蝕量的評價。 It should be noted that the conductive substrate was removed from the etchant at 60 seconds, 120 seconds, and 180 seconds after immersion to the etching solution, and was cleaned, and then the side etching amount was evaluated as described above. .
(試料的製作條件) (Sample production conditions)
在以下所說明的條件下製作了導電性基板,並藉由上述評價方法進行了評價。 A conductive substrate was produced under the conditions described below, and evaluated by the evaluation method described above.
〔實施例1〕 [Example 1]
製作了具有圖1A所示的結構的導電性基板。 A conductive substrate having a structure shown in FIG. 1A was produced.
(金屬層形成步驟) (Metal layer forming step)
在長度為300m,寬度為250mm,並且厚度為100μm的長條狀的聚對酞酸乙二酯樹脂(PET)製絕緣性基材的一個面上,作為金屬層進行了銅層的成膜。 A film of a copper layer was formed as a metal layer on one surface of a long insulating substrate made of polyethylene terephthalate resin (PET) having a length of 300 m, a width of 250 mm, and a thickness of 100 μm.
在金屬層形成步驟中,實施了金屬薄膜層形成步驟和金屬鍍層形成步驟。 In the metal layer forming step, a metal thin film layer forming step and a metal plating layer forming step are performed.
首先,對金屬薄膜層形成步驟進行說明。 First, a metal thin film layer forming step will be described.
在金屬薄膜層形成步驟中,作為基材使用了上述的絕緣性基材,並在絕緣性基材的一個面上作為金屬薄膜層形成了銅薄膜層。 In the metal thin film layer forming step, the aforementioned insulating base material was used as a base material, and a copper thin film layer was formed as a metal thin film layer on one surface of the insulating base material.
在金屬薄膜層形成步驟中,首先,將預先加熱至60℃並去除了水分的上述絕緣性基材設置在濺射裝置的室內。 In the metal thin film layer forming step, first, the above-mentioned insulating base material which has been heated to 60 ° C. in advance and removed moisture is set in a chamber of a sputtering apparatus.
接著,將室內排氣至1×10-3Pa之後,導入氬氣,並使室內的壓力為1.3Pa。 Next, after evacuating the room to 1 × 10 -3 Pa, argon gas was introduced and the pressure in the room was 1.3 Pa.
向預先設置在濺射裝置的陰極上的銅靶提供電力,由此在絕緣性基材的一個面上進行了厚度為0.7μm的銅薄膜層的成膜。 Power was supplied to a copper target provided in advance on the cathode of the sputtering device, thereby forming a copper thin film layer having a thickness of 0.7 μm on one surface of the insulating base material.
接下來,在金屬鍍層形成步驟中作為金屬鍍層形成了銅鍍層。就銅鍍層而言,採用電鍍法進行了銅鍍層的厚度為0.3μm的成膜。 Next, a copper plating layer was formed as the metal plating layer in the metal plating layer forming step. The copper plating layer was formed into a copper plating layer having a thickness of 0.3 μm by an electroplating method.
藉由實施以上的金屬薄膜層形成步驟和金屬鍍層形成步驟,作為金屬層形成了厚度為1.0μm的銅層。 By performing the above-mentioned metal thin film layer forming step and metal plating layer forming step, a copper layer having a thickness of 1.0 μm was formed as the metal layer.
將金屬層形成步驟中所製作的絕緣性基材上形成了厚度為1.0μm的銅層的基板浸漬在20g/L的硫酸內30sec(秒),清洗後實施了以下的粗化鍍層形成步驟。 The substrate having the copper layer having a thickness of 1.0 μm formed on the insulating base material produced in the metal layer forming step was immersed in 20 g / L of sulfuric acid for 30 sec (seconds), and the following roughened plating layer forming step was performed after cleaning.
(粗化鍍層形成步驟) (Coarse plating layer forming step)
在粗化鍍層形成步驟中,使用鍍液並採用電解鍍法在銅層的一個面上形成了粗化鍍層。 In the roughening plating layer forming step, a roughening plating layer is formed on one surface of the copper layer using a plating solution and an electrolytic plating method.
需要說明的是,作為鍍液,調製了含有鎳離子、銅離子、醯胺 硫酸、及氫氧化鈉的鍍液。鍍液中,藉由添加硫酸鎳6水合物和硫酸銅5水合物,進行了鎳離子和銅離子的供給。 In addition, as a plating solution, a plating solution containing nickel ions, copper ions, ammonium sulfuric acid, and sodium hydroxide was prepared. In the plating solution, nickel ions and copper ions were supplied by adding nickel sulfate hexahydrate and copper sulfate pentahydrate.
之後,對各成分進行了添加和調製,以使鍍液中的鎳離子的濃度為6.5g/L,銅離子的濃度為0.2g/L,並且醯胺硫酸的濃度為11g/L。 Thereafter, each component was added and prepared so that the concentration of nickel ions in the plating solution was 6.5 g / L, the concentration of copper ions was 0.2 g / L, and the concentration of ammonium sulfuric acid was 11 g / L.
此外,將氫氧化鈉水溶液添加至鍍液,並將鍍液的pH值調整為3.6。 Further, an aqueous sodium hydroxide solution was added to the plating solution, and the pH value of the plating solution was adjusted to 3.6.
在粗化鍍層形成步驟中,於鍍液的溫度為40℃,電流密度為0.08A/dm2,並且電解鍍時間為180sec的條件下進行了電解鍍,由此形成了粗化鍍層。 In the roughening plating layer forming step, electrolytic plating was performed under the conditions that the temperature of the plating solution was 40 ° C., the current density was 0.08 A / dm 2 , and the electrolytic plating time was 180 sec, thereby forming a roughening plating layer.
所形成的粗化鍍層的膜厚為111nm。 The thickness of the formed rough-plated layer was 111 nm.
對藉由以上步驟所獲得的導電性基板實施了上述的粗化鍍層的成分分析、粗化鍍層所含有的結晶的形狀和尺寸的評價、及側蝕量的評價。結果示於表1。 The conductive substrate obtained in the above steps was subjected to the component analysis of the roughened plating described above, the evaluation of the shape and size of crystals contained in the roughened plating, and the evaluation of the amount of side etching. The results are shown in Table 1.
〔實施例2~實施例10〕 [Examples 2 to 10]
各實施例中,除了對形成粗化鍍層時的鍍液中的鎳離子濃度、銅離子濃度、pH值、粗化鍍層成膜時的電流密度、及電解鍍時間如表1所示進行了變更這點之外,與實施例1同樣地製作了導電性基板,並進行了評價。結果示於表1。 In each example, in addition to the changes in the nickel ion concentration, copper ion concentration, pH value, current density at the time of film formation of the roughened layer, and electrolytic plating time in the roughened layer when forming the roughened layer were changed as shown in Table 1. Except for this point, a conductive substrate was produced in the same manner as in Example 1 and evaluated. The results are shown in Table 1.
〔比較例1~比較例4〕 [Comparative Example 1 to Comparative Example 4]
各比較例中,除了對形成粗化鍍層時的鍍液中的鎳離子濃度、銅離子濃度、pH值、粗化鍍層成膜時的電流密度、及電解鍍時間如表1所示進行了變更這點之外,與實施例1同樣地製作了導電性基板,並進行了評價。結果示於表1。 In each comparative example, in addition to the changes in the nickel ion concentration, copper ion concentration, pH value, current density at the time of film formation of the roughened layer, and electrolytic plating time in the formation of the roughened layer as shown in Table 1, Except for this point, a conductive substrate was produced in the same manner as in Example 1 and evaluated. The results are shown in Table 1.
由表1所示的結果可確認到,在實施例1~實施例10中,粗化鍍層含有粒狀或針狀的結晶。另外還確認到了,在粒狀結晶的情況下,平均晶粒尺寸為50nm以上且150nm以下,在針狀結晶的情況下,平均長度為100nm以上且300nm以下,平均寬度為30nm以上且80nm以下,並且平均縱橫比為2.0以上且4.5以下。 From the results shown in Table 1, it was confirmed that in Examples 1 to 10, the roughened plating layer contained granular or needle-like crystals. It was also confirmed that in the case of granular crystals, the average grain size is 50 nm to 150 nm, in the case of acicular crystals, the average length is 100 nm to 300 nm, and the average width is 30 nm to 80 nm. The average aspect ratio is 2.0 or more and 4.5 or less.
另一方面,在比較例1~比較例4中,盡管也確認到了粗化鍍層含有粒狀或針狀的結晶,但其尺寸不滿足上述範圍。 On the other hand, in Comparative Examples 1 to 4, although it was also confirmed that the roughened plating layer contained granular or needle-like crystals, the size thereof did not satisfy the above range.
其結果為,確認到了在實施例1~實施例10中可充分抑制側蝕量,但在比較例1~比較例4中側蝕量則較大。 As a result, it was confirmed that the amount of side erosion can be sufficiently suppressed in Examples 1 to 10, but the amount of side erosion was larger in Comparative Examples 1 to 4.
以上對導電性基板和導電性基板的製造方法藉由實施方式和實施例等進行了說明,但本發明並不限定於上述實施方式和實施例等。在申請專利範圍記載的本發明的主旨的範圍內還可進行各種各樣的變形和變更。 As mentioned above, although the conductive substrate and the manufacturing method of a conductive substrate were demonstrated using embodiment, an Example, etc., this invention is not limited to the said embodiment, an Example, etc. Various modifications and changes can be made within the scope of the gist of the present invention described in the patent application scope.
本申請主張基於2017年4月17日向日本專利廳申請的特願2017- 081580號的優先權,並將特願2017-081580號的全部內容引用於本申請。 This application claims priority based on Japanese Patent Application No. 2017-081580 filed with the Japan Patent Office on April 17, 2017, and the entire contents of Japanese Patent Application No. 2017-081580 are incorporated herein by reference.
Claims (5)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017081580 | 2017-04-17 | ||
JPJP2017-081580 | 2017-04-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201842625A true TW201842625A (en) | 2018-12-01 |
TWI765021B TWI765021B (en) | 2022-05-21 |
Family
ID=63855842
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW107112918A TWI765021B (en) | 2017-04-17 | 2018-04-16 | Conductive substrate, method for manufacturing the same |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP6954345B2 (en) |
CN (1) | CN110537393B (en) |
TW (1) | TWI765021B (en) |
WO (1) | WO2018193935A1 (en) |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52145769A (en) * | 1976-05-31 | 1977-12-05 | Nippon Mining Co | Method of surface treating printed circuit copper foil |
TW317575B (en) * | 1994-01-21 | 1997-10-11 | Olin Corp | |
JP3313277B2 (en) * | 1995-09-22 | 2002-08-12 | 古河サーキットフォイル株式会社 | Electrodeposited copper foil for fine pattern and its manufacturing method |
JP3295308B2 (en) * | 1996-06-28 | 2002-06-24 | 株式会社日鉱マテリアルズ | Electrolytic copper foil |
JP3258308B2 (en) * | 2000-02-03 | 2002-02-18 | 株式会社日鉱マテリアルズ | Copper foil excellent in laser drilling property and method for producing the same |
JP2006005149A (en) * | 2004-06-17 | 2006-01-05 | Furukawa Circuit Foil Kk | Conductive substrate and circuit board material with resistive layer |
JP2007046095A (en) * | 2005-08-09 | 2007-02-22 | Mitsubishi Shindoh Co Ltd | Copper foil, and surface treatment method therefor |
JP2007103440A (en) * | 2005-09-30 | 2007-04-19 | Mitsui Mining & Smelting Co Ltd | Wiring board and method of manufacturing the same |
WO2007145164A1 (en) * | 2006-06-12 | 2007-12-21 | Nippon Mining & Metals Co., Ltd. | Rolled copper or copper alloy foil with roughened surface and method of roughening rolled copper or copper alloy foil |
JP4973231B2 (en) * | 2006-09-05 | 2012-07-11 | 日立化成工業株式会社 | Copper etching method and wiring board and semiconductor package using this method |
KR101228168B1 (en) * | 2007-09-28 | 2013-01-30 | 제이엑스 닛코 닛세키 킨조쿠 가부시키가이샤 | Copper foil for printed circuit and copper clad laminate |
JP4978456B2 (en) * | 2007-12-19 | 2012-07-18 | 日立電線株式会社 | Copper foil for printed circuit |
WO2009154066A1 (en) * | 2008-06-17 | 2009-12-23 | 日鉱金属株式会社 | Copper foil for printed circuit board and copper clad laminate plate for printed circuit board |
MY161680A (en) * | 2010-09-27 | 2017-05-15 | Jx Nippon Mining & Metals Corp | Copper foil for printed wiring board, method for producing said copper foil, resin substrate for printed wiring board and printed wiring board |
JP5417538B1 (en) * | 2012-06-11 | 2014-02-19 | Jx日鉱日石金属株式会社 | Surface-treated copper foil, laminate using the same, printed wiring board, electronic device, and method for manufacturing printed wiring board |
JP2014152352A (en) * | 2013-02-06 | 2014-08-25 | Sh Copper Products Corp | Composite copper foil and production method thereof |
TW201400643A (en) * | 2013-08-09 | 2014-01-01 | Xin Hong Co Ltd | Pattern conductive trace structure and formation method thereof |
JP2015200025A (en) * | 2014-03-31 | 2015-11-12 | Jx日鉱日石金属株式会社 | Carrier-provided copper foil, printed wiring board, laminate sheet, electronic equipment, laminate and method of producing printed wiring board |
KR102390079B1 (en) * | 2015-04-28 | 2022-04-25 | 스미토모 긴조쿠 고잔 가부시키가이샤 | conductive substrate |
WO2017033740A1 (en) * | 2015-08-26 | 2017-03-02 | 住友金属鉱山株式会社 | Conductive substrate |
-
2018
- 2018-04-11 JP JP2019513577A patent/JP6954345B2/en active Active
- 2018-04-11 CN CN201880025236.7A patent/CN110537393B/en active Active
- 2018-04-11 WO PCT/JP2018/015248 patent/WO2018193935A1/en active Application Filing
- 2018-04-16 TW TW107112918A patent/TWI765021B/en active
Also Published As
Publication number | Publication date |
---|---|
JP6954345B2 (en) | 2021-10-27 |
JPWO2018193935A1 (en) | 2020-03-05 |
CN110537393A (en) | 2019-12-03 |
CN110537393B (en) | 2022-09-20 |
WO2018193935A1 (en) | 2018-10-25 |
TWI765021B (en) | 2022-05-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103731974B (en) | 2 layers of flexible substrate and using 2 layers of flexible substrate as the printed wiring board of base material | |
TWI406614B (en) | Printed wiring substrate and producing method thereof | |
KR101674781B1 (en) | Copper foil for printed wiring board, as well as laminate, printed wiring board, and electronic component using same | |
JP2013089910A (en) | Flexible printed board and manufacturing method of the same | |
JP2005161840A (en) | Ultra-thin copper foil with carrier and printed circuit | |
JP4955104B2 (en) | Method for forming an electronic circuit | |
JP5769030B2 (en) | Metallized resin film and method for producing the same | |
JP2001181886A (en) | Electrolytic copper foil | |
TWI568865B (en) | Layer 2 flexible wiring substrate and manufacturing method thereof, and two-layer flexible wiring board and manufacturing method thereof | |
WO2010018790A1 (en) | Multilayer laminated circuit board having multiple conduction part | |
JP6353193B2 (en) | Copper foil with carrier, method for producing a copper-clad laminate using the copper foil with carrier, method for producing a printed wiring board using the copper foil with carrier, and method for producing a printed wiring board | |
TWI791428B (en) | Manufacturing method of blackening plating solution and conductive substrate | |
TWI765021B (en) | Conductive substrate, method for manufacturing the same | |
TWI762618B (en) | conductive substrate | |
JP4294363B2 (en) | Two-layer flexible copper-clad laminate and method for producing the two-layer flexible copper-clad laminate | |
JP2011091114A (en) | Printed circuit board and method of manufacturing the same | |
JP5835670B2 (en) | Printed wiring board and manufacturing method thereof | |
WO2017130867A1 (en) | Conductive substrate | |
TWI791427B (en) | Blackening plating solution and method of manufacturing conductive substrate | |
WO2017130869A1 (en) | Blackening plating solution and method for manufacturing conductive substrate | |
JP6667982B2 (en) | Flexible wiring board | |
JP2014122414A (en) | Copper foil with carrier | |
TW201247041A (en) | Method for forming electronic circuit, electronic circuit, and copper-clad laminated board for forming electronic circuit | |
WO2010021278A1 (en) | Multilayer laminated circuit board wherein resin films having different thermal expansion coefficients are laminated | |
JP2008091596A (en) | Copper-coated polyimide substrate with smooth surface, and its manufacturing method |