TW201836116A - 半導體封裝結構及其形成方法 - Google Patents
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Abstract
一種半導體封裝結構及其形成方法。半導體封裝結構包括半導體晶粒、封膠層及電感。半導體晶粒包括主動表面、背表面與側表面。側表面在主動表面與背表面之間。封膠層覆蓋半導體晶粒的背表面與側表面。電感在封膠層中。半導體晶粒的側表面面向電感。
Description
本發明是有關於一種半導體封裝結構及其形成方法,且特別是有關於一種具有電感之半導體封裝結構及其形成方法。
半導體封裝結構一般會將含有主動元件的半導體晶粒與被動元件例如電感封裝在一起,其中係將電感配置在半導體晶粒的上方。然而,電感會佔據與半導體晶粒電性連接之重佈層可分佈的區域,使得重佈層的配置受到限制。另一方面,重佈層的配置區域也會限制電感的設計使得無法形成能提供強作用的電感。佈局上難以權衡。此外,半導體晶粒亦會受到電感的干擾影響。
本發明係有關於一種半導體封裝結構及其形成方法,可能克服先前技術的問題。
根據本揭露之一概念,提出一種半導體封裝結構,其包括一半導體晶粒、一封膠層及一電感。半導體晶粒包括一主動表面、一背表面與一側表面。側表面在主動表面與背表面之間。封膠層覆蓋半導體晶粒的背表面與側表面。電感在封膠層中。半導體晶粒的側表面面向電感。
根據本揭露之另一概念,提出一種半導體封裝結構,其包括一封膠層、一半導體晶粒、一電感及一重佈層。封膠層具有相對的一第一封膠表面與一第二封膠表面。半導體晶粒具有一主動表面並嵌在封膠層中。電感從封膠層的第一封膠表面延伸穿過封膠層至封膠層的第二封膠表面。重佈層從半導體晶粒的主動表面與封膠層的第二封膠表面沿著遠離封膠層的第一封膠表面的一方向延伸。
根據本揭露之又另一概念,提出一種半導體封裝結構的形成方法,其包括以下步驟。形成一封膠層以覆蓋一半導體晶粒。封膠層具有相對的一第一封膠表面與一第二封膠表面。形成一電感在與半導體晶粒之一側表面並置的封膠層中並從第一封膠表面延伸穿過封膠層至第二封膠表面。
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式詳細說明如下:
實施例中,電感與半導體晶粒是分別配置在封膠層之不重疊的區域中,因此電感可設計成具有較大的尺寸以提供更強的電感作用,且半導體晶粒不會受到電感的干擾。此外,重佈層是配置在與電感不同的垂直位置,因此重佈層的佈線不需要考慮電感的區域面積而能具有更大的佈局彈性。
以下係以一些實施例做說明。須注意的是,本揭露並非顯示出所有可能的實施例,未於本揭露提出的其他實施態樣也可能可以應用。再者,圖式上的尺寸比例並非按照實際產品等比例繪製。因此,說明書和圖示內容僅作敘述實施例之用,而非作為限縮本揭露保護範圍之用。另外,實施例中之敘述,例如細部結構、製程步驟和材料應用等等,僅為舉例說明之用,並非對本揭露欲保護之範圍做限縮。實施例之步驟和結構各之細節可在不脫離本揭露之精神和範圍內根據實際應用製程之需要而加以變化與修飾。以下是以相同/類似的符號表示相同/類似的元件做說明。
第1圖繪示根據一實施例之半導體封裝結構的剖面示意圖。半導體封裝結構可包括半導體晶粒102、封膠層104、電感106與重佈層(redistribution layer; RDL)108。半導體晶粒102具有相對的主動表面110A與背表面110B,及在主動表面110A與背表面110B之間的側表面110S。主動表面110A可具有接觸墊112於其上或其中。封膠層104覆蓋半導體晶粒102的背表面110B與側表面110S。
實施例中,半導體晶粒102與電感106是分別配置在封膠層104不重疊的區域中。如第1圖所示,電感106設置在半導體晶粒102之側表面110S側的封膠層104中。因此半導體晶粒102並不會受到電感106的干擾影響。此外,電感106能設計成造成較強電感作用的佈置。舉例來說,一實施例中,電感106的厚度大於半導體晶粒102的厚度。半導體晶粒102的厚度可由主動表面110A與背表面110B之間的間距定義。一實施例中,電感106的厚度可等於封膠層104的厚度。舉例來說,封膠層104的厚度可由封膠層104之相對的第一封膠表面114與第二封膠表面116之間的距離定義。電感106可延伸在封膠層104的第一封膠表面114與第二封膠表面116之間。
實施例中,電感106能根據半導體晶粒102配置成任意的圖案。舉例來說,請參照第2圖所繪示根據一實施例之在封膠層104中的半導體晶粒102與電感106的俯視圖,其中電感106具有圍繞半導體晶粒102的螺紋圖案。第3圖所繪示根據另一實施例之在封膠層104中的半導體晶粒102與電感106的俯視圖,其中電感106是完全設置在半導體晶粒102的外側。其他實施例中,電感106的數目、配置區域與形狀可視實際需求任意變化。舉例來說,電感106可具有圓形迴紋圖案、橢圓形迴紋圖案、方形迴紋圖案、六邊形迴紋圖案、不規則形迴紋圖案、或其它圖案。
請參照第1圖,重佈層108可配置在半導體晶粒102的主動表面110A與封膠層104的第二封膠表面116上的絕緣層118中。重佈層108可電性連接半導體晶粒102的接觸墊112。重佈層108可電性連接電感106。舉例來說,半導體晶粒102可利用重佈層108電性連接至電感106及形成在半導體晶粒102之主動表面110A的其他元件例如主動元件,並能透過重佈層108在絕緣層118之上表面119露出部分形成的接觸端點與外部裝置電性連接。
如第1圖所示,重佈層108與電感106是分別位在封膠層104之第二封膠表面116的上、下方,因此重佈層108的配置並不需要考慮電感106。重佈層108可具有更大的佈局彈性。一實施例中,舉例來說,重佈層108的佈局區域與電感106的區域重疊。在一實施例中,重佈層108的佈局區域大於半導體晶粒102的區域,是以重佈層108呈扇開方式(fan-out)配置。
一實施例中,重佈層108的接觸端點上可視實際需求配置焊料120,例如焊球。
根據一實施例之半導體封裝結構的製造流程可利用第4圖至第8圖與第1圖說明。
請參照第4圖,可利用黏著層222將半導體晶粒102以主動表面110A朝向載體224的方向設置在載體224上。
一實施例中,舉例來說,半導體晶粒102係為一晶圓作為半導體基底經過半導體積體電路製程在其前表面上形成各種積體電路元件後,最後經切割製程所定義出的晶粒。換句話說,半導體晶粒102的側表面110S可為晶圓之切割道經切割後所形成的切割表面。根據實施例之半導體晶粒102亦可稱作半導體積體電路晶粒。一實施例中,舉例來說,半導體晶粒102可包括邏輯(logic)積體電路晶粒、電源(power)積體電路晶粒等等。
以第5圖所示之半導體晶粒102的剖面示意圖為例,可利用積體電路製程在半導體基底226其相對於背表面110B的基底前表面228形成主動元件230例如含有源極S、汲極D及閘極G的金屬氧化半導體(MOS)元件,並形成穿過介電層232的內連接件234電性連接主動元件230與被介電層232外露的接觸墊112。內連接件234可包括接觸通孔(contact via)、形成在介電層232之各層間介電膜上的導線、或接觸插塞(contact plug)等等。最後,晶圓切割後定義出半導體晶粒102。
請參照第6圖,形成封膠層104以覆蓋半導體晶粒102的背表面110B與側表面110S,並可覆蓋載體224。舉例來說,封膠層104可包括環氧樹脂、聚醯亞胺(Polyimide; PI)、酚醛樹脂(phenolic)、矽膠(silicone)、或上述之組合。
請參照第7圖,移除封膠層104在半導體晶粒102之側表面110S側的一部分,以形成貫穿開口236。舉例來說,可利用雷射方式從第一封膠表面114移除封膠層104直到露出載體224。
請參照第8圖,然後,移除載體224。可利用無電鍍製程形成導電層238填充貫穿開口236以形成電感106。本揭露不限於此。其他實施例中,可使用其他合適的方法形成導電層238在貫穿開口236中。也可在形成導電層238之後移除載體224。導電層238可例如包括銅或其他合適的導電材料。
請參照第8圖,形成重佈層108。重佈層108可從半導體晶粒102的主動表面110A與電感106延伸在封膠層104的第二封膠表面116上。重佈層108可從半導體晶粒102的主動表面110A、電感106及封膠層104的第二封膠表面116穿過絕緣層118並分佈在絕緣層118的上表面119。重佈層108在絕緣層118之上表面119露出部分可形成接觸端點,提供與外部裝置電性接觸。
請參照第1圖,一實施例中,重佈層108的接觸端點上可視實際需求配置焊料120,例如焊球,或其它合適的端點結構。
根據以上,實施例中,電感與半導體晶粒是分別配置在封膠層之不重疊的區域中,因此電感可設計成具有較大的尺寸以提供更強的電感作用,且半導體晶粒不會受到電感的干擾。此外,重佈層是配置在與電感不同的垂直位置,因此重佈層能以更大的彈性佈局。
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
102‧‧‧半導體晶粒
104‧‧‧封膠層
106‧‧‧電感
108‧‧‧重佈層
110A‧‧‧主動表面
110B‧‧‧背表面
110S‧‧‧側表面
112‧‧‧接觸墊
114‧‧‧第一封膠表面
116‧‧‧第二封膠表面
118‧‧‧絕緣層
119‧‧‧上表面
120‧‧‧焊料
222‧‧‧黏著層
224‧‧‧載體
226‧‧‧半導體基底
228‧‧‧前表面
230‧‧‧主動元件
232‧‧‧介電層
234‧‧‧內連接件
236‧‧‧貫穿開口
238‧‧‧導電層
D‧‧‧汲極
G‧‧‧閘極
S‧‧‧源極
第1圖繪示根據一實施例之半導體封裝結構的剖面示意圖。 第2圖所繪示根據一實施例之封膠層、半導體晶粒與電感的俯視圖。 第3圖繪示根據另一實施例之封膠層、半導體晶粒與電感的俯視圖。 第4圖至第8圖繪示根據一實施例之半導體封裝結構的製造方法。
Claims (20)
- 一種半導體封裝結構,包括: 一半導體晶粒,包括一主動表面、一背表面與一側表面,該側表面在該主動表面與該背表面之間; 一封膠層,覆蓋該半導體晶粒的該背表面與該側表面;及 一電感,在該封膠層中,其中該半導體晶粒的該側表面面向該電感。
- 如申請專利範圍第1項所述之半導體封裝結構,其中該半導體晶粒的該側表面係該半導體晶粒的一外側表面。
- 如申請專利範圍第1項所述之半導體封裝結構,其中該電感鄰接該封膠層。
- 如申請專利範圍第1項所述之半導體封裝結構,其中該半導體晶粒的該主動表面具有一接觸墊於其上或其中。
- 如申請專利範圍第1項所述之半導體封裝結構,其中該電感的一厚度是大於該半導體晶粒之該主動表面與該背表面之間的一間距。
- 如申請專利範圍第1項所述之半導體封裝結構,其中該電感的厚度是等於該封膠層的厚度。
- 如申請專利範圍第1項所述之半導體封裝結構,更包括一重佈層(redistribution layer; RDL),在該半導體晶粒的該主動表面上。
- 如申請專利範圍第1項所述之半導體封裝結構,其中鄰接該電感的該封膠層是同時鄰接該半導體晶粒的該側表面與該背表面。
- 如申請專利範圍第1項所述之半導體封裝結構,其中該電感與該半導體晶粒互不重疊。
- 如申請專利範圍第1項所述之半導體封裝結構,更包括一重佈層,在該半導體晶粒的該主動表面上,其中該半導體晶粒的該主動表面具有一接觸墊於其上或其中,該電感藉由該重佈層與該接觸墊電性連接至該半導體晶粒。
- 一種半導體封裝結構,包括: 一封膠層,具有相對的一第一封膠表面與一第二封膠表面; 一半導體晶粒,具有一主動表面並嵌在該封膠層中; 一電感,從該封膠層的該第一封膠表面延伸穿過該封膠層至該封膠層的該第二封膠表面;及 一重佈層,從該半導體晶粒的該主動表面與該封膠層的該第二封膠表面沿著遠離該封膠層的該第一封膠表面的一方向延伸。
- 如申請專利範圍第11項所述之半導體封裝結構,其中該第一封膠表面是該封膠層之一上表面與一下表面其中之一,該第二封膠表面是該封膠層之該上表面與該下表面其中之另一。
- 如申請專利範圍第11項所述之半導體封裝結構,其中該電感是延伸穿過在該半導體晶粒之一側表面上的該封膠層並延伸超過該半導體晶粒的一背表面,該半導體晶粒的該側表面是在該背表面與該主動表面之間。
- 一種半導體封裝結構的形成方法,包括: 形成一封膠層以覆蓋一半導體晶粒,其中該封膠層具有相對的一第一封膠表面與一第二封膠表面;及 形成一電感在與該半導體晶粒之一側表面並置的該封膠層中並從該第一封膠表面延伸穿過該封膠層至該第二封膠表面。
- 如申請專利範圍第14項所述之半導體封裝結構的形成方法,其中該電感的形成方法包括: 移除該封膠層在該半導體晶粒之該側表面上的一部分以形成從該第一封膠表面延伸穿過該封膠層至該第二封膠表面的一貫穿開口;及 以一導電層填充該貫穿開口。
- 如申請專利範圍第14項所述之半導體封裝結構的形成方法,更包括形成一重佈層在該半導體晶粒的一主動表面與該封膠層的該第二封膠表面上。
- 如申請專利範圍第14項所述之半導體封裝結構的形成方法,更包括: 設置該半導體晶粒在一載體上; 形成一貫穿開口穿過該封膠層並露出該載體;及 在形成該貫穿開口之後,移除該載體。
- 如申請專利範圍第17項所述之半導體封裝結構的形成方法,其中該半導體晶粒具有一主動表面面向該載體。
- 如申請專利範圍第17項所述之半導體封裝結構的形成方法,包括以一導電層填充該貫穿開口以形成該電感。
- 如申請專利範圍第14項所述之半導體封裝結構的形成方法,更包括在形成該電感之後形成一重佈層。
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