TW201832318A - 形成具有淺溝槽隔離（ｓｔｉ）區之積體電路的方法及所產生的ｉｃ結構 - Google Patents

形成具有淺溝槽隔離（ｓｔｉ）區之積體電路的方法及所產生的ｉｃ結構 Download PDF

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TW201832318A
TW201832318A TW106128588A TW106128588A TW201832318A TW 201832318 A TW201832318 A TW 201832318A TW 106128588 A TW106128588 A TW 106128588A TW 106128588 A TW106128588 A TW 106128588A TW 201832318 A TW201832318 A TW 201832318A
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layer
semiconductor
sidewall spacers
trenches
forming
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TW106128588A
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TWI681503B (zh
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安東尼Ｋ 史塔佩爾
史蒂芬Ｍ 宣克
西瓦Ｐ 阿度蘇米利
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美商格芯（美國）集成電路科技有限公司
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Abstract

揭示一種積體電路(IC)形成方法，其中，在一半導體層內形成數個溝槽以界定(數個)半導體台面。該方法初始只在該等溝槽內形成側壁間隔體於該(等)半導體台面的暴露側壁上，而不是立即用隔離材料填滿該等溝槽以及執行平坦化製程以在裝置形成前完成該等STI區。在該等側壁間隔體形成後，使用該(等)半導體台面形成(數個)裝置(例如，場效電晶體、矽電阻器等等)，且視需要，在相鄰半導體台面之間的溝槽內可形成(數個)附加裝置(例如，多晶矽電阻器)。隨後，沉積中段(MOL)介電質(例如，共形蝕刻停止層及毯覆層間介電質(ILD)層)於該(等)裝置上方，藉此填滿在該等溝槽內的任何殘留空間且完成該等STI區。也揭示一種使用該方法所形成的IC結構。

Description

形成具有淺溝槽隔離(STI)區之積體電路的方法及所產生的IC結構
本發明係有關於積體電路(IC)，且更特別的是，有關於形成具有淺溝槽隔離(STI)區之積體電路(IC)結構的改良方法及所產生的IC結構。
具體而言，在使用絕緣體上覆半導體晶圓(例如，絕緣體上覆矽(SOI)晶圓)的習知積體電路(IC)加工中，藉由形成淺溝槽隔離(STI)區來界定用於裝置區的半導體台面。具體言之，此類加工以包括半導體基板(例如，矽基板)、在半導體基板上之絕緣體層(例如，埋藏氧化物(BOX)層)及在絕緣體層上之半導體層(例如，矽層)的絕緣體上覆半導體晶圓開始。微影圖案化及蝕刻該半導體層以形成數個溝槽，該等溝槽垂直或幾乎垂直地延伸穿過半導體層到絕緣體層或進入絕緣體層且側向包圍用於在半導體層內之裝置區的半導體台面。然後，沉積隔離材料(例如，氧化矽)以填滿該等溝槽，且執行平坦化製程(例如，化學 機械研磨(CMP)製程)以便從半導體台面的頂面移除隔離材料，藉此形成STI區。半導體裝置(例如，場效電晶體(FET)、雙極型接面電晶體(BJT)、二極體等等)隨後形成於該等半導體台面中，以及該等STI區提供電氣隔離。可惜，包括形成此種STI的IC加工可能成本高又耗時。因此，本技藝亟須一種形成具有淺溝槽隔離(STI)區之積體電路(IC)結構的改良方法。
鑑於上述，揭示於本文的是形成具有側壁間隔體及中段(MOL)含介電質淺溝槽隔離(STI)區之積體電路(IC)結構的方法之具體實施例。具體言之，在該方法中，在半導體層內可形成溝槽以界定至少一半導體台面。該方法初始只在該等溝槽內形成側壁間隔體於該(等)半導體台面的暴露側壁上，而不是立即用隔離材料填滿該等溝槽以及執行平坦化製程(例如，化學機械研磨(CMP)製程)以在裝置形成前完成該等STI區。在該等側壁間隔體形成後，可使用該(等)半導體台面形成(數個)裝置(例如，場效電晶體、雙極型接面電晶體、異質接面雙極電晶體、電容器、電阻器等等)，且視需要，可在相鄰半導體台面之間的溝槽內形成(數個)附加裝置(例如，電阻器)。隨後，可沉積中段(MOL)介電質(例如，共形蝕刻停止層及毯覆層間介電質(ILD)層)於該等裝置上方且於在該等溝槽內的任何殘留空間中，藉此完成該等STI區。本文也揭示使用上述方法所形成的IC結構之具體實施例。
一般而言，揭示於本文的是形成具有側壁間隔體及中段(MOL)含介電質淺溝槽隔離(STI)區之積體電路(IC)結構的方法之具體實施例。該方法包括在一半導體層中形成數個溝槽以界定至少一半導體台面，其具有數個第一側壁。第一側壁間隔體可形成於該等溝槽內以便側向鄰接該半導體台面的該等第一側壁。在該等第一側壁間隔體形成後，但是在該等溝槽被完全填滿前，可使用該半導體台面形成一半導體裝置(例如，場效電晶體(FET)、電阻器等等)。在該半導體裝置完成後，至少一中段(MOL)介電層(例如，毯覆層間介電質(ILD)層)可沉積於該半導體裝置上方且於在該等溝槽內的任何殘留空間中。應注意，該等第一側壁間隔體與該毯覆ILD層可由不同的介電質材料製成。
更特別的是，揭示於本文之方法的一具體實施例可包括：提供一絕緣體上覆半導體晶圓，其包括基板、在該基板上的絕緣體層，以及在該絕緣體層上的半導體層。在該半導體層中可形成數個溝槽以在該絕緣體層上界定有數個第一側壁的多個半導體台面。第一側壁間隔體可形成於該等溝槽內以便側向鄰接該等半導體台面的第一側壁。在該等第一側壁間隔體形成後，但是在該等溝槽被完全填滿前，可使用該等半導體台面形成各種不同類型的半導體裝置(例如，一或更多FET、一或更多電阻器等等)。視需要，在形成該等半導體裝置於該等半導體台面內時，在該等溝槽中之任一內可形成(數個)附加裝置(例如，電阻 器)以便側向位於相鄰半導體台面之間。在該等半導體裝置及視需要附加裝置完成後，可沉積一或更多中段(MOL)介電層(例如，共形蝕刻停止層，接著是毯覆層間介電質(ILD)層)於該等半導體裝置及任何附加裝置上方且於在該等溝槽內的任何殘留空間中。該等第一側壁間隔體與該毯覆ILD層再度可由不同的介電質材料製成。
本文也揭示根據上述方法所形成的積體電路(IC)結構之具體實施例以便具有側壁間隔體及中段(MOL)含介電質淺溝槽隔離(STI)區。一般而言，揭示於本文的IC結構可具有垂直延伸穿過一半導體層的數個溝槽。這些溝槽可界定至少一半導體台面。第一側壁間隔體可在該等溝槽內側向鄰接該(等)半導體台面的第一側壁。該IC結構更可包括使用該至少一半導體台面形成的至少一半導體裝置(例如，場效電晶體、電阻器等等)。例如，該IC結構可包括類型相同或不同的多個半導體裝置，其中各半導體裝置整個或部份包含在半導體台面中。視需要，該IC結構也可包括側向位於相鄰半導體台面之間的該等溝槽中之任一內的(數個)附加裝置(例如，電阻器)。另外，至少一中段介電層(例如，毯覆層間介電質(ILD)層)可在該(等)半導體裝置及附加裝置上方且在該等溝槽內的任何殘留空間中。如以上方法所述，該等第一側壁間隔體與該毯覆ILD層可由不同的介電質材料製成。
10、12、14、16、18‧‧‧步驟
20、22、24、26、28‧‧‧步驟
30、32‧‧‧步驟
100‧‧‧積體電路(IC)結構
101‧‧‧絕緣體上覆半導體晶圓、晶圓
102‧‧‧基板
103‧‧‧絕緣體層
104‧‧‧半導體層
105‧‧‧犧性介電層
106a‧‧‧半導體台面、第一半導體台面
106b‧‧‧半導體台面、第二半導體台面
106c‧‧‧半導體台面、第三半導體台面
107‧‧‧共形氧化物層、二氧化矽層、氧化矽襯裡
108‧‧‧第一側壁間隔體
110a‧‧‧半導體裝置、第一FET
110b‧‧‧半導體裝置、第二FET
110c‧‧‧半導體裝置、第一電阻器
111‧‧‧第二電阻器、多晶矽電阻器、附加裝置、 電阻器
116‧‧‧第一側壁、側壁
120‧‧‧閘極
121‧‧‧閘極介電層、介電質
122‧‧‧閘極導體層、導體
123‧‧‧第一部份
124‧‧‧第二部份
132‧‧‧第二側壁間隔體
133‧‧‧第三側壁間隔體
136‧‧‧第二側壁
140‧‧‧共形保護層
145‧‧‧自對準矽化物層
150‧‧‧共形蝕刻停止層
160‧‧‧毯覆層間介電質(ILD)層、ILD層
181‧‧‧通道區
182‧‧‧源極/汲極區
1911-1914‧‧‧溝槽
由以下參考附圖的詳細說明可更加了解本 發明，附圖不一定是按比例繪製。
第1圖的流程圖圖示形成具有側壁間隔體及中段(MOL)含介電質淺溝槽隔離(STI)區之積體電路(IC)結構的方法之具體實施例；第2圖的橫截面圖圖示根據第1圖之流程圖形成的部份完成結構；第3圖的橫截面圖圖示根據第1圖之流程圖形成的部份完成結構；第4圖的橫截面圖圖示根據第1圖之流程圖形成的部份完成結構；第5圖的橫截面圖圖示根據第1圖之流程圖形成的部份完成結構；第6圖的橫截面圖圖示根據第1圖之流程圖形成的部份完成結構；第7A圖及第7B圖的替代橫截面圖圖示根據第1圖之流程圖形成的部份完成結構；第8圖的橫截面圖圖示根據第1圖之流程圖形成的部份完成結構；第9圖的橫截面圖圖示根據第1圖之流程圖形成的部份完成結構；第10圖的橫截面圖圖示根據第1圖之流程圖形成的部份完成結構；第11圖的橫截面圖圖示根據第1圖之流程圖形成的部份完成結構； 第12圖的橫截面圖圖示根據第1圖之流程圖形成的部份完成結構；以及第13圖的橫截面圖圖示根據第1圖之流程圖形成的部份完成結構。
如上述，在使用絕緣體上覆半導體晶圓(例如，絕緣體上覆矽(SOI)晶圓)的習知積體電路(IC)加工中，藉由形成淺溝槽隔離(STI)區來界定用於裝置區的半導體台面。具體言之，此類加工以包括半導體基板(例如，矽基板)、在半導體基板上之絕緣體層(例如，埋藏氧化物(BOX)層)及在絕緣體層上之半導體層(例如，矽層)的絕緣體上覆半導體晶圓開始。微影圖案化及蝕刻該半導體層以形成數個溝槽，該等溝槽垂直或幾乎垂直地延伸穿過半導體層到絕緣體層或進入絕緣體層且側向包圍用於在半導體層內之裝置區的半導體台面。然後，沉積隔離材料(例如，氧化矽)以填滿該等溝槽，且執行平坦化製程(例如，化學機械研磨(CMP)製程)以便從半導體台面的頂面移除隔離材料，藉此形成STI區。半導體裝置(例如，場效電晶體(FET)、雙極型接面電晶體(BJT)、二極體等等)隨後形成於半導體台面中，以及該等STI區提供電氣隔離。可惜，包括形成此種STI的IC加工可能成本高又耗時。
鑑於上述，揭示於本文的是形成具有側壁間隔體及中段(MOL)含介電質淺溝槽隔離(STI)區之積體電路(IC)結構的方法之具體實施例。具體言之，在該方法 中，在半導體層內可形成溝槽以在絕緣體層上界定至少一半導體台面。該方法初始只在該等溝槽內形成側壁間隔體於該(等)半導體台面的暴露側壁上，而不是立即用隔離材料填滿該等溝槽以及執行平坦化製程(例如，化學機械研磨(CMP)製程)以在裝置形成前完成該等STI區。在該等側壁間隔體形成後，可使用該(等)半導體台面形成(數個)裝置(例如，場效電晶體、雙極型接面電晶體、異質接面雙極電晶體、電容器、電阻器等等)，且視需要，可在相鄰半導體台面之間的溝槽內形成(數個)附加裝置(例如，電阻器)。隨後，可沉積中段(MOL)介電質(例如，共形蝕刻停止層及毯覆層間介電質(ILD)層)於該等裝置上方且沉積於該等溝槽內的任何殘留空間中，藉此完成該等STI區。本文也揭示使用上述方法所形成的IC結構之具體實施例。
更特別的是，請參考第1圖的流程圖，揭示於本文的是形成具有側壁間隔體及中段(MOL)含介電質淺溝槽隔離(STI)區之積體電路(IC)結構的方法之具體實施例。該方法以絕緣體上覆半導體晶圓101(例如，絕緣體上覆矽(SOI)晶圓或任何其他合適的絕緣體上覆半導體晶圓)開始(步驟10，參考第2圖)。此一晶圓101可包括基板102(例如，矽基板或任何其他合適基板，包括但不限於：石英玻璃基板或碳化矽(SiC)基板)、在基板102上的絕緣體層103(例如，埋藏氧化物(BOX)層或其他合適絕緣體層)、以及在絕緣體層103上的半導體層104(例如，矽層或任何其他合適的單晶或多晶半導體層)。熟諳此藝者會認識 到各種層在晶圓101中的必要厚度可取決於應用而有所不同。例如，就射頻(RF)應用而言，半導體層104的厚度可在50至150奈米之間；然而，就習知互補金屬氧化物半導體(CMOS)應用而言，半導體層104的厚度可在10至100奈米之間。在任何情形下，在任何額外加工之前，可清洗晶圓101，且視需要，在半導體層104頂面上相對薄的犧牲介電層105。犧牲介電層105可包括，例如，一或更多層的二氧化矽(SiO2)或氮化矽(SiN)。犧牲介電層105可用例如熱氧化及/或化學氣相沉積(CVD)形成以便有5至50奈米的厚度。
可形成實質垂直穿過犧牲介電層105及半導體層104至少到絕緣體層103的溝槽1911-1914(步驟12，參考第3圖)。具體言之，使用習知微影圖案化及蝕刻製程可形成此類溝槽1911-1914以便在絕緣體層103上界定一或更多半導體台面106a-106c。如圖示，溝槽1911-1914的蝕刻可在絕緣體層103的頂面停止，或可延伸進入絕緣體層103的一些深度而不暴露基板102的頂面。為了本揭示內容的目的，半導體台面(在此也被稱為半導體主體)為半導體材料的一離散區(discrete area)，其係由半導體層圖案化而成且可用來形成一或更多半導體裝置。這些半導體裝置可包括主動裝置(例如，場效電晶體(FET)、雙極型接面電晶體(BJT)、異質接面雙極電晶體(HBT)等等)及/或被動裝置(例如，電阻器、電容器、二極體等等)。為了圖解說明，第3圖圖示由溝槽1911-1914界定的3個半導體台 面(亦即，第一半導體台面106a、第二半導體台面106b及第三半導體台面106c)；不過，應瞭解，第3圖非旨在限制且可執行步驟12以便界定任何數目的一或更多半導體台面。在任何情形下，各半導體台面106a-106c可具有由溝槽1911-1914界定的第一側壁116(亦即，垂直面)。
視需要，可形成相對薄的共形氧化物層107以便覆蓋及緊鄰各半導體台面106a-106c的頂面及第一側壁且進一步以便覆蓋及緊鄰在溝槽1911-1914內之絕緣體層103的暴露部份(步驟14，參考第4圖)。例如，可形成相對薄的二氧化矽層107(例如，5至15奈米氧化物層)(例如，用化學氣相沉積(CVD))於半導體台面及絕緣體層103上方。另外或替換地，可形成熱氧化物層(例如，用熱氧化)於半導體台面106a-106c的暴露側壁上。
接下來，在溝槽1911-1914內可形成第一側壁間隔體108以便側向鄰接各半導體台面的第一側壁116，特別是，以便側向包圍各半導體台面以及以利從絕緣體層103到半導體台面的頂面保護及覆蓋各半導體台面的第一側壁116(亦即，垂直面)(步驟16，參考第5圖)。
更特別的是，可沉積側壁間隔體材料共形層(例如，用化學氣相沉積(CVD))以便覆蓋各半導體台面106a-106c的頂面及第一側壁116，且以利於覆蓋在溝槽1911-1914內之絕緣體層103的暴露部份。此側壁間隔體材料，例如，可為氮化矽、氮氧化矽、碳氧化矽(silicon oxycarbide)、鋁土、或任何其他合適的介電質材料，它與 絕緣體層103的介電質材料及共形氧化物層107(若有的話)的介電質材料不同。側壁間隔體材料共形層的厚度，例如，可在20至100奈米之間。在沉積側壁間隔體材料後，可執行選擇性非等向性蝕刻製程以便從水平面移除側壁間隔體材料，留下在垂直面上的側壁間隔體材料。亦即，相較於在與絕緣體層頂面平行的方向，側壁間隔體材料在與絕緣體層103頂面垂直之方向的蝕刻速率可明顯快些。另外，對於絕緣體層103的絕緣體材料、共形氧化物層107(若有的話)的介電質材料及半導體台面106a-106c的半導體材料，可選擇性地蝕刻側壁間隔體材料(亦即，以明顯較快的速率蝕刻)，藉此形成在溝槽1911-1914內且側向鄰接半導體台面106a-106c之第一側壁116的第一側壁間隔體108，如圖示。或者，選擇性非等向性蝕刻製程可進一步蝕刻穿過共形氧化物層107(若有的話)，且視需要，部份進入絕緣體層103。在任何情形下，此選擇性非等向性蝕刻製程應在暴露基板102的頂面之前停止。例如氮化矽、氮氧化矽、碳氧化矽等等之介電質材料的選擇性非等向性蝕刻製程為本技藝所習知。因此，本專利說明書省略此類製程的細節讓讀者聚焦在所揭示之方法的最重要方面。
應瞭解，第一側壁間隔體108的寬度取決於第一間隔體材料之共形層的厚度與在與絕緣體層103頂面平行之方向的蝕刻速率。更應瞭解，如果在步驟14形成共形氧化物層107(及/或熱氧化物層)，則用共形氧化物層107(如圖示)及/或熱氧化物層的垂直部份，使第一側壁間 隔體108與第一側壁116實體分離。不過，如果在步驟14既不形成共形氧化物層107也不形成熱氧化物層，則第一側壁間隔體108會緊鄰第一側壁116。
在第一側壁間隔體108形成後，但是在溝槽1911-1914填滿隔離材料以形成淺溝槽隔離(STI)區於其中之前，可使用一或更多半導體台面106a-106c來形成一或更多半導體裝置110a-110c(步驟18)。具體言之，該(等)半導體台面106a-106c可用來形成一或更多主動裝置(例如，場效電晶體(FET)、雙極型接面電晶體(BJT)、異質接面雙極電晶體(HBT)等等)及/或一或更多被動裝置(例如，電阻器、電容器、二極體等等)。視需要，在使用半導體台面形成半導體裝置的此步驟18期間，在溝槽1911-1914中之至少一者內可形成至少一附加裝置(例如，電阻器、電感器等等)以便側向位於兩個相鄰半導體台面之間。
為了圖解說明，以下使用示範子步驟(sub-process)20-28更詳細地描述步驟18以形成下列半導體裝置：以第一方向定向且使用第一半導體台面106a形成的第一FET 110a；以與第一方向垂直之第二方向定向且使用第二半導體台面106b形成的第二FET 110b；使用第三半導體台面106c形成的第一電阻器110c(例如，矽電阻器)，以及在側向位於第二半導體台面106b、第三半導體台面106c之間的溝槽1913中形成的附加裝置(例如，第二電阻器111，特別是，多晶矽電阻器)。
為了在步驟18使用該(等)半導體台面來形 成半導體裝置，且視需要，形成在相鄰半導體台面之間的附加裝置，可首先清洗該(等)半導體台面的頂面。具體言之，暴露該(等)半導體台面的頂面係藉由例如使用濕及乾蝕刻化學劑(例如水性或蒸氣氫氟酸(HF))的組合來蝕刻去掉任何介電質材料。接下來，在該(等)半導體台面106a-c上方形成多層堆疊(步驟20)。具體言之，可形成在該(等)半導體台面上方的閘極介電層121。閘極介電層121可由一或更多層的任何合適的閘極介電質材料製成，包括但不限於：二氧化矽(SiO2)或高K介電質材料。在一具體實施例中，該閘極介電層可為氧化物層。例如，藉由沉積共形氧化物層於該(等)半導體台面上方(例如，使用化學氣相沉積(CVD)製程、原子層沉積(ALD)或任何其他合適沉積製程)，可形成此一氧化物層，如第6圖所示。或者，藉由熱氧化半導體台面的頂面，可形成此一氧化物層。接下來，閘極導體層122可形成於閘極介電層121上。閘極導體層122可由一或更多層的合適閘極導體材料製成，包括但不限於：多晶矽或金屬。在一具體實施例中，閘極導體層122可為多晶矽層。此一多晶矽層可為共形多晶矽層，如第7A圖所示。例如，使用例如快速熱CVD或液相CVD的CVD製程，可形成此一共形多晶矽層。或者，該多晶矽層可為非共形多晶矽層，如第7B圖所示。例如，使用高密度電漿CVD製程，可形成此一非共形多晶矽層。在任何情形下，閘極導體層122可形成於該(等)半導體台面106a-106c上方且於溝槽1911-1914內，藉此形成多層堆疊。
應注意，可形成該多層堆疊使得該堆疊在溝槽1911-1914內的部份大約與半導體台面106a-c有相同的高度(例如，從絕緣體層103的頂面測量)(如圖示)、較少的高度或較大的高度。更應注意，視需要，可研磨該多層堆疊(例如，使用CMP製程)以減少堆疊在半導體台面106a-c以上的高度(例如，藉由減少最下面、中間及頂部矽層的頂面高度來實現所欲閘極高度及/或改善後續接觸微影焦深)。
在任何情形下，隨後可微影圖案化及蝕刻該多層堆疊以形成帶圖案的介電質121-導體122形狀(例如，帶圖案的多晶矽-氧化矽形狀)(步驟22，參考第8圖)。具體言之，在步驟22可微影圖案化及蝕刻該堆疊，使得所產生的帶圖案形狀形成下列各物中之任一或更多：在半導體台面上用於FET的閘極(例如，參考在第一半導體台面106a頂面上用於第一FET 110a以及在第二半導體台面106b頂面上用於第二FET 110b的閘極)；用於某些其他類型之半導體裝置(例如，MOS電容器)的閘極(未圖示)；以及在溝槽中側向位於相鄰半導體台面之間的附加裝置，例如電阻器(例如，參考第二電阻器111，特別是，在溝槽1913中的多晶矽電阻器)。
該方法更可包括：形成附加側壁間隔體於所有實質垂直面上(步驟24，參考第9圖)。具體言之，可沉積(例如，用化學氣相沉積(CVD))附加側壁間隔體材料共形層於部份完成的IC結構上方。此附加側壁間隔體材料， 例如，可為氧化矽、氮氧化矽、碳氧化矽或任何其他合適介電質材料中之任一或更多。因此，該附加側壁間隔體材料可為與使用於第一側壁間隔體108者相同的介電質材料或不同的介電質材料。在任何情形下，附加側壁間隔體材料共形層的厚度，例如，可在50至100奈米之間。在沉積該附加側壁間隔體材料後，可執行選擇性非等向性蝕刻製程以便從水平面移除該附加側壁間隔體材料，留下在垂直面上的附加側壁間隔體材料。亦即，相較於在與絕緣體層103頂面平行的方向，該附加側壁間隔體材料在與絕緣體層103頂面垂直之方向的蝕刻速率可明顯快些。另外，對於絕緣體層103的絕緣體材料、共形氧化物層107(若有的話)的介電質材料、半導體台面106a-106c的半導體材料以及在步驟22形成之任何帶圖案形狀的多晶矽材料(例如，閘極120及第二電阻器111)，可選擇性地蝕刻該附加側壁間隔體材料(亦即，以明顯較快的速率蝕刻)。結果，此選擇性非等向性蝕刻製程會實質同時地形成側向緊鄰在步驟22形成之各種帶圖案形狀之第二側壁136的第二側壁間隔體132(例如，參考在閘極120上和在第二電阻器111上的第二側壁間隔體132)以及在溝槽1911-1914內側向緊鄰第一側壁間隔體108(例如，在第一側壁116對面)的第三側壁間隔體133。如上述，例如氮化矽、氮氧化矽、碳氧化矽等等之介電質材料的選擇性非等向性蝕刻製程為本技藝所習知。因此，本專利說明書省略此類製程的細節讓讀者聚焦在所揭示之方法的最重要方面。
接下來，在步驟28不需要形成自對準矽化物於暴露矽表面上的任何半導體裝置上方可形成共形保護層140，以下會更詳細地描述(步驟26，參考第10圖)。例如，可沉積且進一步微影及蝕刻共形保護層140以便覆蓋不需要形成矽化物(例如，矽電阻器110c與多晶矽電阻器111)的任何裝置以及暴露需要形成矽化物(例如，第一FET 110a與第二FET 110b)的任何裝置。特別是，此共形保護層應為與先前用來形成第二及第三側壁間隔體132-133之附加側壁間隔體材料不同的介電質材料，藉此可蝕刻該共形保護層而不破壞第二及第三側壁間隔體132-133。視實際需要，可執行附加加工以完成半導體裝置(步驟28，參考第11圖)。例如，就第一FET 110a及第二FET 110b而言，此附加加工可包括但不限於：摻雜物植入製程以在通道區181相對兩側上的半導體台面106a及106b內形成各種摻雜物植入區(例如，視需要的暈輪(halo)(未圖示)，視需要的源極/汲極延伸部(未圖示)，以及源極/汲極區182)；在源極/汲極區182及閘極120之暴露表面上的自對準矽化物層145形成物；等等。應瞭解，提供此附加製程清單是為了圖解說明而非旨在窮盡列出完成FET結構所需的所有加工步驟。另外或替換地，取決於FET設計，可形成各種其他製程。
應瞭解，提供可在步驟18使用半導體台面用來形成半導體裝置及視需要形成附加裝置於相鄰半導體台面之間的上述子步驟20-28和附圖是為了圖解說明而非 旨在限制。例如，在該方法的一具體實施例中，使用該一或更多半導體台面中之每一者可以只形成單一類型的半導體裝置(例如，如上述的主動裝置或被動裝置)。在該方法的其他具體實施例中，使用該等半導體台面可形成主動裝置(例如，場效電晶體(FET)、雙極型接面電晶體(BJT)、異質接面雙極電晶體(HBT)等等)及/或被動裝置(例如，電阻器、電容器、二極體等等)的不同組合。另外或替換地，在該等溝槽內可不形成附加裝置(例如，多晶矽電阻器)，或在相同或不同的溝槽內可形成有相同或不同類型的多個附加裝置。另外，儘管只圖示在各半導體台面內形成的單一半導體裝置，然而在同一個半導體台面內可形成多個半導體裝置。
在任何情形下，在步驟18使用半導體台面形成半導體裝置以及在相鄰半導體台面之間的溝槽內的任何附加裝置後，可沉積至少一中段(MOL)介電層於各種裝置上方以及沉積於在溝槽1911-1914內的任何殘留空間中，藉此完成淺溝槽隔離(STI)結構(步驟30，參考第12圖至第13圖)。例如，可沉積共形蝕刻停止層150於半導體裝置110a-c上方、於任何附加裝置111上方、以及於在溝槽1911-1914內的任何殘留空間中(參考第12圖)。然後，可沉積毯覆層間介電質(ILD)層160於共形蝕刻停止層150上且予以平坦化(例如，使用化學機械研磨(CMP)製程)(參考，第13圖)。共形蝕刻停止層150，例如，可由氮化矽製成。毯覆ILD層160可由氧化矽或任何其他合適ILD材 料(例如，硼磷矽玻璃(borophosphosilicate glass，BPSG)、正矽酸乙酯(tetraethyl orthosilicate，TEOS)、氟化正矽酸乙酯(FTEOS)等等)製成。
如上述，在步驟30可沉積MOL介電層(亦即，共形蝕刻停止層150與毯覆ILD層160)於在溝槽1911-1914內的任何殘留空間中。因此，可沉積MOL介電層的一部份(亦即，共形蝕刻停止層150及毯覆ILD層160(取決於可用空間)的一部份)於溝槽1911-1914之中至少一些內。例如，該等MOL介電層，包括共形蝕刻停止層150及毯覆ILD層160，可填滿在給定溝槽內的相對大空間，致使所產生的STI包含共形蝕刻停止層150與ILD層160兩者的一部份(例如，參考溝槽1911-1912及1914)。不過，當在裝置形成後殘留在給定溝槽內的給定空間大小相對小(例如，淺或窄)時，共形蝕刻停止層150可完全填滿該空間，致使所產生的STI不包含ILD層160的任何部份(例如，參考溝槽1913)。此外，如果殘留在給定溝槽內的給定空間之深寬比相對高，則共形蝕刻停止層150或ILD層160可能在該溝槽的頂端發生夾止(pinch off)，致使在該溝槽內產生空洞(未圖示)。
隨後可形成穿過MOL介電層到半導體裝置的接觸，且可形成BEOL金屬層級(metal level)以完成IC結構(32)。用於形成接觸及BEOL金屬層級的技術為本技藝所習知，因此，本專利說明書省略這些技術的細節讓讀者聚焦在所揭示之方法的最重要方面。
請參考第13圖，本文也揭示根據上述方法所形成之積體電路(IC)結構100以便具有側壁間隔體及中段(MOL)含介電質淺溝槽隔離(STI)區的具體實施例。IC結構100可為絕緣體上覆半導體結構。亦即，IC結構100可形成於絕緣體上覆半導體晶圓(例如，絕緣體上覆矽(SOI)晶圓或任何其他合適的絕緣體上覆半導體晶圓)上，致使它包括基板102(例如，矽基板或任何其他合適基板，包括但不限於：石英玻璃基板或碳化矽(SiC)基板)，在基板102上的絕緣體層103(例如，埋藏氧化物(BOX)層或其他合適絕緣體層)，以及在絕緣體層103上的半導體層(例如，矽層或任何其他合適單晶半導體層)。熟諳此藝者會認識到各種層的必要厚度可取決於應用而有所不同。例如，就射頻(RF)應用而言，半導體層的厚度可在50至150奈米之間；然而，就習知互補金屬氧化物半導體(CMOS)應用而言，半導體層的厚度可在10至100奈米之間。溝槽1911-1914可垂直延伸穿過半導體層到絕緣體層103以便在絕緣體層103上界定一或更多半導體台面106a-106c。視需要，相對薄的共形氧化物層107可為溝槽1911-1914的襯裡。另外或替換地，熱氧化物層可在溝槽側壁上。
另外，第一側壁間隔體108可在溝槽1911-1914內以便側向鄰接各半導體台面106a-106c的第一側壁116。第一側壁間隔體108例如可由氮化矽、氮氧化矽、碳氧化矽、鋁土或任何其他合適介電質材料製成，它與絕緣體層103的介電質材料及共形氧化物層107(若有的 話)的介電質材料不同。
IC結構100更可包括使用一或更多半導體台面106a-106c形成的一或更多半導體裝置(例如，參考半導體裝置110a-110c)。具體言之，IC結構100可包括一或更多主動裝置(例如，場效電晶體(FET)、雙極型接面電晶體(BJT)、異質接面雙極電晶體(HBT)等等)及/或一或更多被動裝置(例如，電阻器、電容器、二極體等等)。視需要，IC結構100更可包括在溝槽1911-1914中之至少一者內的至少一附加裝置(例如，電阻器、電感器等等)以便側向位於兩個相鄰半導體台面之間。
為了圖解說明，包括下列4個半導體裝置的IC結構100圖示於第13圖且更詳細地予以描述如下：以第一方向定向且使用第一半導體台面106a形成的第一FET 110a；以與第一方向垂直之第二方向定向且使用第二半導體台面106b形成的第二FET 110b；使用第三半導體台面106c形成的第一電阻器110c(例如，矽電阻器)，以及形成於在側向位於第二半導體台面106b、第三半導體台面106c之間的溝槽1913中的附加裝置(例如，第二電阻器111，特別是，多晶矽電阻器)。
IC結構100更可包括帶圖案導體-介電質形狀(例如，帶圖案多晶矽-氧化物形狀)。具體言之，如以上在說明該方法時所述，可微影圖案化及蝕刻包括介電層(例如，氧化矽層)及導體層(例如，多晶矽層)的多層堆疊以形成帶圖案導體-介電質形狀(例如，多晶矽-氧化物形狀)。這 些帶圖案形狀可包括，例如，下列各物中之任一或更多：在通道區181上面位於第一半導體台面106a頂面上用於第一FET 110a的閘極120；在通道區181上面位於第二半導體台面106b頂面上用於第二FET 110b的閘極；用於某些其他類型之半導體裝置的閘極(未圖示)；以及側向位於相鄰半導體台面之間的溝槽中的附加裝置(例如，參考第二電阻器111，特別是，在溝槽1913的多晶矽電阻器)。
如上述，第一FET 110a與第二FET 110b，以及它們各自的閘極會以不同的方向定向。第13圖圖示在通道區181延伸越過第一FET 110a之長度及越過第二FET 110b之寬度的垂直橫截面。如圖中第二FET 110b所示，視需要可微影圖案化及蝕刻閘極120以便具有在半導體台面之頂面上且橫越通道區181的第一部份123，以及在第一側壁間隔體108上方側向延伸且進入至少一鄰近溝槽(例如，參考溝槽1933)的第二部份124。必要時，這允許閘極接觸在絕緣體材料上方垂直對準，而不是直接在通道區181上方。
應注意，帶圖案導體-介電質形狀或彼等在溝槽1911-1914內的部份(例如，第二電阻器111或第二FET 110之閘極的第二部份124)可具有與半導體台面106a-c相同的高度(例如，從絕緣體層103的頂面測量)(如圖示)，較小的高度，或較大的高度。更應注意，視需要，帶圖案導體-介電質形狀或彼等在半導體台面頂面上的部份(例如，第一FET 110a的閘極與第二FET 110b之閘極的第一部份 123)可具有與帶圖案導體-介電質形狀或彼等在溝槽內之部份(如圖示)相同的厚度，或可在加工期間加以研磨以減少在半導體台面上面的高度(例如，藉由減少最下面、中間及頂部矽層的頂面高度來實現所欲閘極高度及/或改善後續接觸微影焦深)。
IC結構100更可具有附加側壁間隔體，其包括側向緊鄰帶圖案多晶矽介電質形狀(亦即，閘極120及任何附加裝置，例如第二電阻器111)之第二側壁136的第二側壁間隔體132，以及在溝槽1911-1914內側向緊鄰第一側壁間隔體108(例如，在第一側壁116對面)的第三側壁間隔體133。該等附加側壁間隔體(亦即，第二側壁間隔體132與第三側壁間隔體133)，例如，可由氧化矽、氮氧化矽、碳氧化矽或任何其他合適介電質材料製成。因此，該等附加側壁間隔體可由與使用於第一側壁間隔體108者相同的介電質材料或不同的介電質材料製成。
IC結構100更可包括只在半導體裝置中之一些(例如，第一電阻器110c及第二電阻器111)上方的共形保護層140。此共形保護層140，例如，可由氮化矽製成，特別是，可由與第二側壁間隔體132及第三側壁間隔體133不同的介電質材料製成。如上文所詳述的，此共形保護層140提供一些半導體裝置(例如，電阻器110c及111)在加工其他半導體裝置(例如，第一FET 110a及第二FET 110b)期間(例如，在自對準矽化物形成期間等等)的保護。
應瞭解，第13圖非意圖具有限制性。如上 述IC結構100可包括使用一或更多半導體台面106a-106c形成的一或更多半導體裝置，以及視需要，在溝槽1911-1914中之至少一者內的一或更多附加裝置，以便側向位於兩個相鄰半導體台面之間。因此，IC結構100可包括使用半導體台面形成的一或更多主動裝置(例如，場效電晶體(FET)、雙極型接面電晶體(BJT)、異質接面雙極電晶體(HBT)等等)及/或一或更多被動裝置(例如，電阻器、電容器、二極體等等)的不同組合，而不是如以上所述方式組配且圖示於第13圖的。另外或替換地，IC結構100可不包括在溝槽內的附加裝置(例如，多晶矽電阻器)或在同一個或不同溝槽內有相同或不同類型的多個附加裝置。另外，儘管只圖示使用各半導體台面形成的單一半導體裝置，然而IC結構100可包括使用同一個半導體台面形成的多個半導體裝置。
在任何情形下，IC結構100更可包括至少一中段(MOL)介電層。例如，MOL介電層可包括覆蓋半導體裝置110a-c及任何附加裝置111的共形蝕刻停止層150以及在共形蝕刻停止層150上的毯覆層間介電質(ILD)層160。共形蝕刻停止層150，例如，可由氮化矽製成。毯覆ILD層160可由氧化矽或任何其他合適ILD材料製成(例如，硼磷矽玻璃(BPSG)、正矽酸乙酯(TEOS)、氟化正矽酸乙酯(FTEOS)等等)。
如以上在說明該等方法時所述，在形成裝置後，在側向鄰接半導體裝置110a-c及/或含有附加裝置 111的溝槽1911-1914中，可沉積MOL介電層於其任何殘留空間中。因此，MOL介電層的一部份(亦即，共形蝕刻停止層150及毯覆ILD層160(取決於可用空間)的一部份)可在溝槽1911-1914中之至少一些內。例如，該等MOL介電層，包括共形蝕刻停止層150及毯覆ILD層160，可填滿在給定溝槽內的相對大空間，致使所產生的STI包含共形蝕刻停止層150與ILD層160兩者的一部份(例如，參考溝槽1911-1912及1914)。不過，當在裝置形成後殘留在給定溝槽內的給定空間大小相對小(例如，淺或窄)時，共形蝕刻停止層150可完全填滿該空間，致使所產生的STI不包含ILD層160的任何部份(例如，參考溝槽1913)。此外，如果殘留在給定溝槽內的給定空間之深寬比相對高，共形蝕刻停止層150或ILD層160可能在該溝槽的頂端發生夾止，致使在該溝槽內產生空洞(未圖示)。
因此，IC結構100可具有至少一STI區，其包括：視需要的氧化矽襯裡107，在襯裡上側向鄰接相鄰半導體台面之側壁116的第一側壁間隔體108；側向鄰接第一側壁間隔體108的第三側壁間隔體133；共形蝕刻停止層150；以及填滿任何殘留空間的毯覆ILD 160(例如，參考在溝槽1911及1912中的STI區)。另外或替換地，IC結構100可具有其中有些或全部有相同特徵的至少一STI區以及嵌在其中的附加裝置(例如，參考嵌入溝槽1913中之STI區的第二電阻器111)。
應瞭解，用於本文的術語是只為了要描述 該等揭示結構及方法而非旨在限制。例如，如本文所使用的，英文單數形式“一(a)”、“一(an)”、及“該(the)”旨在也包括複數形式，除非上下文中另有明確指示。另外，如本文所使用的，用語“包含(comprises)”及/或“包含(comprising)”、或者“包括(includes)”及/或“包括(including)”係具體描述提及之特徵、整數、步驟、操作、元件及/或組件的存在，但不排除存在或加入一或更多其他特徵、整數、步驟、操作、元件及/或彼等之群組。此外，如本文所使用的，諸如“右”、“左”、“垂直”、“水平”、“頂部”、“底部”、“上”、“下”、“底下”、“下面”、“下層”、“上面”，“上覆”、“平行”、“垂直”之類的用語旨在描述彼等在定向及圖示於附圖中(除非另有明示)時的相對位置，以及諸如“接觸”、“直接接觸”、“抵接”、“直接鄰接”、“緊鄰”之類的用語旨在表示至少一元件實體接觸另一元件(沒有其他元件隔開所述元件)。如本文所使用的，片語“側向位於”係指按照在圖中的取向，一元件位在另一元件的一側，而不是在該另一元件的上方或下方。下列申請專利範圍中所有手段或步驟加上功能元件的對應結構、材料、動作及等效物旨在包括與如申請專利範圍所主張的其他元件結合用以完成功能的任何結構、材料或動作。
為了圖解說明已呈現本揭示內容之各種具體實施例的描述，但是並非旨在窮盡或限定於所揭示的具體實施例。本技藝一般技術人員明白仍有許多修改及變體而不脫離所述具體實施例的範疇及精神。使用於本文的術 語經選定成可最好地解釋具體實施例的原理、實際應用或優於在市上可找到之技術的技術改善，或使得本技藝一般技術人員能夠了解揭示於本文的具體實施例。

Claims (20)

  1. 一種方法，包含：在一半導體層中形成數個溝槽以界定至少一半導體台面，該半導體台面具有數個第一側壁；形成在該等溝槽內且側向鄰接該半導體台面之該等第一側壁的數個第一側壁間隔體；在該等第一側壁間隔體之該形成步驟之後且在完全填滿該等溝槽之前，使用該半導體台面形成一裝置；以及，沉積一毯覆層間介電層，其中，該等第一側壁間隔體與該毯覆層間介電層包含不同的介電質材料。
  2. 如申請專利範圍第1項所述之方法，其中，該等第一側壁間隔體包含氮化矽。
  3. 如申請專利範圍第1項所述之方法，其中，該毯覆層間介電層之該沉積步驟更包含：沉積該毯覆層間介電層於該溝槽內且於該裝置上面。
  4. 如申請專利範圍第1項所述之方法，更包含，在該毯覆層間介電層之該沉積步驟之前，形成一共形蝕刻停止層於該裝置上方且於該溝槽內，其中，該共形蝕刻停止層包含與該毯覆層間介電層不同的介電質材料。
  5. 如申請專利範圍第1項所述之方法，其中，該裝置之該形成步驟包含：形成閘極於該半導體台面的頂面上，其中，該方法更包含，在該裝置之該形成步驟之 後且在該毯覆層間介電層之該沉積步驟之前，實質同時地形成數個第二側壁間隔體及數個第三側壁間隔體，致使該等第二側壁間隔體側向鄰接該閘極的第二側壁，且致使該等第三側壁間隔體在該等溝槽內側向鄰接該等第一側壁間隔體，以及其中，該等第二側壁間隔體及該等第三側壁間隔體包含與該等第一側壁間隔體不同的介電質材料。
  6. 如申請專利範圍第5項所述之方法，其中，該閘極具有在該半導體台面之該頂面上面的第一部份與在該溝槽內的第二部份。
  7. 一種方法，包含：提供一絕緣體上覆半導體晶圓，其包含基板、在該基板上的半導體層，以及在該半導體層上的絕緣體層；在該半導體層中形成數個溝槽以在該絕緣體層上界定多個半導體台面，其中，該等半導體台面具有數個第一側壁；在該等溝槽內形成側向鄰接該等半導體台面之該等第一側壁的數個第一側壁間隔體；在該等第一側壁間隔體之該形成步驟之後，使用該等半導體台面形成數個裝置，且在該等裝置之該形成步驟期間，在側向位於相鄰半導體台面之間的溝槽內形成一附加裝置；以及，沉積一毯覆層間介電層，其中，該等第一側壁間 隔體與該等層間介電層包含不同的介電質材料。
  8. 如申請專利範圍第7項所述之方法，其中，該等第一側壁間隔體包含氮化矽。
  9. 如申請專利範圍第7項所述之方法，其中，該毯覆層間介電層之該沉積步驟更包含：沉積該毯覆層間介電層於該等溝槽中之至少一些內且於該附加裝置及該等裝置上面。
  10. 如申請專利範圍第7項所述之方法，更包含，在該毯覆層間介電層之該沉積步驟之前，沉積共形蝕刻停止層，其中，該共形蝕刻停止層包含與該毯覆層間介電層不同的介電質材料。
  11. 如申請專利範圍第7項所述之方法，其中，該等裝置之該形成步驟包含：至少使用一第一半導體台面形成一場效電晶體以及使用一第二半導體台面形成一第一電阻器，以及其中，該附加裝置之該形成步驟包含：形成一第二電阻器。
  12. 如申請專利範圍第11項所述之方法，其中，該等裝置之該形成步驟和該附加裝置之該形成步驟包含：沉積一氧化矽層；沉積一多晶矽層於該氧化矽層上以形成一多層堆疊；以及圖案化該多層堆疊以形成多晶矽-氧化矽形狀，該 等多晶矽-氧化矽形狀包括：在該第一半導體台面之頂面上用於該場效電晶體的一閘極；以及該第二電阻器，以及其中，該方法更包含：實質同時地形成數個第二側壁間隔體及數個第三側壁間隔體，致使該等第二側壁間隔體側向鄰接該等多晶矽-氧化矽形狀的數個第二側壁，且致使該等第三側壁間隔體在該等溝槽內側向鄰接該等第一側壁間隔體，其中，該等第二側壁間隔體及該等第三側壁間隔體包含與該等第一側壁間隔體不同的介電質材料；形成一保護層於該第一電阻器及該第二電阻器上方；執行一摻雜物植入製程以在該第一半導體台面中形成用於該場效電晶體的源極/汲極區；以及，形成數個矽化物層於該等源極/汲極區上。
  13. 如申請專利範圍第12項所述之方法，其中，該閘極具有在該第一半導體台面之該頂面上面的第一部份與在一鄰近溝槽內的第二部份。
  14. 一種積體電路結構，包含：數個溝槽，垂直延伸穿過一半導體層，該等溝槽界定至少一半導體台面；數個第一側壁間隔體，在該等溝槽內側向鄰接該至少一半導體台面之數個第一側壁； 至少一裝置，包含該至少一半導體台面；以及，毯覆層間介電層，在該至少一裝置上方，其中，該等第一側壁間隔體與該等毯覆層間介電層包含不同的介電質材料。
  15. 如申請專利範圍第14項所述之積體電路結構，其中，該等第一側壁間隔體包含氮化矽，其中，該毯覆層間介電層在該等溝槽中之至少一些內，其中，該積體電路結構更包含在該至少一裝置與該毯覆層間介電層之間的一共形蝕刻停止層，以及其中，該共形蝕刻停止層包含與該毯覆層間介電層不同的介電質材料。
  16. 如申請專利範圍第14項所述之積體電路結構，其中，該至少一裝置包含場效電晶體與電阻器中之任一者。
  17. 如申請專利範圍第16項所述之積體電路結構，其中，該場效電晶體包含在該半導體台面之頂面上的一閘極，其中，該積體電路結構更包含數個第二側壁間隔體與數個第三側壁間隔體，其中，該等第二側壁間隔體側向鄰接該閘極的第二側壁，其中，該等第三側壁間隔體在該等溝槽內側向鄰接該等第一側壁間隔體，以及其中，該等第二側壁間隔體及該等第三側壁間隔 體包含與該第一側壁間隔體不同的介電質材料。
  18. 如申請專利範圍第17項所述之積體電路結構，其中，該閘極具有在該半導體台面之該頂面上面的第一部份與在一鄰近溝槽內的第二部份。
  19. 如申請專利範圍第14項所述之積體電路結構，更包含在相鄰半導體台面之間的該等溝槽中之一者內的一附加裝置。
  20. 如申請專利範圍第19項所述之積體電路結構，其中，該附加裝置包含一多晶矽電阻器。
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