CN108511385B - 形成具有sti区的集成电路的方法及所产生的ic结构 - Google Patents

形成具有sti区的集成电路的方法及所产生的ic结构 Download PDF

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CN108511385B
CN108511385B CN201711402145.4A CN201711402145A CN108511385B CN 108511385 B CN108511385 B CN 108511385B CN 201711402145 A CN201711402145 A CN 201711402145A CN 108511385 B CN108511385 B CN 108511385B
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CN108511385A (zh
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安东尼·K·史塔佩尔
史蒂芬·M·宣克
西瓦·P·阿度苏米利
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GlobalFoundries US Inc
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Abstract

本发明涉及形成具有STI区的集成电路的方法及所产生的IC结构，其揭示一种集成电路(IC)形成方法，其中，在一半导体层内形成数个沟槽以界定半导体台面。该方法初始只在该沟槽内形成侧壁间隔体于该半导体台面的暴露侧壁上，而不是立即用隔离材料填满该沟槽以及执行平坦化工艺以在装置形成前完成该STI区。在该侧壁间隔体形成后，使用该半导体台面形成装置(例如，场效应晶体管、硅电阻器等等)，且视需要，在相邻半导体台面之间的沟槽内可形成附加装置(例如，多晶硅电阻器)。随后，沉积中段(MOL)介电质(例如，共形蚀刻停止层及毯覆层间介电质(ILD)层)于该装置上方，藉此填满在该沟槽内的任何残留空间且完成该STI区。也揭示一种使用该方法所形成的IC结构。

Description

形成具有STI区的集成电路的方法及所产生的IC结构
技术领域
本发明有关于集成电路(IC)，且更特别的是，有关于形成具有浅沟槽隔离(shallow trench isolation；STI)区的集成电路(IC)结构的改良方法及所产生的IC结构。
背景技术
具体而言，在使用绝缘体上覆半导体晶片(例如，绝缘体上覆硅(SOI)晶片)的习知集成电路(IC)加工中，通过形成浅沟槽隔离(STI)区来界定用于装置区的半导体台面。具体言之，此类加工以包括半导体衬底(例如，硅衬底)、在半导体衬底上的绝缘体层(例如，埋藏氧化物(BOX)层)及在绝缘体层上的半导体层(例如，硅层)的绝缘体上覆半导体晶片开始。光刻图案化及蚀刻该半导体层以形成数个沟槽，该沟槽垂直或几乎垂直地延伸穿过半导体层到绝缘体层或进入绝缘体层且侧向包围用于在半导体层内的装置区的半导体台面。然后，沉积隔离材料(例如，氧化硅)以填满该沟槽，且执行平坦化工艺(例如，化学机械研磨(CMP)工艺)以便从半导体台面的顶面移除隔离材料，藉此形成STI区。半导体装置(例如，场效应晶体管(FET)、双极型接面晶体管(BJT)、二极管等等)随后形成于该半导体台面中，以及该STI区提供电气隔离。可惜，包括形成此种STI的IC加工可能成本高又耗时。因此，本领域亟须一种形成具有浅沟槽隔离(STI)区的集成电路(IC)结构的改良方法。
发明内容
鉴于上述，揭示于本文的是形成具有侧壁间隔体及中段(MOL)含介电质浅沟槽隔离(STI)区的集成电路(IC)结构的方法的具体实施例。具体言之，在该方法中，在半导体层内可形成沟槽以界定至少一半导体台面。该方法初始只在该沟槽内形成侧壁间隔体于该半导体台面的暴露侧壁上，而不是立即用隔离材料填满该沟槽以及执行平坦化工艺(例如，化学机械研磨(CMP)工艺)以在装置形成前完成该STI区。在该侧壁间隔体形成后，可使用该半导体台面形成(数个)装置(例如，场效应晶体管、双极型接面晶体管、异质接面双极晶体管、电容器、电阻器等等)，且视需要，可在相邻半导体台面之间的沟槽内形成(数个)附加装置(例如，电阻器)。随后，可沉积中段(MOL)介电质(例如，共形蚀刻停止层及毯覆层间介电质(ILD)层)于该装置上方且于在该沟槽内的任何残留空间中，藉此完成该STI区。本文也揭示使用上述方法所形成的IC结构的具体实施例。
一般而言，揭示于本文的是形成具有侧壁间隔体及中段(MOL)含介电质浅沟槽隔离(STI)区的集成电路(IC)结构的方法的具体实施例。该方法包括在一半导体层中形成数个沟槽以界定至少一半导体台面，其具有数个第一侧壁。第一侧壁间隔体可形成于该沟槽内以便侧向邻接该半导体台面的该第一侧壁。在该第一侧壁间隔体形成后，但是在该沟槽被完全填满前，可使用该半导体台面形成一半导体装置(例如，场效应晶体管(FET)、电阻器等等)。在该半导体装置完成后，至少一中段(MOL)介电层(例如，毯覆层间介电质(ILD)层)可沉积于该半导体装置上方且于在该沟槽内的任何残留空间中。应注意，该第一侧壁间隔体与该毯覆ILD层可由不同的介电质材料制成。
更特别的是，揭示于本文的方法的一具体实施例可包括：提供一绝缘体上覆半导体晶片，其包括衬底、在该衬底上的绝缘体层，以及在该绝缘体层上的半导体层。在该半导体层中可形成数个沟槽以在该绝缘体层上界定有数个第一侧壁的多个半导体台面。第一侧壁间隔体可形成于该沟槽内以便侧向邻接该半导体台面的第一侧壁。在该第一侧壁间隔体形成后，但是在该沟槽被完全填满前，可使用该等半导体台面形成各种不同类型的半导体装置(例如，一或更多FET、一或更多电阻器等等)。视需要，在形成该半导体装置于该半导体台面内时，在该沟槽中的任一内可形成(数个)附加装置(例如，电阻器)以便侧向位于相邻半导体台面之间。在该半导体装置及视需要附加装置完成后，可沉积一或更多中段(MOL)介电层(例如，共形蚀刻停止层，接着是毯覆层间介电质(ILD)层)于该半导体装置及任何附加装置上方且于在该沟槽内的任何残留空间中。该第一侧壁间隔体与该毯覆ILD层再度可由不同的介电质材料制成。
本文也揭示根据上述方法所形成的集成电路(IC)结构的具体实施例以便具有侧壁间隔体及中段(MOL)含介电质浅沟槽隔离(STI)区。一般而言，揭示于本文的IC结构可具有垂直延伸穿过一半导体层的数个沟槽。这些沟槽可界定至少一半导体台面。第一侧壁间隔体可在该沟槽内侧向邻接该半导体台面的第一侧壁。该IC结构更可包括使用该至少一半导体台面形成的至少一半导体装置(例如，场效应晶体管、电阻器等等)。例如，该IC结构可包括类型相同或不同的多个半导体装置，其中各半导体装置整个或部分包含在半导体台面中。视需要，该IC结构也可包括侧向位于相邻半导体台面之间的该沟槽中的任一内的(数个)附加装置(例如，电阻器)。另外，至少一中段介电层(例如，毯覆层间介电质(ILD)层)可在该半导体装置及附加装置上方且在该沟槽内的任何残留空间中。如以上方法所述，该第一侧壁间隔体与该毯覆ILD层可由不同的介电质材料制成。
附图说明
由以下参考附图的详细说明可更加了解本发明，附图不一定是按比例绘制。
图1的流程图图示形成具有侧壁间隔体及中段(MOL)含介电质浅沟槽隔离(STI)区的集成电路(IC)结构的方法的具体实施例；
图2的横截面图图示根据图1的流程图形成的部分完成结构；
图3的横截面图图示根据图1的流程图形成的部分完成结构；
图4的横截面图图示根据图1的流程图形成的部分完成结构；
图5的横截面图图示根据图1的流程图形成的部分完成结构；
图6的横截面图图示根据图1的流程图形成的部分完成结构；
图7A及7B的替代横截面图图示根据图1的流程图形成的部分完成结构；
图8的横截面图图示根据图1的流程图形成的部分完成结构；
图9的横截面图图示根据图1的流程图形成的部分完成结构；
图10的横截面图图示根据图1的流程图形成的部分完成结构；
图11的横截面图图示根据图1的流程图形成的部分完成结构；
图12的横截面图图示根据图1的流程图形成的部分完成结构；以及
图13的横截面图图示根据图1的流程图形成的部分完成结构。
具体实施方式
如上述，在使用绝缘体上覆半导体晶片(例如，绝缘体上覆硅(SOI)晶片)的习知集成电路(IC)加工中，通过形成浅沟槽隔离(STI)区来界定用于装置区的半导体台面。具体言之，此类加工以包括半导体衬底(例如，硅衬底)、在半导体衬底上的绝缘体层(例如，埋藏氧化物(BOX)层)及在绝缘体层上的半导体层(例如，硅层)的绝缘体上覆半导体晶片开始。光刻图案化及蚀刻该半导体层以形成数个沟槽，该沟槽垂直或几乎垂直地延伸穿过半导体层到绝缘体层或进入绝缘体层且侧向包围用于在半导体层内的装置区的半导体台面。然后，沉积隔离材料(例如，氧化硅)以填满该沟槽，且执行平坦化工艺(例如，化学机械研磨(CMP)工艺)以便从半导体台面的顶面移除隔离材料，藉此形成STI区。半导体装置(例如，场效应晶体管(FET)、双极型接面晶体管(BJT)、二极管等等)随后形成于半导体台面中，以及该STI区提供电气隔离。可惜，包括形成此种STI的IC加工可能成本高又耗时。
鉴于上述，揭示于本文的是形成具有侧壁间隔体及中段(MOL)含介电质浅沟槽隔离(STI)区的集成电路(IC)结构的方法的具体实施例。具体言之，在该方法中，在半导体层内可形成沟槽以在绝缘体层上界定至少一半导体台面。该方法初始只在该沟槽内形成侧壁间隔体于该半导体台面的暴露侧壁上，而不是立即用隔离材料填满该沟槽以及执行平坦化工艺(例如，化学机械研磨(CMP)工艺)以在装置形成前完成该STI区。在该侧壁间隔体形成后，可使用该半导体台面形成(数个)装置(例如，场效应晶体管、双极型接面晶体管、异质接面双极晶体管、电容器、电阻器等等)，且视需要，可在相邻半导体台面之间的沟槽内形成(数个)附加装置(例如，电阻器)。随后，可沉积中段(MOL)介电质(例如，共形蚀刻停止层及毯覆层间介电质(ILD)层)于该装置上方且沉积于该沟槽内的任何残留空间中，藉此完成该STI区。本文也揭示使用上述方法所形成的IC结构的具体实施例。
更特别的是，请参考图1的流程图，揭示于本文的是形成具有侧壁间隔体及中段(MOL)含介电质浅沟槽隔离(STI)区的集成电路(IC)结构的方法的具体实施例。该方法以绝缘体上覆半导体晶片101(例如，绝缘体上覆硅(SOI)晶片或任何其他合适的绝缘体上覆半导体晶片)开始(步骤10，参考图2)。此一晶片101可包括衬底102(例如，硅衬底或任何其他合适衬底，包括但不限于：石英玻璃衬底或碳化硅(SiC)衬底)、在衬底102上的绝缘体层103(例如，埋藏氧化物(BOX)层或其他合适绝缘体层)、以及在绝缘体层103上的半导体层104(例如，硅层或任何其他合适的单晶或多晶半导体层)。熟谙此艺者会认识到各种层在晶片101中的必要厚度可取决于应用而有所不同。例如，就射频(RF)应用而言，半导体层104的厚度可在50至150纳米之间；然而，就习知互补金属氧化物半导体(CMOS)应用而言，半导体层104的厚度可在10至100纳米之间。在任何情形下，在任何额外加工之前，可清洗晶片101，且视需要，在半导体层104顶面上相对薄的牺牲介电层105。牺牲介电层105可包括，例如，一或更多层的二氧化硅(SiO2)或氮化硅(SiN)。牺牲介电层105可用例如热氧化及/或化学气相沉积(CVD)形成以便有5至50纳米的厚度。
可形成实质垂直穿过牺牲介电层105及半导体层104至少到绝缘体层103的沟槽1911-1914(步骤12，参考图3)。具体言之，使用习知光刻图案化及蚀刻工艺可形成此类沟槽1911-1914以便在绝缘体层103上界定一或更多半导体台面106a-106c。如图示，沟槽1911-1914的蚀刻可在绝缘体层103的顶面停止，或可延伸进入绝缘体层103的一些深度而不暴露衬底102的顶面。为了本揭示内容的目的，半导体台面(在此也被称为半导体主体)为半导体材料的一离散区(discrete area)，其由半导体层图案化而成且可用来形成一或更多半导体装置。这些半导体装置可包括主动装置(例如，场效应晶体管(FET)、双极型接面晶体管(BJT)、异质接面双极晶体管(HBT)等等)及/或被动装置(例如，电阻器、电容器、二极管等等)。为了图解说明，图3图示由沟槽1911-1914界定的3个半导体台面(亦即，第一半导体台面106a、第二半导体台面106b及第三半导体台面106c)；不过，应了解，图3非旨在限制且可执行步骤12以便界定任何数目的一或更多半导体台面。在任何情形下，各半导体台面106a-106c可具有由沟槽1911-1914界定的第一侧壁116(亦即，垂直面)。
视需要，可形成相对薄的共形氧化物层107以便覆盖及紧邻各半导体台面106a-106c的顶面及第一侧壁且进一步以便覆盖及紧邻在沟槽1911-1914内的绝缘体层103的暴露部分(步骤14，参考图4)。例如，可形成相对薄的二氧化硅层107(例如，5至15纳米氧化物层)(例如，用化学气相沉积(CVD))于半导体台面及绝缘体层103上方。另外或替换地，可形成热氧化物层(例如，用热氧化)于半导体台面106a-106c的暴露侧壁上。
接下来，在沟槽1911-1914内可形成第一侧壁间隔体108以便侧向邻接各半导体台面的第一侧壁116，特别是，以便侧向包围各半导体台面以及以利从绝缘体层103到半导体台面的顶面保护及覆盖各半导体台面的第一侧壁116(亦即，垂直面)(步骤16，参考图5)。
更特别的是，可沉积侧壁间隔体材料共形层(例如，用化学气相沉积(CVD))以便覆盖各半导体台面106a-106c的顶面及第一侧壁116，且以利于覆盖在沟槽1911-1914内的绝缘体层103的暴露部分。此侧壁间隔体材料，例如，可为氮化硅、氮氧化硅、碳氧化硅(siliconoxycarbide)、铝土、或任何其他合适的介电质材料，它与绝缘体层103的介电质材料及共形氧化物层107(若有的话)的介电质材料不同。侧壁间隔体材料共形层的厚度，例如，可在20至100纳米之间。在沉积侧壁间隔体材料后，可执行选择性非等向性蚀刻工艺以便从水平面移除侧壁间隔体材料，留下在垂直面上的侧壁间隔体材料。亦即，相比于在与绝缘体层顶面平行的方向，侧壁间隔体材料在与绝缘体层103顶面垂直的方向的蚀刻速率可明显快些。另外，对于绝缘体层103的绝缘体材料、共形氧化物层107(若有的话)的介电质材料及半导体台面106a-106c的半导体材料，可选择性地蚀刻侧壁间隔体材料(亦即，以明显较快的速率蚀刻)，藉此形成在沟槽1911-1914内且侧向邻接半导体台面106a-106c的第一侧壁116的第一侧壁间隔体108，如图示。或者，选择性非等向性蚀刻工艺可进一步蚀刻穿过共形氧化物层107(若有的话)，且视需要，部分进入绝缘体层103。在任何情形下，此选择性非等向性蚀刻工艺应在暴露衬底102的顶面之前停止。例如氮化硅、氮氧化硅、碳氧化硅等等的介电质材料的选择性非等向性蚀刻工艺为本领域所习知。因此，本专利说明书省略此类工艺的细节让读者聚焦在所揭示的方法的最重要方面。
应了解，第一侧壁间隔体108的宽度取决于第一间隔体材料的共形层的厚度与在与绝缘体层103顶面平行的方向的蚀刻速率。更应了解，如果在步骤14形成共形氧化物层107(及/或热氧化物层)，则用共形氧化物层107(如图示)及/或热氧化物层的垂直部分，使第一侧壁间隔体108与第一侧壁116实体分离。不过，如果在步骤14既不形成共形氧化物层107也不形成热氧化物层，则第一侧壁间隔体108会紧邻第一侧壁116。
在第一侧壁间隔体108形成后，但是在沟槽1911-1914填满隔离材料以形成浅沟槽隔离(STI)区于其中之前，可使用一或更多半导体台面106a-106c来形成一或更多半导体装置110a-110c(步骤18)。具体言之，该半导体台面106a-106c可用来形成一或更多主动装置(例如，场效应晶体管(FET)、双极型接面晶体管(BJT)、异质接面双极晶体管(HBT)等等)及/或一或更多被动装置(例如，电阻器、电容器、二极管等等)。视需要，在使用半导体台面形成半导体装置的此步骤18期间，在沟槽1911-1914中的至少一者内可形成至少一附加装置(例如，电阻器、电感器等等)以便侧向位于两个相邻半导体台面之间。
为了图解说明，以下使用示范子步骤(sub-process)20-28更详细地描述步骤18以形成下列半导体装置：以第一方向定向且使用第一半导体台面106a形成的第一FET 110a；以与第一方向垂直的第二方向定向且使用第二半导体台面106b形成的第二FET 110b；使用第三半导体台面106c形成的第一电阻器110c(例如，硅电阻器)，以及在侧向位于第二半导体台面106b、第三半导体台面106c之间的沟槽1913中形成的附加装置(例如，第二电阻器111，特别是，多晶硅电阻器)。
为了在步骤18使用该半导体台面来形成半导体装置，且视需要，形成在相邻半导体台面之间的附加装置，可首先清洗该半导体台面的顶面。具体言之，暴露该半导体台面的顶面通过例如使用湿及干蚀刻化学剂(例如水性或蒸气氢氟酸(HF))的组合来蚀刻去掉任何介电质材料。接下来，在该半导体台面106a-c上方形成多层堆栈(步骤20)。具体言之，可形成在该半导体台面上方的栅极介电层121。栅极介电层121可由一或更多层的任何合适的栅极介电质材料制成，包括但不限于：二氧化硅(SiO2)或高K介电质材料。在一具体实施例中，该栅极介电层可为氧化物层。例如，通过沉积共形氧化物层于该半导体台面上方(例如，使用化学气相沉积(CVD)工艺、原子层沉积(ALD)或任何其他合适沉积工艺)，可形成此一氧化物层，如图6所示。或者，通过热氧化半导体台面的顶面，可形成此一氧化物层。接下来，栅极导体层122可形成于栅极介电层121上。栅极导体层122可由一或更多层的合适栅极导体材料制成，包括但不限于：多晶硅或金属。在一具体实施例中，栅极导体层122可为多晶硅层。此一多晶硅层可为共形多晶硅层，如图7A所示。例如，使用例如快速热CVD或液相CVD的CVD工艺，可形成此一共形多晶硅层。或者，该多晶硅层可为非共形多晶硅层，如图7B所示。例如，使用高密度电浆CVD工艺，可形成此一非共形多晶硅层。在任何情形下，栅极导体层122可形成于该半导体台面106a-106c上方且于沟槽1911-1914内，藉此形成多层堆栈。
应注意，可形成该多层堆栈使得该堆栈在沟槽1911-1914内的部分大约与半导体台面106a-c有相同的高度(例如，从绝缘体层103的顶面测量)(如图示)、较少的高度或较大的高度。更应注意，视需要，可研磨该多层堆栈(例如，使用CMP工艺)以减少堆栈在半导体台面106a-c以上的高度(例如，通过减少最下面、中间及顶部硅层的顶面高度来实现所欲栅极高度及/或改善后续接触光刻焦深)。
在任何情形下，随后可光刻图案化及蚀刻该多层堆栈以形成带图案的介电质121-导体122形状(例如，带图案的多晶硅-氧化硅形状)(步骤22，参考图8)。具体言之，在步骤22可光刻图案化及蚀刻该堆栈，使得所产生的带图案形状形成下列各物中的任一或更多：在半导体台面上用于FET的栅极(例如，参考在第一半导体台面106a顶面上用于第一FET 110a以及在第二半导体台面106b顶面上用于第二FET 110b的栅极)；用于某些其他类型的半导体装置(例如，MOS电容器)的栅极(未图示)；以及在沟槽中侧向位于相邻半导体台面之间的附加装置，例如电阻器(例如，参考第二电阻器111，特别是，在沟槽1913中的多晶硅电阻器)。
该方法更可包括：形成附加侧壁间隔体于所有实质垂直面上(步骤24，参考图9)。具体言之，可沉积(例如，用化学气相沉积(CVD))附加侧壁间隔体材料共形层于部分完成的IC结构上方。此附加侧壁间隔体材料，例如，可为氧化硅、氮氧化硅、碳氧化硅或任何其他合适介电质材料中的任一或更多。因此，该附加侧壁间隔体材料可为与使用于第一侧壁间隔体108者相同的介电质材料或不同的介电质材料。在任何情形下，附加侧壁间隔体材料共形层的厚度，例如，可在50至100纳米之间。在沉积该附加侧壁间隔体材料后，可执行选择性非等向性蚀刻工艺以便从水平面移除该附加侧壁间隔体材料，留下在垂直面上的附加侧壁间隔体材料。亦即，相比于在与绝缘体层103顶面平行的方向，该附加侧壁间隔体材料在与绝缘体层103顶面垂直的方向的蚀刻速率可明显快些。另外，对于绝缘体层103的绝缘体材料、共形氧化物层107(若有的话)的介电质材料、半导体台面106a-106c的半导体材料以及在步骤22形成的任何带图案形状的多晶硅材料(例如，栅极120及第二电阻器111)，可选择性地蚀刻该附加侧壁间隔体材料(亦即，以明显较快的速率蚀刻)。结果，此选择性非等向性蚀刻工艺会实质同时地形成侧向紧邻在步骤22形成的各种带图案形状的第二侧壁136的第二侧壁间隔体132(例如，参考在栅极120上和在第二电阻器111上的第二侧壁间隔体132)以及在沟槽1911-1914内侧向紧邻第一侧壁间隔体108(例如，在第一侧壁116对面)的第三侧壁间隔体133。如上述，例如氮化硅、氮氧化硅、碳氧化硅等等的介电质材料的选择性非等向性蚀刻工艺为本领域所习知。因此，本专利说明书省略此类工艺的细节让读者聚焦在所揭示的方法的最重要方面。
接下来，在步骤28不需要形成自对准硅化物于暴露硅表面上的任何半导体装置上方可形成共形保护层140，以下会更详细地描述(步骤26，参考图10)。例如，可沉积且进一步光刻及蚀刻共形保护层140以便覆盖不需要形成硅化物(例如，硅电阻器110c与多晶硅电阻器111)的任何装置以及暴露需要形成硅化物(例如，第一FET 110a与第二FET110b)的任何装置。特别是，此共形保护层应为与先前用来形成第二及第三侧壁间隔体132-133的附加侧壁间隔体材料不同的介电质材料，藉此可蚀刻该共形保护层而不破坏第二及第三侧壁间隔体132-133。视实际需要，可执行附加加工以完成半导体装置(步骤28，参考图11)。例如，就第一FET 110a及第二FET 110b而言，此附加加工可包括但不限于：掺杂物植入工艺以在沟道区181相对两侧上的半导体台面106a及106b内形成各种掺杂物植入区(例如，视需要的晕轮(halo)(未图示)，视需要的源极/漏极延伸部(未图示)，以及源极/漏极区182)；在源极/漏极区182与栅极120的暴露表面上的自对准硅化物层145形成物；等等。应了解，提供此附加工艺清单是为了图解说明而非旨在穷尽列出完成FET结构所需的所有加工步骤。另外或替换地，取决于FET设计，可形成各种其他工艺。
应了解，提供可在步骤18使用半导体台面用来形成半导体装置及视需要形成附加装置于相邻半导体台面之间的上述子步骤20-28和附图是为了图解说明而非旨在限制。例如，在该方法的一具体实施例中，使用该一或更多半导体台面中的每一者可以只形成单一类型的半导体装置(例如，如上述的主动装置或被动装置)。在该方法的其他具体实施例中，使用该半导体台面可形成主动装置(例如，场效应晶体管(FET)、双极型接面晶体管(BJT)、异质接面双极晶体管(HBT)等等)及/或被动装置(例如，电阻器、电容器、二极管等等)的不同组合。另外或替换地，在该沟槽内可不形成附加装置(例如，多晶硅电阻器)，或在相同或不同的沟槽内可形成有相同或不同类型的多个附加装置。另外，尽管只图示在各半导体台面内形成的单一半导体装置，然而在同一个半导体台面内可形成多个半导体装置。
在任何情形下，在步骤18使用半导体台面形成半导体装置以及在相邻半导体台面之间的沟槽内的任何附加装置后，可沉积至少一中段(MOL)介电层于各种装置上方以及沉积于在沟槽1911-1914内的任何残留空间中，藉此完成浅沟槽隔离(STI)结构(步骤30，参考图12至图13)。例如，可沉积共形蚀刻停止层150于半导体装置110a-c上方、于任何附加装置111上方、以及于在沟槽1911-1914内的任何残留空间中(参考图12)。然后，可沉积毯覆层间介电质(ILD)层160于共形蚀刻停止层150上且予以平坦化(例如，使用化学机械研磨(CMP)工艺)(参考，图13)。共形蚀刻停止层150，例如，可由氮化硅制成。毯覆ILD层160可由氧化硅或任何其他合适ILD材料(例如，硼磷硅玻璃(borophosphosilicate glass，BPSG)、正硅酸乙酯(tetraethyl orthosilicate，TEOS)、氟化正硅酸乙酯(FTEOS)等等)制成。
如上述，在步骤30可沉积MOL介电层(亦即，共形蚀刻停止层150与毯覆ILD层160)于在沟槽1911-1914内的任何残留空间中。因此，可沉积MOL介电层的一部分(亦即，共形蚀刻停止层150及毯覆ILD层160(取决于可用空间)的一部分)于沟槽1911-1914之中至少一些内。例如，该MOL介电层，包括共形蚀刻停止层150及毯覆ILD层160，可填满在给定沟槽内的相对大空间，致使所产生的STI包含共形蚀刻停止层150与ILD层160两者的一部分(例如，参考沟槽1911-1912及1914)。不过，当在装置形成后残留在给定沟槽内的给定空间大小相对小(例如，浅或窄)时，共形蚀刻停止层150可完全填满该空间，致使所产生的STI不包含ILD层160的任何部分(例如，参考沟槽1913)。此外，如果残留在给定沟槽内的给定空间的深宽比相对高，则共形蚀刻停止层150或ILD层160可能在该沟槽的顶端发生夹止(pinch off)，致使在该沟槽内产生空洞(未图示)。
随后可形成穿过MOL介电层到半导体装置的接触，且可形成BEOL金属层级(metallevel)以完成IC结构(32)。用于形成接触及BEOL金属层级的技术为本领域所习知，因此，本专利说明书省略这些技术的细节让读者聚焦在所揭示的方法的最重要方面。
请参考图13，本文也揭示根据上述方法所形成的集成电路(IC)结构100以便具有侧壁间隔体及中段(MOL)含介电质浅沟槽隔离(STI)区的具体实施例。IC结构100可为绝缘体上覆半导体结构。亦即，IC结构100可形成于绝缘体上覆半导体晶片(例如，绝缘体上覆硅(SOI)晶片或任何其他合适的绝缘体上覆半导体晶片)上，致使它包括衬底102(例如，硅衬底或任何其他合适衬底，包括但不限于：石英玻璃衬底或碳化硅(SiC)衬底)，在衬底102上的绝缘体层103(例如，埋藏氧化物(BOX)层或其他合适绝缘体层)，以及在绝缘体层103上的半导体层(例如，硅层或任何其他合适单晶半导体层)。熟谙此艺者会认识到各种层的必要厚度可取决于应用而有所不同。例如，就射频(RF)应用而言，半导体层的厚度可在50至150纳米之间；然而，就习知互补金属氧化物半导体(CMOS)应用而言，半导体层的厚度可在10至100纳米之间。沟槽1911-1914可垂直延伸穿过半导体层到绝缘体层103以便在绝缘体层103上界定一或更多半导体台面106a-106c。视需要，相对薄的共形氧化物层107可为沟槽1911-1914的衬里。另外或替换地，热氧化物层可在沟槽侧壁上。
另外，第一侧壁间隔体108可在沟槽1911-1914内以便侧向邻接各半导体台面106a-106c的第一侧壁116。第一侧壁间隔体108例如可由氮化硅、氮氧化硅、碳氧化硅、铝土或任何其他合适介电质材料制成，它与绝缘体层103的介电质材料及共形氧化物层107(若有的话)的介电质材料不同。
IC结构100更可包括使用一或更多半导体台面106a-106c形成的一或更多半导体装置(例如，参考半导体装置110a-110c)。具体言之，IC结构100可包括一或更多主动装置(例如，场效应晶体管(FET)、双极型接面晶体管(BJT)、异质接面双极晶体管(HBT)等等)及/或一或更多被动装置(例如，电阻器、电容器、二极管等等)。视需要，IC结构100更可包括在沟槽1911-1914中的至少一者内的至少一附加装置(例如，电阻器、电感器等等)以便侧向位于两个相邻半导体台面之间。
为了图解说明，包括下列4个半导体装置的IC结构100图标于图13且更详细地予以描述如下：以第一方向定向且使用第一半导体台面106a形成的第一FET 110a；以与第一方向垂直的第二方向定向且使用第二半导体台面106b形成的第二FET 110b；使用第三半导体台面106c形成的第一电阻器110c(例如，硅电阻器)，以及形成于在侧向位于第二半导体台面106b、第三半导体台面106c之间的沟槽1913中的附加装置(例如，第二电阻器111，特别是，多晶硅电阻器)。
IC结构100更可包括带图案导体-介电质形状(例如，带图案多晶硅-氧化物形状)。具体言之，如以上在说明该方法时所述，可光刻图案化及蚀刻包括介电层(例如，氧化硅层)及导体层(例如，多晶硅层)的多层堆栈以形成带图案导体-介电质形状(例如，多晶硅-氧化物形状)。这些带图案形状可包括，例如，下列各物中的任一或更多：在沟道区181上面位于第一半导体台面106a顶面上用于第一FET 110a的栅极120；在沟道区181上面位于第二半导体台面106b顶面上用于第二FET 110b的栅极；用于某些其他类型的半导体装置的栅极(未图示)；以及侧向位于相邻半导体台面之间的沟槽中的附加装置(例如，参考第二电阻器111，特别是，在沟槽1913的多晶硅电阻器)。
如上述，第一FET 110a与第二FET 110b，以及它们各自的栅极会以不同的方向定向。图13图标在沟道区181延伸越过第一FET 110a的长度及越过第二FET 110b的宽度的垂直横截面。如图中第二FET110b所示，视需要可光刻图案化及蚀刻栅极120以便具有在半导体台面的顶面上且横越沟道区181的第一部分123，以及在第一侧壁间隔体108上方侧向延伸且进入至少一邻近沟槽(例如，参考沟槽1933)的第二部分124。必要时，这允许栅极接触在绝缘体材料上方垂直对准，而不是直接在沟道区181上方。
应注意，带图案导体-介电质形状或彼等在沟槽1911-1914内的部分(例如，第二电阻器111或第二FET 110的栅极的第二部分124)可具有与半导体台面106a-c相同的高度(例如，从绝缘体层103的顶面测量)(如图示)，较小的高度，或较大的高度。更应注意，视需要，带图案导体-介电质形状或彼等在半导体台面顶面上的部分(例如，第一FET110a的栅极与第二FET 110b的栅极的第一部分123)可具有与带图案导体-介电质形状或彼等在沟槽内的部分(如图示)相同的厚度，或可在加工期间加以研磨以减少在半导体台面上面的高度(例如，通过减少最下面、中间及顶部硅层的顶面高度来实现所欲栅极高度及/或改善后续接触光刻焦深)。
IC结构100更可具有附加侧壁间隔体，其包括侧向紧邻带图案多晶硅介电质形状(亦即，栅极120及任何附加装置，例如第二电阻器111)的第二侧壁136的第二侧壁间隔体132，以及在沟槽1911-1914内侧向紧邻第一侧壁间隔体108(例如，在第一侧壁116对面)的第三侧壁间隔体133。该附加侧壁间隔体(亦即，第二侧壁间隔体132与第三侧壁间隔体133)，例如，可由氧化硅、氮氧化硅、碳氧化硅或任何其他合适介电质材料制成。因此，该附加侧壁间隔体可由与使用于第一侧壁间隔体108者相同的介电质材料或不同的介电质材料制成。
IC结构100更可包括只在半导体装置中的一些(例如，第一电阻器110c及第二电阻器111)上方的共形保护层140。此共形保护层140，例如，可由氮化硅制成，特别是，可由与第二侧壁间隔体132及第三侧壁间隔体133不同的介电质材料制成。如上文所详述的，此共形保护层140提供一些半导体装置(例如，电阻器110c及111)在加工其他半导体装置(例如，第一FET 110a及第二FET 110b)期间(例如，在自对准硅化物形成期间等等)的保护。
应了解，图13非意图具有限制性。如上述IC结构100可包括使用一或更多半导体台面106a-106c形成的一或更多半导体装置，以及视需要，在沟槽1911-1914中的至少一者内的一或更多附加装置，以便侧向位于两个相邻半导体台面之间。因此，IC结构100可包括使用半导体台面形成的一或更多主动装置(例如，场效应晶体管(FET)、双极型接面晶体管(BJT)、异质接面双极晶体管(HBT)等等)及/或一或更多被动装置(例如，电阻器、电容器、二极管等等)的不同组合，而不是如以上所述方式组配且图示于图13的。另外或替换地，IC结构100可不包括在沟槽内的附加装置(例如，多晶硅电阻器)或在同一个或不同沟槽内有相同或不同类型的多个附加装置。另外，尽管只图示使用各半导体台面形成的单一半导体装置，然而IC结构100可包括使用同一个半导体台面形成的多个半导体装置。
在任何情形下，IC结构100更可包括至少一中段(MOL)介电层。例如，MOL介电层可包括覆盖半导体装置110a-c及任何附加装置111的共形蚀刻停止层150以及在共形蚀刻停止层150上的毯覆层间介电质(ILD)层160。共形蚀刻停止层150，例如，可由氮化硅制成。毯覆ILD层160可由氧化硅或任何其他合适ILD材料制成(例如，硼磷硅玻璃(BPSG)、正硅酸乙酯(TEOS)、氟化正硅酸乙酯(FTEOS)等等)。
如以上在说明该方法时所述，在形成装置后，在侧向邻接半导体装置110a-c及/或含有附加装置111的沟槽1911-1914中，可沉积MOL介电层于其任何残留空间中。因此，MOL介电层的一部分(亦即，共形蚀刻停止层150及毯覆ILD层160(取决于可用空间)的一部分)可在沟槽1911-1914中的至少一些内。例如，该MOL介电层，包括共形蚀刻停止层150及毯覆ILD层160，可填满在给定沟槽内的相对大空间，致使所产生的STI包含共形蚀刻停止层150与ILD层160两者的一部分(例如，参考沟槽1911-1912及1914)。不过，当在装置形成后残留在给定沟槽内的给定空间大小相对小(例如，浅或窄)时，共形蚀刻停止层150可完全填满该空间，致使所产生的STI不包含ILD层160的任何部分(例如，参考沟槽1913)。此外，如果残留在给定沟槽内的给定空间的深宽比相对高，共形蚀刻停止层150或ILD层160可能在该沟槽的顶端发生夹止，致使在该沟槽内产生空洞(未图示)。
因此，IC结构100可具有至少一STI区，其包括：视需要的氧化硅衬里107，在衬里上侧向邻接相邻半导体台面的侧壁116的第一侧壁间隔体108；侧向邻接第一侧壁间隔体108的第三侧壁间隔体133；共形蚀刻停止层150；以及填满任何残留空间的毯覆ILD 160(例如，参考在沟槽1911及1912中的STI区)。另外或替换地，IC结构100可具有其中有些或全部有相同特征的至少一STI区以及嵌在其中的附加装置(例如，参考嵌入沟槽1913中的STI区的第二电阻器111)。
应了解，用于本文的术语是只为了要描述该揭示结构及方法而非旨在限制。例如，如本文所使用的，英文单数形式“一(a)”、“一(an)”、及“该(the)”旨在也包括复数形式，除非上下文中另有明确指示。另外，如本文所使用的，用语“包含(comprises)”及/或“包含(comprising)”、或者“包括(includes)”及/或“包括(including)”具体描述提及的特征、整数、步骤、操作、组件及/或组件的存在，但不排除存在或加入一或更多其他特征、整数、步骤、操作、组件及/或彼等的群组。此外，如本文所使用的，诸如“右”、“左”、“垂直”、“水平”、“顶部”、“底部”、“上”、“下”、“底下”、“下面”、“下层”、“上面”，“上覆”、“平行”、“垂直”之类的用语旨在描述彼等在定向及图示于附图中(除非另有明示)时的相对位置，以及诸如“接触”、“直接接触”、“抵接”、“直接邻接”、“紧邻”之类的用语旨在表示至少一组件实体接触另一组件(没有其他组件隔开所述组件)。如本文所使用的，词组“侧向位于”指按照在图中的取向，一组件位在另一组件的一侧，而不是在该另一组件的上方或下方。下列权利要求书中所有手段或步骤加上功能组件的对应结构、材料、动作及等效物旨在包括与如权利要求书所主张的其他组件结合用以完成功能的任何结构、材料或动作。
为了图解说明已呈现本揭示内容的各种具体实施例的描述，但是并非旨在穷尽或限定于所揭示的具体实施例。本领域一般技术人员明白仍有许多修改及变体而不脱离所述具体实施例的范畴及精神。使用于本文的术语经选定成可最好地解释具体实施例的原理、实际应用或优于在市上可找到的技术的技术改善，或使得本领域一般技术人员能够了解揭示于本文的具体实施例。

Claims (15)

1.一种形成集成电路结构的方法，包含：
在一半导体层中形成数个沟槽以界定至少一半导体台面，该半导体台面具有数个第一侧壁；
形成在该沟槽内且侧向邻接该半导体台面的该第一侧壁的数个第一侧壁间隔体；
在该第一侧壁间隔体的该形成步骤之后且在完全填满该沟槽之前，使用该半导体台面形成一装置，其中，形成该装置包含：
形成具有第一部分与第二部分的栅极，该第一部分在该半导体台面的顶面上，该第二部分在该半导体台面的一侧上的一个该第一侧壁间隔体上方侧向延伸且进入该数个沟槽中的一个；及
形成数个第二侧壁间隔体与一第三侧壁间隔体，其中，该第二侧壁间隔体侧向邻接该栅极的该第一部分与该第二部分的第二侧壁，且其中，该第三侧壁间隔体侧向邻接该半导体台面的在该栅极的该第二部分对面的另一侧上的另一个该第一侧壁间隔体；以及
沉积一毯覆层间介电层，其中，该第一侧壁间隔体与该毯覆层间介电层包含不同的介电质材料。
2.如权利要求1所述的方法，其中，该第一侧壁间隔体包含氮化硅。
3.如权利要求1所述的方法，其中，该毯覆层间介电层的该沉积步骤更包含：沉积该毯覆层间介电层于该数个沟槽内且于该装置上面。
4.如权利要求1所述的方法，更包含，在该毯覆层间介电层的该沉积步骤之前，形成一共形蚀刻停止层于该装置上方且于该数个沟槽内，其中，该共形蚀刻停止层包含与该毯覆层间介电层不同的介电质材料。
5.如权利要求1所述的方法，
其中，该第二侧壁间隔体及该第三侧壁间隔体包含与该第一侧壁间隔体不同的介电质材料。
6.一种形成集成电路结构的方法，包含：
提供一绝缘体上覆半导体晶片，其包含衬底、在该衬底上的半导体层，以及在该半导体层上的绝缘体层；
在该半导体层中形成数个沟槽以在该绝缘体层上界定多个半导体台面，其中，该半导体台面具有数个第一侧壁；
在该沟槽内形成侧向邻接该半导体台面的该第一侧壁的数个第一侧壁间隔体；
在该第一侧壁间隔体的该形成步骤之后，使用该半导体台面形成数个装置，其中，形成该数个装置包含：
使用第一半导体台面形成至少一场效应晶体管以及使用第二半导体台面形成第一电阻器，其中，该至少一场效应晶体管包含具有第一部分与第二部分的栅极，该第一部分在该第一半导体台面的顶面上，该第二部分在该第一半导体台面的一侧上的一个第一侧壁间隔体上方侧向延伸且进入该数个沟槽中的一个，且在该装置的该形成步骤期间，在侧向位于相邻半导体台面之间的沟槽内形成一附加装置，其中，形成该附加装置包含形成第二电阻器；及
形成数个第二侧壁间隔体与数个第三侧壁间隔体，其中，该第二侧壁间隔体侧向邻接该第二电阻器与该栅极的该第一部分与该第二部分的第二侧壁，且其中，该第三侧壁间隔体侧向邻接该第二半导体台面的该第一侧壁间隔体且侧向邻接该第一半导体台面的在该栅极的该第二部分对面的另一侧上的另一个该第一侧壁间隔体；以及
沉积一毯覆层间介电层，其中，该第一侧壁间隔体与该层间介电层包含不同的介电质材料。
7.如权利要求6所述的方法，其中，该第一侧壁间隔体包含氮化硅。
8.如权利要求6所述的方法，其中，该毯覆层间介电层的该沉积步骤更包含：沉积该毯覆层间介电层于该沟槽中的至少一些内且于该附加装置及该装置上面。
9.如权利要求6所述的方法，更包含，在该毯覆层间介电层的该沉积步骤之前，沉积共形蚀刻停止层，其中，该共形蚀刻停止层包含与该毯覆层间介电层不同的介电质材料。
10.如权利要求6所述的方法，
其中，该装置的该形成步骤和该附加装置的该形成步骤包含：
沉积一氧化硅层；
沉积一多晶硅层于该氧化硅层上以形成一多层堆栈；以及
图案化该多层堆栈以形成多晶硅-氧化硅形状，该多晶硅-氧化硅形状包括：
在该第一半导体台面的该顶面上用于该场效应晶体管的该栅极；以及
该第二电阻器，以及
其中，该第二侧壁间隔体及该第三侧壁间隔体包含与该第一侧壁间隔体不同的介电质材料；其中，该方法更包含：
形成一保护层于该第一电阻器及该第二电阻器上方；
执行一掺杂物植入工艺以在该第一半导体台面中形成用于该场效应晶体管的源极/漏极区；以及，
形成数个硅化物层于该源极/漏极区上。
11.一种集成电路结构，包含：
数个沟槽，垂直延伸穿过一半导体层，该沟槽界定至少一半导体台面；
数个第一侧壁间隔体，在该沟槽内侧向邻接该至少一半导体台面的数个第一侧壁；
至少一装置，包含该至少一半导体台面，其中，该至少一装置包含电阻器与包含栅极的场效应晶体管，该栅极具有第一部分与第二部分，该第一部分在该半导体台面的顶面上，该第二部分在该半导体台面的一侧上的一个该第一侧壁间隔体上方侧向延伸且进入该数个沟槽中的一个；
数个第二侧壁间隔体，侧向邻接该栅极的该第一部分与该第二部分的第二侧壁；
数个第三侧壁间隔体，侧向邻接该电阻器的该第一侧壁间隔体且侧向邻接该半导体台面的在该栅极的该第二部分对面的另一侧上的另一个该第一侧壁间隔体；以及
毯覆层间介电层，在该至少一装置上方，其中，该第一侧壁间隔体与该毯覆层间介电层包含不同的介电质材料。
12.如权利要求11所述的集成电路结构，
其中，该第一侧壁间隔体包含氮化硅，
其中，该毯覆层间介电层在该沟槽中的至少一些内，
其中，该集成电路结构更包含在该至少一装置与该毯覆层间介电层之间的一共形蚀刻停止层，以及
其中，该共形蚀刻停止层包含与该毯覆层间介电层不同的介电质材料。
13.如权利要求11所述的集成电路结构，
其中，该第二侧壁间隔体及该第三侧壁间隔体包含与该第一侧壁间隔体不同的介电质材料。
14.如权利要求11所述的集成电路结构，更包含在相邻半导体台面之间的该沟槽中的一者内的一附加装置。
15.如权利要求14所述的集成电路结构，其中，该附加装置包含一多晶硅电阻器。
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