TW201830637A - 半導體裝置及方法 - Google Patents

半導體裝置及方法 Download PDF

Info

Publication number
TW201830637A
TW201830637A TW106134972A TW106134972A TW201830637A TW 201830637 A TW201830637 A TW 201830637A TW 106134972 A TW106134972 A TW 106134972A TW 106134972 A TW106134972 A TW 106134972A TW 201830637 A TW201830637 A TW 201830637A
Authority
TW
Taiwan
Prior art keywords
substrate
rdl
polymer layer
layer
connectors
Prior art date
Application number
TW106134972A
Other languages
English (en)
Other versions
TWI660482B (zh
Inventor
林俊成
吳集錫
余振華
蔡柏豪
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201830637A publication Critical patent/TW201830637A/zh
Application granted granted Critical
Publication of TWI660482B publication Critical patent/TWI660482B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1143—Manufacturing methods by blanket deposition of the material of the bump connector in solid form
    • H01L2224/11436—Lamination of a preform, e.g. foil, sheet or layer
    • H01L2224/1144—Lamination of a preform, e.g. foil, sheet or layer by transfer printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13105—Gallium [Ga] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本發明實施例係關於一種半導體裝置，其包含：一基板；一第一重佈層(RDL)，其在該基板一第一側上方；一或多個半導體晶粒，其或其等在該第一RDL上方且電耦合至該第一RDL；及一囊封劑，其在該第一RDL上方且圍繞該一或多個半導體晶粒。該半導體裝置亦包含附接至與該第一側相對之該基板之一第二側的連接器，該等連接器電耦合至該第一RDL。該半導體裝置進一步包含：一聚合物層，其在該基板之該第二側上，該等連接器在位於該基板遠端之該聚合物層之一第一表面上方自該聚合物層突出。接觸該等連接器之該聚合物層之一第一部分具有一第一厚度，且在相鄰連接器之間之該聚合物層之一第二部分具有小於該第一厚度之一第二厚度。

Description

半導體裝置及方法
本發明實施例係有關半導體裝置及方法。
歸因於各種電子組件(例如，電晶體、二極體、電阻器、電容器等)之整合密度之持續改良，半導體產業已經歷快速增長。對於大部分而言，整合密度之此改良源自最小構件大小之重複減小(例如，使半導體程序節點朝向次20 nm節點縮小)，其允許更多組件被整合於一給定區域中。隨著最近對微型化、更高速度及更大頻寬以及更低功率消耗及延遲之需求已增長，愈來愈需要更小且更創新之半導體晶粒之封裝技術。 隨著半導體技術進一步進步，堆疊及接合半導體裝置已作為進一步減小一半導體裝置之實體大小之一有效替代品出現。在一堆疊半導體裝置中，主動電路(諸如邏輯、記憶體、處理器電路及類似者)至少部分製造於單獨基板上，且接著實體且電接合在一起以形成一功能裝置。歸因於堆疊半導體裝置中使用之不同材料之熱膨脹係數(CTE)的差異，可發生堆疊半導體裝置之翹曲，其可不利地影響半導體裝置之功能性。若未經補償，則半導體裝置之嚴重翹曲可導致裝置故障及/或負面地影響半導體製程之產率。
本發明的一實施例係關於一種半導體裝置，其包括：一基板；一第一重佈層(RDL)，其在該基板之一第一側上方；一或多個半導體晶粒，其或其等在該第一RDL上方且電耦合至該第一RDL；一囊封劑，其在該第一RDL上方且圍繞該一或多個半導體晶粒；連接器，其等附接至與該第一側相對之該基板之一第二側，該等連接器電耦合至該第一RDL；及一聚合物層，其在該基板之該第二側上，該等連接器在位於該基板遠端之該聚合物層之一第一表面上方自該聚合物層突出，其中接觸該等連接器之該聚合物層之一第一部分具有一第一厚度，且在相鄰連接器之間之該聚合物層的一第二部分具有小於該第一厚度之一第二厚度。 本發明的一實施例係關於一種方法，其包括：接納一中介層，其中該中介層包括：第一基板；一第一重佈層(RDL)，其在該第一基板之一第一側上方；及複數個外部連接器，其等在與該第一側相對之該第一基板之一第二側上，該複數個外部連接器電耦合至該第一RDL；將複數個晶粒附接至該中介層之該第一RDL；使用一第一介電材料填充該中介層與該複數個晶粒之間之一間隙；及在將該中介層附接至一第二基板之前，將一第二介電材料施配在該第一基板之該第二側上而不覆蓋該複數個外部連接器之頂部表面。 本發明的一實施例係關於一種方法，其包括：接納一中介層，該中介層包括：一第一重佈層(RDL)，其在一基板之一第一側上方；及複數個外部連接器，其等附接至與該第一側相對之該基板之一第二側；將複數個晶粒附接至該第一RDL；使用一底膠材料填充該複數個晶粒與該第一RDL之間之一間隙；在該第一RDL上方且圍繞該複數個晶粒及該底膠材料形成一模塑料；將一聚合物材料施配於該基板之該第二側上而不覆蓋位於該基板遠端之該複數個外部連接器之頂部表面；及固化該聚合物材料。
下列揭露提供用於實施所提供標的物之不同構件之許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露。當然，此等僅為實例且不旨在限制。舉例而言，在下列描述中一第一構件形成於一第二構件上方或上可包含其中該第一構件及該第二構件形成為直接接觸之實施例，且亦可包含其中額外構件可形成在該第一構件與該第二構件之間，使得該第一構件及該第二構件可不直接接觸之實施例。 此外，為便於描述，空間相對術語(諸如「底下」、「下方」、「下」、「上方」、「上」及類似者)在本文中可用以描述一個元件或構件與另一(些)元件或構件之關係，如圖中所繪示。除圖中描繪之定向之外，該等空間相對術語亦意欲涵蓋裝置在使用或操作中之不同定向。設備可以其他方式定向(旋轉90度或成其他定向)且可相應地同樣解釋本文中使用之空間相對描述詞。 圖1A繪示在一些實施例中之一半導體裝置100之一俯視圖。在圖1A中，一半導體晶粒111附接至一第一基板123之一第一側。一或多個半導體晶粒(例如，113、113A、115、115A)附接至第一基板123之第一側，且相鄰於半導體晶粒111。如圖1A中所繪示，半導體晶粒111放置於第一基板123之一中心區域上方，且半導體晶粒113、113A、115及115A放置於第一基板123之邊緣區域(例如，接近外部周邊之區域)上方。半導體晶粒111、113、113A、115及115A可為任何適合晶粒，諸如邏輯晶粒、DRAM晶粒、SRAM晶粒、此等晶粒之組合或類似者。另外，儘管半導體晶粒111、113、113A、115、115A可係相同類型之裝置(例如，所有晶粒皆係DRAM晶粒)，然其等可替代地係不同類型之晶粒。例如，半導體晶粒111可係一邏輯晶粒(諸如一晶片上系統(SoC)晶粒)，且半導體晶粒113、113A、115、115A可係記憶體晶粒(諸如高頻寬記憶體(HBM)晶粒)。半導體晶粒111、113、113A、115、115A亦可包括多個晶粒之一堆疊。可替代地利用任何適合組合之半導體晶粒及任何數目個半導體晶粒，且所有此等數目、組合及功能性完全旨在包含於實施例之範疇內。注意，為清晰起見，圖1A中未繪示底膠材料133及模塑料135 (參見圖1B)。 圖1B係圖1A中沿線A-A之半導體裝置100之一橫截面視圖。如圖1B中所繪示，半導體裝置100包含一中介層150，該中介層150包含：一第一基板123；一第一重佈層(RDL) 131，其在第一基板123之一第一側123U上；外部連接器125，其等在第一基板123之一第二側123L上；及導電路徑121 (例如，諸如貫穿基板通路(TSV)之導電路徑)，其在第一基板123中且將第一RDL 131與外部連接器125電耦合。 半導體晶粒111、113及115 (及半導體晶粒113A及115A，其等在圖1B之橫截面視圖中不可見)經由連接器(亦可稱為外部接點) 117 (例如，117A、117B及117C)實體且電耦合至第一RDL 131。一底膠材料(亦稱為一底膠填充) 133可填充半導體晶粒111、113、115與第一RDL 131之間之一間隙。如圖1B中所繪示，在第一基板123之第一側123U上方且圍繞半導體晶粒111、113、115及底膠材料133形成一模塑料135。底膠材料133及模塑料135可統稱為一囊封劑。在其中僅使用底膠材料133或僅使用模塑料135之實施例中，底膠材料133或模塑料135可統稱為一囊封劑。 仍參考圖1B，一聚合物層129形成於第一基板123之第二側123L上。儘管聚合物層129在下文之論述中用作為實例，然應瞭解其他適合(若干)介電層亦可用來取代聚合物層129且完全旨在包含於本揭露之範疇內。聚合物層129選擇性地形成於第一基板123之第二側123L上方(例如，在相鄰外部連接器125之間)而不覆蓋外部連接器125之頂部表面(例如，具有焊料127之表面)。例如，聚合物層129接觸外部連接器125之側壁，但不接觸或覆蓋外部連接器125之頂部表面。在所繪示實施例中，外部連接器125突出超出位於第一基板123遠端之聚合物層129之下表面。 儘管圖1B中未展示，然一介電層(例如，一鈍化層)可形成於第一基板123之第二側123L上方(例如，在第一基板123與外部連接器125之間)。此介電層亦可用來防止或減小金屬擴散(例如，外部連接器125之金屬之擴散)至第一基板123中，且可包括適合介電材料，諸如氧化矽、氮化矽、低介電係數介電質(諸如碳摻雜之氧化物)、極低介電係數介電質(諸如多孔碳摻雜之二氧化矽)、其組合或類似者。在一些實施例中，介電層可包括一聚合物材料，諸如低溫聚醯亞胺(PI)、聚苯并㗁唑(PBO)、其組合或類似者。可使用任何適合形成方法(諸如化學氣相沈積(CVD)、物理氣相沈積(PVD))來形成介電層。 在下文中描述半導體裝置100之細節。半導體晶粒111可包括一第二基板111S、在第二基板上之第一電組件(未個別地繪示)、第一金屬化層(在圖1B中藉由標記為112之單層表示)、一第一鈍化層(未展示)及第一外部接點117A (在圖1B中繪示為已接合至中介層150之導電墊132，下文進一步論述)。在一實施例中，第二基板111S可包括塊狀矽(摻雜或未摻雜)或一絕緣體上覆矽(SOI)基板之一主動層。通常，一SOI基板包括一半導體材料層，諸如矽、鍺、矽鍺、SOI、絕緣體上覆矽鍺(SGOI)或其組合。可使用之其他基板包含多層基板、梯度基板或混合定向基板。 第一電組件包括可用來產生針對半導體晶粒111之設計之所要結構及功能需求的多種主動裝置(例如，電晶體)及被動裝置(諸如電容器、電阻器、電感器)及類似者。可使用任何適合方法而在第二基板111S內或其上別處形成第一電組件。 第一金屬化層112形成於第二基板111S及第一電組件上方且經設計以連接各種第一電組件以形成功能電路。在一實施例中，第一金屬化層112係由介電材料及導電材料之交替層形成且可透過任何適合程序(諸如沈積、鑲嵌、雙鑲嵌等)而形成。在一實施例中，可存在藉由至少一個層間介電層(ILD)而與第二基板111S分離之四個金屬化層，但第一金屬化層112之精確數目取決於半導體晶粒111之設計。 第一鈍化層(未展示)可形成於第一金屬化層112上方，以便為下方結構提供一定程度之保護。第一鈍化層可係由一或多種適合介電材料製成，諸如氧化矽、氮化矽、低介電係數介電質(諸如碳摻雜之氧化物)、極低介電係數介電質(諸如多孔碳摻雜之二氧化矽)、此等之組合或類似者。儘管可透過諸如化學氣相沈積(CVD)之一程序形成第一鈍化層，然可利用任何適合程序。 導電墊102可形成於第一金屬化層112上方且與其電接觸。導電墊102可包括鋁，但可替代地使用其他材料，諸如銅。可使用一沈積程序(諸如濺鍍或鍍覆)以形成一材料層(未展示)而形成導電墊102，且接著可透過一適合程序(諸如光微影遮罩及蝕刻)移除該材料層之部分以形成導電墊102。然而，可利用任何其他適合程序來形成導電墊102。 第一外部接點117A可形成於導電墊102上以為第一金屬化層112及(例如)第一基板123上之第一RDL 131之間之接點提供導電區域。在一實施例中，第一外部接點117A可係諸如微凸塊之接點凸塊且可包括諸如錫之一材料或諸如銀或銅之其他適合材料。在其中第一外部接點117A係錫銲凸塊之一實施例中，可藉由初始透過任何適合方法(諸如蒸鍍、電鍍、印刷、銲料轉移、植球)形成一錫層而形成第一外部接點117A。一旦已在結構上形成一錫層，便可執行一回焊以便使材料塑形為具有約例如10 µm至100 µm之一直徑之所要凸塊形狀，但是可替代地利用任何適合大小。 然而，如一般技術者將認識到，儘管第一外部接點117A已在上文被描述為微凸塊，然此等僅旨在為闡釋性且不旨在限制實施例。實情係，可替代地利用任何適合類型之外部接點，諸如受控倒疊晶片連接(C4)凸塊、銅柱、一銅層、一鎳層、一無鉛(LF)層、一無電鎳無電鈀浸金(ENEPIG)層、一Cu/LF層、一Sn/Ag層、一Sn/Pb、此等之組合或類似者。可針對第一外部接點117A利用任何適合外部連接器及用於形成外部連接器之任何適合程序，且所有此等外部連接器完全旨在包含於實施例之範疇內。 半導體晶粒113可包括一第三基板113S、第二電組件(圖1B中未個別地繪示)、第二金屬化層(圖1B中藉由標記為114之單層表示)、一第二鈍化層(未展示)及第二外部接點117B。在一實施例中，第三基板113S、第二電組件、第二金屬化層114、第二鈍化層及第二外部接點117B可分別類似於第二基板111S、第一電組件、第一金屬化層112、第一鈍化層及第一外部接點117A，但是其等可替代地係由不同程序形成之不同材料。例如，各種裝置及層之精確安置及形成將至少部分取決於半導體晶粒113之所要功能性。 半導體晶粒115可包括一第四基板115S、第三電組件(圖1B中未個別地繪示)、第三金屬化層(圖1B中藉由標記為116之單層表示)、一第三鈍化層(未展示)及第三外部接點117C。在一實施例中，第四基板115S、第三電組件、第三金屬化層116、第三鈍化層及第三外部接點117C可分別類似於第二基板111S、第一電組件、第一金屬化層112、第一鈍化層及第一外部接點117A，但是其等可替代地係由不同程序形成之不同材料。例如，各種裝置及層之精確安置及形成將至少部分取決於半導體晶粒115之所要功能性。 觀看中介層150，第一基板123可係(例如)一矽基板(摻雜或未摻雜)或一絕緣體上覆矽(SOI)基板之一主動層。然而，第一基板123可替代地係可提供一適合保護及/或互連功能性之一玻璃基板、一陶瓷基板、一聚合物基板或任何其他基板。此等及任何其他適合材料可替代地用於第一基板123。 在一些實施例中，第一基板123可包含電組件，諸如電阻器、電容器、信號分佈電路、此等之組合或類似者。此等電組件可係主動的、被動的或其組合。在其他實施例中，第一基板123中不含主動及被動電組件兩者。所有此等組合完全旨在包含於實施例之範疇內。 另外，在一些實施例中，在製程中之此階段，第一基板123係一半導體晶圓，諸如一十二英寸半導體晶圓。例如，第一基板123可延伸超出圖1B中所繪示之邊界以包含額外部分，該等額外部分亦將包括(例如)用於製造額外結構之TSV。因而，當半導體晶粒(例如，半導體晶粒111、113及115)接合至第一基板123時，經組合結構將在一晶圓上晶片(CoW)組態中。 導電路徑121可係TSV或任何其他適合導電路徑。在其中導電路徑121係TSV之實施例中，可藉由以下形成TSV：初始形成部分穿過第一基板123之導電路徑，接著稍後薄化第一基板123以曝露導電路徑。在其他實施例中，導電路徑121在初始形成時延伸穿過第一基板123，且無需第一基板123之薄化。可藉由以下形成導電路徑121：在第一基板123上形成一適合光阻劑或一硬遮罩；圖案化該光阻劑或該硬遮罩；及接著蝕刻第一基板123以產生開口(例如，TSV開口)。 一旦已形成針對導電路徑121之開口，便可使用例如一襯層(圖1B中未單獨繪示)、一阻障層(圖1B中亦未單獨繪示)及一導電材料填充開口。在一實施例中，襯層可係由一程序(諸如化學氣相沈積、氧化、物理氣相沈積、原子層沈積或類似者)形成之一介電材料(諸如氮化矽、氧化矽、一介電聚合物、此等之組合或類似者)。 阻障層可包括諸如氮化鈦之一導電材料，但是可替代地利用其它材料，諸如氮化鉭、鈦、另一介電質或類似者。可使用一CVD程序(諸如電漿輔助CVD (PECVD))形成阻障層。然而，可替代地使用其他替代程序，諸如濺鍍或金屬有機化學氣相沈積(MOCVD)、原子層沈積(ALD)。阻障層可經形成以便輪廓化為導電路徑121之開口之下方形狀。 導電材料可包括銅，但是可替代地利用其他適合材料，諸如鋁、鎢、合金、摻雜多晶矽、其組合及類似者。可藉由以下形成導電材料：沈積一晶種層且接著將銅電鍍至該晶種層上，填充且過填充導電路徑121之開口。一旦已填充導電路徑121之開口，便可透過諸如化學機械拋光(CMP)之一研磨程序移除開口外側之過量阻障層及過量導電材料，但是可使用任何適合移除程序。 一旦已形成導電路徑121，便可在第一基板123之第一側123U上形成第一重佈層(RDL) 131，以便在導電路徑121、外部接點117及半導體晶粒111、113及115之間提供互連性。第一RDL 131包括放置於第一RDL 131之一或多個介電層中之導電構件(導電線及/或通路)。可使用用於在積體電路中形成互連結構之常用方法形成第一重佈層131之導電構件。在一實施例中，第一RDL 131之導電構件包括由一金屬(諸如鋁、銅、鎢、鈦或其組合)形成之至少一個導電層。可藉由以下形成至少一個導電層：形成一晶種層；使用一經圖案化光阻劑(未繪示)覆蓋該晶種層，且接著在該光阻劑之開口內在該晶種層上鍍覆金屬。一旦完成，便移除光阻劑及光阻劑下方之晶種層之部分，從而留下至少一個導電層，其可具有在約0.5 μm與約30 μm之間之一厚度，具有約5 μm之一寬度。第一RDL 131之一或多個介電層可包括氧化矽、氮化矽、低介電係數介電質(諸如碳摻雜之氧化物)、極低介電係數介電質(諸如多孔碳摻雜之二氧化矽)、此等之組合或類似者，且可透過諸如化學氣相沈積(CVD)、物理氣相沈積(PVD)或任何其他適合沈積方法之一程序形成。 在已形成第一RDL 131之後，可在第一RDL 131上方形成一選用第四鈍化層(未展示)，且可穿過第四鈍化層形成通路以提供對第一RDL 131之電接達。在一實施例中，第四鈍化層可係由一或多個適合介電材料製成，諸如氧化矽、氮化矽、低介電係數介電質(諸如碳摻雜之氧化物)、極低介電係數介電質(諸如多孔碳摻雜之二氧化矽)、低溫聚醯亞胺(PI)、聚苯并㗁唑(PBO)、此等之組合或類似者。可透過諸如化學氣相沈積(CVD)、旋轉塗覆及/或微影程序之程序形成第四鈍化層，但是可利用任何適合程序。 一旦已形成第一重佈層131 (及選用第四鈍化層，若形成)，導電墊132便可在第一基板123之第一側123U上形成於第一RDL 131上方且形成為與第一RDL 131電連接。導電墊132可包括鋁，但可替代地使用其他材料，諸如銅。可使用一沈積程序(諸如濺鍍)以形成一材料層(未展示)而形成導電墊132且接著可透過一適合程序(諸如光微影遮罩及蝕刻)移除該材料層之部分以形成導電墊132。然而，可利用任何其他適合程序來形成導電墊132。 儘管圖1B中未展示，然一第二RDL可形成於第一基板123之第二側123L上方且可透過(例如)導電路徑121電耦合至第一RDL 131。另外，一第五鈍化層(未展示)可形成在第二RDL上方。第二RDL及第五鈍化層之材料及形成方法可分別類似於第一RDL 131及第四鈍化層之材料及形成方法，且因此此處未重複細節。 接著，外部連接器125可形成於第一基板123之第二側123L上方且可透過(例如)導電路徑121電耦合至第一RDL 131。在其中一第二RDL及一第五鈍化層形成於第一基板123之第二側123L上方之情況中，外部連接器125形成於第五鈍化層上方且電耦合至第二RDL，該第二RDL繼而透過(例如)導電路徑121電耦合至第一RDL 131。在後續處理中，外部連接器125可(例如)藉由一回焊程序實體且電耦合至另一基板(未展示)，以形成基板上覆晶圓上覆晶片(CoWoS)結構。在所繪示實施例中，外部連接器125係具有在約20 µm與約70 µm之間(諸如40 µm)之一高度及約40 µm與約170 µm之間(諸如80 µm)之一寬度的銅柱。如圖1B中所繪示，焊料127形成於外部連接器125之頂部表面上且可具有在約10 µm與約50 µm之間之一高度。上文所繪示之外部連接器125及焊料127之尺寸僅係非限制性實例，外部連接器125及焊料127之任何其他適合尺寸係可行的且完全旨在包含於本揭露之範疇內。 在另一實施例中，外部連接器125可係諸如受控倒疊晶片連接(C4)凸塊之接點凸塊且可包括諸如錫之一材料及諸如銀或銅之其他適合材料。在其中外部連接器125係錫焊凸塊之一實施例中，可藉由初始透過任何適合方法(諸如蒸鍍、電鍍、印刷、銲料轉移、植球等)形成一錫層而形成外部連接器125。一旦已在結構上形成一錫層，便執行一回焊以便使材料塑形為具有(例如)約80 µm之一直徑之所要凸塊形狀。 然而，如一般技術者將認識到，儘管外部連接器125已在上文描述為C4凸塊，然此等僅旨在為闡釋性的且不旨在限制實施例。實情係，可替代地利用任何適合類型之外部接點，諸如微凸塊、銅柱、一銅層、一鎳層、一無鉛(LF)層、一無電鎳無電鈀浸金(ENEPIG)層、一Cu/LF層、一Sn/Ag層、一Sn/Pb、此等之組合或類似者。可針對外部連接器125利用任何適合外部連接器及用於形成外部連接器之任何適合程序，且所有此等外部連接器完全旨在包含於實施例之範疇內。 一旦準備就緒，便可使用(例如)一接合程序將半導體晶粒111、113及115接合至中介層150。在其中第一外部接點117係焊料微凸塊之一實施例中，可藉由以下執行接合程序：首先將第一外部接點117與其等各自導電墊132對準，且接著將第一外部接點117安置成與導電墊132實體接觸。一旦接觸，接著便可執行一回焊程序以便回焊第一外部接點117，藉此將第一外部接點117與導電墊132接合。 一旦接合，底膠材料133便可注入或以其他方式形成於中介層150與半導體晶粒111、113及115之間之空間中。第一底膠材料133可(例如)包括一液態環氧樹脂，其經施配於半導體晶粒111、113、115與第一基板123之間，且接著經固化以硬化。此第一底膠材料133可用於防止在第一外部接點117中形成裂紋，其中通常由熱應力導致裂紋。 如圖1B中所繪示，底膠填充133亦可填充在相鄰半導體晶粒之側壁之間的間隙119 (參見圖1A)。間隙119之大小(例如，寬度)之範圍可從約30 µm至約300 µm，且可針對各種設計需求及考慮進行調整。例如，較小間隙大小允許更高整合密度且導致半導體裝置100之較小大小，但可使用底膠填充133 (其可比模塑料135更昂貴)來填充間隙119。相反地，較大間隙大小允許使用模塑料135來填充間隙119，但可導致較大裝置大小，且可導致半導體裝置100之更大翹曲，如在下文更詳細論述。 取決於間隙119之大小，歸因於基於間隙119之大小之毛細管力，底膠填充133可延伸至半導體晶粒111、113及115之上表面，如圖1B之實例中所繪示。在其他實施例中，歸因於較寬間隙119 (因此較弱毛細管力)，底膠填充133延伸於半導體晶粒111、113及115 (未展示)之上表面下方。與模塑料135比較，底膠材料133可具有一更快流速、一均勻且無空隙流動圖案及一更快固化排程。另外，底膠材料133可能能夠填充具有模塑料135可能無法填充之小間隙大小(例如，具有介於約10 µm與60 µm之間之大小的間隙)之間隙(例如，間隙119或在中介層150與半導體晶粒111、113及115之間之間隙)。 接著，模塑料135形成於第一基板123之第一側123U上(例如，在第一RDL 131上方)。在一些實施例中，模塑料135圍繞半導體晶粒111、113、115及底膠材料133。模塑料135可包括(例如)環氧樹脂、一有機聚合物、添加或未添加二氧化矽基或玻璃填料之聚合物或其他材料。在一些實施例中，當適用時，模塑料135包括作為一凝膠型液體之一液體模塑料(LMC)。當適用時，模塑料135亦可包括一液體或固體。替代地，模塑料135可包括其他絕緣及/或囊封材料。在一些實施例中，使用一晶圓級成型程序來應用模塑料135。可使用(例如)壓縮成型、轉移成型、成型底膠填充(MUF)或其他方法來使模塑料135成型。 接著，在一些實施例中，使用一固化程序來固化模塑料135。固化程序可包括使用一退火程序或其他加熱程序將模塑料135加熱至一預定溫度達一預定時間段。固化程序亦可包括一紫外線(UV)光曝露程序、一紅外線(IR)能量曝露程序、其組合或其與一加熱程序之組合。替代地，可使用其他方法固化模塑料135。在一些實施例中，不包含一固化程序。 儘管圖1B展示填充中介層150與半導體晶粒111、113、115之間之間隙的底膠材料133，然若間隙大小大(例如，大於10 µm)，則可使用模塑料135取代底膠材料133來填充間隙。類似地，當間隙119之大小大(例如，大於40 µm)時，則模塑料135可取代底膠填充133 (圖1B中未展示)來填充間隙119。底膠填充133與模塑料135之不同組合係可行的且完全旨在包含於本揭露之範疇內。 歸因於模塑料135、底膠填充133及/或半導體裝置100中使用之其他材料的CTE之間之差異，可發生半導體裝置100之翹曲。例如，底膠材料133之CTE可介於約15百萬分率/度(ppm/ºC)至約200 ppm/ºC之間(諸如120 ppm/ºC)，且模塑料135之CTE可介於約4 ppm/ºC至約80 ppm/ºC之間(諸如26 ppm/ºC)。在圖1B之實例中，模塑料135放置於中介層150之邊緣區域103 (例如，接近中介層150之外部周邊之區域，諸如其中放置半導體晶粒113及115之區域)中且圍繞底膠材料133，因此在高溫(例如，高於200ºC)下，底膠材料133膨脹大於模塑料135，其可導致中介層150之邊緣區域103相對於中介層150之中心區域101 (例如，接近中介層150之中心之區域，諸如其中放置半導體晶粒111之區域)向下彎曲。在用以將半導體裝置100之外部連接器125耦合至另一基板(圖1B中未展示)之對應導電構件(例如，導電墊或連接器)以形成基板上覆晶圓上覆晶片(CoWoS)結構之一隨後回焊程序期間，上文所描述之翹曲可導致中心區域101中之冷焊點(cold joint)及/或邊緣區域103中之銲錫橋接(solder bridge)(例如，焊料連接相鄰外部連接器125，因此導致電短路)。冷焊點及銲錫橋接不利地影響CoWoS結構之可靠性且減小半導體製造之產率。如下文所論述，形成聚合物層129以減小半導體裝置100之翹曲且防止或減少冷焊點及/或銲錫橋接。 仍參考圖1B，聚合物層129形成於第一基板123之第二側123L上。聚合物層129選擇性地施配於第二側123L上方，例如在相鄰外部連接器125之間而不覆蓋外部連接器125之頂部表面(例如，具有焊料127之表面)。在一些實施例中，聚合物層129包括聚醯亞胺(PI)、聚苯并㗁唑(PBO)、樹脂、環氧樹脂、丙烯酸類聚合物、其組合或類似者。在一些實施例中，聚合物層129包括諸如具有一填充材料(例如，氧化矽)之環氧樹脂之一模塑料。在一實施例中，聚合物層129包括一底膠材料。在施配至第一基板123之第二側123L上時，聚合物層129可處於一液體狀態。可使用任何適合施配工具或方法(例如，噴射、施配)來形成聚合物層129。 聚合物層129之組合物、位置、厚度及/或體積可經調諧以達成一預定CTE及/或應力位準以抵消半導體裝置100之翹曲。例如，在其中底膠材料133之體積主導(例如，佔據大於總體積之約60%)底膠填充133及模塑料135之總體積之實施例中，聚合物層129之CTE及/或應力位準可經調諧(例如，藉由改變聚合物層129之組合物、位置、厚度及/或體積)以匹配底膠材料133之CTE及/或應力位準來補償半導體裝置100之翹曲。在一些實施例中，聚合物層129之體積或厚度經調整(例如，增大)以補償半導體裝置100之翹曲。作為另一實例，當聚合物層129之一體積小於底膠材料133之一體積時，聚合物層129之CTE及/或應力位準可經調諧成高於底膠材料133之CTE及/或應力位準以提供足夠補償來減小半導體裝置100之翹曲。作為又一實例，當使用模塑料135取代底膠材料133時，聚合物層129之CTE及/或應力位準可經調諧以匹配模塑料135之CTE及/或應力位準。 圖1C展示圖1B中之區域105之一放大視圖。在所繪示實例中，歸因於外部連接器125上之聚合物層129之濕潤，接觸外部連接器125之側壁之聚合物層129的一第一部分具有一高度H2 (亦稱為聚合物層129之一厚度H2)，及遠離外部連接器125 (在兩個相鄰外部連接器125之半途)之聚合物層129之一第二部分具有一高度H1 (亦稱為聚合物層129之一厚度H1)。高度H2大於高度H1，且位於第一基板123遠端之聚合物層129之下表面129U可具有接近外部連接器125之一圓形輪廓，如圖1C之實例中所繪示。高度H1及高度H2之值可取決於各種設計因素，例如外部連接器125之大小、聚合物層129之可濕性及用來補償使用聚合物層129之翹曲量。例如，在其中外部連接器125之高度(沿與H2相同之方向量測)係約40 µm之一實施例中，高度H1係介於約2 µm至約40 µm之間，及高度H2係介於約10 µm至約70 µm之間。高度H1及高度H2之其他尺寸係可行的且完全旨在包含於本揭露之範疇內。 儘管高度H2經展示為大於圖1C之實例中之高度H1，然在一些實施例中，取決於聚合物層129之材料及外部連接器125上之聚合物層129之可濕性，高度H2可與高度H1相同(例如，聚合物層129具有一均勻厚度)，且聚合物層129可具有接觸外部連接器125之側壁之一平坦上表面129F (參見虛線)。 在圖1B中，聚合物層129放置於在中心區域101及邊緣區域103中之第一基板123之第二側123L上。圖1D繪示另一實施例半導體裝置180，其類似於圖1B中之半導體裝置100但具有聚合物層129之不同位置。特定言之，半導體裝置180之聚合物層129放置於第一基板123之第二側123L之一第一部分上方，且第二側123L之一第二部分未被聚合物層129覆蓋(例如，曝露)。例如，在圖1D中，中心區域101不含聚合物層129(例如，未被其覆蓋)，且聚合物層129形成於邊緣區域103中。聚合物層129之此等及其他變動及/或修改係可行的且完全旨在包含於本揭露之範疇內。 在一些實施例中，聚合物層129之厚度(例如，圖1C中之高度H1)及位置(例如，圖1B及圖1D中之中心區域101及/或邊緣區域103)判定聚合物層129之體積。可變動聚合物層129之組合物、厚度及/或體積以達成一目標應力位準以抵消由(例如)底膠填充133及模塑料135導致之應力。在其中聚合物層129放置於中介層150之中心區域101及邊緣區域103兩者中之實施例中(參見圖1B)，聚合物層129之一厚度(例如，圖1C中之高度H1)可介於2 µm與40 µm之間，且聚合物層129之應力位準(例如，彈性模數)可介於1 GPa至約10 GPa之間。在其中聚合物層129放置於中介層150之邊緣區域103中之實施例中(參見圖1D)，聚合物層129之一厚度(例如，圖1C中之高度H1)可介於2 µm與40 µm之間，且聚合物層129之應力位準(例如，彈性模數)可介於1 GPa至約10 GPa之間。 圖2A至圖2D繪示根據一實施例之在各種製造階段之一半導體結構200的橫截面視圖。圖2A至圖2D中之相同數字指示與圖1B中相同之元件或結構，且圖2A至圖2D中具有後綴M之一數字指示包括圖1B中無後綴M之結構之一各自元件之多個複本的一組件或結構。例如，圖2A中之中介層150M包括複數個區域202、204及206，其中各區域對應於圖1B中之中介層150。 在圖2A中，提供一中介層150M。中介層150M包括一基板123M、一RDL層131M、導電路徑121 (例如，TSV或其他導電路徑)及外部連接器125 (例如，C4凸塊)。中介層150M具有複數個區域202、204及206。如將在下文更詳細描述，在一隨後切割程序(參見圖2D)之後，半導體結構200之區域(例如，202、204及206)之各者變為諸如圖1B中之半導體裝置100之一半導體裝置。 儘管圖2A中未展示，然一介電層(例如，一鈍化層)可形成於基板123M之一第二側123L上方，例如，在基板123M與外部連接器125之間。此介電層可用來防止或減小至基板123M中之金屬擴散(例如，外部連接器125之金屬之擴散)。關於此介電層之材料及形成方法之細節類似於上文參考圖1B所描述之材料及形成方法，因此在此處不重複。 為形成半導體結構200，在中介層150M之區域(例如，202、204及206)之各者中，半導體晶粒111、113及115透過連接器117 (例如，微凸塊)實體且電耦合至RDL 131M之對應部分。底膠填充133填充中介層150M與半導體晶粒111、113及115之間之間隙。在RDL 131M上方且圍繞半導體晶粒111、113及115及底膠填充133形成模塑料135。關於底膠填充133及模塑料135之材料及形成方法之細節類似於上文參考圖1B所描述之材料及形成方法，因此在此處不重複。 在圖2B中，一聚合物材料129'選擇性地沈積於基板123M上方(例如，在相鄰外部連接器125之間)，使得聚合物材料129'不覆蓋外部連接器125之上表面(例如，位於基板123M遠端之外部連接器125之表面)。聚合物材料129'之組合物可與上文圖1B中所描述之聚合物層129相同，因此在此處不重複細節。使用施配工具201施配聚合物材料129'。在一些實施例中，施配工具201具有內建加熱元件，使得聚合物材料129'在沈積時處於一液體狀態。在一些實施例中，施配工具201具有一內建UV光源，使得聚合物材料129'在沈積時處於一液體狀態。 經沈積聚合物材料129'在基板123M上方形成聚合物層129，如圖2C中所繪示。取決於外部連接器125上之聚合物層129之可濕性，聚合物層129可具有位於基板123M遠端之一平坦上表面129U，其中平坦上表面129U接觸外部連接器125之側壁，如圖2C中所繪示。在其他實施例中，聚合物層129之上表面可具有接近外部連接器125之一圓形輪廓(例如，類似於圖1C)，且聚合物層129可具有在遠離外部連接器125 (例如，在相鄰外部連接器125之半途)之一第一部分中之一第一高度H1及在接近外部連接器125 (例如，接觸其之外側)之一第二部分中之一第二高度H2，其中H2大於H1。上文參考圖1C論述高度H1及高度H2之尺寸，因此在此處不重複細節。 一旦形成聚合物層129，便執行一固化程序以完全固化聚合物層129。在一些實施例中，固化程序係在介於約130ºC至約250ºC之間(諸如180ºC)之一溫度下執行且執行達介於約30分鐘至約4小時之間(諸如90分鐘)之一時間間隔之一熱固化程序。在其他實施例中，執行一紫外線(UV)固化程序以固化聚合物層129。可使用具有介於約300 nm至約396 nm之間之一波長的UV光執行UV固化程序，且UV固化程序之一時間間隔可介於約5秒至約180秒之間。上文固化程序僅係實例，其他固化程序及方法亦係可行的且完全旨在包含於本揭露之範疇內。 在其他實施例中，執行一固化程序以部分固化聚合物層129。例如，執行一UV固化程序以部分固化聚合物層129。部分UV固化程序可使用與上文所論述之完全UV固化程序相同之波長但其與不同之一時間間隔。例如，可調整(例如，縮短) UV固化程序之時間間隔以達成不同固化位準(例如，完全固化或部分固化)。類似地，可使用一熱固化程序以部分固化聚合物層129。可修改上文所論述之完全熱固化程序之溫度及/或持續時間(例如，降低溫度及/或縮短持續時間)，以達成不同固化位準。可在一隨後回焊程序(例如，用以將半導體裝置100之外部連接器125附接至另一基板以形成一CoWoS結構之一回焊程序)中進一步固化經部分固化聚合物層129，因此聚合物層129可在隨後回焊程序之後完全固化。 接著，在圖2D中，在固化程序之後，例如，使用切割工具205 (其可係一切割刀片或一雷射切割工具)沿不同區域(例如，圖2A中之202、204、206)之邊界切割半導體結構200。在切割程序之後，形成複數個半導體裝置100 (亦參見圖1B)。注意，在各種實施例中，在形成中介層(例如，中介層150)之外部連接器(例如，圖1B中之125、圖3B中之305及圖5C中之507)之後且在將中介層附接至另一基板(例如，以形成一CoWoS結構)之前形成聚合物層129。 圖2D展示放置於各半導體裝置100之中心區域及邊緣區域上方之聚合物層129。在一些實施例中，聚合物層129可形成於各半導體裝置100之各區域上方，且各半導體裝置100之中心區域不含聚合物層129(例如，未被其覆蓋)，類似於圖1D。對聚合物層129之此等及其他變動及/或修改係可行的且完全旨在包含於本揭露之範疇內。 圖3A至圖3C繪示根據一實施例之在各種製造階段之一半導體裝置300的橫截面視圖。為簡單起見，圖3A至圖3C僅繪示一個半導體裝置300，其中理解數十個、數百個或甚至數千個半導體裝置300可形成於一中介層上且隨後經單粒化以形成複數個半導體裝置300。圖3A至圖3C中之相同數字指示與圖1B中相同之元件或結構。除非另外描述，否則具有相同數字之元件或結構係由相同材料並使用相同形成方法形成，因此不重複細節。 在圖3A中，形成一半導體裝置300。半導體裝置300類似於圖1B中之半導體裝置100，惟在圖3A中，外部連接器305係由焊料形成且未形成聚合物層129除外。可藉由以下步驟形成外部連接器305：首先在第一基板123之第二側123L上方沈積一光阻劑(未展示)；圖案化該光阻劑以在其中待形成外部連接器305之位置處形成開口；及使用適合沈積方法(諸如鍍覆)在該等開口中形成焊料。在所繪示實例中，外部連接器305之各者具有平坦(例如，筆直)側壁305S，且因此在一外部連接器305之兩個相對側壁305S之間的一寬度自接觸第一基板123之側壁305S之一第一端至位於第一基板123之側壁305S遠端之一第二端保持實質上均勻。 如圖3A中所繪示，使用施配工具201將一聚合物材料129'選擇性地施配於第一基板123之第二側123L上方而不覆蓋外部連接器305之頂部表面305T，例如在相鄰外部連接器305之間及/或緊靠外部連接器305。經沈積聚合物材料129'形成聚合物層129，如圖3B中所展示。 接著，如圖3B中所繪示，藉由一固化程序303固化(例如，完全固化或部分固化)聚合物層129。在一些實施例中，固化程序303係經執行以完全固化聚合物層129之一UV固化程序。可使用具有介於約300 nm至約396 nm之間之一波長的UV光執行UV固化程序且執行UV固化程序介於約5秒至約180秒之間之一時間間隔以完全固化聚合物層129。在其他實施例中，執行一UV固化程序以部分固化聚合物層129，及一隨後回焊程序完成聚合物層129之固化。部分UV固化程序可使用與完全UV固化程序相同之波長但與其不同之一時間間隔。例如，可調整(例如，縮短) UV固化程序之時間間隔以達成不同固化位準(例如，完全固化或部分固化)。在固化程序303 (一部分UV固化程序或一完全UV固化程序)之後，聚合物層129在一隨後回焊程序期間硬化且為外部連接器305提供支撐及/或約束。在上文之論述中，UV固化用作為固化程序303之一非限制性實例。其他適當固化程序亦可使用且完全旨在包含於本揭露之範疇內。 接著，在圖3C中，執行一回焊程序307。回焊程序307熔化外部連接器305 (在所繪示實例中，其等係由焊料製成)。歸因於熔化焊料之表面張力，在回焊程序307完成之後，外部連接器305之第一部分305B (突出於聚合物層129上方之部分)具有一圓形輪廓(例如，一球體或一球體之部分)。注意，歸因於藉由經硬化(例如，部分固化或完全固化)聚合物層129提供之約束，在回焊程序307完成之後，外部連接器305之第二部分305A (在第一部分305B與第一基板123之間之外部連接器305的部分)維持平坦(例如，筆直)側壁。在其中藉由固化程序303部分固化聚合物層129之實施例中，回焊程序307亦完成固化程序，且因此在回焊程序307之後，完全固化聚合物層129。 圖3B及圖3C繪示在第一基板123之第二側123L上方形成且覆蓋半導體裝置300之中心區域及邊緣區域之聚合物層129。在其他實施例(未展示)中，聚合物層129形成於半導體裝置300之邊緣區域中，且半導體裝置300之中心區域不含聚合物層129，類似於圖1D。對聚合物層129之此等及其他變動及/或修改係可行的且完全旨在包含於本揭露之範疇內。 圖4繪示圖3C中之區域309之一放大視圖。如圖4中所繪示，外部連接器305之第一部分305B具有一寬度W2，該寬度W2大於外部連接器305之第二部分305A之一寬度W1。在一些實施例中，寬度W2係在介於約80 µm至約120 µm之間之一範圍中，且寬度W1係在介於約40 µm至約80 µm之間之一範圍中。 在圖4之實例中，歸因於外部連接器305上之聚合物層129之濕潤，接觸外部連接器305之側壁之聚合物層129的一第一部分具有一高度H4 (亦稱為聚合物層129之一厚度H4)，及遠離外部連接器305(例如，在兩個相鄰外部連接器305之半途)之聚合物層之一第二部分具有一高度H3 (亦稱為聚合物層129之一厚度H3)。高度H4大於高度H3，且位於第一基板123遠端之聚合物層129之下表面可具有接近外部連接器305之一圓形輪廓，如圖4之實例中所繪示。高度H3及高度H4之值可取決於各種設計因素，例如，外部連接器305之大小、聚合物層129之可濕性及用來補償使用聚合物層129之翹曲量。例如，在其中外部連接器305之高度(沿與H3相同之方向量測)係約70 µm之一實施例中，高度H3係介於約2 µm至約40 µm之間，及高度H4係介於約10 µm至約70 µm之間。高度H3及高度H4之其他尺寸係可行的且完全旨在包含於本揭露之範疇內。 儘管高度H4經展示為大於圖4之實例中之高度H3，然在一些實施例中，取決於聚合物層129之材料及外部連接器305上之聚合物層129之可濕性，高度H4可與高度H3相同，且聚合物層129可具有接觸外部連接器305之側壁之一平坦上表面129F (參見虛線)。 圖5A至圖5C繪示在一些實施例中之在各種製造階段之一半導體裝置500的橫截面視圖。為簡單起見，圖5A至圖5C僅繪示一個半導體裝置，其中理解數十個、數百個或甚至數千個半導體裝置500可形成於一中介層上且隨後經單粒化以形成複數個半導體裝置500。圖5A至圖5C中之相同數字指示與圖1B中相同之元件或結構。除非另外描述，否則具有相同數字之元件或結構係由相同材料且使用相同形成方法形成，因此不重複細節。 在圖5A中，形成一半導體裝置500。在施配聚合物材料129'之前，半導體裝置500類似於圖3A中之半導體裝置300，此處不重複細節。 接著，在圖5B中，執行一回焊程序501。作為回焊程序501之一結果，在回焊程序完成之後，由焊料製成之外部連接器305熔化及再固化。歸因於熔化焊料之表面張力，在回焊程序之後，外部連接器305之輪廓改變成一圓形輪廓(例如，一球體或一球體之部分)。在回焊程序501之後，外部連接器305在下文中指示為外部連接器507。 接著，如圖5C中所繪示，使用施配工具201將聚合物材料129'選擇性地施配於第一基板123之第二側123L上方而不覆蓋外部連接器507之頂部表面507T，例如，在相鄰外部連接器507之間及/或緊靠外部連接器507。經沈積聚合物材料129'形成聚合物層129。 一旦形成聚合物層129，便可執行一固化程序(諸如UV固化或熱固化)以固化聚合物層129。在一些實施例中，固化程序係在介於約130ºC至約250ºC之間(諸如180ºC)之一溫度下執行且執行達介於約30分鐘至約4小時之間(諸如90分鐘)之一時間間隔之一熱固化程序。在其他實施例中，執行一UV固化程序以固化聚合物層129。可使用具有介於約350 nm至約396 nm之間之一波長的UV光執行UV固化程序，且針對UV固化程序之一時間間隔可介於約5秒至約180秒之間。上文之固化程序僅係實例，其他固化程序及方法亦係可行的且完全旨在包含於本揭露之範疇內。 圖5C展示形成於第一基板123之第二側123L上方且覆蓋半導體裝置500之中心區域及邊緣區域之聚合物層129。在其他實施例(未展示)中，聚合物層129形成於半導體裝置500之邊緣區域中，且半導體裝置500之中心區域不含聚合物層129(例如，未被其覆蓋)，類似於圖1D。對聚合物層129之此等及其他變動及/或修改係可行的且完全旨在包含於本揭露之範疇內。 圖6展示圖5C中之區域505之一放大視圖。如圖6中所繪示，歸因於外部連接器507上之聚合物層129之濕潤，接觸外部連接器507之側壁之聚合物層129之一第一部分具有一高度H6，且遠離外部連接器507(例如，在兩個相鄰外部連接器507之半途)之聚合物層之一第二部分具有一高度H5。高度H6大於高度H5，且位於第一基板123遠端之聚合物層129之下表面可具有接近外部連接器507之一圓形輪廓，如圖6之實例中所繪示。高度H5及高度H6之值可取決於各種設計因素，例如，外部連接器507之大小、聚合物層129之可濕性及用來補償使用聚合物層129之翹曲量。例如，在其中外部連接器507之高度(沿與H2相同之方向量測)係約70 µm之一實施例中，高度H5係介於約2 µm至約40 µm之間，且高度H6係介於約10 µm至約70 µm之間。針對高度H5及高度H6之其他尺寸係可行的且完全旨在包含於本揭露之範疇內。 儘管高度H6經展示為大於圖6之實例中之高度H5，然在一些實施例中，取決於聚合物層129之材料及在外部連接器507上之聚合物層129之可濕性，高度H6可與高度H5相同，且聚合物層129可具有接觸外部連接器507之側壁之一平坦上表面129F (參看虛線)。 圖7繪示無聚合物層129之一習知半導體裝置與具有聚合物層129之一實施例裝置之間的效能比較。特定言之，曲線601對應於習知裝置，且曲線603對應於具有聚合物層129之實施例裝置(例如，半導體裝置100、300或500)。x軸表示溫度(其自室溫上升至258ºC，接著下降回至室溫)，且y軸表示以微米(µm)為單位之翹度量。一正翹曲值指示半導體裝置之邊緣部分(例如，圖1B之區域103中之半導體裝置100的部分)相對於半導體裝置之中心部分(例如，圖1B之區域101中之半導體裝置100的部分)向上彎曲。相反地，一負翹曲值指示半導體裝置之邊緣部分相對於半導體裝置之中心部分向下彎曲。可藉由量測中心區域101與邊緣區域103中之外部連接器之頂部表面之間的距離而判定翹曲值。自圖7可看出，在室溫及高溫(例如，約258ºC)兩者下，實施例裝置皆具有小於習知裝置之翹曲。在圖7中，最差翹曲(例如，經量測翹曲之絕對值之最大值)係約60 µm。實施例裝置之減小翹曲指示半導體裝置上之較小應力、較低裝置故障率及改良之裝置效能。減小或防止冷焊點及/或焊點之橋接。 圖8繪示根據一些實施例之製造一半導體裝置之一方法1000的一流程圖。應瞭解，圖8中所展示之實施例方法僅係許多可能實施例方法之一實例。一般技術者將辨識許多變動、替代及修改。例如，可添加、移除、取代、重新配置及重複如圖8中所繪示之各種步驟。 參考圖8，在步驟1010處，提供一中介層。中介層包含：一第一重佈層(RDL)，其在一基板之一第一側上方；及複數個外部連接器，其等附接至與該第一側相對之該基板之一第二側。在步驟1020處，將複數個晶粒附接至第一RDL。在步驟1030處，使用一底膠材料填充複數個晶粒與第一RDL之間之一空間。在步驟1040處，在第一RDL上方且圍繞複數個晶粒及底膠材料形成一模塑料。在步驟1050處，藉由將一聚合物材料施配於基板之第二側上而不覆蓋位於基板遠端之複數個連接器之頂部表面而抵消底膠材料及模塑料之應力。在步驟1060處，固化聚合物材料。 本揭露之優點包含減小半導體裝置中之翹曲。減小的翹曲防止冷焊點及/或焊點之橋接。裝置可靠性改良，且半導體處理之產率改良。 在一些實施例中，一半導體裝置包含：一基板；一第一重佈層(RDL)，其在該基板之一第一側上方；一或多個半導體晶粒，其或其等在該第一RDL上方且電耦合至該RDL；及一囊封劑，其在該第一RDL上方且圍繞該一或多個半導體晶粒。半導體裝置亦包含附接至與該第一側相對之該基板之一第二側的連接器，該等連接器電耦合至該第一RDL。半導體裝置進一步包含：一聚合物層，其在該基板之該第二側上，該等連接器在位於該基板遠端之該聚合物層之一第一表面上方自該聚合物層突出，其中接觸該等連接器之該聚合物層之一第一部分具有一第一厚度，且在相鄰連接器之間之該聚合物層的一第二部分具有小於該第一厚度之一第二厚度。 在其他實施例中，一種方法包含接納一中介層，其中該中介層包含：一第一基板；一第一重佈層(RDL)，其在該第一基板之一第一側上方；及複數個外部連接器，其等在與該第一側相對之該第一基板之一第二側上，該複數個外部連接器電耦合至該第一RDL。方法進一步包含：將複數個晶粒附接至該中介層之該第一RDL；使用一第一介電材料填充該中介層與該複數個晶粒之間之一間隙；及在將該中介層附接至一第二基板之前，將一第二介電材料施配於該第一基板之該第二側上而不覆蓋該複數個外部連接器之頂部表面。 在又一實施例中，一種方法包含接納一中介層，該中介層具有：一第一重佈層(RDL)，其在一基板之一第一側上方；及複數個外部連接器，其等附接至與該第一側相對之該基板之一第二側。方法亦包含：將複數個晶粒附接至該第一RDL；使用一底膠材料填充該複數個晶粒與該第一RDL之間之一空間；及在該第一RDL上方且圍繞該複數個晶粒及該底膠材料形成一模塑料。方法進一步包含：將一聚合物材料施配於該基板之該第二側上而不覆蓋位於該基板遠端之該複數個外部連接器之頂部表面；及固化該聚合物材料。 儘管已參考闡釋性實施例描述本揭露，然此描述不旨在解釋為一限制意義。在參考描述之後，熟習此項技術者將明白闡釋性實施例之各種修改及組合以及本揭露之其他實施例。因此，隨附發明申請專利範圍旨在涵蓋任何此等修改或實施例。
100‧‧‧半導體裝置
101‧‧‧中心區域
102‧‧‧導電墊
103‧‧‧邊緣區域
105‧‧‧區域
111‧‧‧半導體晶粒
111S‧‧‧第二基板
112‧‧‧第一金屬化層
113‧‧‧半導體晶粒
113A‧‧‧半導體晶粒
113S‧‧‧第三基板
114‧‧‧第二金屬化層
115‧‧‧半導體晶粒
115A‧‧‧半導體晶粒
115S‧‧‧第四基板
116‧‧‧第三金屬化層
117‧‧‧連接器/外部接點/第一外部接點
117A‧‧‧第一外部接點
117B‧‧‧第二外部接點
117C‧‧‧第三外部接點
119‧‧‧間隙
121‧‧‧導電路徑
123‧‧‧第一基板
123L‧‧‧第二側
123M‧‧‧基板
123U‧‧‧第一側
125‧‧‧外部連接器
127‧‧‧焊料
129‧‧‧聚合物層
129'‧‧‧聚合物材料
129F‧‧‧平坦上表面
129U‧‧‧平坦上表面/下表面
131‧‧‧第一重佈層(RDL)
131M‧‧‧重佈層(RDL)
132‧‧‧導電墊
133‧‧‧底膠材料/底膠填充
135‧‧‧模塑料
150‧‧‧中介層
150M‧‧‧中介層
180‧‧‧半導體裝置
200‧‧‧半導體結構
201‧‧‧施配工具
202‧‧‧區域
204‧‧‧區域
205‧‧‧切割工具
206‧‧‧區域
300‧‧‧半導體裝置
303‧‧‧固化程序
305‧‧‧外部連接器
305A‧‧‧第二部分
305B‧‧‧第一部分
305S‧‧‧側壁
305T‧‧‧頂部表面
307‧‧‧回焊程序
309‧‧‧區域
500‧‧‧半導體裝置
501‧‧‧回焊程序
505‧‧‧區域
507‧‧‧外部連接器
507T‧‧‧頂部表面
601‧‧‧曲線
603‧‧‧曲線
1000‧‧‧方法
1010‧‧‧步驟
1020‧‧‧步驟
1030‧‧‧步驟
1040‧‧‧步驟
1050‧‧‧步驟
1060‧‧‧步驟
H1‧‧‧高度/厚度
H2‧‧‧高度/厚度
H3‧‧‧高度/厚度
H4‧‧‧高度/厚度
H5‧‧‧高度
H6‧‧‧高度
w1‧‧‧寬度
w2‧‧‧寬度
為更完全理解本揭露及其優點，現參考結合附圖進行之下文描述，其中： 圖1A及圖1B分別繪示在一些實施例中之一半導體裝置之一俯視圖及一橫截面視圖； 圖1C繪示圖1B之一區域中之一放大視圖； 圖1D繪示在一實施例中之一半導體裝置之一橫截面視圖； 圖2A至圖2D繪示根據一實施例之在各種製造階段之一半導體裝置的橫截面視圖； 圖3A至圖3C繪示在一實施例中之在各種製造階段之一半導體裝置的橫截面視圖； 圖4繪示圖3C之一區域之一放大視圖； 圖5A至圖5C繪示在一實施例中之在各種製造階段之一半導體裝置的橫截面視圖； 圖6繪示圖5C之一區域中之一放大視圖； 圖7繪示在一些實施例中之一實施例半導體裝置之效能；及 圖8繪示在一些實施例中之形成一半導體裝置之一方法之一流程圖。

Claims (20)

  1. 一種半導體裝置，其包括： 一基板； 一第一重佈層(RDL)，其在該基板之一第一側上方； 一或多個半導體晶粒，其或其等在該第一RDL上方且電耦合至該第一RDL； 一囊封劑，其在該第一RDL上方且圍繞該一或多個半導體晶粒； 連接器，其等附接至與該第一側相對之該基板之一第二側，該等連接器電耦合至該第一RDL；及 一聚合物層，其在該基板之該第二側上，該等連接器在位於該基板遠端之該聚合物層之一第一表面上方自該聚合物層突出，其中接觸該等連接器之該聚合物層之一第一部分具有一第一厚度，且在相鄰連接器之間之該聚合物層的一第二部分具有小於該第一厚度之一第二厚度。
  2. 如請求項1之半導體裝置，其中該聚合物層包括選自基本上由以下組成之群組之一材料：聚醯亞胺(PI)、聚苯并㗁唑(PBO)、樹脂、環氧樹脂、丙烯酸類聚合物、一底膠材料、一模塑料或其組合。
  3. 如請求項1之半導體裝置，其中該聚合物層放置於該基板之邊緣區域中，且其中該基板之一中心區域不含該聚合物層。
  4. 如請求項1之半導體裝置，其中該囊封劑包括： 一底膠材料，其在該基板與該一或多個半導體晶粒之間之一間隙中；及 一模塑料，其在該基板之該第一側上方且圍繞該一或多個半導體晶粒。
  5. 如請求項1之半導體裝置，其中該等連接器之一第一部分比該聚合物層之該第一表面更遠離該基板延伸，且該等連接器之一第二部分放置於該基板與該等連接器之該第一部分之間，其中該第二部分具有平坦側壁，且該第一部分具有彎曲側壁。
  6. 如請求項5之半導體裝置，其中該第一部分之一第一寬度大於該第二部分之一第二寬度。
  7. 一種方法，其包括： 接納一中介層，其中該中介層包括： 第一基板； 一第一重佈層(RDL)，其在該第一基板之一第一側上方；及 複數個外部連接器，其等在與該第一側相對之該第一基板之一第二側上，該複數個外部連接器電耦合至該第一RDL； 將複數個晶粒附接至該中介層之該第一RDL； 使用一第一介電材料填充該中介層與該複數個晶粒之間之一間隙；及 在將該中介層附接至一第二基板之前，將一第二介電材料施配在該第一基板之該第二側上而不覆蓋該複數個外部連接器之頂部表面。
  8. 如請求項7之方法，其進一步包括執行一回焊程序以將該複數個外部連接器接合至該第二基板之各自導電構件。
  9. 如請求項8之方法，其中該聚合物材料具有接觸該複數個外部連接器之一第一部分及遠離該複數個外部連接器之一第二部分，其中該第一部分具有大於該第二部分之一第二厚度之一第一厚度。
  10. 如請求項8之方法，其中該聚合物材料具有一均勻厚度。
  11. 如請求項8之方法，其中該施配包括將該聚合物材料施配於該中介層之邊緣區域中，且使該中介層之一中心區域保持不含該聚合物材料。
  12. 如請求項8之方法，其進一步包括在該施配之後，固化該聚合物材料。
  13. 如請求項12之方法，其中該固化包括部分地固化該聚合物材料。
  14. 如請求項12之方法，其進一步包括在該固化該聚合物材料之後，執行一回焊程序，其中該回焊程序修改在位於該基板遠端之該第二介電材料之一第一表面上方突出的該複數個外部連接器之一者之一第一部分的一輪廓。
  15. 如請求項14之方法，其中該複數個外部連接器之該一者之該第一部分具有一第一寬度，且放置於該第一基板與該第一部分之間之該複數個外部連接器的該一者之一第二部分具有一第二寬度，其中該第一寬度大於該第二寬度。
  16. 一種方法，其包括： 接納一中介層，該中介層包括：一第一重佈層(RDL)，其在一基板之一第一側上方；及複數個外部連接器，其等附接至與該第一側相對之該基板之一第二側； 將複數個晶粒附接至該第一RDL； 使用一底膠材料填充該複數個晶粒與該第一RDL之間之一間隙； 在該第一RDL上方且圍繞該複數個晶粒及該底膠材料形成一模塑料； 將一聚合物材料施配於該基板之該第二側上而不覆蓋位於該基板遠端之該複數個外部連接器之頂部表面；及 固化該聚合物材料。
  17. 如請求項16之方法，其進一步包括將該中介層之該複數個外部連接器實體且電耦合至另一基板之導電構件。
  18. 如請求項16之方法，其中接觸該複數個外部連接器之該聚合物材料之一第一部分比遠離該複數個外部連接器之該聚合物材料之一第二部分更遠離該基板延伸。
  19. 如請求項16之方法，其中該複數個外部連接器係由焊料製成，且其中該方法進一步包括執行一回焊程序以在該施配該聚合物材料之前，修改該複數個外部連接器之輪廓。
  20. 如請求項16之方法，其中該固化包括一紫外線固化程序或一熱固化成。
TW106134972A 2016-11-14 2017-10-12 半導體裝置及方法 TWI660482B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662421903P 2016-11-14 2016-11-14
US62/421,903 2016-11-14
US15/641,091 US10141253B2 (en) 2016-11-14 2017-07-03 Semiconductor device and method
US15/641,091 2017-07-03

Publications (2)

Publication Number Publication Date
TW201830637A true TW201830637A (zh) 2018-08-16
TWI660482B TWI660482B (zh) 2019-05-21

Family

ID=62108062

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106134972A TWI660482B (zh) 2016-11-14 2017-10-12 半導體裝置及方法

Country Status (4)

Country Link
US (4) US10141253B2 (zh)
KR (1) KR102023243B1 (zh)
CN (1) CN108074896B (zh)
TW (1) TWI660482B (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102017106055B4 (de) * 2017-03-21 2021-04-08 Tdk Corporation Trägersubstrat für stressempflindliches Bauelement und Verfahren zur Herstellung
US10600664B2 (en) * 2017-05-03 2020-03-24 Applied Materials, Inc. Fluorescence based thermometry for packaging applications
WO2019045936A1 (en) * 2017-09-01 2019-03-07 Kateeva, Inc. TWO-STAGE PROCESS FOR FORMING CURED POLYMERIC FILMS FOR ENCAPSULATION OF ELECTRONIC DEVICES
KR102404058B1 (ko) * 2017-12-28 2022-05-31 삼성전자주식회사 반도체 패키지
KR102397902B1 (ko) 2018-01-29 2022-05-13 삼성전자주식회사 반도체 패키지
US10340249B1 (en) 2018-06-25 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11024616B2 (en) * 2019-05-16 2021-06-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
JP2021034600A (ja) * 2019-08-27 2021-03-01 ローム株式会社 半導体装置
US20210202472A1 (en) * 2019-12-27 2021-07-01 Intel Corporation Integrated circuit structures including backside vias
US11380611B2 (en) 2020-03-30 2022-07-05 Taiwan Semiconductor Manufacturing Co., Ltd. Chip-on-wafer structure with chiplet interposer
DE102020119971B4 (de) * 2020-03-30 2022-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiterstruktur mit Chip-on-Wafer-Struktur mit Chiplet-Interposer und Verfahren zum Bilden derselben
CN114330201A (zh) * 2020-09-29 2022-04-12 中科寒武纪科技股份有限公司 封装结构、装置、板卡及布局集成电路的方法
TWI746231B (zh) 2020-10-27 2021-11-11 財團法人工業技術研究院 重布線結構及其形成方法
US20220367413A1 (en) * 2021-05-13 2022-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Packages With Multiple Types of Underfill and Method Forming The Same
US20230299031A1 (en) * 2022-03-15 2023-09-21 Texas Instruments Incorporated Semiconductor device with solder on pillar

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1328590B1 (de) * 2000-10-11 2011-08-03 Chemetall GmbH Verfahren zur vorbehandlung oder/und beschichtung von metallischen oberflächen vor der umformung mit einem lackähnlichen überzug und verwendung der derart beschichteten substrate
US7491636B2 (en) * 2005-07-19 2009-02-17 Micron Technology, Inc. Methods for forming flexible column die interconnects and resulting structures
KR101789765B1 (ko) * 2010-12-16 2017-11-21 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8643148B2 (en) * 2011-11-30 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer structures and methods for forming the same
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US9263412B2 (en) * 2012-03-09 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and packaged semiconductor devices
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9786631B2 (en) 2014-11-26 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Device package with reduced thickness and method for forming same
US9899238B2 (en) 2014-12-18 2018-02-20 Intel Corporation Low cost package warpage solution

Also Published As

Publication number Publication date
KR102023243B1 (ko) 2019-09-19
TWI660482B (zh) 2019-05-21
US20210335701A1 (en) 2021-10-28
KR20180054429A (ko) 2018-05-24
US10622297B2 (en) 2020-04-14
US11764139B2 (en) 2023-09-19
US11062987B2 (en) 2021-07-13
US20200243435A1 (en) 2020-07-30
US10141253B2 (en) 2018-11-27
US20190096796A1 (en) 2019-03-28
CN108074896A (zh) 2018-05-25
US20180138116A1 (en) 2018-05-17
CN108074896B (zh) 2020-07-31

Similar Documents

Publication Publication Date Title
TWI660482B (zh) 半導體裝置及方法
US10985137B2 (en) Stacked integrated circuit structure and method of forming
TWI708351B (zh) 半導體封裝及其製造方法
US11276656B2 (en) Integrated fan-out structure and method of forming
US11901258B2 (en) Iintegrated fan-out packages with embedded heat dissipation structure
TWI717561B (zh) 封裝結構及其形成方法
KR102210975B1 (ko) 반도체 패키지 내의 도전성 비아 및 그 형성 방법
CN102097337A (zh) 使用重组晶圆的半导体器件制造的方法和设备
TWI673848B (zh) 積體電路封裝及其形成方法
CN108695175B (zh) 半导体结构的制造方法
US11304290B2 (en) Semiconductor structures and methods
US9418956B2 (en) Zero stand-off bonding system and method
US20240063083A1 (en) Redistribution Structure with Warpage Tuning Layer
US20230062138A1 (en) Semiconductor package structure and method for forming the same
TW202339029A (zh) 包括銅柱陣列的半導體結構及其形成方法