TW201828428A - 封裝體裝置及其製造方法 - Google Patents

封裝體裝置及其製造方法 Download PDF

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Publication number
TW201828428A
TW201828428A TW106101446A TW106101446A TW201828428A TW 201828428 A TW201828428 A TW 201828428A TW 106101446 A TW106101446 A TW 106101446A TW 106101446 A TW106101446 A TW 106101446A TW 201828428 A TW201828428 A TW 201828428A
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Taiwan
Prior art keywords
dielectric layer
electronic component
forming
rearrangement
layer
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TW106101446A
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English (en)
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TWI609468B (zh
Inventor
洪英博
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欣興電子股份有限公司
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Priority to TW106101446A priority Critical patent/TWI609468B/zh
Priority to US15/460,249 priority patent/US9935046B1/en
Application granted granted Critical
Publication of TWI609468B publication Critical patent/TWI609468B/zh
Publication of TW201828428A publication Critical patent/TW201828428A/zh

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Abstract

本發明提供一種封裝體裝置及其製造方法。封裝體裝置包含基板、重佈局結構、電路板結構、第一連接件以及第一電子元件。重佈局結構設置於基板上。重佈局結構包含第一介電層以及第一金屬層。電路板結構設置於重佈局結構上。電路板結構包含第二介電層以及第二金屬層，其中，電路板結構中的第二介電層有複數個突起物嵌設於重佈局層的第一介電層中。第一電子元件設置於重佈局結構上，而第一連接件設置於重佈局結構與第一電子元件之間，以連接重佈局結構與第一電子元件。

Description

封裝體裝置及其製造方法
本發明是有關於一種封裝體裝置及其製造方法。
隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功能、高性能的研發方向。為滿足半導體元件高積集度(Integration)以及微型化(Miniaturization)的要求，重佈局結構的各項要求亦越來越高。舉例來說，重佈局結構中的線路之線寬與線距(Pitch)要求越來越小，線路重分佈結構的整體厚度也希望越小越好。伴隨著微型化的要求，勢必需要提升接點良率及整體可靠度。
在製備封裝體裝置時，後來形成的電路板裝置會堆疊在先前已經形成好的重分佈結構之上，此時先前已經形成好的重分佈結構容易受到擠壓而導致變形、翹曲，進而造成電路板裝置與重分佈結構之間接點良率下降及整體可靠度下降的問題。為了改善上述的問題，相關領域莫不費盡 心思開發。如何能提供一種具有高可靠度之封裝體裝置及其製備方法，實屬當前重要研發課題之一，亦成為當前相關領域亟需改進的目標。
本發明之一技術態樣是在提供一種封裝體裝置及其製造方法，此技術態樣可以提升封裝體裝置的接點良率、結構穩定度和結構平整度。
根據本發明一實施方式，系提供一種封裝體裝置的製造方法，包含以下步驟。形成至少一重佈局結構於基板上，其包含以下步驟：形成第一介電層於基板上、移除部分的第一介電層以形成複數個第一開口並填充第一金屬層於第一開口中。然後，形成複數個溝槽於重佈局結構之第一側上。接著，形成電路板結構於重佈局結構之第一側上，且重佈局結構電性連接至電路板結構。其中，形成該電路板結構包含：形成第二介電層於重佈局結構之第一側上，並填入於溝槽之中、移除部分的第二介電層以形成複數個第二開口、以及填充一第二金屬層於第二開口。然後，移除基板。
在本發明之一或多個實施方式中，更包含配置第一電子元件於重佈局結構之相對於第一側之第二側上，以使第一電子元件電性連接至重佈局結構。
於本發明之一或多個實施方式中，其中形成溝 槽於重佈局結構係形成貫穿重佈局結構之溝槽。
根據本發明另一實施方式，一種封裝體裝置的製造方法包含以下步驟。形成至少一重佈局結構於基板上，其包含以下步驟：形成第一介電層於基板上、移除部分的第一介電層以形成複數個第一開口、以及填充第一金屬層於第一開口中。然後，移除部分的第一介電層，以形成複數個溝槽於重佈局結構之第一側上。接著，配置第一電子元件於重佈局結構之第一側上，以使第一電子元件電性連接至重佈局結構。然後，形成模封層覆蓋重佈局結構與第一電子元件，並填入溝槽之中。接著，移除基板。
於本發明之一或多個實施方式中，形成溝槽於重佈局結構係形成貫穿重佈局結構之溝槽。
於本發明之一或多個實施方式中，更包含於形成模封層前，形成複數個導電柱於重佈局結構之第一側上，並使導電柱電性連接至重佈局結構。薄化模封層，以暴露導電柱。複數個第二連接件於模封層之上，並使第二連接件電性連接導電柱，以及配置電子元件於第二連接件之上，以形成層疊封裝結構(package on package)。
根據本發明另一實施方式，一種封裝體裝置，包含重佈局結構、電路板結構、第一電子元件和第一連接件。重佈局結構包含第一介電層以及複數個位於第一介電層之中的第一金屬線路。電路板結構設置於重佈局結構之第一 側。電路板結構包含第二介電層，其中第二介電層有複數個突起物嵌設於重佈局結構中。電路板結構更包含複數個位於第二介電層之中第二金屬線路，且第二金屬線路與重佈局結構電性連接。第一電子元件設置於重佈局結構之相對於第一側之第二側上。複數個第一連接件設置於重佈局結構與第一電子元件之間，以電性連接重佈局結構與第一電子元件。
於本發明之一或多個實施方式中，第二介電層的突起物係貫穿重佈局結構。
於本發明之一或多個實施方式中，第二介電層的楊氏模數(Young’s modulus)大於第一介電層的楊氏模數。
於本發明之一或多個實施方式中，第二介電層的熱膨脹係數小於第一介電層的熱膨脹係數。
根據本發明另一實施方式，一種封裝體裝置，包含至少一重佈局結構、第一電子元件、複數個第一連接件和模封層。重佈局結構包含第一介電層以及複數個位於第一介電層之中的第一金屬線路。第一電子元件，設置於重佈局結構上。複數個第一連接件，設置於重佈局結構與第一電子元件之間，以電性連接重佈局結構與第一電子元件。模封層覆蓋重佈局結構與第一電子元件，且模封層具有複數個突起物嵌設於重佈局結構中。
於本發明之一或多個實施方式中，其中模封層 的楊氏模數(Young’s modulus)大於第一介電層的楊氏模數。
100、200、300‧‧‧封裝體裝置
110、710、810‧‧‧基板
112、712、812‧‧‧離型膜
210、714、814‧‧‧重佈局結構
212、716、816‧‧‧第一介電層
214、718、818‧‧‧第一金屬線路
310、312、720、820‧‧‧溝槽
410‧‧‧電路板結構
412‧‧‧第二介電層
414‧‧‧第二金屬線路
416、510、728、834‧‧‧防銲結構
512、614、824‧‧‧導電柱
610、724、828‧‧‧第一電子元件
612、722、826‧‧‧第一連接件
726、830‧‧‧模封層
832‧‧‧金屬層
836‧‧‧第二連接件
838‧‧‧第二電子元件
為使本發明之特徵、優點與實施例能更明顯易懂，所附圖示之說明如下：第1圖到第6C圖係繪示根據本發明一實施例之封裝體裝置的製造方法之不同步驟的剖面圖；第7圖到第10圖係繪示根據本發明另一實施例之封裝體裝置的製造方法之不同步驟的剖面圖；第11圖到第15圖係繪示根據本發明另一實施例之封裝體裝置的製造方法之不同步驟的剖面圖。
以下將以圖式揭露本發明之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
此外，相對詞彙，如『下』或『底部』與『上』 或『頂部』，用來描述文中在附圖中所示的一元件與另一元件之關係。相對詞彙是用來描述裝置在附圖中所描述之外的不同方位是可以被理解的。例如，如果一附圖中的裝置被翻轉，元件將會被描述原為位於其它元件之『下』側將被定向為位於其他元件之『上』側。例示性的詞彙『下』，根據附圖的特定方位可以包含『下』和『上』兩種方位。同樣地，如果一附圖中的裝置被翻轉，元件將會被描述原為位於其它元件之『下方』或『之下』將被定向為位於其他元件上之『上方』。例示性的詞彙『下方』或『之下』，可以包含『上方』和『上方』兩種方位。
第1圖至第6C圖分別繪示依照本發明一實施方式之封裝體裝置100的製造方法之不同步驟的剖面圖。
如第1圖所繪示的實施方式中，提供基板110並形成離型膜112於基板110上。基板110之材質可為玻璃、金屬或有機板材。離型膜112之材質可為乙烯對苯二甲酸酯(Polyethylene Terephthalate，PET)。應了解到，以上所舉之基板110和離型膜112之材質僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇基板110和離型膜112之材質。
如第2圖所繪示的實施方式中，形成一重佈局結構210於基板110上。重佈局結構包含第一介電層212和由第一金屬層所形成的第一金屬線路214。形成重佈局結構 210的方法包含，形成第一介電層212於基板110上，之後，移除部分的第一介電層212以形成複數個第一開口。接著，填充第一金屬層於複數個第一開口中，以形成複數個第一金屬線路214。本發明所屬技術領域中具有通常知識者，可視實際需要，重複形成重佈局結構210的步驟，以形成複數個重佈局結構210。
在本發明之部分實施例中，第一金屬線路214的材質包含鋁、銅、鎢或其組合，但不以此為限，其他合適的導電材料同樣可以用於形成第一金屬線路214。在本發明之部分實施例中，第一介電層212係由可形成高密度細線路的材料所組成。在部分實施例中，第一介電層212的材料為感光型材料(photoimageable dielectric material)，例如成聚苯噁唑(polybenzoxazole,PBO)。應了解到，以上所舉之第一介電層212之材質僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇第一介電層212之材質。
如第3A圖與第3B圖所繪示的實施方式中，分別形成複數個溝槽310、312於重佈局結構210之第一側上。特別是在無金屬線路的重佈局結構區域中，移除部分第一介電層212以形成複數個溝槽310、312。值得注意的是，複數個溝槽310可完全貫穿第一介電層212，以暴露出離型膜112(如第3A圖所繪示)。複數個溝槽312也可僅部分貫穿 第一介電層212(如第3B圖所繪示)。在部分實施例中，溝槽310、312的側壁可為彎曲或平整。在部分實施例中，溝槽310、312的寬度可為30~300μm，例如50μm、100μm、200μm或250μm。在部分實施例中，可視需要調整溝槽深度。其中，複數個溝槽係藉由乾式蝕刻製程、濕式蝕刻製程、曝光顯影製程或雷射製程而形成。
如第4A圖所繪示的實施方式中，係形成電路板結構410於第3A圖的重佈局結構210之第一側上。電路板結構410的形成方式包含以下步驟，首先，形成第二介電層412於重佈局結構210之第一側上，並填入完全貫穿第一介電層212的溝槽310之中，以使第二介電層412有複數個突起物嵌設於重佈局結構210。移除部分的第二介電層412以形成複數個第二開口。接著，填充第二金屬層於複數個第二開口之中，以形成複數個第二金屬線路414。然後，在電路板結構410上形成防銲結構416。本發明所屬技術領域中具有通常知識者，可視實際需要，重複形成電路板結構410的步驟，以形成複數個電路板結構410。
如第4B圖所繪示的實施方式中，係形成電路板結構410於第3B圖的重佈局結構210之第一側上。電路板結構410的形成方式包含以下步驟，首先，形成第二介電層412於重佈局結構210之第一側上，並填入部分貫穿第一介電層212的溝槽312之中，以使第二介電層412有複數個突起物 嵌設於重佈局結構210。移除部分的第二介電層412以形成複數個第二開口。接著，填充第二金屬層複數個第二開口之中，以形成複數個第二金屬線路414。然後，在電路板結構410上形成防銲結構416。本發明所屬技術領域中具有通常知識者，可視實際需要，重複形成電路板結構410的步驟，以形成複數個電路板結構410。
在本發明之部分實施例中，第二金屬線路414的材質包含鋁、銅、鎢或其組合，但不以此為限，其他合適的導電材料同樣可以用於形成第二金屬線路414。在本發明之部分實施例中，第二介電層的材料可為樹脂(Resin)、環氧樹脂(Epoxy)、聚醯亞胺(Polyimide，PI)、B一三氮樹脂(Bismaleimide triazine，BT)、纖維浸含樹脂(Prepreg，PP)、ABF樹脂[Ajinomoto Build up Film，日本味之素公司(Ajinomoto Co.，Ltd.)所供應的一種環氧樹脂絕緣膜]或其他適合的材料。在本發明之部分實施例中，第二介電層412材料的熱膨脹係數小於該第一介電層212材料的熱膨脹係數。在本發明之部分實施例中，第二介電層412材料的楊氏係數高於該第一介電層212材料的楊氏係數。
在本發明之部分實施例的製造過程中，在重佈局結構210之第一介電層212中形成複數個溝槽310、312，並將欲堆疊在重佈局結構210之上的電路板結構410之第二 介電層414填入重佈局結構210的複數個溝槽310、312中，此製程方法及其所產生的結構能提升整體結構之穩定度，並可避免在形成電路板結構410時，重佈局結構210發生變形或翹曲的現象。因此，本發明實施例可提高接點良率，整體可靠度及平整度。
在第4A圖所繪示的實施方式中，封裝體裝置100可接續分別形成如第5A-5C圖之不同態樣。
在第5A圖所繪示的實施方式中，封裝體裝置係移除基板110(繪示於第4A圖中)和離型膜112(繪示於第4A圖中)，並翻轉整個封裝體裝置，使重佈局結構210之第一側位於下方。
如第5B圖所繪示的實施方式中，封裝體裝置係移除基板110(繪示於第4A圖中)和離型膜112(繪示於第4A圖中)，並在重佈局結構210上形成防銲結構510。然後，翻轉整個封裝體裝置，使重佈局結構210之第一側位於下方。
如第5C圖所繪示的實施方式中，封裝體裝置係移除基板110(繪示於第4A圖中)和離型膜112(繪示於第4A圖中)，並在重佈局結構210上形成防銲結構510及導電柱512(例如：銅柱結構)。然後，翻轉整個封裝體裝置，使重佈局結構210之第一側位於下方。
本發明所屬技術領域中具有通常知識者，應了解，移除基板110和離型膜112，並形成防銲結構510及導 電柱512於重佈局結構210上也可執行於第4B圖中的封裝體裝置(未繪示)。
如第6A-6C圖所繪示的實施方式中，分別配置一第一電子元件610於第5A-5C圖所示重佈局結構210之相對於第一側之第二側上。如第6A圖所繪示，第一電子元件610藉由第一連接件612電性連接至重佈局結構210之相對於第一側之第二側上。如第6B圖所繪示，第一電子元件610藉由第一連接件612電性連接至有形成防銲結構510的重佈局結構210之相對於第一側之第二側上上。如第6C圖所繪示，第一電子元件610係藉由第一連接件612電性連接至有防銲結構510及導電柱614的重佈局結構210上的導電柱614上。在本發明之部分實施方式中，第一連接件612可為材質為錫的焊球或焊接突起物。在本發明之部分實施方式中，第一電子元件610可為主動元件或被動元件，其中，主動元件可為半導體晶片，被動元件可為電阻元件、電容元件、電感元件或晶片型被動元件
第7圖至第10圖分別繪示依照本發明另一實施方式之封裝體裝置200的製造方法之不同步驟的剖面圖。
如第7圖所繪示的實施方式中，提供基板710，基板710上有離型膜712。重佈局結構714位於基板710上。重佈局結構714的形成方式包含，形成第一介電層716於基板710上，之後，移除部分的第一介電層716以形成複 數個第一開口。填充第一金屬層於複數個第一開口中，以形成複數個第一金屬線路718。本發明所屬技術領域中具有通常知識者，可視實際需要，重複形成重佈局結構714的步驟，以形成複數個重佈局結構714。形成複數個溝槽720於重佈局結構714之第一側上。特別是在無金屬線路的重佈局結構區域中，移除部分第一介電層716以形成複數個溝槽720。值得注意的是，複數個溝槽720可完全貫穿第一介電層716，以暴露出離型膜712(如第7圖所繪示)。複數個溝槽720也可僅部分貫穿第一介電層716(未繪示)。在部分實施例中，溝槽720的側壁可為彎曲或平整。在部分實施例中，溝槽720的寬度可為30μm~300μm，例如50μm、100μm、200μm或250μm。在部分實施例中，可視需要調整溝槽深度。其中，複數個溝槽係藉由乾式蝕刻製程、濕式蝕刻製程、曝光顯影製程或雷射製程而形成。
請繼續參閱第7圖所繪示的實施方式，形成複數個第一連接件722於重佈局結構714上，配置第一電子元件724於第一連接件722上，使第一電子元件724藉由第一連接件722電性連接至重佈局結構714。在本發明之部分實施方式中，第一連接件722可為材質為錫的焊球或焊接突起物。在本發明之部分實施方式中，第一電子元件724可為主動元件或被動元件，其中，主動元件可為半導體晶片，被動元件可為電阻元件、電容元件、電感元件或晶片型被動元件。
在第7圖所繪示的封裝體裝置200中，基板710之材質可為玻璃、金屬或有機板材。離型膜712之材質可為乙烯對苯二甲酸酯(Polyethylene Terephthalate，PET)。應了解到，以上所舉之基板710和離型膜712之材質僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇基板710和離型膜712之材質。在本發明之部分實施例中，第一金屬線路718的材質包含鋁、銅、鎢或其組合，但不以此為限，其他合適的導電材料同樣可以用於形成第一金屬線路718。在本發明之部分實施例中，第一介電層716係由可形成高密度細線路的材料所組成。在部分實施例中，第一介電層716的材料為感光型材料(photoimageable dielectric material)，例如成聚苯噁唑(polybenzoxazole,PBO)。應了解到，以上所舉之第一介電層716之材質僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇第一介電層716之材質。
如第8圖所繪示的實施方式中，覆蓋模封層726於重佈局結構714及第一電子元件724上，且填入於複數個溝槽720中，以使模封層726有複數個突起物嵌設於重佈局結構714中。模封層的材料可為環氧樹酯。以上所舉之模封材料僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇模封層之材 質。在本發明之部分實施例中，模封層726材料的熱膨脹係數小於第一介電層716材料的熱膨脹係數。在本發明之部分實施例中，模封層726材料的楊氏係數高於第一介電層716材料的楊氏係數。
如第9圖所繪示的實施方式中，移除基板710及離型膜712。
如第10圖所繪示的實施方式中，可選擇性形成防銲結構728於重佈局結構714之一側。
第11圖至第15圖分別繪示依照本發明一實施方式之封裝體裝置300的製造方法之不同步驟的剖面圖。
如第11圖所繪示的實施方式中，提供一基板810，基板810上有一離型膜812。一重佈局結構814位於基板810上。重佈局結構814的形成方式包含，形成第一介電層816於基板810上，之後，移除部分的第一介電層816以形成複數個第一開口。填充第一金屬層於複數個第一開口中，以形成複數個第一金屬線路818。本發明所屬技術領域中具有通常知識者，可視實際需要，重複形成重佈局結構814的步驟，以形成複數個重佈局結構814。接著，形成複數個溝槽820於重佈局結構814之第一側上。特別是在無金屬線路的重佈局結構區域中，移除部分第一介電層816以形成複數個溝槽820。值得注意的是，複數個溝槽820可完全貫穿第一介電層816，以暴露出離型膜812(如第11圖所繪 示)。複數個溝槽820也可僅部分貫穿第一介電層816(未繪示)。在部分實施例中，溝槽820的側壁可為彎曲或平整。在部分實施例中，溝槽820的寬度可為30μm~300μm，例如50μm、100μm、200μm或250μm。在部分實施例中，可視需要調整溝槽深度。其中，複數個溝槽係藉由乾式蝕刻製程、濕式蝕刻製程、曝光顯影製程或雷射製程而形成。
請繼續參閱第11圖的實施方式中，形成複數個導電柱824於第一金屬線路818上，以使導電柱824與第一金屬線路818電性連接。在本發明之部分實施例中，第一金屬線路818和導電柱824的材質包含鋁、銅、鎢或其組合，但不以此為限，其他合適的導電材料同樣可以用於形成第一金屬線路818。在本發明之部分實施例中，第一介電層816係由可形成高密度細線路的材料所組成。在部分實施例中，第一介電層816的材料為感光型材料(photoimageable dielectric material)，例如成聚苯噁唑(polybenzoxazole,PBO)。應了解到，以上所舉之第一介電層816之材質僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇第一介電層816之材質。
如第12圖所繪示的實施方式中，形成複數個第一連接件826於重佈局結構814上，並配置一第一電子元件828於複數個第一連接件826上，以使第一電子元件828電 性連接至重佈局結構814。值得注意的是，複數個導電柱824比第一電子元件828高。在本發明之部分實施方式中，第一連接件826可為材質為錫的焊球或焊接突起物。在本發明之部分實施方式中，第一電子元件828可為主動元件或被動元件，其中，主動元件可為半導體晶片，被動元件可為電阻元件、電容元件、電感元件或晶片型被動元件。
如第13圖所繪示的實施方式中，覆蓋模封層830於重佈局結構814、複數個導電柱824與第一電子元件828之上，並且模封層830填入重佈局結構814的複數個溝槽820中，以使模封層830有複數個突起物嵌設於重佈局結構814中。蝕刻並薄化模封層830以暴露複數個導電柱824。模封層830的材料可為環氧樹酯。以上所舉之模封材料僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇模封層830之材質。在本發明之部分實施例中，模封層830材料的熱膨脹係數小於第一介電層816材料的熱膨脹係數。在本發明之部分實施例中，模封層830材料的楊氏係數高於第一介電層816材料的楊氏係數。
如第14圖所繪示的實施方式中，形成一金屬層832於模封層830上，以使金屬層832電性連接至導電柱824。然後，形成防銲結構834於金屬層832之上。接著，移除基板810與離型膜812。
如第15圖所繪示的實施方式中，形成複數個第二連接件836於金屬層832上，並使第二連接件836電性連接至導電柱824。接著，配置第二電子元件838於第二連接件上，以形成層疊封裝結構(package on package)。在本發明之部分實施方式中，第二連接件836可為材質為錫的焊球或焊接突起物，但不以此為限。在本發明之部分實施方式中，第二電子元件838可為主動元件或被動元件，其中，主動元件可為半導體晶片，被動元件可為電阻元件、電容元件、電感元件或晶片型被動元件。在本發明之部分實施方式中，第二電子元件838可為一封裝體裝置。
本發明上述實施方式系藉由形成複數個溝槽310、312、720、820於重佈局結構中，再將之後欲形成在重佈局結構上的電路板結構之第二介電層或模封材料填入重佈局結構中第一介電層的複數個溝槽中。在重佈局結構中，沒有金屬線路結構的區域皆可依所需情形形成溝槽，且溝槽可為半貫穿第一重佈局層，或全貫穿第一重佈局層。在本發明之部分實施例中，第二介電層或模封材料的熱膨脹係數小於該第一介電層的熱膨脹係數。在本發明之部分實施例中，第二介電層或模封材料的楊氏係數高於該第一介電層的楊氏係數。此製造方法避免第一重佈局層的結構發生翹曲或扭曲，進而提升結構穩定度、平整度及接點良率。
雖然本發明已以實施方式揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。

Claims (12)

  1. 一種封裝體裝置的製造方法，包含：形成至少一重佈局結構於一基板上，包含：形成一第一介電層於該基板上；移除部分的該第一介電層以形成複數個第一開口；以及填充一第一金屬層於該些第一開口中；形成複數個溝槽於該重佈局結構之一第一側上；形成一電路板結構於該重佈局結構之該第一側上，且該重佈局結構電性連接至該電路板結構，其中，形成該電路板結構包含：形成一第二介電層於該重佈局結構之該第一側上，並填入於該些溝槽之中；移除部分的該第二介電層以形成複數個第二開口；以及填充一第二金屬層於該些第二開口；以及移除該基板。
  2. 如請求項1所述的製造方法，更包含配置一第一電子元件於該重佈局結構之相對於該第一側之一第二側上，以使該第一電子元件電性連接至該重佈局結構。
  3. 如請求項1所述的製造方法，其中形成該些溝槽於該重佈局結構係形成貫穿該重佈局結構之溝槽。
  4. 一種封裝體裝置的製造方法，包含：形成至少一重佈局結構於一基板上，包含；形成一第一介電層於該基板上；移除部分的該第一介電層以形成複數個第一開口；以及填充一第一金屬層於該些第一開口中；移除部分的該第一介電層，以形成複數個溝槽於該重佈局結構之一第一側上；配置一第一電子元件於該重佈局結構之該第一側上，以使該第一電子元件電性連接至該重佈局結構；形成一模封層覆蓋該重佈局結構與該第一電子元件，並填入該些溝槽之中；以及移除該基板。
  5. 如請求項4所述的製造方法，其中形成該些溝槽於該重佈局結構係形成貫穿該重佈局結構之溝槽。
  6. 如請求項4所述的製造方法，更包含： 於形成該模封層前，形成複數個導電柱於該重佈局結構之該第一側上，並使該些導電柱電性連接至該重佈局結構；薄化該模封層，以暴露該些導電柱；形成複數個第二連接件於該模封層之上，並使該些第二連接件電性連接該些導電柱；以及配置一第二電子元件於該些第二連接件之上，以形成一層疊封裝結構(package on package)。
  7. 一種封裝體裝置，包含：至少一重佈局結構，包含：一第一介電層；以及複數個第一金屬線路，位於該第一介電層之中；一電路板結構，設置於該重佈局結構之一第一側，該電路板結構包含：一第二介電層，其中該第二介電層具有複數個突起物嵌設於該重佈局結構中；以及複數個第二金屬線路，位於該第二介電層之中，且與該重佈局結構電性連接；一第一電子元件，設置於該重佈局結構之相對於該第一側之一第二側上；以及複數個第一連接件，設置於該重佈局結構與該第一電子元件之間，以電性連接該重佈局結構與該第一電子元件。
  8. 如請求項7所述的封裝體裝置，其中該第二介電層的該些突起物係貫穿該重佈局結構。
  9. 如請求項7所述的封裝體裝置，其中該第二介電層的楊氏模數(Young’s modulus)大於該第一介電層的楊氏模數。
  10. 如請求項7所述的封裝體裝置，其中該第二介電層的熱膨脹係數小於該第一介電層的熱膨脹係數。
  11. 一種封裝體裝置，包含：至少一重佈局結構，包含：一第一介電層；以及複數個第一金屬線路，位於該第一介電層之中；一第一電子元件，設置於該重佈局結構上；複數個第一連接件，設置於該重佈局結構與該第一電子元件之間，以電性連接該重佈局結構與該第一電子元件；以及一模封層，覆蓋該重佈局結構與該第一電子元件，且該模封層具有複數個突起物嵌設於該重佈局結構中。
  12. 如請求項11所述的封裝體裝置，其中該模封層的楊氏模數(Young’s modulus)大於該第一介電層的楊氏模數。
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