TWI809986B - 封裝結構及其製作方法 - Google Patents

封裝結構及其製作方法 Download PDF

Info

Publication number
TWI809986B
TWI809986B TW111127038A TW111127038A TWI809986B TW I809986 B TWI809986 B TW I809986B TW 111127038 A TW111127038 A TW 111127038A TW 111127038 A TW111127038 A TW 111127038A TW I809986 B TWI809986 B TW I809986B
Authority
TW
Taiwan
Prior art keywords
layer
hole
active chip
conductive
redistribution layer
Prior art date
Application number
TW111127038A
Other languages
English (en)
Other versions
TW202406064A (zh
Inventor
張簡上煜
Original Assignee
力成科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力成科技股份有限公司 filed Critical 力成科技股份有限公司
Priority to TW111127038A priority Critical patent/TWI809986B/zh
Priority to US18/083,579 priority patent/US20240030121A1/en
Application granted granted Critical
Publication of TWI809986B publication Critical patent/TWI809986B/zh
Publication of TW202406064A publication Critical patent/TW202406064A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/08235—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bonding area connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1011—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/182—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/186—Material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Packages (AREA)

Abstract

本發明提供一種封裝結構及其製作方法。封裝結構包括重佈線層、導電柱、主動晶片、封裝層以及另一重佈線層。導電柱與主動晶片並排設置於重佈線層上。封裝層環繞主動晶片及導電柱，其中封裝層具有設置於主動晶片與重佈線層之間的第一穿孔以及設置於導電柱與重佈線層之間的第二穿孔，且第一穿孔的深度小於第二穿孔的深度。所述另一重佈線層設置於主動晶片遠離於重佈線層的一側，並透過導電柱電性連接重佈線層。

Description

封裝結構及其製作方法
本發明有關一種封裝結構及其製作方法，特別是有關一種具有夾設於兩重佈線層之間的主動晶片的封裝結構及其製作方法。
隨著半導體技術的進步，晶片中的電路密度越來越高，以提升晶片的運作效能，並縮小晶片的尺寸。在傳統晶片設計上，為了促進晶片的散熱，通常會增加晶片的厚度。如此一來，當晶片在進行封裝時，導電柱(conductive pillar)的高度也需增高，使得導電柱的高度高於晶片的厚度。然而，隨著用於形成導電柱的光阻層的厚度越高，穿孔的寬度會越大，以致於限制了導電柱的分布密度。並且，光阻層的厚度有一定的限制，使得導電柱的高度無法持續提升，從而限制了能夠進行封裝的晶片的厚度。為此，如何解決晶片厚度受限的問題已成為該領域研究人員的一大課題。
根據本發明的一實施例，提供一種封裝結構，其包括重佈線層、導電柱、主動晶片、封裝層以及另一重佈線層。導電柱與主動晶片並排設置於重佈線層上，且主動晶片具有接墊。封裝層環繞主動晶片及導電柱，其中封裝層 具有第一穿孔以及第二穿孔，第一穿孔設置於主動晶片的接墊與重佈線層之間，第二穿孔設置於導電柱與重佈線層之間，且第一穿孔的深度小於第二穿孔的深度。所述另一重佈線層設置於主動晶片遠離於重佈線層的一側，並透過導電柱電性連接重佈線層。
根據本發明的另一實施例，提供一種封裝結構的製作方法。首先，於載板上形成重佈線層。接著，於重佈線層上形成導電柱並設置主動晶片，其中主動晶片具有接墊，朝向主動晶片遠離重佈線層的一側。然後，於重佈線層、導電柱以及主動晶片上形成封裝層，其中封裝層環繞導電柱以及主動晶片，封裝層具有第一穿孔以及第二穿孔，第一穿孔曝露出主動晶片的接墊，第二穿孔曝露出導電柱，且第一穿孔的深度小於第二穿孔的深度。隨後，於封裝層遠離重佈線層的一側上形成另一重佈線層。然後，移除載板。
1:封裝結構
12,20:重佈線層
121,121a,201,201a:介電層
122,122a,202,202a:導電層
14:導電柱
16:主動晶片
16a:接墊
16m:主體部
16n:絕緣層
16S1:主動面
16S2:背面
18,323:封裝層
1a:半成品結構
24:黏著層
26:抗翹曲層
28,34:導電端子
30:電子元件
32:封裝元件
321:晶片
322:線路層
36:載板
38:離型層
H1,H2:深度
HD:水平方向
L1:第一走線
L2:第二走線
M1:金屬層
S12,S14,S16,S18,S110:步驟
SE1:介面層
T1:厚度
T2:高度
TD:俯視方向
TH1:第一穿孔
TH2:第二穿孔
TH3:第三穿孔
TH4:第四穿孔
W1,W2:孔徑
第1圖繪示本發明一實施例的封裝結構的剖視示意圖。
第2圖繪示本發明另一實施例的封裝結構的剖面示意圖。
第3圖繪示本發明一實施例的封裝結構的製作方法流程圖。
第4圖至第8圖繪示本發明一實施例在製作方法的不同步驟中的結構剖視示意圖。
下文結合具體實施例和附圖對本揭露的內容進行詳細描述，且為了使本揭露的內容更加清楚和易懂，下文各附圖為可能為簡化的示意圖，且其中的元件可能並非按比例繪製。並且，附圖中的各元件的數量與尺寸僅為示意， 並非用於限制本揭露的範圍。
以下實施例中所提到的方向用語，例如：上、下、左、右、前或後等，僅是參考附加圖式的方向。因此，使用的方向用語是用來說明並非用來限制本發明。必需了解的是，為特別描述或圖示之元件可以此技術人士所熟知之各種形式存在。
當元件或膜層被稱為在另一元件或另一膜層上或之上時，應被瞭解為所述的元件或膜層是直接位於另一元件或另一膜層上，也可以是兩者之間存在有其他的元件或膜層(非直接)。但相反地，當元件或膜層被稱為「直接」在另一個元件或膜層「上」時，則應被瞭解兩者之間不存在有插入的元件或膜層。
於文中提及一元件「電性連接」或「耦接」另一元件時，可包括「元件與另一元件之間可更存在其它元件而將兩者電性連接」的情況，或是包括「元件與另一元件之間未存有其它元件而直接電性連接」的情況。若於文中提及一元件「直接電性連接」或「直接耦接」另一元件時，則指「元件與另一元件之間未存有其它元件而直接電性連接」的情況。
請參考第1圖，其繪示本發明一實施例的封裝結構的剖視示意圖。如第1圖所示，本實施例所提供的封裝結構1可包括重佈線層12、導電柱14、主動晶片16、封裝層18以及重佈線層20。導電柱14、主動晶片16與封裝層18可設置於重佈線層12上，且封裝層18可環繞導電柱14以及主動晶片16。重佈線層20可設置於主動晶片16遠離重佈線層12的一側，並透過導電柱14電性連接重佈線層12。主動晶片16可具有接墊16a，且封裝層18可具有至少一個第一穿孔TH1以及至少一個第二穿孔TH2，其中第一穿孔TH1可設置於主動晶片16的接墊16a與重佈線層12之間，且第二穿孔TH2可設置於導電柱14與重佈線層12之間。
值得說明的是，重佈線層12可透過第一穿孔TH1電性連接主動晶片16，並透過第二穿孔TH2電性連接導電柱14，由於第一穿孔TH1的深度H1可小於 第二穿孔TH2的深度H2，因此重佈線層12可電性連接至位於不同平面的元件，例如導電柱14以及接墊16a。如此，主動晶片16的厚度T1可不需小於導電柱14的高度T2，從而降低或避免主動晶片16的厚度T1受限於導電柱14的高度T2的情況。透過此設計，主動晶片16的厚度T1可為了改善散熱或其他需求而增厚。舉例來說，導電柱14的高度T2可小於或等於主動晶片16的厚度T1。主動晶片16的厚度T1可例如大於或等於200微米(μm)。
具體來說，重佈線層12可包括至少一層介電層121以及至少一層導電層122。在本實施例中，重佈線層12可分別包括複數層介電層121以及複數層導電層122，但不限於此。在一些實施例中，重佈線層12中的導電層122的數量以及介電層121的數量可依據實際需求作調整。
在本實施例的重佈線層12中，導電層122與介電層121可依序交替堆疊，用以將位於重佈線層12上的元件(例如，導電柱14與主動晶片16)電性連接至位於重佈線層12下的元件(例如，導電端子28及/或電子元件30)。介電層121可具有至少一穿孔，使得與介電層121相鄰並位於介電層121兩側的導電層122可透過穿孔電性連接，從而讓最下層的導電層122可電性連接至最上層的導電層122。每層的導電層122可包括複數條走線或接墊，且走線的佈局結構可依據實際需求作對應的設計。任一層的導電層122的兩相鄰走線或接墊之間的間距也可依據實際需求而調整為不同或相同。舉例來說，最上層的導電層122的接墊間距(例如，細節距(fine pitch))可小於最下層的導電層122的接墊間距，及/或距離主動晶片16較近的導電層122的走線間距可小於較遠的導電層122的走線間距，以達到扇出(fan out)的效果，但不以此為限。
如第1圖所示，在封裝結構1的俯視方向TD上，第一穿孔TH1可對應主動晶片16的接墊16a設置，且第二穿孔TH2可對應導電柱14設置。在本實施例中，主動晶片16的接墊16a可面向重佈線層12，使得重佈線層12可透過第一穿孔 TH1直接電性連接主動晶片16，但本發明不限於此。第一穿孔TH1在一水平方向HD上的孔徑W1可例如隨著距離主動晶片16越遠而越大。第一穿孔TH1的孔徑W1的最小值可例如小於接墊16a的寬度。第二穿孔TH2在水平方向HD上的孔徑W2也可例如隨著距離導電柱14越遠而越大。第二穿孔TH2的孔徑W2的最小值可例如小於或等於導電柱14的寬度。並且，第二穿孔TH2的孔徑W2可大於第一穿孔TH1的孔徑W1。在本實施例中，一部分封裝層18可進一步設置於重佈線層12與主動晶片16之間，且一部分封裝層18可位於重佈線層12與導電柱14之間，但不限於此。在一些實施例中，封裝層18可不位於重佈線層12與導電柱14之間。
如第1圖所示，重佈線層12可包括至少一條第一走線L1以及至少一條第二走線L2，其中第一走線L1可設置於封裝層18的第一穿孔TH1中，並電性連接主動晶片16的接墊16a，第二走線L2可設置於封裝層18的第二穿孔TH2中，並電性連接導電柱14。在本實施例中，第一走線L1可設置於封裝層18靠近重佈線層12的表面，並延伸至第一穿孔TH1中。第一穿孔TH1的孔徑W1的一半可例如小於或等於導電層122的厚度，使得第一走線L1可填滿第一穿孔TH1。由於位於接墊16a與重佈線層12之間的第一穿孔TH1可在製作過程中曝露出接墊16a(如第5圖所示)，因此設置於第一穿孔TH1中的第一走線L1可直接與接墊16a接觸。在此情況下，主動晶片16的接墊16a上可不需具有導電凸塊(conductive bump)，因此可省略製作導電凸塊的時間與成本，及/或可降低封裝結構1的厚度。
如第1圖所示，第二穿孔TH2的深度H2與孔徑W2可大於導電層122的厚度，因此第二走線L2可沿著第二穿孔TH2的側壁設置並沿著導電柱14被第二穿孔TH2曝露出的表面設置。換言之，第二走線L2並未填滿第二穿孔TH2，第二走線L2可例如與封裝層18的表面、第二穿孔TH2的側壁以及導電柱14的表面所形成的階梯表面共形。在此情況下，與第二走線L2相鄰的介電層121a(例如，最上層介電層121a)的一部分可設置於第二穿孔TH2中。介電層121a可例如填滿第 二穿孔TH2。值得說明的是，由於第一穿孔TH1的深度H1可小於第二穿孔TH2的深度H2，因此第一走線L1在俯視方向TD上的高度可小於第二走線L2在俯視方向TD上的高度。在導電柱14的高度T2小於或等於接墊16a靠近重佈線層12的表面與重佈線層20之間的距離(即，主動晶片16的厚度T1與黏著層24的厚度總和)的情況下，第一走線L1與第二走線L2仍可分別電性連接至接墊16a與導電柱14，從而解決主動晶片16的厚度T1受限的問題。在一些實施例中，黏著層24的厚度很小，因此接墊16a靠近重佈線層12的表面與重佈線層20之間的距離可接近主動晶片16的厚度T1。
在本實施例中，第一走線L1與第二走線L2可由相同的導電層122所形成，例如由最鄰近封裝層18的導電層122a(即，最上層導電層122a)所形成。進一步來說，如第1圖下側的放大圖所示，導電層122a可包括介面層SE1以及金屬層M1，且介面層SE1可設置於金屬層M1與封裝層18之間以及金屬層M1與接墊16a(或導電柱14)之間。以第一走線L1為例，介面層SE1可沿著封裝層18的下表面、第一穿孔TH1的側壁及接墊16a的表面設置，且金屬層M1可設置於第一穿孔TH1中。雖圖未示，第二走線L2的介面層SE1可沿著封裝層18的下表面、第二穿孔TH2的側壁及導電柱14的表面設置，且金屬層M1設置於介面層SE1遠離封裝層18的表面。介面層SE1不僅可提升金屬層M1與接墊16a(或導電柱14)之間的接合力，也可用於提升金屬層M1與封裝層18之間的接合力。介面層SE1可例如為晶種層或其他合適的膜層。介面層SE1與金屬層M1可例如包括銅、鈦、其他合適的材料或上述至少兩者的組合。
如第1圖所示，導電柱14與主動晶片16可設置於重佈線層12與重佈線層20之間。在第1圖的實施例中，主動晶片16可電性連接重佈線層12，且透過導電柱14，主動晶片16可進一步電性連接重佈線層20。
在第1圖的實施例中，導電柱14的數量可為複數個，且導電柱14可以 圍繞主動晶片16的方式分散設置於主動晶片16的周圍，但不限於此。在一些實施例中，導電柱14的數量可為至少一個。在一些實施例中，導電柱14可例如包括單層或多層結構。導電柱14可例如包括銅、鎳、錫(tin)、銀(silver)、其他合適的材料、上述至少兩者的合金或上述的組合，但不限於此。
如第1圖所示，主動晶片16可另包括主體部16m以及絕緣層16n，其中接墊16a可設置於主體部16m上，且絕緣層16n可設置於接墊16a上，並具有曝露出對應的接墊16a的開口。主體部16m可例如包括積體電路，接墊16a可例如為鋁墊，但不限於此。在一些實施例中，主動晶片16具有接墊16a的表面可稱為主動面16S1，但不限於此。在本實施例中，封裝結構1可另包括黏著層24，用以將主動晶片16相對於主動面16S1的背面16S2黏貼於重佈線層20上，但本發明不限於此。黏著層24可例如包括晶片黏著膜(die attach film,DAF)、雙面膠或其他合適的材料。在本文中，水平方向HD可例如平行於主動晶片16的背面16S2，俯視方向TD可例如垂直於主動晶片16的背面16S2。
在本文中，主動晶片16可指包括主動元件的晶片，主動元件可包括電晶體、二極體、積體電路、光電元件或其他具有增益的合適元件，但不限於此。在本文中，晶片也可以稱為晶粒，但不限於此。主動晶片16可例如包括電源管理晶片(power management integrated circuit,PMIC)、微機電系統(micro-electro-mechanical-system,MEMS)晶片、特殊應用積體電路晶片(application-specific integrated circuit,ASIC)、動態隨機存取記憶體(dynamic random access memory,DRAM)晶片、靜態隨機存取記憶體(static random access memory,SRAM)晶片、高頻寬記憶體(high bandwidth memory,HBM)晶片、系統晶片(system on chip,SoC)、高效能運算(high performance computing,HPC)晶片或其他類似的主動晶片，但不限於此。
如第1圖所示，重佈線層20可包括至少一層介電層201以及至少一層 導電層202。在本實施例中，重佈線層20可分別包括複數層介電層201以及複數層導電層202，但不限於此。在一些實施例中，重佈線層20中的導電層202的數量以及介電層201的數量可依據實際需求作調整。
在本實施例的重佈線層20中，介電層201與導電層202可依序交替堆疊，用以將位於重佈線層20上的元件(例如，第2圖所示的封裝元件32)電性連接至位於重佈線層20下的元件(例如，導電柱14)。介電層201可具有至少一穿孔，使得與介電層201相鄰並位於介電層201兩側的導電層202可透過穿孔電性連接，從而讓最下層的導電層202可電性連接至最上層的導電層202。每層的導電層202可包括複數條走線或接墊，且走線的佈局結構可依據實際需求作對應的設計。在本實施例中，重佈線層20的導電層202的數量可例如不同於重佈線層12的導電層122的數量。舉例來說，鄰近主動晶片16的接墊16a的重佈線層12的導電層122的數量可大於遠離接墊16a的重佈線層20的導電層202的數量。
如第1圖所示，封裝結構1可選擇性另包括抗翹曲層26，設置於重佈線層20遠離主動晶片16的一側，用以降低封裝結構1產生翹曲。舉例來說，當重佈線層20的介電層201的數量小於重佈線層12的介電層121的數量，或者當重佈線層20的介電層201與導電層202的總數量小於重佈線層12的介電層121與導電層122的總數量時，位於主動晶片16上下側的應力會不同，使得封裝結構1容易產生翹曲。透過將抗翹曲層26設置於介電層的數量較少的一側，可有助於平衡主動晶片16上下側的應力，從而降低翹曲。抗翹曲層26的厚度可例如為介電層201的厚度的至少兩倍。抗翹曲層26的厚度可例如大於20微米。另外，抗翹曲層26的楊氏模量可例如大於聚醯亞胺(polyimide)的楊氏模量。抗翹曲層26可例如包括矽氧烷聚合物(例如台灣信越矽利光(shin-etsu chemical)的模塑材料)、乾膜類型的防焊(solder resist)材料、味之素積層膜(ajinomoto build-up film,ABF)或其他合適的材料。
如第1圖所示，重佈線層20可包括一導電層202a與一介電層201a，其中介電層201a設置於導電層202a與抗翹曲層26之間。介電層201a可具有複數個第三穿孔TH3，抗翹曲層26可具有複數個第四穿孔TH4，且第三穿孔TH3與對應的第四穿孔TH4可曝露出導電層202a。
如第1圖所示，封裝結構1可選擇性另包括複數個導電端子28，設置於重佈線層12遠離主動晶片16的一側，並用於與其他元件接合與電性連接。在本實施例中，封裝結構1還可選擇性包括電子元件30，設置於重佈線層12遠離主動晶片16的一側，並與重佈線層12電性連接。舉例來說，電子元件30可為包括主動元件及/或被動元件的晶片。電子元件30可例如包括多層陶瓷電容(multilayer ceramic capacitor,MLCC)、積體被動元件(integrated passive device,IPD)或其他合適的元件。
第2圖繪示本發明另一實施例的封裝結構的剖面示意圖。如第2圖所示，本實施例的封裝結構2與第1圖所示的封裝結構1的區別在於，還可包至少一封裝元件32，設置於重佈線層20上。封裝元件32可透過導電端子34與重佈線層20接合並電性連接。舉例來說，每個導電端子34可設置於對應的第三穿孔TH3與第四穿孔TH4中。封裝元件32可例如包括至少一晶片321、線路層322、封裝層323及/或其他合適的元件，其中封裝層323可例如將晶片321密封於線路層322上，且晶片321可透過線路層322電連接到導電端子34，從而電性連接至重佈線層20。線路層322可包括至少一層介電層以及至少一層導電層，用以將晶片321電性連接至重佈線層20。晶片321可例如電源管理晶片、微機電系統晶片、記憶體晶片、系統晶片、高效能運算晶片或其他類似的晶片。線路層322可例如包括重佈線層、電路板、或其他具有線路的膜層或基板。本發明的封裝元件32不以此上述為限，而可為任何形式或種類的元件。本實施例的封裝結構2中的其他部分可相同於封裝結構1，因此在此不多贅述。
請參考第3圖至第8圖，其中第3圖繪示本發明一實施例的封裝結構的製作方法流程圖，且第4圖至第8圖繪示本發明一實施例在製作方法的不同步驟中的結構剖視示意圖。如第3圖所示，本實施例所提供的製作方法可例如包括依序進行的步驟S12至步驟S110，並將搭配第1圖與第4至8圖詳述於下文中。在一些實施例中，步驟S12至步驟S110之前、之後或其中任兩個步驟之間或在進行其中任一個步驟的同時間也可進行其他步驟。
如第3圖與第4圖所示，在步驟S12中，先提供載板36。然後，於載板36上形成重佈線層20。形成重佈線層20的方式可例如依序交替形成介電層201與導電層202。介電層201可例如包括聚醯亞胺或其他合適的材料。導電層202可包括銅、鎳、鋁、鎢、其他合適的材料或上述的組合。需說明的是，本實施例重佈線層20中最鄰近載板36的介電層201a在步驟S12中可不具有穿孔，但不限於此。
在本實施例中，載板36上可選擇性具有離型層(release layer)38，且重佈線層20形成於離型層38上，但不限於此。載板36可用以承載形成於其上的膜層或元件，載板36可例如包括玻璃、晶圓基板、金屬或其他合適的支撐材料，但不限於此。離型層38可用以在完成後續步驟之後將載板36與其上所形成的元件(例如，第7圖所示的半成品結構1a)分離。離型層38的解離方式可例如包括光解離或其他合適的方式。離型層38可例如包括聚乙烯(polyethylene,PE)、聚對苯二甲酸乙二酯(polyethylene terephthalate,PET)、環氧樹脂(epoxy)、定向拉伸聚丙烯(oriented polypropylene,OPP)或其他合適的材料，但不限於此。
如第3圖與第4圖所示，在步驟S14中，於重佈線層20上形成導電柱14並設置主動晶片16。在本實施例中，導電柱14可在設置主動晶片16之前形成在重佈線層20上，但不限於此。主動晶片16可以主動面16S1朝上的方式(即，接墊16a朝向主動晶片16遠離重佈線層20的一側)透過黏著層24將其背面16S2貼附於 重佈線層20上。值得一提的是，導電柱14與主動晶片16是並排設置於重佈線層20上，因此導電柱14靠近重佈線層20的表面與黏著層24靠近重佈線層20的表面可例如位於同一平面上。在本實施例中，主動晶片16的接墊16a上不具有凸塊，且在此情況下，導電柱14的高度T2可小於接墊16a遠離重佈線層20的表面與重佈線層20之間的距離，即主動晶片16的厚度T1與黏著層24的厚度總和。例如，導電柱14的高度T2可小於主動晶片16的厚度T1。
如第3圖與第5圖所示，在步驟S16中，於重佈線層20、導電柱14以及主動晶片16上形成封裝層18。封裝層18可例如包括感光封裝材料、模塑化合物(molding compound)或其他合適的封裝材料，但不限於此。感光封裝材料可包括矽氧烷聚合物(例如台灣信越矽利光的SINR)，或其他合適的有機材料。模塑化合物可例如包括環氧樹脂(epoxy)或其他合適的材料。在本實施例中，封裝層18可例如為乾膜(dry film)類型的感光封裝材料，並透過貼合製程(lamination process)設置在導電柱14與主動晶片16上，並環繞導電柱14及主動晶片16。
然後，於封裝層18中形成第一穿孔TH1及第二穿孔TH2。第一穿孔TH1可分別曝露出對應的主動晶片16的接墊16a，第二穿孔TH2可分別曝露出對應的導電柱14。在本實施例中，當封裝層18可例如包括感光封裝材料時，第一穿孔TH1與第二穿孔TH2可例如透過微影製程(即曝光與顯影製程)或進一步搭配蝕刻製程形成。在此情況下，接墊16a在形成第一穿孔TH1與第二穿孔TH2的過程中不易受到損壞，因此接墊16a上可不需形成導電凸塊，從而可省略製作導電凸塊的時間與成本，及/或可降低後續所形成的封裝結構1的厚度。此外，由於導電柱14的高度T2可小於接墊16a遠離重佈線層20的表面與重佈線層20之間的距離，因此第二穿孔TH2的深度H2可大於第一穿孔TH1的深度H1，但不限於此。此外，第二穿孔TH2的孔徑W2也可大於第一穿孔TH1的孔徑W1，但不限於此。需說明的是，具有不同深度的第一穿孔TH1與第二穿孔TH2可由同一製程所形 成，因此可降低製作成本及/或簡化步驟。
在一些實施例中，當封裝層18包括模塑材料時，第一穿孔TH1與第二穿孔TH2可例如透過雷射鑽孔(laser drilling)製程所形成。在此情況下，為了降低或避免接墊16a受到雷射鑽孔製程損壞，可在主動晶片16設置於重佈線層20上之前，選擇性於接墊16a上形成導電凸塊。
如第3圖與第6圖所示，在步驟S18中，於封裝層18、接墊16a與導電柱14上形成重佈線層12，從而形成半成品結構1a。形成重佈線層12的方式可例如依序交替形成導電層122與介電層121。在本實施例中，最鄰近主動晶片16的導電層122a(即第一個形成的導電層122a)可形成於封裝層18的上表面上，並形成於封裝層18的第一穿孔TH1與第二穿孔TH2中。由於第二穿孔TH2的孔徑W2(如第5圖所示)大於第一穿孔TH1的孔徑W1，因此導電層122a可不填滿第二穿孔TH2，而是填滿第一穿孔TH1。緊接著在導電層122a形成之後所形成的介電層121a可形成於導電層122a上，並填入第二穿孔TH2中，例如可進一步填滿第二穿孔TH2。
在一些實施例中，形成導電層122a的方式可例如包括先於封裝層18上形成介面層SE1，於介面層SE1上形成具有穿孔的圖案化光阻層(圖未示)，以曝露出部分介面層SE1，於曝露出的介面層SE1上形成金屬層M1，然後移除圖案化光阻層以及介面層SE1未形成有金屬層M1的部分。形成介面層SE1的方式可例如包括物理氣相沉積製程或其他合適的製程。形成金屬層M1的方式可例如包括電鍍(electroplating)製程或其他合適的製程。此外，其他導電層122形成的方式也可例如相同或類似形成導電層122a的方式，在此不多贅述。介電層121的材料可例如相同或類似於介電層201的材料。導電層122的材料可例如相同或類似於導電層202的材料。
如第3圖與第7圖所示，在步驟S110中，移除載板36與離型層38，以 曝露出重佈線層20中最鄰近載板36的介電層201a。移除載板36的方式可例如包括對離型層38照射光線，以降低離型層38的黏著力，進而移除載板36，但不限於此。然後，可上下翻轉半成品結構1a，並選擇性於重佈線層20遠離主動晶片16的一側上設置抗翹曲層26。設置抗翹曲層26的方式可例如包括貼合製程(lamination process)或其他合適的製程。接著，於抗翹曲層26中形成第四穿孔TH4，並於最鄰近載板36的介電層201a中形成第三穿孔TH3。在本實施例中，第三穿孔TH3與第四穿孔TH4可由同一製程所形成，因此可降低製作成本及/或簡化步驟，但不限於此。在此情況下，第三穿孔TH3的側壁可與對應的第四穿孔TH4的側壁共平面。第三穿孔TH3與第四穿孔TH4的形成方式可例如包括雷射鑽孔、乾蝕刻或其他合適的製程。
如第8圖所示，在移除載板36之後，可於重佈線層12遠離主動晶片16的一側上設置導電端子28。設置導電端子28的方式可例如包括電鍍、沉積、植球(ball mounting)、迴焊(reflow)及/或其他合適的製程。導電端子28可例如包括焊球、導電凸塊或其他合適的導電端子。焊球可例如包括錫球。導電凸塊可例如包括多層結構。導電凸塊可例如包括銅、鎳、錫、銀、其他合適的材料、上述至少兩者的合金或上述的組合，但不限於此。在一些實施例中，在移除載板36與設置導電端子28之間或在設置導電端子28之後，可選擇性於重佈線層12遠離主動晶片16的一側上設置電子元件30。
如第8圖所示，在形成導電端子28或電子元件30之後，可選擇性進行單體化製程(singulation process)，以形成至少一個封裝結構1，如第1圖所示。單體化製程可例如包括切割製程或其他合適的製程。在第7圖與第8圖的實施例中，由於半成品結構1a可包括至少兩個主動晶片16，因此單體化製程可將不同的主動晶片16分隔開，以形成至少兩個封裝結構1，但不限於此。在一些實施例中，當半成品結構1a僅能用於單一封裝結構1時，可不需進行單體化製程，但不 限於此。
在一些實施例中，如第2圖所示，在形成封裝結構1之後，可進一步於重佈線層20遠離主動晶片16的一側上設置封裝元件32。舉例來說，導電端子34可先設置於封裝元件32的線路層322下，然後以導電端子34對應第四穿孔TH4的方式將封裝元件32接合於重佈線層20上。封裝元件32可例如參照上文，且導電端子34可例如相同或類似導電端子28，在此不多贅述。
綜上所述，在本發明的封裝結構中，透過封裝層中具有不同深度的第一穿孔與第二穿孔，分別對應第一穿孔與第二穿孔的主動晶片與導電柱可電連接至同一重佈線層，因此主動晶片的厚度可不需小於導電柱的高度，從而解決主動晶片的厚度受限的問題。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1:封裝結構
12,20:重佈線層
121,121a,201,201a:介電層
122,122a,202,202a:導電層
14:導電柱
16:主動晶片
16a:接墊
16m:主體部
16n:絕緣層
16S1:主動面
16S2:背面
18:封裝層
24:黏著層
26:抗翹曲層
28:導電端子
30:電子元件
H1,H2:深度
HD:水平方向
L1:第一走線
L2:第二走線
M1:金屬層
SE1:介面層
T1:厚度
T2:高度
TD:俯視方向
TH1:第一穿孔
TH2:第二穿孔
TH3:第三穿孔
TH4:第四穿孔
W1,W2:孔徑

Claims (7)

  1. 一種封裝結構，包括：一重佈線層；一導電柱與一主動晶片，並排設置於該重佈線層上，其中該主動晶片具有一接墊；一封裝層，環繞該主動晶片及該導電柱，其中該封裝層具有一第一穿孔以及一第二穿孔，該第一穿孔設置於該主動晶片的該接墊與該重佈線層之間，該第二穿孔設置於該導電柱與該重佈線層之間，且該第一穿孔的深度小於該第二穿孔的深度；以及另一重佈線層，設置於該主動晶片遠離於該重佈線層的一側，並透過該導電柱電性連接該重佈線層，其中該重佈線層包括一第一走線以及一第二走線，該第一走線填滿該第一穿孔，該第二走線沿著該第二穿孔的側壁以及該導電柱的表面設置，該第一走線與該第二走線由相同的導電層所形成，該導電層包括一介面層以及一金屬層，依序設置於該封裝層上，且該金屬層設置於該第一穿孔中。
  2. 如請求項1所述的封裝結構，其中該重佈線層包括一介電層，設置於該第二穿孔中。
  3. 如請求項1所述的封裝結構，另包括一抗翹曲層，設置於該另一重佈線層遠離該主動晶片的一側，且該重佈線層的介電層數量不同於該另一重佈線層的介電層數量。
  4. 如請求項1所述的封裝結構，其中該封裝層設置於該重佈線層與該主動晶片之間。
  5. 如請求項1所述的封裝結構，其中該第一穿孔的孔徑小於該第二穿孔的孔徑。
  6. 如請求項1所述的封裝結構，其中該封裝層包括感光封裝材料或模塑材料。
  7. 一種封裝結構的製作方法，包括：於一載板上形成一重佈線層；於該重佈線層上形成一導電柱並設置一主動晶片，其中該主動晶片具有一接墊，朝向該主動晶片遠離該重佈線層的一側；於該重佈線層、該導電柱以及該主動晶片上形成一封裝層，其中該封裝層環繞該導電柱以及該主動晶片，該封裝層具有一第一穿孔以及一第二穿孔，該第一穿孔曝露出該主動晶片的該接墊，該第二穿孔曝露出該導電柱，且該第一穿孔的深度小於該第二穿孔的深度；於該封裝層遠離該重佈線層的一側上形成另一重佈線層；以及移除該載板。
TW111127038A 2022-07-19 2022-07-19 封裝結構及其製作方法 TWI809986B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW111127038A TWI809986B (zh) 2022-07-19 2022-07-19 封裝結構及其製作方法
US18/083,579 US20240030121A1 (en) 2022-07-19 2022-12-19 Package structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW111127038A TWI809986B (zh) 2022-07-19 2022-07-19 封裝結構及其製作方法

Publications (2)

Publication Number Publication Date
TWI809986B true TWI809986B (zh) 2023-07-21
TW202406064A TW202406064A (zh) 2024-02-01

Family

ID=88149451

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111127038A TWI809986B (zh) 2022-07-19 2022-07-19 封裝結構及其製作方法

Country Status (2)

Country Link
US (1) US20240030121A1 (zh)
TW (1) TWI809986B (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106935519A (zh) * 2013-05-03 2017-07-07 日月光半导体制造股份有限公司 半导体封装构造及其制造方法
TW201926631A (zh) * 2017-11-30 2019-07-01 南韓商三星電機股份有限公司 半導體封裝
TW202038405A (zh) * 2019-04-12 2020-10-16 力成科技股份有限公司 半導體封裝及其製造方法
TW202129858A (zh) * 2020-01-03 2021-08-01 南韓商三星電子股份有限公司 半導體封裝

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106935519A (zh) * 2013-05-03 2017-07-07 日月光半导体制造股份有限公司 半导体封装构造及其制造方法
TW201926631A (zh) * 2017-11-30 2019-07-01 南韓商三星電機股份有限公司 半導體封裝
TW202038405A (zh) * 2019-04-12 2020-10-16 力成科技股份有限公司 半導體封裝及其製造方法
TW202129858A (zh) * 2020-01-03 2021-08-01 南韓商三星電子股份有限公司 半導體封裝

Also Published As

Publication number Publication date
TW202406064A (zh) 2024-02-01
US20240030121A1 (en) 2024-01-25

Similar Documents

Publication Publication Date Title
US11887952B2 (en) Semiconductor device encapsulated by molding material attached to redistribution layer
TWI702663B (zh) 半導體裝置及其製造方法
US11282761B2 (en) Semiconductor packages and methods of manufacturing the same
US9502386B2 (en) Fan-out package structure and methods for forming the same
TWI649845B (zh) 半導體封裝結構及其製造方法
US9876002B2 (en) Microelectronic package with stacked microelectronic units and method for manufacture thereof
US9437536B1 (en) Reversed build-up substrate for 2.5D
TW201714275A (zh) 半導體封裝結構及其形成方法
US8263871B2 (en) Mount board and semiconductor module
KR102647008B1 (ko) 팬 아웃 패키지 및 이의 형성 방법
US10332854B2 (en) Anchoring structure of fine pitch bva
TW201828428A (zh) 封裝體裝置及其製造方法
KR20140115597A (ko) 반도체패키지, 반도체패키지유닛 및 반도체패키지 제조방법
TW202133351A (zh) 半導體封裝
TWI809986B (zh) 封裝結構及其製作方法
TWI810841B (zh) 封裝元件及其製作方法
TWI773360B (zh) 電子封裝件及其承載結構與製法
TWI832348B (zh) 封裝結構及其製作方法
US20240213223A1 (en) Semiconductor package and method of manufacturing the semiconductor package
KR102457349B1 (ko) 반도체 패키지들 및 이의 제조 방법들
TWI807660B (zh) 封裝元件及其製作方法
TW202230666A (zh) 半導體封裝