TW201820472A - 半導體結構及其製造方法 - Google Patents
半導體結構及其製造方法 Download PDFInfo
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- TW201820472A TW201820472A TW106122686A TW106122686A TW201820472A TW 201820472 A TW201820472 A TW 201820472A TW 106122686 A TW106122686 A TW 106122686A TW 106122686 A TW106122686 A TW 106122686A TW 201820472 A TW201820472 A TW 201820472A
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- wafer
- dielectric layer
- semiconductor structure
- item
- tungsten
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 239000004065 semiconductor Substances 0.000 title claims description 32
- 238000004140 cleaning Methods 0.000 claims abstract description 79
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 48
- 239000010937 tungsten Substances 0.000 claims abstract description 48
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 40
- 239000000126 substance Substances 0.000 claims abstract description 37
- 238000011049 filling Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 188
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 49
- 229910052799 carbon Inorganic materials 0.000 claims description 49
- 239000000243 solution Substances 0.000 claims description 48
- 229910052751 metal Inorganic materials 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 45
- 238000005498 polishing Methods 0.000 claims description 36
- 239000011229 interlayer Substances 0.000 claims description 29
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 150000001412 amines Chemical class 0.000 claims description 13
- 230000007935 neutral effect Effects 0.000 claims description 13
- 239000012670 alkaline solution Substances 0.000 claims description 12
- 239000007788 liquid Substances 0.000 claims description 7
- 239000003929 acidic solution Substances 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 44
- 239000003112 inhibitor Substances 0.000 description 19
- 238000005229 chemical vapour deposition Methods 0.000 description 13
- 125000006850 spacer group Chemical group 0.000 description 13
- 239000007769 metal material Substances 0.000 description 11
- 229910021332 silicide Inorganic materials 0.000 description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 10
- 239000000758 substrate Substances 0.000 description 10
- 230000007797 corrosion Effects 0.000 description 9
- 238000005260 corrosion Methods 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000002513 implantation Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 230000002378 acidificating effect Effects 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000000137 annealing Methods 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000009969 flowable effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 239000012263 liquid product Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical compound [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000007983 Tris buffer Substances 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000007853 buffer solution Substances 0.000 description 1
- 239000006172 buffering agent Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 210000003608 fece Anatomy 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- IZXGZAJMDLJLMF-UHFFFAOYSA-N methylaminomethanol Chemical compound CNCO IZXGZAJMDLJLMF-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 150000007524 organic acids Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000011780 sodium chloride Substances 0.000 description 1
- 239000001509 sodium citrate Substances 0.000 description 1
- NLJMYIDDQXHKNR-UHFFFAOYSA-K sodium citrate Chemical compound O.O.[Na+].[Na+].[Na+].[O-]C(=O)CC(O)(CC([O-])=O)C([O-])=O NLJMYIDDQXHKNR-UHFFFAOYSA-K 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- -1 tungsten ions Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02052—Wet cleaning only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
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Abstract
半導體結構的製造方法包含在晶圓上形成第一介電層,蝕刻第一介電層以形成開口,填充含鎢材料至開口中,以及對晶圓實施化學機械研磨。在化學機械研磨之後,使用弱鹼性溶液對晶圓實施清潔。
Description
本發明實施例係有關於半導體結構及其製造方法,且特別關於具有接觸插塞連接至矽化物區的半導體結構及其製造方法。
在積體電路的製造中,接觸插塞用於連接電晶體的源極和汲極區以及閘極。源極/汲極接觸插塞通常與源極/汲極矽化物區連接,源極/汲極接觸插塞係藉由形成接觸開口暴露出源極/汲極區,沉積金屬層,實施退火讓金屬層與源極/汲極區反應,填充鎢至剩餘的接觸開口中,以及實施化學機械研磨(Chemical Mechanical Polish,CMP)來移除過量的鎢而形成。然後,實施清潔步驟。
本發明的一些實施例提供半導體結構的製造方法,此方法包含在晶圓上形成第一介電層,蝕刻第一介電層以形成第一開口,填充含鎢材料至第一開口中,對晶圓實施第一化學機械研磨,以及在第一化學機械研磨之後,使用弱鹼性溶液對晶圓實施第一清潔。
本發明的一些實施例提供半導體結構的製造方 法,此方法包含形成層間介電層,其具有一部分與電晶體的閘極堆疊在相同水平高度,其中層間介電層和閘極堆疊是晶圓的一部分,蝕刻層間介電層以形成源極/汲極接觸開口,其中通過源極/汲極接觸開口暴露出電晶體的源極/汲極區,在晶圓上沉積第一含鎢材料,其中第一含鎢材料包括一部分填充源極/汲極接觸開口,對晶圓實施化學機械研磨以移除第一含鎢材料的過量部分,使用包括有機胺的清潔溶液清潔晶圓,其中清潔溶液是弱鹼性溶液,以及乾燥晶圓。
本發明的一些實施例提供半導體結構,其包含第一介電層,第一金屬插塞位於第一介電層中,其中第一金屬插塞的頂面與第一介電層的頂面大體上共平面,富含碳層覆蓋在第一金屬插塞上方且與第一金屬插塞接觸,其中富含碳層具有第一碳濃度,其高於第一金屬插塞的第二碳濃度,以及第二介電層覆蓋在富含碳層上方且與富含碳層接觸。
10‧‧‧晶圓
20‧‧‧基底
22‧‧‧源極/汲極區
24‧‧‧閘極介電層
26、26A、26B‧‧‧閘極堆疊
28‧‧‧閘極電極
30‧‧‧閘極間隔物
34‧‧‧接觸蝕刻停止層
36‧‧‧層間介電層
38‧‧‧硬遮罩
40‧‧‧接觸開口
44‧‧‧接觸間隔物
46‧‧‧金屬層
46A‧‧‧底部部分
46B‧‧‧側壁部分
48‧‧‧蓋層
50‧‧‧矽化物區
52‧‧‧退火
54、76、84、94‧‧‧金屬材料
56、56’‧‧‧源極/汲極接觸插塞
57‧‧‧研磨墊
58、58’‧‧‧清潔溶液
61、61’‧‧‧刷子
62‧‧‧層
64‧‧‧清潔空氣
66、92‧‧‧凹陷
68‧‧‧蝕刻停止層
70、95‧‧‧介電層
72、90‧‧‧導電部件
74、82‧‧‧黏著/阻障層
78‧‧‧閘極接觸開口
80‧‧‧閘極接觸插塞
86‧‧‧富含碳層
200‧‧‧製程流程圖
202、204、206、208、210、212、216、218、220‧‧‧步驟
W1、W2、W3‧‧‧寬度
D、D1、D2‧‧‧深度
藉由以下的詳述配合所附圖式,可以更加理解本發明實施例的觀點。值得注意的是,根據本產業的標準慣例,各個不同部件(feature)未必按照比例繪製。事實上,為了清楚地討論,各個不同部件的尺寸可隨意被增加或減少。
第1至12圖係根據一些實施例顯示形成電晶體以及接觸插塞的各個中間階段之剖面示意圖。
第13圖顯示具有富含碳層留在接觸插塞的頂端上之接觸插塞的剖面示意圖。
第14圖顯示使用酸性溶液或中性液體對額外的金屬部件 實施清潔。
第15圖係根據一些實施例顯示形成電晶體的製程流程圖。
以下敘述提供了許多不同的實施例或範例,用於實施本發明實施例的不同部件。下面描述了組件和配置的具體範例,以簡化本發明實施例。當然,這些僅僅是範例,並非意圖限制本發明實施例。舉例而言,敘述中若提及第一部件形成於第二部件之上,可能包含形成第一和第二部件直接接觸的實施例,也可能包含額外的部件形成於第一和第二部件之間,使得第一和第二部件不會直接接觸的實施例。另外,本發明實施例可能在許多範例中重複參照的標號及/或字母。這些重複的目的是為了簡化和清楚,其本身並非用於表示各種實施例及/或所討論的配置之間的關係。
再者,在以下敘述中可使用空間上相關措辭,例如「在......之下」、「在......下方」、「下方的」、「在......上方」、「上方的」和其他類似的用語,以簡化一元件或部件與其他元件或其他部件之間如圖所示之關係的陳述。此空間相關措辭除了包含圖式所描繪之方位,還包含裝置在使用或操作中的不同方位。裝置可以朝其他方位定位(旋轉90度或在其他方位),且在此使用的空間相關描述可依此相應地解讀。
根據各種示範實施例提供具有接觸插塞連接至矽化物區(silicide region)的電晶體及其製造方法,以圖示說明形成電晶體的各個中間階段,並討論一些實施例的變化。在各種示意圖和說明的實施例中,相似的參照標號用於標示相似的元 件。第1至12圖所示的步驟也示意地顯示於第15圖所示的製程流程圖200中。
第1至12圖是根據一些示範實施例,顯示形成電晶體及個別的接觸插塞之各個中間階段的剖面示意圖。參考第1圖,提供晶圓10。晶圓10包含基底20,其可由半導體材料例如矽、矽鍺、矽碳、三五族(III-V)化合物半導體材料或類似材料形成。基底20可以是整體基底(bulk substrate)或絕緣體上的半導體(Semiconductor-On-Insulator,SOI)基底。
在基底20上形成共同稱作閘極堆疊26的閘極堆疊26A與26B。根據本發明的一些實施例,閘極堆疊26A與26B形成閘極堆疊條(晶圓10的上視角度中)形式,其具有互相平行的縱向方向,其中將閘極堆疊26A與26B之間的距離最小化。每一個閘極堆疊26A與26B可包含閘極介電層24、在閘極介電層24上的閘極電極28以及在閘極電極28上的硬遮罩38。根據本發明的一些實施例,閘極堆疊26是置換(replacement)閘極堆疊,置換閘極堆疊由形成虛設(dummy)閘極堆疊(未顯示),移除虛設閘極堆疊以形成凹陷,以及在凹陷中形成置換閘極所形成。因此,每一個閘極介電層24包含在各自的閘極電極28底下的底部部分,以及在各自的閘極電極28之側壁上的側壁部分,側壁部分形成圍繞各自的閘極電極28的環形。
根據本發明的一些實施例,形成源極和汲極區22(此後稱作源極/汲極區22)延伸至基底20中。根據另一些的實施例,在形成如第2圖所示的接觸開口之後,形成源極/汲極區22。源極/汲極區22的一個或多個可以是被閘極堆疊26A與26B 共用的共同源極區或共同汲極區。因此,閘極堆疊26A可與在閘極堆疊26A之相對側的源極/汲極區22結合形成第一電晶體,並且閘極堆疊26B可與在閘極堆疊26B之相對側的源極/汲極區22結合形成第二電晶體,第一電晶體與第二電晶體可以並聯方式電性連接,作為單一的電晶體。
閘極介電層24可以是單層或是包含複數層的複合層。舉例而言,閘極介電層24可包含界面氧化物層,以及在氧化物層上的高介電常數(high-k)介電層。氧化物層可以是透過熱氧化或化學氧化所形成的氧化矽層。高介電常數介電層可以具有大於7或甚至大於20的介電常數。示範的高介電常數材料包含氧化鉿、氧化鋯、氧化鑭以及類似材料。
根據本發明的一些實施例,每一個閘極電極28具有由均質的導電材料所形成的單層結構。根據另一些實施例,每一個閘極電極28具有複合結構,此複合結構包含由TiN、TaSiN、WN、TiAl、TiAlN、TaC、TaN、鋁或前述之合金所形成的複數層。形成閘極電極28可包含物理氣相沉積(Physical Vapor Deposition,PVD)、金屬有機化學氣相沉積(Metal-Organic Chemcal Vapor Deposition,MOCVD)及/或其他適當的方法。舉例而言,硬遮罩38可由氮化矽形成。
根據本發明的另一些實施例,閘極堆疊26A與26B是藉由沉積毯覆的閘極介電層和毯覆的閘極電極層(例如多晶矽層),然後將毯覆的閘極介電層和毯覆的閘極電極層圖案化形成,而不是置換閘極堆疊。
再參考第1圖,形成接觸蝕刻停止層(Contact Etch Stop Layer,CESL)34覆蓋基底20,並且接觸蝕刻停止層34可延伸在閘極間隔物30的側壁上。根據本發明的一些實施例,接觸蝕刻停止層34是由氮化矽、碳化矽或其他介電材料形成。在接觸蝕刻停止層34以及閘極堆疊26A與26B上形成層間介電層(Inter-Layer Dielectric,ILD)36。層間介電層36可由氧化物例如磷矽酸鹽玻璃(Phospho-Silicate Glass,PSG)、硼矽酸鹽玻璃(Boron-Silcate Glass,BSG)、摻雜硼的磷酸鹽矽玻璃(Boron-Doped Phospho-Silicate Glass,BPSG)、四乙氧基矽烷(Tetra Ethyl Ortho Silicate,TEOS)或類似材料形成。舉例而言,此形成可包含化學氣相沉積(CVD)、可流動化學氣相沉積(Flowable CVD,FCVD)、旋轉塗佈(spin-on coating)或類似方法。
參考第2圖,蝕刻層間介電層36和接觸蝕刻停止層34以形成接觸開口40。此個別的步驟在第15圖所示的製程流程圖200之步驟202說明。根據一些實施例,接觸開口40是源極/汲極接觸開口。接觸開口40暴露出源極/汲極區22(如果已經形成)。根據本發明的一些實施例,接觸開口40具有小於約40nm的寬度W1,其深度D可大於約45nm。
根據一些實施例,其中源極/汲極區22在此時尚未形成,可實施預先非晶相化植入(Pre-Amorphization Implantion,PAI)以及源極/汲極植入來形成源極/汲極區22,其中用於形成源極/汲極區22的非晶相化植入(PAI)種類和植入雜質經由接觸開口40植入至基底20中。為了控制後續源極/汲極區植入的深度,可使用鍺、矽或類似材料實施非晶相化植入 (PAI),此非晶相化植入(PAI)破壞植入區的晶格結構。如果個別的電晶體是p型電晶體,可使用硼或銦實施源極/汲極植入,或者如果對應的電晶體是n型電晶體,可使用磷、砷或銻實施源極/汲極植入。
第3圖是根據本發明的一些實施例,顯示接觸(插塞)間隔物44之形成。形成接觸間隔物44可包含沉積一或多層順應性(conformal)的介電層。介電層延伸至接觸開口40中,並且包含在層間介電層36的側壁上的垂直部分,以及在接觸開口40的底部和在層間介電層36上的水平部分。使用順應性沉積製程例如原子層沉積(Atomic Layer Deposition,ALD)、化學氣相沉積(CVD)或類似製程實施沉積製程,使得沉積層的水平部分與垂直部分具有相似的厚度。接著,實施異向性蝕刻來移除水平部分,留下垂直部分作為接觸間隔物44。可使用氨氣(NH3)和NF3作為蝕刻氣體實施異向性蝕刻。值得注意的是,當從晶圓10的上視角度觀之,在同一個接觸開口40中的接觸間隔物44是整體間隔物環的一部份。
根據本發明的一些實施例,接觸間隔物44是由對於氧化物具有高蝕刻選擇性的介電材料所形成,使得在後續的清潔製程(在此製程中移除氧化物)中接觸間隔物44不會受損。舉例而言,接觸間隔物44可由氮化矽、矽氧碳化物(silicon oxy-carbide)、氮氧化矽或類似材料形成。
在本發明另一些的實施例中,不形成接觸間隔物44。因此,使用虛線顯示接觸間隔物44以表示此步驟可以實施或略過。根據這些實施例,後續形成的金屬層46(第4圖)可具有 與層間介電層36的側壁接觸的側壁部分。
接下來,參考第4圖,沉積金屬層46。此個別的步驟在第15圖所示的製程流程圖200之步驟204說明。根據本發明的一些實施例,金屬層46是鈦(Ti)層,其可使用物理氣相沉積(PVD)形成。金屬層46包含在接觸開口40之底部的底部部分46A,以及在層間介電層36的側壁表面上的側壁部分46B。金屬層46有兩個功能。第一個功能是金屬層46的底部部分46A與底下的源極/汲極區22反應,以形成源極/汲極矽化物區。第二個功能是金屬層46作為後續形成的覆蓋/黏著層的黏著層。
參考第5圖,沉積蓋層48。此個別的步驟在第15圖所示的製程流程圖200之步驟206說明。蓋層48也作為擴散阻障層。根據本發明的一些實施例,蓋層48由金屬氮化物例如氮化鈦形成。可使用物理氣相沉積(PVD)、化學氣相沉積(CVD)或類似製程形成蓋層48。
第6圖顯示用於形成矽化物區50的矽化物製程(silicidation process)。根據本發明的一些實施例,透過退火52實施矽化物製程,其用箭號表示。此個別的步驟在第15圖所示的製程流程圖200之步驟208說明。可透過快速熱退火(Rapid Thermal Anneal,RTA)、爐管退火或類似製程實施退火。因此,金屬層46的底部部分46A與源極/汲極區22反應以形成矽化物區50。在矽化物製程之後,如第6圖所示,金屬層46的側壁部分46B保留。根據本發明的一些實施例,金屬層46的底部部分46A完全反應,並且矽化物區50的頂面與蓋層48的底面接觸。
接下來,金屬材料54填充至剩餘的接觸開口40 中,並且所得到的晶圓10顯示於第7圖。此個別的步驟在第15圖所示的製程流程圖200之步驟210說明。金屬材料54可由含鎢材料形成,此含鎢材料可由純的或大體上純的鎢(例如,具有原子百分比大於約95%)形成。在本發明另一些的實施例中,金屬材料54包含鈦。金屬材料54不含銅、鈷或類似材料,因為這些材料在後續製程中的表現不同於鎢,因此這些材料無法從本發明的實施例受益。
接下來,如第7圖所示,實施平坦化製程例如化學機械研磨(Chemcal Mechanical Polish,CMP)來移除在層間介電層36上的金屬材料54、蓋層48以及金屬層46之過量部分。如第8圖所示,因此形成源極/汲極接觸插塞56。此個別的步驟在第15圖所示的製程流程圖200之步驟212說明。第7圖示意地顯示研磨墊57。在真實的化學機械研磨(CMP)製程中,研磨墊57的尺寸/直徑可大於晶圓10的尺寸。在化學機械研磨(CMP)的過程中,研磨墊57可以面朝上,而晶圓10可面朝下且壓在研磨墊57上。在化學機械研磨(CMP)的過程中,旋轉晶圓10。在化學機械研磨(CMP)的過程中,施加研磨液(slurry)(未顯示)於研磨墊57上。
在化學機械研磨(CMP)完成之後,在清潔步驟中清潔晶圓10。此個別的步驟在第15圖所示的製程流程圖200之步驟214說明。第8圖示意地說明示範的清潔製程。在清潔過程中,刷子61可用於刷洗晶圓10,以刷掉化學機械研磨過程中所產生的降落物、研磨液以及副產物。根據本發明的一些實施例,刷子61是滾筒海綿刷,如圖所示其在清潔過程中旋轉。刷 子61也可以是筆刷。在示範的清潔中,首先使用滾筒海綿刷來刷洗晶圓10,接著使用筆刷清潔。當使用刷子61來刷洗晶圓10時,舉例而言,也可透過噴霧器對晶圓10施加清潔溶液58,使得化學機械研磨(CMP)過程中所產生的降落物、研磨液以及副產物被移除。在清潔的過程中,刷子61物理性地接觸晶圓10。使用溫度在約18℃至約21℃之間的清潔溶液58,以在約1.5分鐘至約2.5分鐘之間的時間實施此清潔步驟。
清潔環境可產生包含源極/汲極接觸插塞56的電流電極(galvanic electrode),並且部份的晶圓10電性連接至源極/汲極接觸插塞56,特別是N型金屬氧化物半導體(NMOS)電晶體以及N型井區。因此,引導電子從源極/汲極接觸插塞56離開進入源極/汲極區22中。金屬例如鎢損失電子至基底20,從而變成帶正電荷的金屬離子。在產生的腐蝕中金屬離子可損失至清潔溶液58中,導致金屬損失和源極/汲極接觸插塞56的凹陷。隨著凹陷,源極/汲極接觸插塞56的頂面將會低於層間介電層36的頂面。在源極/汲極接觸插塞56的寬度W2非常小,例如小於約20nm的實施例中,所產生的凹陷深且窄(具有高深寬比(aspect ratio)),並且後續形成上方的導電部件,如第12圖所示之導孔(via)或接觸插塞72,難以完全填充凹陷。根據本發明的一些實施例,在清潔溶液58中使用抑制劑,以減少且可能消除在清潔製程的過程中源極/汲極接觸插塞56的凹陷。
可以理解的是,清潔溶液58需要的酸鹼(PH)值與源極/汲極接觸插塞56的材料有關,源極/汲極接觸插塞56的表面將會被清潔。不同材料對於不同種類的清潔溶液有不同反 應。因此,在傳統製程中,在個別的化學機械研磨(CMP)之後,使用強鹼進行銅的清潔,並且在個別的化學機械研磨(CMP)之後,使用酸性或中性液體進行鎢的清潔。然而,酸性溶液可腐蝕/蝕刻鎢。此外,即使清潔溶液是中性,亦即PH值是7.0,在清潔的過程中會發生電流反應(galvanic reaction),並且鎢也會被腐蝕。在傳統的清潔製程中,使用酸性及/或中性清潔溶液清潔鎢插塞,因為酸性及/或中性清潔溶液的一些性質對鎢有反應。然而,酸性及/或中性清潔溶液也會造成鎢插塞的腐蝕。在傳統的結構中,由清潔引起的鎢損失沒有發生問題。原因是傳統結構中的鎢插塞是相對寬的,並且清潔所造成的凹陷之深度相較於鎢插塞的寬度是相對小的。因此,後續形成的上方導電材料可輕易地填充凹陷而不會造成斷路(open circuit)。然而,在積體電路的較新世代中,鎢插塞的寬度非常小,例如,可達到約20nm或更小。傳統清潔引起的腐蝕深度變得與源極/汲極接觸插塞56的寬度相當且有時候更大,導致深且窄的凹陷。當形成上方的導電部件72(第12圖)例如接觸插塞、導孔、金屬線等時,難以完全填充這樣的凹陷,並且可能導致斷路。
根據本發明的一些實施例,在清潔溶液58(其含有水)中加入抑制劑來防止鎢插塞的腐蝕。根據本發明的一些實施例,抑制劑由有機胺(organic amine)形成,有機胺例如可以是C5H15NO2。C5H15NO2的分子量等於121.18。抑制劑例如有機胺使得清潔溶液58的PH值為鹼/鹼性的(basic/alkaline)(具有PH值大於7.0)。這與傳統上在對鎢的化學機械研磨之後所使用的清潔溶液不同。清潔溶液58中的抑制劑附著至源極/汲極接觸 插塞56暴露出來的表面,其中繪示層62以表示附著的抑制劑。抑制劑帶負電荷,層62是碳濃縮層(carbon-concentrated layer),並且層62保護底下的源極/汲極接觸插塞56免於被清潔溶液58凹陷。因此,附著的抑制劑電性上切斷清潔溶液58與源極/汲極接觸插塞56之間的路徑,以及防止電子流入至源極/汲極區22,並且防止正電的鎢離子溶解至清潔溶液58中,因此減少腐蝕。
當清潔溶液58是具有PH值在7.0(不包含)至約8.0之間的範圍內之弱鹼性溶液時,清潔溶液58中的抑制劑作用良好。換言之,PH值大於7.0且小於約8.0。在中性或酸性環境中,抑制劑無法附著至源極/汲極接觸插塞56的表面,並且腐蝕將會發生。另一方面,如果清潔溶液58的PH值增加至大於約8.0或更高,抑制劑也開始逐漸失去它的抑制功能,並且鎢將會被個別的強鹼溶液腐蝕/蝕刻。根據本發明的一些實施例,調整清潔溶液的PH值大於7.0且小於約8.0使得抑制劑得以作用。
根據本發明的一些實施例,藉由調整有機胺的濃度達到清潔溶液58的PH值之調整。舉例而言,清潔溶液58中的有機胺的濃度可調整在約0.5%至約2%之間。可在清潔溶液58中加入緩衝劑,例如三羥甲基氨基甲烷((hydroxymethyl)aminomethane,TRIS)或檸檬酸鈉鹽(saline sodium citrate,SSC),讓清潔溶液58成為緩衝溶液,使得清潔溶液58的PH值可在期望的範圍內(在7.0至約8.0之間)保持定值。根據一些實施例,可加入其他化學品例如HCl來調整清潔溶液58的PH值。
在使用清潔溶液58清潔晶圓10之後,晶圓10上的 殘留物被剝離且刷除。如第9圖所示,對晶圓10吹送清潔空氣64來乾燥晶圓10。此個別的步驟在第15圖所示的製程流程圖200之步驟216說明。在完成化學機械研磨(CMP)的時間點至開始乾燥晶圓10的時間點(或完全乾燥晶圓10的時間點)的期間,沒有使用中性清潔溶液或酸性溶液來清潔晶圓10。此外,沒有使用PH值明顯高於8.0(例如8.5)的強鹼性溶液。因此,將源極/汲極接觸插塞56的腐蝕最小化。第9圖顯示所得到的晶圓10,其具有示意繪出的凹陷66(如果藉由清潔步驟形成)。藉由使用根據本發明實施例的方法來實施清潔,因為降低了腐蝕,凹陷66的深度D1可小於約50Å。在清潔之前,如果源極/汲極接觸插塞56具有部分凸出於層間介電層36的頂面,在清潔之後,源極/汲極接觸插塞56的頂面也可與層間介電層36的頂面共平面或是高於層間介電層36的頂面。
在如第1至9圖所示的步驟中,形成電晶體300。參考第10圖,根據本發明的一些實施例,形成蝕刻停止層68,接著形成介電層70。根據一些實施例,介電層70是層間介電層,因此也可稱為層間介電層(ILD1)70。根據一些實施例,也可省略蝕刻停止層68。因此,使用虛線顯示蝕刻停止層68來表示其可以形成或不形成。蝕刻停止層68可由碳化矽、氮氧化矽、矽碳氮化物、前述之組合或前述之複合層形成。可使用沉積方法例如化學氣相沉積(CVD)、電漿增強化學氣相沉積(Plasma Enhanced CVD,PECVD)、原子層沉積(ALD)或類似方法來形成蝕刻停止層68。介電層70可包含選自於PSG、BSG、BPSG、摻雜氟的矽玻璃(Flouorine-doped Silicon Glass,FSG)或TEOS 的材料。介電層70也可由無孔的低介電常數介電材料形成,其可以是含碳介電材料。可使用旋轉塗佈、可流動化學氣相沉積(FCVD)或類似製程形成介電層70,或者可使用例如化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)、低壓化學氣相沉積(Low Pressure CVD,LPCVD)或類似方法之沉積方法形成介電層70。
第10圖進一步顯示導電部件72之形成。蝕刻停止層68、介電層70以及導電部件72之形成在第15圖所示的製程流程圖200之步驟218說明。根據本發明的一些實施例,導電部件72是接觸插塞,並且沒有形成如第10圖所示的蝕刻停止層68。根據另一些實施例,導電部件72是銅導孔或銅線,且在這些實施例中,形成蝕刻停止層68。
導電部件72之形成可包含在蝕刻停止層68與介電層70內形成開口以暴露出源極/汲極接觸插塞56,在此開口中填充導電材料,以及實施平坦化。導電部件72可包含導電的黏著/阻障層74以及在黏著/阻障層74上的金屬材料76。黏著/阻障層74可由選自於鈦、氮化鈦、鉭、氮化鉭、前述之組合或前述之多層的材料所形成。金屬材料76可由鎢、銅、鋁或前述之合金形成,並且可使用物理氣相沉積(PVD)、金屬有機化學氣相沉積(MOCVD)或電鍍形成。如果因為清潔製程而形成第9圖中的凹陷66是有利的,因為根據本發明的一些實施例凹陷66是淺的,因此可輕易地填充導電部件72至凹陷66中而不會產生斷路。
第11和12圖顯示閘極接觸插塞之形成。此個別的 步驟在第15圖所示的製程流程圖200之步驟220說明。實施蝕刻製程來蝕刻介電層70、蝕刻停止層68、層間介電層36以及遮罩層38(第10圖),以形成如第11圖所示的閘極接觸開口78。接下來,以導電材料填充閘極接觸開口78來形成如第12圖所示的閘極接觸插塞80。根據本發明的一些實施例,閘極接觸插塞80包含導電的黏著/阻障層82,以及在黏著/阻障層82上的金屬材料84。黏著/阻障層82可由選自於鈦、氮化鈦、鉭、氮化鉭、前述之組合或前述之多層的材料所形成。金屬材料84可由鎢、銅、鋁或前述之合金所形成。
第13圖顯示留在源極/汲極接觸插塞56’之一些部分上的富含碳層86,富含碳層86包含層62(亦即附著的抑制劑)(第8圖)與其上方和底下的材料混合。根據一些實施例,源極/汲極接觸插塞56’與源極/汲極接觸插塞56在同一晶粒/晶圓上,並且與源極/汲極接觸插塞56同時形成。值得注意的是,儘管源極/汲極接觸插塞56’描繪為靠近閘極堆疊26,實際上源極/汲極接觸插塞56’可與閘極堆疊26隔開。源極/汲極接觸插塞56’不具有上方的導孔或接觸插塞與源極/汲極接觸插塞56’連接,並且在源極/汲極接觸插塞56’上形成富含碳層86且在最終結構中保留富含碳層86。富含碳層86可包含殘留的有機胺之混合物,此混合物是第8圖中的層62(亦即附著的抑制劑)。富含碳層86也可包含源極/汲極接觸插塞56’的材料及/或蝕刻停止層68或介電層70(當不形成蝕刻停止層68時)的材料。富含碳層86具有比下方的源極/汲極接觸插塞56’高的碳濃度。富含碳層86中的碳的百分比也可比上方的蝕刻停止層68(或介電層70)高。 根據一些實施例,富含碳層86中的碳的原子百分比源極/汲極接觸插塞56’以及上方的蝕刻停止層68(或介電層70,如果不形成蝕刻停止層68)中的碳的原子百分比高出15%或更高。可以理解的是,儘管在清潔的過程中層間介電層36也暴露於清潔溶液58(第8圖),因為鎢傾向於帶正電荷,並且清潔溶液58中的抑制劑以及層間介電層36傾向於為負電荷,抑制劑傾向於累積在源極/汲極接觸插塞56’與56的頂面,而不會在層間介電層36的頂面。因此,在如第13圖所示的結構中,在源極/汲極接觸插塞56’的頂面上有富含碳層86,而在層間介電層36的頂面上沒有富含碳層86。
在清潔製程之後立即的時間點,富含碳層86可存在於源極/汲極接觸插塞56’與56全部的頂面上。在形成蝕刻停止層68及介電層70之後,只要這些表面不再暴露出,對應的富含碳層將會被保存。舉例而言,如果導電部件72比底下的源極/汲極接觸插塞56窄,在形成用於填入導電部件72的開口時,可不暴露出源極/汲極接觸插塞56的一些頂面部分。因此,源極/汲極接觸插塞56的這些表面部分也將具有富含碳層位於其上且與其接觸。
第14圖顯示導電部件90之清潔,導電部件90與源極/汲極接觸插塞56形成在相同的晶圓上。導電部件90可由與源極/汲極接觸插塞56相似的金屬形成,並且可由鎢形成。根據一些實施例,導電部件90是閘極電極(例如第1圖中的標號28)、接觸插塞、金屬墊或重佈線。導電部件90的寬度W3大於寬度W2(第8圖的源極/汲極接觸插塞56)。導電部件90之形成包 含在介電層95中形成開口(以導電部件90填充),填充金屬材料94,其可包含鎢,以及實施化學機械研磨(CMP)。在化學機械研磨(CMP)之後,使用刷子61’以及清潔溶液58’實施清潔。根據本發明的一些實施例,清潔溶液58’包含有機酸,其可包含檸檬酸(C6H8O7)。也可使用中性液體(也以58’表示)例如去離子水實施此清潔。根據一些實施例,由於腐蝕所形成的凹陷92具有大於約100Å的深度D2。儘管此深度大於深度D1(第9圖),因為導電部件90的寬度W3遠大於寬度W2(例如,W3/W2之比值可以是2.0或以上),不會有凹陷92的填洞(gap filling)問題,並且將不會產生斷路。因此,根據本發明的實施例,可根據個別的被清潔部件之寬度來選擇清潔溶液。舉例而言,當形成晶圓時,例如透過基於是否可以填充凹陷66(第9圖)而不產生缺陷的實驗,預先決定臨界寬度(threshold width)。舉例而言,臨界寬度可以是50nm,並且藉由多種因素決定。在清潔全部含鎢部件的寬度大於臨界寬度時,使用酸性溶液及/或中性液體/溶液,並且在清潔全部含鎢部件的寬度等於或小於臨界寬度時,使用前述之弱鹼性溶液。
本發明的實施例具有一些有利的部件。藉由在用於清潔晶圓的清潔溶液中採用抑制劑,保護接觸插塞免於受到清潔溶液引起的腐蝕,並且減少接觸的損失。此外,在化學機械研磨(CMP)之後實施清潔的過程中,藉由調整抑制劑的PH值,各自的化學品(例如有機胺)可作為抑制劑。
根據本發明的一些實施例,半導體結構的製造方法包含在晶圓上形成第一介電層,蝕刻第一介電層以形成開 口,填充含鎢材料至開口中,以及對晶圓實施化學機械研磨。在化學機械研磨之後,使用弱鹼性溶液對晶圓實施清潔。
根據本發明的一些實施例,半導體結構的製造方法包含形成層間介電層(ILD),其具有一部分與電晶體的閘極堆疊在相同水平高度,層間介電層和閘極堆疊是晶圓的一部分。蝕刻層間介電層以形成源極/汲極接觸開口。通過源極/汲極接觸開口暴露出電晶體的源極/汲極區。在晶圓上沉積含鎢材料,其中含鎢材料的一部分填充源極/汲極接觸開口。對晶圓實施化學機械研磨以移除含鎢材料的過量部分。接著,使用包含有機胺的清潔溶液清潔晶圓,其中清潔溶液是弱鹼性溶液。接著,乾燥晶圓。
根據本發明的一些實施例,半導體結構包含第一介電層,以及在第一介電層中的金屬插塞。金屬插塞的頂面與第一介電層的頂面大體上共平面。富含碳層覆蓋在金屬插塞上方且與金屬插塞接觸。富含碳層具有第一碳濃度,其高於金屬插塞的第二碳濃度。第二介電層覆蓋在富含碳層上方且與富含碳層接觸。
前述概述了一些實施例的部件,使得本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。本發明所屬技術領域中具有通常知識者應可理解,他們可以輕易使用本發明實施例作為基礎,設計或修改其他的製程或是結構,以達到與在此介紹的實施例相同的目的及/或優點。本發明所屬技術領域中具有通常知識者也應理解,此類等效的結構並不悖離本發明實施例的精神與範疇,並且在不悖離本發 明實施例的精神與範疇的情況下,在此可以做各種的改變、取代和替換。因此,本發明之保護範圍當視後附之申請專利範圍所界定為準。
Claims (20)
- 一種半導體結構的製造方法,包括:在一晶圓上形成一第一介電層;蝕刻該第一介電層以形成一第一開口;填充一含鎢材料至該第一開口中;對該晶圓實施一第一化學機械研磨;以及在該第一化學機械研磨之後,使用一弱鹼性溶液對該晶圓實施一第一清潔。
- 如申請專利範圍第1項所述之半導體結構的製造方法,其中該弱鹼性溶液包括一有機胺。
- 如申請專利範圍第2項所述之半導體結構的製造方法,其中該有機胺包括C 5H 15NO 2。
- 如申請專利範圍第2項所述之半導體結構的製造方法,其中該弱鹼性溶液的PH值在7.0至8.0之間的範圍內。
- 如申請專利範圍第1項所述之半導體結構的製造方法,更包括形成一源極/汲極區,其中該含鎢材料的一部分在該第一化學機械研磨之後留下作為一接觸插塞,且該接觸插塞電性耦接至該源極/汲極區。
- 如申請專利範圍第1項所述之半導體結構的製造方法,更包括在該含鎢材料上形成一第二介電層且與該含鎢材料接觸,其中在該含鎢材料與該第二介電層之間形成一富含碳層,且該富含碳層與該含鎢材料和該第二介電層接觸。
- 如申請專利範圍第1項所述之半導體結構的製造方法,更包括: 在該晶圓上形成一第二介電層;蝕刻該第二介電層以形成一第二開口,其中該第二開口比該第一開口寬;填充一第二含鎢材料至該第二開口中;對該晶圓實施一第二化學機械研磨;以及在該第二化學機械研磨之後,使用一酸性溶液或一中性液體對該晶圓實施一第二清潔。
- 一種半導體結構的製造方法,包括:形成一層間介電層(ILD)具有一部分與一電晶體的一閘極堆疊在相同水平高度,其中該層間介電層和該閘極堆疊是一晶圓的一部分;蝕刻該層間介電層以形成一源極/汲極接觸開口,其中通過該源極/汲極接觸開口暴露出該電晶體的一源極/汲極區;在該晶圓上沉積一第一含鎢材料,其中該第一含鎢材料包括一部分填充該源極/汲極接觸開口;對該晶圓實施一化學機械研磨以移除該第一含鎢材料的過量部分;使用包括有機胺的一清潔溶液清潔該晶圓,其中該清潔溶液是弱鹼性溶液;以及乾燥該晶圓。
- 如申請專利範圍第8項所述之半導體結構的製造方法,其中從完成該化學機械研磨的一第一時間點至完全地乾燥該晶圓的一第二時間點,沒有使用中性液體清潔該晶圓。
- 如申請專利範圍第9項所述之半導體結構的製造方法,其中 從完成該化學機械研磨的一第一時間點至完全地乾燥該晶圓的一第二時間點,沒有使用酸性溶液清潔該晶圓。
- 如申請專利範圍第8項所述之半導體結構的製造方法,其中該清潔溶液的PH值在大於7.0且小於8.0的範圍內。
- 如申請專利範圍第8項所述之半導體結構的製造方法,其中該有機胺包括C 5H 15NO 2。
- 如申請專利範圍第12項所述之半導體結構的製造方法,更包括:填充一第二含鎢材料至該晶圓內的一額外的開口,其中該額外的開口比該源極/汲極接觸開口寬;對該晶圓實施一額外的化學機械研磨以移除該第二含鎢材料在該額外的開口之外的過量部分;以及在該額外的化學機械研磨之後,使用一酸性溶液或一中性液體清潔該晶圓。
- 如申請專利範圍第8項所述之半導體結構的製造方法,更包括添加一緩衝劑至該清潔溶液中,以穩定該清潔溶液中的PH值。
- 一種半導體結構,包括:一第一介電層;一第一金屬插塞,位於第一介電層中,其中該第一金屬插塞的一頂面與該第一介電層的一頂面大體上共平面;一富含碳層,覆蓋在該第一金屬插塞上方且與該第一金屬插塞接觸,其中該富含碳層具有一第一碳濃度高於該第一金屬插塞的一第二碳濃度;以及 一第二介電層,覆蓋在該富含碳層上方且與該富含碳層接觸。
- 如申請專利範圍第15項所述之半導體結構,其中該第二介電層包含碳且具有一第三碳濃度,並且該第一碳濃度高於該第三碳濃度。
- 如申請專利範圍第16項所述之半導體結構,其中該第一碳濃度比該第二碳濃度與該第三碳濃度兩者皆高出15%以上。
- 如申請專利範圍第15項所述之半導體結構,其中該富含碳層的邊緣與該第一金屬插塞的邊緣相接。
- 如申請專利範圍第15項所述之半導體結構,更包括:一第二金屬插塞,位於該第一介電層中,其中該第二金屬插塞的一頂面與該第一介電層的該頂面大體上共平面;以及一第三金屬插塞,位於該第一金屬插塞上且與該第一金屬插塞接觸,其中在該第二金屬插塞與該第三金屬插塞之間沒有富含碳層。
- 如申請專利範圍第15項所述之半導體結構,其中該富含碳層包括有機胺。
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TWI791256B (zh) * | 2020-09-25 | 2023-02-01 | 大陸商中芯國際集成電路製造(上海)有限公司 | 半導體結構及其形成方法 |
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Publication number | Publication date |
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CN108122828A (zh) | 2018-06-05 |
DE102017118311A1 (de) | 2018-05-30 |
KR20180060950A (ko) | 2018-06-07 |
KR102003602B1 (ko) | 2019-07-24 |
CN108122828B (zh) | 2021-04-20 |
TWI631624B (zh) | 2018-08-01 |
US10109523B2 (en) | 2018-10-23 |
US10916473B2 (en) | 2021-02-09 |
US20180350675A1 (en) | 2018-12-06 |
US20180151427A1 (en) | 2018-05-31 |
US20200051855A1 (en) | 2020-02-13 |
US10510594B2 (en) | 2019-12-17 |
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