TW201801195A - 垂直鰭式場效電晶體及其製造方法與具有其的半導體裝置 - Google Patents

垂直鰭式場效電晶體及其製造方法與具有其的半導體裝置

Info

Publication number
TW201801195A
TW201801195A TW106115923A TW106115923A TW201801195A TW 201801195 A TW201801195 A TW 201801195A TW 106115923 A TW106115923 A TW 106115923A TW 106115923 A TW106115923 A TW 106115923A TW 201801195 A TW201801195 A TW 201801195A
Authority
TW
Taiwan
Prior art keywords
spacer
field effect
effect transistor
gate electrode
primary
Prior art date
Application number
TW106115923A
Other languages
English (en)
Other versions
TWI713121B (zh
Inventor
鄭修然
姜明吉
Original Assignee
三星電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三星電子股份有限公司 filed Critical 三星電子股份有限公司
Publication of TW201801195A publication Critical patent/TW201801195A/zh
Application granted granted Critical
Publication of TWI713121B publication Critical patent/TWI713121B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本發明提供一種垂直鰭式場效電晶體（V-FinFET）如下。基底具有下部源極/汲極（S/D）。鰭式結構從下部源極/汲極的上表面垂直地延伸。鰭式結構包含具有上側壁部分、下側壁部分以及位於其間的中心側壁部分的側壁。上部S/D安置於鰭式結構的上表面上。上部間隔物安置於上側壁部分上。下部間隔物安置於下側壁部分上。包含閘氧化物層以及第一閘電極的堆疊結構安置於下部間隔物的上表面、中心側壁部分以及上部間隔物的下表面上。第二閘電極安置於第一閘電極上。

Description

垂直鰭式場效電晶體及其製造方法與具有其的半導體裝置
本發明概念涉及垂直鰭式場效電晶體（V-FinFET），具有V-FinFET的半導體裝置以及製造所述V-FinFET的方法。
相關申請案的交叉參考 本申請案主張於2016年6月16日在美國專利商標局申請的美國臨時專利申請案第62/351,010號及於2016年10月11日在美國專利商標局申請的美國非臨時專利申請案第15/290,456號的權益，所述申請案的公開內容在此以全文引用的方式併入本文中。
電晶體一直是平面的。隨著電晶體的縮小（shrink），泄漏電流增大，耗盡電池組並且加熱半導體晶片。為了減小泄漏電流，已經提出各種電晶體結構。
根據本發明概念的示範性實施例，提供一種垂直鰭式場效電晶體（V-FinFET）如下。基底具有下部源極/汲極（S/D）。鰭式結構從下部S/D的上表面垂直地延伸。鰭式結構包含具有上側壁部分、下側壁部分以及定位於其間的中心側壁部分的側壁。上部S/D安置於鰭式結構的上表面上。上部間隔物（spacer）安置於上側壁部分上。下部間隔物安置於下側壁部分上。包含閘氧化物層以及第一閘電極的堆疊結構安置於下部間隔物的上表面、中心側壁部分以及上部間隔物的下表面上。第二閘電極安置於第一閘電極上。
根據本發明概念的示範性實施例，提供一種半導體裝置如下。半導體裝置包含第一垂直鰭式場效電晶體（V-FinFET）。第一V-FinFET包含具有下部源極/汲極（S/D）的基底以及安置於下部S/D的上表面上的第一鰭式結構。第一鰭式結構包含具有下側壁部分、上側壁部分以及定位於其間的中心側壁部分的側壁。第一V-FinFET更包含安置於第一鰭式結構的上表面上的上部S/D、安置於下側壁部分上的下部間隔物以及安置於上側壁部分上的上部間隔物。上部間隔物包含第一側壁以及第二側壁，上部間隔物的第一側壁與上側壁部分接觸。第一V-FinFET更包含堆疊結構，所述堆疊結構包含閘氧化物層以及第一閘電極。堆疊結構插入於上部間隔物與下部間隔物之間。堆疊結構的第一側壁與第一鰭式結構的側壁相接觸。堆疊結構的第二側壁與上部間隔物的第二側壁垂直對準。
根據本發明概念的示範性實施例，提供製造垂直鰭式場效電晶體（V-FinFET）的方法如下。下部S/D形成於基底中。初級堆疊結構形成於基底上。初級堆疊結構包含堆疊於彼此上的初級下部間隔物層、犧牲層以及初級上部間隔物層。穿過初級堆疊結構的第一溝槽經形成以暴露下部S/D。鰭式結構形成於第一溝槽中且形成於下部S/D上。上部S/D形成於鰭式結構以及初級堆疊結構上。鰭式結構從下部S/D磊晶生長（epitaxially grown）。
通過參考本發明概念的附圖詳細描述其示範性實施例，本發明概念的這些以及其它特徵將變得更加顯而易見。
應瞭解，為了說明的簡單和清晰起見，圖中說明的元件未必按比例繪製。舉例來說，為了清楚起見，可相對於其它元件誇大一些元件的尺寸。另外，在認為適當時已在圖式中重複參考標號以指示對應或類似元件。
雖然可能未能示出一些橫截面圖的對應平面圖和/或透視圖，但是本文中所說明的的裝置結構的橫截面圖提供對於沿著兩個不同方向（如將在平面圖中所說明）和/或在三個不同方向上（如將在透視圖中所說明）延伸的多個裝置結構的支持。兩個不同方向可或可不相互正交。三個不同方向可包含可與兩個不同方向正交的第三方向。多個裝置結構可集成於同一電子裝置中。舉例來說，當以橫截面圖說明裝置結構（例如，記憶體單元結構或電晶體結構）時，電子裝置可包含多個裝置結構（例如，記憶體單元結構或電晶體結構），如將由電子裝置的平面圖說明。多個裝置結構可布置成陣列和/或二維圖案。
下文將參考附圖來詳細描述本發明概念的示範性實施例。然而，本發明概念可以不同形式實施，並且不應被解釋為受限於本文所闡述的實施例。更將理解，當元件被稱作在另一元件或基底“上”時，其可直接地在另一元件或基底上，或也可以存在介入層。更將理解，當元件被稱作“耦接”到另一元件或“連接”到另一元件時，其可直接耦接到另一元件或連接到另一元件，或者也可以存在介入元件。
圖1繪示根據本發明概念的示範性實施例的包含第一垂直鰭式場效電晶體（V-FinFET）100A以及第二垂直鰭式場效電晶體（V-FinFET）100B的半導體裝置100的橫截面圖。第一V-FinFET 100A和第二V-FinFET 100B可為N型電晶體或P型電晶體。舉例來說，第一V-FinFET 100A和第二V-FinFET 100B具有相同類型的半導體或不同類型的半導體。
第一V-FinFET 100A與第二V-FinFET 100B實質上類似，且因此為了方便描述，下文將描述第一V-FinFET 100A且將其稱為V-FinFET 100A。第一V-FinFET 100A的描述可適用於第二V-FinFET 100B。如果第二V-FinFET 100B為不同類型的電晶體，那麼經摻入源極/汲極中的雜質將不同。
V-FinFET 100A包含鰭式結構160、下部源極/汲極（S/D）120以及上部源極/汲極（S/D）130。鰭式結構160安置於下部S/D 120的上表面上且安置於上部S/D 130的下表面之下。舉例來說，從下部S/D 120的上表面垂直地延伸的鰭式結構160插入於下部S/D 120與上部S/D 130之間。在此情形下，鰭式結構160的高度H1與沿上部S/D 130與下部S/D 120之間的鰭式結構160的側壁160-S測量的V-FinFET 100A的閘極長度相等。
經由使用離子植入製程或擴散製程將雜質摻入基底110中而形成下部S/D 120。基底110可由矽（Si）或矽和鍺的合金（SiGe）形成。如果V-FinFET 100A為N型電晶體，那麼雜質可為N型雜質，例如，磷（P）、砷（As）或銻（Sb）。如果V-FinFET 100A為P型電晶體，那麼雜質可為P型雜質，例如，硼（B）、鋁（Al）或鎵（Ga）。
V-FinFET 100A可具有鰭式結構160中的通道。舉例來說，當V-FinFET 100A接通時，可沿鰭式結構160的側壁160-S形成通道且電晶體接通電流（turn-on current）可沿所述通道流動。
V-FinFET 100A更包含閘氧化物層170、第一閘電極180、下部間隔物140以及上部間隔物150。閘氧化物層170和第一閘電極180插入於上部間隔物150與下部間隔物140之間。舉例來說，閘氧化物層170和第一閘電極180的堆疊結構插入於上部間隔物150與下部間隔物140之間。
上部間隔物150和下部間隔物140形成於鰭式結構160的側壁160-S上。上部間隔物150包含第一側壁150-S1和第二側壁150-S2。下部間隔物140包含第一側壁140-S1和第二側壁140-S2。鰭式結構160的側壁160-S包含上側壁部分、下側壁部分以及定位於上側壁部分與下側壁部分之間的中心側壁部分。
舉例來說，上部間隔物150的第一側壁150-S1安置於鰭式結構160的上側壁部分上。在示範性實施例中，上部間隔物150的第一側壁150-S1可與鰭式結構160的上側壁部分相接觸。
舉例來說，下部間隔物140的第一側壁140-S1安置於鰭式結構160的下側壁部分上。在示範性實施例中，下部間隔物140的第一側壁140-S1可與鰭式結構160的下側壁部分相接觸。
下部間隔物140由兩個相鄰的第一V-FinFET 100A及第二V-FinFET 100B共享。在此情形下，下部間隔物140也安置於第二V-FinFET 100B的鰭式結構160'的側壁上。在示範性實施例中，第二側壁140-S2可與第二V-FinFET 100B的鰭式結構160'的側壁相接觸。
上部間隔物150可由使用化學氣相沉積（CVD）製程或電漿增强型CVD（PECVD）製程沉積的氮化矽而形成。上部間隔物150和下部間隔物140可具有包含氮化矽的實質上相同的材料。
根據示範性實施例，鰭式結構160形成於初級上部間隔物層、犧牲層以及初級下部間隔物層的初級堆疊結構內且因此可經由控制初級堆疊結構的厚度而確定V-FinFET 100A的閘極長度。可針對圖4描述初級堆疊結構。
閘氧化物層170形成於上部間隔物150的下表面和下部間隔物140的上表面上。閘氧化物層170也形成於在上部間隔物150與下部間隔物140之間暴露的鰭式結構160的中心側壁部分上。因此，閘氧化物層170為C形。
閘氧化物層170可由包含HfO2 或HfSiO的高介電常數介電材料（high-k dielectric material）形成。可使用各種沉積製程來形成閘氧化物層170，所述製程包含化學氣相沉積（CVD）製程、電漿增强型CVD（PECVD）製程、金屬有機CVD（MOCVD）製程或原子層沉積製程（ALD）。
第一閘電極180安置於閘氧化物層170上。在此情形下，閘氧化物層170插入於第一閘電極180與鰭式結構160的側壁160-S之間；閘氧化物層170插入於上部間隔物150與第一閘電極180之間；以及閘氧化物層170插入於下部間隔物140與第一閘電極180之間。在此情形下，第一閘電極180保形地（comformally）形成於閘氧化物層170上且為C形。因此，閘氧化物層170和第一閘電極180的堆疊結構SS以閘氧化物層170和第一閘電極180的堆疊結構SS的側壁與鰭式結構160的側壁160-S相接觸且堆疊結構SS的另一側壁與上部間隔物150的第二側壁150-S2垂直對準的方式插入於上部間隔物150與下部間隔物140之間。
在示範性實施例中，第一閘電極180可完全填充C形的閘氧化物層170，如圖1A中所示。圖1A的其它元件與圖1的其對應元件相同，且因此為了便於描述，在本文中將僅描述圖1與圖1A之間的差異且將省略相同元件的其它描述。
第一閘電極180可由包含TiN的氮化物形成。本發明概念不限於此。第一閘電極180可由至少兩個不同材料層（例如，TiN（氮化鈦）/TaN（氮化鉭）/TiAlC（碳化鈦鋁）形成。
V-FinFET 100A包含安置於兩個相鄰鰭式結構160之間的第二閘電極190。當從V-FinFET 100A的上方查看時，第二閘電極190可圍繞鰭式結構160。第二閘電極190具有與閘氧化物層170與上部間隔物150之間的界面共面的上表面。本發明概念不限於此。舉例來說，第二閘電極190的上表面可比閘氧化物層170與上部間隔物150之間的界面更高或更低。第二閘電極190與第一閘電極180彼此電連接。舉例來說，第二閘電極190與第一閘電極180相接觸。因此，無論第二閘電極190的上表面的位置如何，V-FinFET 100A的閘極長度可由與第一閘電極180電容耦接的鰭式結構160的高度H1確定。
第二閘電極190由兩個相鄰的第一V-FinFET 100A及第二V-FinFET 100B共享。
第二閘電極190填充由上部間隔物150與下部間隔物140之間的第一閘電極180界定的間隙。舉例來說，C形的第一閘電極180接收第二閘電極190的部分190-P以使得閘氧化物層170和第一閘電極180的堆疊結構SS更包含第二閘電極190的部分190-P。
第二閘電極190的部分190-P、第一閘電極180以及閘氧化物層170的堆疊結構SS插入於上部間隔物150與下部間隔物140之間。舉例來說，堆疊結構SS填充上部間隔物150與下部間隔物140之間的空間。在此情形下，第二閘電極190的部分190-P突出至C形的第一閘電極180中。
在圖1A的示範性實施例中，第二閘電極190不突出至C形的第一閘電極180中以使得第二閘電極190的側壁與上部間隔物150的第二側壁150-S2垂直對準。堆疊結構SS'包含閘氧化物層170和第一閘電極180。堆疊結構SS'插入於上部間隔物150與下部間隔物140之間。
返回參看圖1，插入第二閘電極190與下部S/D 120之間的下部間隔物140可用以防止第二閘電極190與下部S/D 120的電性短路（electrical short）。
插入第二閘電極190與上部S/D 130之間的上部間隔物150可用以防止第二閘電極190與上部S/D 130的電性短路。
半導體裝置100更包含絕緣層300、罩蓋層210以及具有閘極接觸電極220A和上部S/D接觸電極220B的接觸電極（contact electrode）。
閘極接觸電極220A穿過絕緣層300以電連接到第二閘電極190。第一歐姆（ohmic）接觸層（在此未圖示）可插入第二閘電極190與閘極接觸電極220A之間以減小其間的接觸電阻。在此情形下，閘極接觸電極220A可與第一歐姆接觸層相接觸。
上部S/D接觸電極220B穿過絕緣層300及罩蓋層210以電連接到上部S/D 130。第二歐姆接觸層（在此未圖示）可插入上部S/D 130與上部S/D接觸電極220B之間。
在下文中，將參考圖2至16描述製造V-FinFET 100A的方法。
圖2為根據本發明概念的示範性實施例的製造圖1的V-FinFET 100A的流程圖。圖3至16表示根據圖2的流程圖形成的V-FinFET 100A的橫截面圖。
圖3表示根據本發明概念的示範性實施例的在執行圖2的步驟S100之後形成的下部S/D 120。
在步驟S100中，執行摻雜過程以使用離子植入製程或擴散製程在基底110中形成下部S/D 120。如果形成N型電晶體，那麼基底110中可摻入N型雜質，例如，磷（P）、砷（As）或銻（Sb）。對於P型電晶體，基底中可摻入P型雜質，例如，硼（B）、鋁（Al）或鎵（Ga）。
基底110可由矽（Si）或矽和鍺的合金（SiGe）形成。
圖4表示根據圖2的步驟S110、步驟S120以及步驟S130的包含初級下部間隔物層140P、犧牲層SL以及初級上部間隔物層150P的初級堆疊結構PSS。在初級堆疊結構PSS中，初級下部間隔物層140P、犧牲層SL以及初級上部間隔物層150P從基底110以所列次序堆疊於彼此上。舉例來說，初級堆疊結構PSS形成於基底110上。
初級下部間隔物層140P可由氮化矽形成。犧牲層SL可由矽或氧化矽形成。初級上部間隔物層150P可由氮化矽形成。在示範性實施例中，初級下部間隔物層140P和初級上部間隔物層150P可由包含氮化矽的實質上相同的材料形成。可根據圖1的V-FinFET的目標閘極長度確定犧牲層SL的厚度TSL 。
圖5表示根據本發明概念的示範性實施例的在執行圖2的步驟S140之後形成於初級堆疊結構PSS中的第一溝槽TR1。
在步驟S140中，可執行微影製程以界定初級堆疊結構PSS中的第一溝槽TR1。舉例來說，經圖案化光阻層（在此未圖示）可形成於圖4的初級上部間隔物層150P上，暴露初級堆疊結構PSS的待形成為第一溝槽TR1的區域。
在形成經圖案化光阻層之後，可在步驟S140中執行方向性蝕刻製程（directional etching process）從而在初級堆疊結構PSS中形成第一溝槽TR1。經圖案化光阻層可用作用於方向性蝕刻製程的蝕刻罩幕。第一溝槽TR1穿過初級堆疊結構PSS以暴露下部S/D 120。第一溝槽TR1界定來自初級下部間隔物層140P的下部間隔物140。第一溝槽TR1也界定來自犧牲層SL的經圖案化犧牲層PSL。初級上部間隔物P150由第一溝槽TR1界定。初級上部間隔物P150經進一步圖案化以形成圖1的上部間隔物150。將參看圖10描述上部間隔物150的形成。
方向性蝕刻製程可包含使用含氟（F）氣體（例如，CF4 ）作為蝕刻氣體的反應性離子蝕刻（RIE）製程。舉例來說，含F氣體可蝕刻矽、氧化矽或氮化矽。
圖6表示根據本發明概念的示範性實施例的在執行圖2的步驟S150之後形成的襯裡200。
在步驟S150中，可在圖5的結果結構上保形地形成初級襯裡（在此未圖示）。舉例來說，初級襯裡可形成於第一溝槽TR1內而不完全填充第一溝槽TR1；初級襯裡也可形成於初級上部間隔物P150的上表面上。
在形成初級襯裡之後，可對初級襯裡執行包含RIE製程的方向性蝕刻製程從而形成襯裡200。在方向性蝕刻製程中移除形成於初級上部間隔物P150和下部S/D 120上的初級襯裡的部分且在執行方向性蝕刻製程之後保持形成於第一溝槽TR1的側壁上的初級襯裡的部分。初級襯裡的剩餘部分被稱作襯裡200。舉例來說，襯裡200形成於第一溝槽TR1的側壁上。
可使用化學氣相沉積（CVD）製程、電漿增强型CVD（PECVD）製程或原子層沉積（ALD）製程來形成初級襯裡。襯裡200可由氮化矽形成。舉例來說，襯裡200可由與上部間隔物150及下部間隔物140實質上相同的材料形成。
襯裡200遮蓋經圖案化犧牲層PSL以防止經圖案化犧牲層PSL在下文所描述的圖2的步驟S160中充當用於磊晶生長製程的晶種層。
圖7表示根據本發明概念的示範性實施例的在執行圖2的步驟S160之後形成的鰭式結構160。
在步驟S160中，鰭式結構160可通過使用下部S/D 120作為晶種層磊晶地形成。襯裡200可防止鰭式結構160從經圖案化犧牲層PSL磊晶生長。在示範性實施例中，鰭式結構160可從下部S/D 120磊晶生長。本發明概念不限於此。舉例來說，可省略襯裡200且因此鰭式結構160可從經圖案化犧牲層PSL磊晶生長。
圖8表示根據本發明概念的示範性實施例的在執行圖2的步驟S170之後形成的上部S/D 130。
在步驟S170中，上部S/D 130可從鰭式結構160磊晶地形成。在上部S/D 130的磊晶生長中，可摻入N型或P型雜質。對於N型電晶體，在上部S/D 130的磊晶生長中摻入N型雜質。對於P型電晶體，在上部S/D 130的磊晶生長中摻入P型雜質。
可原位地（in-situ）或連續地執行鰭式結構160的形成以及上部S/D 130的形成。舉例來說，可使用磊晶生長製程連續地形成鰭式結構160和上部S/D 130。鰭式結構160和上部S/D 130可由矽或矽和鍺的合金形成。
圖9表示根據本發明概念的示範性實施例的在執行圖2的步驟S180之後形成的罩蓋層210。
兩個相鄰的罩蓋層210和210'可界定待形成為如下文所描述的圖10中所示的第二溝槽TR2的區域。在鰭式結構160上形成罩蓋層210，遮蓋上部S/D 130。在另一鰭式結構160'上形成另一罩蓋層210'。
在步驟S180中，可使用CVD製程或PECVD製程在圖8的結果結構上形成初級罩蓋層（在此未圖示）。初級罩蓋層可由TiN形成。在形成初級罩蓋層之後，可執行熱處理以使得初級罩蓋層與上部S/D 130的矽反應。舉例來說，初級罩蓋層的矽化反應可發生於上部S/D 130上。上部間隔物上的初級罩蓋層不具有矽化反應。在蝕刻製程中，上部間隔物上的初級罩蓋層經移除且保持被稱作罩蓋層210的經矽化初級罩蓋層。
圖10表示根據本發明概念的示範性實施例的在執行圖2的步驟S190之後形成的第二溝槽TR2。
在步驟S190中，可對圖9的結果結構執行包含RIE製程的方向性蝕刻製程。罩蓋層210和210'可充當蝕刻罩幕以使得在兩個相鄰的罩蓋層210與210'之間形成第二溝槽TR2。在步驟S190中，可執行方向性蝕刻製程直到通過第二溝槽TR2暴露下部間隔物140為止。第二溝槽TR2穿過圖9的初級上部間隔物P150以界定上部間隔物150。在示範性實施例中，可通過第一溝槽TR1和第二溝槽TR2形成上部間隔物150。第二溝槽TR2進一步圖案化經圖案化犧牲層PSL以使得通過第二溝槽TR2暴露經圖案化犧牲層PSL。
圖11表示根據本發明概念的示範性實施例的在執行圖2的步驟S200之後形成的凹陷溝槽RTR。
在步驟S200中，使用包含濕式蝕刻製程或乾式蝕刻製程的等向性蝕刻（isotropic etching process）製程經由第二溝槽TR2移除經圖案化犧牲層PSL。也可在步驟S200的等向性蝕刻製程中移除襯裡200。舉例來說，圖10的第二溝槽TR2側向凹入以使得通過凹陷溝槽RTR暴露鰭式結構160的側壁。在此情形下，插入上部間隔物150與鰭式結構160之間的襯裡200可保持為第一保持襯裡200'；及插入下部間隔物140與鰭式結構160之間的襯裡200可保持為第二保持襯裡200"。
在示範性實施例中，襯裡200、下部間隔物140以及上部間隔物150可由包含氮化矽的實質上相同的材料形成。在此情形下，第一保持襯裡200'和上部間隔物150可視為如圖11A中所示的具有相同材料的單個元件。在此情形下，第一保持襯裡200'可視為上部間隔物150的部分，如圖11A中所示；及第二保持襯裡200"和下部間隔物140可視為如圖11A中所示的具有相同材料的單個元件。在此情形下，第二保持襯裡200"可視為下部間隔物140的部分，如圖11A中所示。
在下文中，為了便於描述，假設襯裡200、下部間隔物140以及上部間隔物150由包含氮化矽的實質上相同的材料形成。因此，可參看圖11A描述步驟S200的後續過程。本發明概念不限於此。舉例來說，襯裡200可由與上部間隔物150和下部間隔物140的材料不同的材料形成。在此情形下，可對圖11的結果結構執行步驟S200的後續過程。
圖12表示根據本發明概念的示範性實施例的在執行圖2的步驟S210之後形成的初級閘氧化物層170P和初級第一閘電極180P。
可使用包含CVD製程、PECVD製程或MOCVD製程的沉積製程在凹陷溝槽RTR內保形地形成初級閘氧化物層170P。
初級閘氧化物層170P可具有凹陷溝槽RTR並不完全被填充之程度的預定厚度。舉例來說，初級閘氧化物層170P形成於鰭式結構160的側壁、上部間隔物150的下表面以及下部間隔物140的上表面上。初級閘氧化物層170P進一步形成於上部間隔物150的第二側壁150-S2上。上部間隔物150更包含與鰭式結構160的側壁相接觸的第一側壁150-S1。
初級閘氧化物層170P可由包含HfO2 或HfSiO的高介電常數介電材料形成。
初級第一閘電極180P保形地形成於凹陷溝槽RTR內而不完全填充凹陷溝槽RTR。舉例來說，初級第一閘電極180P不完全填充凹陷溝槽RTR的間隙RTR-G。間隙RTR-G插入於上部間隔物150與下部間隔物140之間。
本發明概念不限於此。舉例來說，如圖12A中所示，初級第一閘電極180P完全填充凹陷溝槽RTR的間隙RTR-G，而不完全填充凹陷溝槽RTR或初級第一閘電極180P可完全填充凹陷溝槽RTR。
可使用CVD製程形成初級第一閘電極180P。初級第一閘電極180P可由包含TiN的氮化物形成。本發明概念不限於此。舉例來說，初級第一閘電極180P可包含兩個或多於兩個不同材料層，例如，TiN/TaN/TiAlC。
圖13表示根據本發明概念的示範性實施例的在執行圖2的步驟S220之後形成的第三溝槽TR3。步驟S220應用於圖12的結果結構。
在步驟S220中，可對圖12的結果結構執行包含RIE製程的方向性蝕刻製程以形成第三溝槽TR3。經由步驟S220的方向性蝕刻製程，初級閘氧化物層170P和初級第一閘電極180P分別經圖案化為閘氧化物層170和第一閘電極180。舉例來說，可執行步驟S220的方向性蝕刻製程直到第三溝槽TR3暴露下部間隔物140的上表面為止。在此情形下，罩蓋層210和210'可充當蝕刻罩幕以將初級閘氧化物層170P和初級第一閘電極180P分別圖案化成閘氧化物層170和第一閘電極180。閘氧化物層170和第一閘電極180為C形以使得C形的閘氧化物層170和第一閘電極180部分圍繞第三溝槽TR3的間隙TR3-G。
上部間隔物150也可在步驟S220的方向性蝕刻製程中充當蝕刻罩幕。
第三溝槽TR3的間隙TR3-G與上部間隔物150和下部間隔物140重疊。
可使用NH4 OH/H2 O2 蝕刻初級第一閘電極180P。本發明概念不限於此。舉例來說，可使用初級第一閘電極180P相對於由TiN形成的罩蓋層210和210'具有蝕刻選擇率的蝕刻化學（etch chemistry）。
可使用含有氯（Cl）的蝕刻劑氣體（例如，CCl4 ）蝕刻初級閘氧化物層170P。本發明概念不限於此。舉例來說，可使用初級閘氧化物層170P相對於罩蓋層210和210'具有蝕刻選擇率的蝕刻劑氣體。
返回參看圖12A，可對圖12A的結果結構執行圖2的步驟S220。在此情形下，圖13A表示在執行步驟S220之後形成的第三溝槽TR3'。與圖13的第三溝槽TR3不同，圖13A的第三溝槽TR3'不具有圖13的間隙TR3-G。
圖14表示根據本發明概念的示範性實施例的在執行圖2的步驟S230之後形成的初級第二閘電極層190P。
初級第二閘電極層190P保形地形成於第三溝槽TR3內，填充圖13的第三溝槽TR3。初級第二閘電極層190P也形成於罩蓋層210上。
可執行CVD製程或MOCVD製程形成初級第二閘電極層190P。初級第二閘電極層190P可由包含鎢（W）或銅（Cu）的導電材料形成。
圖15表示根據本發明概念的示範性實施例的在執行圖2的步驟S240之後形成的第二閘電極190。
可使用回蝕製程使圖14的初級第二閘電極層190P凹入從而形成第二閘電極190。由於第一閘電極180經電連接到第二閘電極190且V-FinFET 100A的閘極長度由與第一閘電極180電容耦接的鰭式結構160的高度確定，步驟S240的回蝕製程可具有製程裕度。取决於回蝕製程的製程變化，第二閘電極190的上表面可與閘氧化物層170與上部間隔物150的下表面之間的界面共面、比所述界面更高或更低。為了便於描述，圖15表示其上表面與閘氧化物層170與上部間隔物150的下表面之間的界面共面的第二閘電極190。
圖16表示根據本發明概念的示範性實施例的在執行圖2的步驟S250之後形成的接觸電極220A和220B。
在步驟S250中，絕緣層300形成於圖15的結果結構上。舉例來說，絕緣層300形成於罩蓋層210和第二閘電極190上。接觸電極220A和220B穿過絕緣層300。舉例來說，閘極接觸電極220A穿過絕緣層300以電連接到第二閘電極190；及上部S/D接觸電極220B穿過絕緣層300及罩蓋層210以電連接到上部S/D 130。閘極接觸電極220A可使用罩蓋層210和210'與第二閘電極190自對準。
歐姆接觸層（在此未圖示）可插入閘極接觸電極220A與第二閘電極190之間及上部S/D接觸電極220B與上部S/D 130之間。
下部S/D接觸電極（在此未圖示）可穿過絕緣層300和下部間隔物140以電連接到下部S/D 120。歐姆接觸層（在此未圖示）可插入下部S/D 120與下部S/D接觸電極之間。當從上方查看時，下部間隔物140可圍繞鰭式結構160。因此，下部S/D接觸電極可穿過下部間隔物140以電連接到下部S/D 120。
根據本發明概念的示範性實施例，可在形成鰭式結構之前形成初級下部間隔物層、犧牲層以及初級上部間隔物層的初級堆疊結構以使得V-FinFET的目標閘極長度由犧牲層的厚度確定。
應用於圖13的結果結構的步驟S230至步驟S250可適用於圖13A的結果結構以形成圖1A的半導體裝置100'。本文中為了便於描述而省略關於步驟S230至步驟250的重複描述。
圖17為具有根據本發明概念的示範性實施例所製造的半導體裝置的半導體模組。
參看圖17，半導體模組500包含半導體裝置530。可根據本發明概念的示範性實施例形成半導體裝置530。半導體裝置530安裝在半導體模組基底510上。半導體模組500更包含安裝在半導體模組基底510上的微處理器520。輸入/輸出終端540安置於半導體模組基底510的至少一個側面上。半導體模組500可包含於記憶卡或固態硬碟（solid state drive，SSD）中。
圖18為根據本發明概念的示範性實施例的具有半導體裝置的電子系統的方塊圖。
參看圖18，根據本發明概念的示範性實施例所製造的半導體裝置可包含於電子系統600中。電子系統600包含主體610、微處理器單元620、電源供應器630、功能單元640以及顯示控制器單元650。主體610可包含具有印刷電路板（PCB）或類似物的系統板或主板。微處理器單元620、電源供應器630、功能單元640以及顯示控制器單元650安裝或安置於主體610上。顯示單元660可堆疊在主體610的上表面上。舉例來說，顯示單元660安置於主體610的表面上，顯示由顯示控制器單元650處理的圖像。電源供應器630接收來自外部電源供應器的恒定電壓，並且産生不同的電壓電平以將電壓供應到微處理器單元620、功能單元640、顯示控制器單元650等。微處理器單元620接收來自電源供應器630的電壓以控制功能單元640和顯示單元660。功能單元640可以執行電子系統600的各種功能。舉例來說，當電子系統600為例如手機（cellular phone）或類似物的移動電子産品時，功能單元640可以包含不同組件以通過與外部裝置670進行通信而執行無線通信功能，例如撥號、到顯示單元660的視頻輸出或到揚聲器的語音輸出，並且當包含相機時，它可以充當圖像處理器。在示範性實施例中，如果電子系統600連接到記憶卡以擴展記憶體容量，那麼功能單元640可以充當記憶卡控制器。功能單元640可經由有線或無線通信單元680與外部裝置670交換信號。另外，當電子系統600需要通用序列匯流排（Universal Serial Bus，USB）來擴展功能時，功能單元640可以充當介面控制器。功能單元640可包含根據本發明概念的示範性實施例製造的半導體裝置。
圖19為具有根據本發明概念的示範性實施例所製造的半導體裝置的電子系統的方塊圖。
參考圖19，電子系統700可包含在行動裝置或電腦（computer）中。舉例來說，電子系統700包含記憶體系統712、微處理器714、隨機存取記憶體（random access memory，RAM）716以及用戶介面718，其經配置以使用匯流排720執行數據通信。微處理器714可對電子系統700進行編程（program）並且控制電子系統700。RAM 716可用作微處理器714的可操作記憶體。舉例來說，微處理器714或RAM 716可包含根據本發明概念的示範性實施例所製造的半導體裝置。
微處理器714、RAM 716和/或其它組件可以裝配在單個封裝內。用戶介面718可用於將數據輸入到電子系統700或從電子系統700中輸出數據。記憶體系統712可以儲存微處理器714的可操作代碼（operational codes）、通過微處理器714處理的數據或從外部接收的數據。記憶體系統712可包含控制器和記憶體。
雖然已經參考本發明概念的示範性實施例示出和描述了本發明概念，但是對於所屬技術領域具有通常知識者顯而易見的是在不脫離由所附申請專利範圍限定的本發明概念的精神和範圍的前提下可以作出形式和細節中的不同變化。
100、100'‧‧‧半導體裝置
100A、100B‧‧‧垂直鰭式場效電晶體
110‧‧‧基底
120‧‧‧下部源極/汲極
130‧‧‧上部源極/汲極
140‧‧‧下部間隔物
140P‧‧‧初級下部間隔物層
140-S1、150-S1‧‧‧第一側壁
140-S2、150-S2‧‧‧第二側壁
150‧‧‧上部間隔物
150P‧‧‧初級上部間隔物層
160、160'‧‧‧鰭式結構
160-S‧‧‧側壁
170‧‧‧閘氧化物層
170P‧‧‧初級閘氧化物層
180‧‧‧第一閘電極
180P‧‧‧初級第一閘電極
190‧‧‧第二閘電極
190P‧‧‧初級第二閘電極層
190-P‧‧‧部分
200‧‧‧襯裡
200'‧‧‧第一保持襯裡
200"‧‧‧第二保持襯裡
210、210'‧‧‧罩蓋層
220A、220B‧‧‧接觸電極
300‧‧‧絕緣層
500‧‧‧半導體模組
510‧‧‧半導體模組基底
520‧‧‧微處理器
530‧‧‧半導體裝置
540‧‧‧輸入/輸出終端
600‧‧‧電子系統
610‧‧‧主體
620‧‧‧微處理器單元
630‧‧‧電源供應器
640‧‧‧功能單元
650‧‧‧顯示控制器單元
660‧‧‧顯示單元
670‧‧‧外部裝置
680‧‧‧有線或無線通信單元
700‧‧‧電子系統
712‧‧‧記憶體系統
714‧‧‧微處理器
716‧‧‧隨機存取記憶體
718‧‧‧用戶介面
720‧‧‧匯流排
H1‧‧‧高度
P150‧‧‧初級上部間隔物
PSL‧‧‧經圖案化犧牲層
PSS‧‧‧初級堆疊結構
RTR‧‧‧凹陷溝槽
RTR-G、TR3-G‧‧‧間隙
S100、S110、S120、S130、S140、S150、S160、S170、S180、S190、S200、S210、S220、S230、S240、S250‧‧‧步驟
SL‧‧‧犧牲層
SS‧‧‧堆疊結構
SS'‧‧‧堆疊結構
TR1‧‧‧第一溝槽
TR2‧‧‧第二溝槽
TR3、TR3'‧‧‧第三溝槽
TSL‧‧‧厚度
圖1繪示根據本發明概念的示範性實施例的包含垂直鰭式場效電晶體（V-FinFET）的半導體裝置的橫截面圖。 圖1A繪示根據本發明概念的示範性實施例的包含垂直鰭式場效電晶體（V-FinFET）的半導體裝置的橫截面圖。 圖2繪示根據本發明概念的示範性實施例的製造圖1的V-FinFET以及圖1A的V-FinFET的流程圖。 圖3至16繪示根據圖2的流程圖所形成的圖1的V-FinFET的橫截面圖。 圖11A繪示根據圖2的步驟S190所形成的圖1的V-FinFET的橫截面圖。 圖12A至13A繪示根據圖2的流程圖的圖1A的V-FinFET的橫截面圖。 圖17為具有根據本發明概念的示範性實施例所製造的V-FinFET的半導體模組。 圖18為根據本發明概念的示範性實施例的具有V-FinFET的電子系統的方塊圖。 圖19為具有根據本發明概念的示範性實施例所製造的V-FinFET的電子系統的方塊圖。
100‧‧‧半導體裝置
100A、100B‧‧‧垂直鰭式場效電晶體
110‧‧‧基底
120‧‧‧下部源極/汲極
130‧‧‧上部源極/汲極
140‧‧‧下部間隔物
140-S1、150-S1‧‧‧第一側壁
140-S2、150-S2‧‧‧第二側壁
150‧‧‧上部間隔物
160、160'‧‧‧鰭式結構
160-S‧‧‧側壁
170‧‧‧閘氧化物層
180‧‧‧第一閘電極
190‧‧‧第二閘電極
190-P‧‧‧部分
210‧‧‧罩蓋層
220A、220B‧‧‧接觸電極
300‧‧‧絕緣層
H1‧‧‧高度
SS‧‧‧堆疊結構

Claims (20)

  1. 一種垂直鰭式場效電晶體（V-FinFET），包括： 基底，其具有下部源極/汲極（S/D）； 鰭式結構，其從所述下部源極/汲極的上表面垂直地延伸，其中所述鰭式結構包含具有上側壁部分、下側壁部分以及定位於其間的中心側壁部分的側壁； 上部源極/汲極，其安置於所述鰭式結構的上表面上； 上部間隔物，其安置於所述上側壁部分上； 下部間隔物，其安置於所述下側壁部分上； 堆疊結構，其包含閘氧化物層和第一閘電極，其中所述堆疊結構安置於所述下部間隔物的上表面、所述中心側壁部分以及所述上部間隔物的下表面上；以及 第二閘電極，其安置於所述第一閘電極上。
  2. 如申請專利範圍第1項所述的垂直鰭式場效電晶體， 其中所述閘氧化物層與所述鰭式結構的所述中心側壁部分相接觸，以及 其中所述下部間隔物與所述下側壁部分相接觸且插入所述下部源極/汲極與所述閘氧化物層之間。
  3. 如申請專利範圍第1項所述的垂直鰭式場效電晶體， 其中所述上部間隔物與所述上側壁部分相接觸且插入所述上部源極/汲極與所述閘氧化物層之間。
  4. 如申請專利範圍第1項所述的垂直鰭式場效電晶體， 其中所述第一閘電極為C形以使得所述第一閘電極接收所述第二閘電極的一部分，以及 其中所述第二閘電極的所述部分突出到C形的所述第一閘電極中。
  5. 如申請專利範圍第4項所述的垂直鰭式場效電晶體， 其中所述閘氧化物層為C形以使得所述閘氧化物層插入於C形的所述第一閘電極與所述中心側壁部分之間、C形的所述第一閘電極與所述上部間隔物之間以及C形的所述第一閘電極與所述下部間隔物之間。
  6. 如申請專利範圍第5項所述的垂直鰭式場效電晶體， 其中所述堆疊結構更包含所述第二閘電極的所述部分，以及 其中所述堆疊結構插入於所述上部間隔物與所述下部間隔物之間。
  7. 如申請專利範圍第5項所述的垂直鰭式場效電晶體， 其中所述上部間隔物和所述下部間隔物由包含氮化矽的實質上相同的材料形成。
  8. 如申請專利範圍第1項所述的垂直鰭式場效電晶體，更包含： 罩蓋層，其遮蓋所述上部源極/汲極；以及 上部源極/汲極接觸電極，其穿過所述罩蓋層以使得所述上部源極/汲極接觸電極電連接到所述上部源極/汲極。
  9. 如申請專利範圍第8項所述的垂直鰭式場效電晶體，更包含： 閘極接觸電極，其安置於所述第二閘電極上， 其中所述閘極接觸電極與所述罩蓋層相接觸。
  10. 如申請專利範圍第1項所述的垂直鰭式場效電晶體， 其中所述第一閘電極包含氮化鈦、氮化鉭或碳化鈦鋁。
  11. 一種半導體裝置，包括： 第一垂直鰭式場效電晶體（V-FinFET）， 其中所述第一垂直鰭式場效電晶體包含： 基底，其具有下部源極/汲極（S/D）； 第一鰭式結構，其安置於所述下部源極/汲極的上表面上，其中所述第一鰭式結構包含具有下側壁部分、上側壁部分以及定位於其間的中心側壁部分的側壁； 上部源極/汲極，其安置於所述第一鰭式結構的上表面上； 下部間隔物，其安置於所述下側壁部分上； 第一上部間隔物，其安置於所述上側壁部分上，其中所述第一上部間隔物包含第一側壁和第二側壁，所述第一上部間隔物的所述第一側壁與所述上側壁部分相接觸；以及 堆疊結構，其包含閘氧化物層和第一閘電極， 其中所述堆疊結構插入於所述第一上部間隔物與所述下部間隔物之間， 其中所述堆疊結構的第一側壁與所述第一鰭式結構的所述側壁相接觸，以及 其中所述堆疊結構的第二側壁與所述第一上部間隔物的所述第二側壁垂直對準。
  12. 如申請專利範圍第11項所述的半導體裝置，更包含： 第二垂直鰭式場效電晶體， 其中所述第二垂直鰭式場效電晶體包含： 第二鰭式結構，其位在所述基底上， 其中所述第一垂直鰭式場效電晶體的第二閘電極插入於所述第一鰭式結構與所述第二鰭式結構之間以使得所述第一垂直鰭式場效電晶體和所述第二垂直鰭式場效電晶體共享所述第二閘電極。
  13. 如申請專利範圍第11項所述的半導體裝置， 其中所述第一垂直鰭式場效電晶體的所述閘氧化物層與所述中心側壁部分相接觸。
  14. 如申請專利範圍第12項所述的半導體裝置， 其中所述第一垂直鰭式場效電晶體的所述下部間隔物與所述第一鰭式結構的所述下側壁部分及所述第二鰭式結構的側壁相接觸以使得所述第一垂直鰭式場效電晶體與所述第二垂直鰭式場效電晶體共享所述下部間隔物。
  15. 如申請專利範圍第12項所述的半導體裝置， 其中所述第二垂直鰭式場效電晶體更包含： 第二上部間隔物，其安置於所述第二鰭式結構的側壁上， 其中所述第二上部間隔物與所述第一上部間隔物間隔開。
  16. 一種製造垂直鰭式場效電晶體（V-FinFET）的方法，包括： 在基底中形成下部源極/汲極（S/D）； 在所述基底上形成初級堆疊結構，所述初級堆疊結構包含堆疊於彼此上的初級下部間隔物層、犧牲層以及初級上部間隔物層； 形成穿過所述初級堆疊結構的第一溝槽以暴露所述下部源極/汲極； 在所述第一溝槽中及在所述下部源極/汲極上形成鰭式結構；以及 在所述鰭式結構和所述初級堆疊結構上形成上部源極/汲極， 其中所述鰭式結構從所述下部源極/汲極磊晶生長。
  17. 如申請專利範圍第16項所述的製造垂直鰭式場效電晶體的方法， 其中形成所述初級堆疊結構包含： 在所述基底上形成所述初級下部間隔物層； 在所述初級下部間隔物層上形成所述犧牲層；以及 在所述犧牲層上形成所述初級上部間隔物層， 其中所述犧牲層插入於所述初級下部間隔物層與所述初級上部間隔物層之間。
  18. 如申請專利範圍第17項所述的製造垂直鰭式場效電晶體的方法， 其中所述犧牲層由與所述初級下部間隔物層和所述初級上部間隔物層的材料不同的材料形成。
  19. 如申請專利範圍第18項所述的製造垂直鰭式場效電晶體的方法， 其中所述犧牲層由矽或氧化矽形成，以及 其中所述初級下部間隔物層和所述初級上部間隔物層由氮化矽形成。
  20. 如申請專利範圍第16項所述的製造垂直鰭式場效電晶體的方法，更包含： 形成穿過所述初級上部間隔物層和所述犧牲層的第二溝槽； 移除通過所述第二溝槽暴露的所述犧牲層以使得暴露所述鰭式結構的側壁；以及 在所述鰭式結構的所述側壁上形成閘氧化物層和第一閘電極， 其中所述第一閘電極包含氮化鈦、氮化鉭或碳化鈦鋁。
TW106115923A 2016-06-16 2017-05-15 垂直鰭式場效電晶體及其製造方法與具有其的半導體裝置 TWI713121B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662351010P 2016-06-16 2016-06-16
US62/351,010 2016-06-16
US15/290,456 US9870957B2 (en) 2016-06-16 2016-10-11 Vertical fin field effect transistor (V-FinFET), semiconductor device having V-FinFET and method of fabricating V-FinFET
US15/290,456 2016-10-11

Publications (2)

Publication Number Publication Date
TW201801195A true TW201801195A (zh) 2018-01-01
TWI713121B TWI713121B (zh) 2020-12-11

Family

ID=60659733

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106115923A TWI713121B (zh) 2016-06-16 2017-05-15 垂直鰭式場效電晶體及其製造方法與具有其的半導體裝置

Country Status (4)

Country Link
US (2) US9870957B2 (zh)
KR (1) KR102579867B1 (zh)
CN (1) CN107527909B (zh)
TW (1) TWI713121B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI691020B (zh) * 2018-06-26 2020-04-11 美商格芯（美國）集成電路科技有限公司 在垂直式ｆｉｎｆｅｔ的主動區形成閘極接觸的方法以及藉此而形成的結構

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11088033B2 (en) * 2016-09-08 2021-08-10 International Business Machines Corporation Low resistance source-drain contacts using high temperature silicides
US10840354B2 (en) * 2017-02-06 2020-11-17 International Business Machines Corporation Approach to bottom dielectric isolation for vertical transport fin field effect transistors
US10608114B2 (en) * 2018-06-15 2020-03-31 International Business Machines Corporation Vertical nano-wire complimentary metal-oxide-semiconductor transistor with cylindrical III-V compound and germanium channel
US10957781B2 (en) 2018-07-31 2021-03-23 International Business Machines Corporation Uniform horizontal spacer
US10930758B2 (en) 2018-08-13 2021-02-23 International Business Machines Corporation Space deposition between source/drain and sacrificial layers
US10916638B2 (en) * 2018-09-18 2021-02-09 International Business Machines Corporation Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistance
EP3748683A1 (en) * 2019-06-05 2020-12-09 IMEC vzw A method for forming a verical field-effect transistor device
US11094798B2 (en) * 2019-06-14 2021-08-17 International Business Machines Corporation Vertical FET with symmetric junctions
US11917806B2 (en) 2021-08-12 2024-02-27 Changxin Memory Technologies, Inc. Method of manufacturing semiconductor structure and semiconductor structure
US12029026B2 (en) 2021-08-12 2024-07-02 Changxin Memory Technologies, Inc. Method of manufacturing semiconductor structure and semiconductor structure
US20230061683A1 (en) * 2021-09-01 2023-03-02 Tokyo Electron Limited. Method of Forming 3-Dimensional Spacer

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6798017B2 (en) 2001-08-31 2004-09-28 International Business Machines Corporation Vertical dual gate field effect transistor
KR101015498B1 (ko) * 2003-06-14 2011-02-21 삼성전자주식회사 수직 카본나노튜브 전계효과트랜지스터 및 그 제조방법
KR100906282B1 (ko) * 2004-01-22 2009-07-06 인터내셔널 비지네스 머신즈 코포레이션 수직 ｆｉｎ－ｆｅｔ ｍｏｓ 디바이스
JP4717014B2 (ja) * 2004-01-22 2011-07-06 インターナショナル・ビジネス・マシーンズ・コーポレーション 垂直型ｆｉｎ−ｆｅｔｍｏｓデバイス
KR100994710B1 (ko) 2007-12-21 2010-11-17 주식회사 하이닉스반도체 수직채널트랜지스터의 제조 방법
US7759729B2 (en) 2008-02-07 2010-07-20 International Business Machines Corporation Metal-oxide-semiconductor device including an energy filter
KR101026486B1 (ko) 2008-10-22 2011-04-01 주식회사 하이닉스반도체 반도체 소자 및 그의 제조방법
US8207032B2 (en) * 2010-08-31 2012-06-26 Micron Technology, Inc. Methods of forming pluralities of vertical transistors, and methods of forming memory arrays
KR101802220B1 (ko) 2010-12-20 2017-11-29 삼성전자주식회사 수직형 채널 트랜지스터를 포함하는 반도체 소자 및 그 제조 방법
KR20130134813A (ko) 2012-05-31 2013-12-10 에스케이하이닉스 주식회사 자기정렬된 게이트전극을 구비한 수직채널트랜지스터 및 그 제조 방법
US8975141B2 (en) * 2012-07-31 2015-03-10 GlobalFoundries, Inc. Dual work function FinFET structures and methods for fabricating the same
KR20140106903A (ko) 2013-02-27 2014-09-04 에스케이하이닉스 주식회사 트랜지스터, 이를 구비하는 가변 저항 메모리 장치 및 그의 제조방법
US20140264607A1 (en) * 2013-03-13 2014-09-18 International Business Machines Corporation Iii-v finfets on silicon substrate
US9425296B2 (en) * 2013-09-09 2016-08-23 Qualcomm Incorporated Vertical tunnel field effect transistor
KR20150037168A (ko) 2013-09-30 2015-04-08 에스케이하이닉스 주식회사 수직 채널 트랜지스터를 갖는 반도체 소자 및 그의 제조방법
US9564431B2 (en) * 2014-02-19 2017-02-07 Taiwan Semiconductor Manufacturing Company Limited Semiconductor structures and methods for multi-level work function
US9620591B2 (en) * 2014-02-19 2017-04-11 Taiwan Semiconductor Manufacturing Company Limited Semiconductor structures and methods for multi-level work function and multi-valued channel doping of nanowire transistors to improve drive current
KR20150101726A (ko) 2014-02-27 2015-09-04 에스케이하이닉스 주식회사 터널링 트랜지스터, 그를 포함하는 저항 변화 메모리 장치 및 그 제조방법
US9570288B2 (en) * 2014-03-19 2017-02-14 Ecole Polytechnique Federale De Lausanne (Epfl) Method to fabricate FinFET sensors, in particular, FinFET sensors for ionic, chemical and biological applications on Si-Bulk
KR20160000294A (ko) 2014-06-24 2016-01-04 에스케이하이닉스 주식회사 수직 채널을 갖는 반도체 장치, 그를 포함하는 저항 메모리 장치 및 그 제조방법
US9318447B2 (en) * 2014-07-18 2016-04-19 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and method of forming vertical structure
US9911848B2 (en) 2014-08-29 2018-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical transistor and method of manufacturing the same
US9368572B1 (en) * 2015-11-21 2016-06-14 International Business Machines Corporation Vertical transistor with air-gap spacer
US9525064B1 (en) * 2015-12-16 2016-12-20 International Business Machines Corporation Channel-last replacement metal-gate vertical field effect transistor
US9754933B2 (en) * 2015-12-30 2017-09-05 International Business Machines Corporation Large area diode co-integrated with vertical field-effect-transistors
US9640667B1 (en) * 2016-05-17 2017-05-02 International Business Machines Corporation III-V vertical field effect transistors with tunable bandgap source/drain regions
US9614087B1 (en) * 2016-05-17 2017-04-04 International Business Machines Corporation Strained vertical field-effect transistor (FET) and method of forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI691020B (zh) * 2018-06-26 2020-04-11 美商格芯（美國）集成電路科技有限公司 在垂直式ｆｉｎｆｅｔ的主動區形成閘極接觸的方法以及藉此而形成的結構

Also Published As

Publication number Publication date
TWI713121B (zh) 2020-12-11
KR102579867B1 (ko) 2023-09-15
US20170365526A1 (en) 2017-12-21
CN107527909B (zh) 2023-06-02
US10312156B2 (en) 2019-06-04
CN107527909A (zh) 2017-12-29
US20180114731A1 (en) 2018-04-26
US9870957B2 (en) 2018-01-16
KR20170142094A (ko) 2017-12-27

Similar Documents

Publication Publication Date Title
TWI713121B (zh) 垂直鰭式場效電晶體及其製造方法與具有其的半導體裝置
US10249628B2 (en) Semiconductor device having buried gate structure and method of fabricating the same
US9627514B1 (en) Semiconductor device and method of fabricating the same
KR102432268B1 (ko) 반도체 소자 및 그 제조 방법.
CN107393960B (zh) 垂直场效应晶体管及其制造方法
KR101843442B1 (ko) 반도체 소자 제조 방법
US9177891B2 (en) Semiconductor device including contact pads
CN106057803B (zh) 具有在隔离区上的间隔件的半导体器件
CN106716638B (zh) 半导体存储器件及其制造方法
US9786784B1 (en) Vertical field effect transistor and method of fabricating the same
US9793171B2 (en) Buried source-drain contact for integrated circuit transistor devices and method of making same
CN114420644A (zh) 半导体结构及其制造方法
KR102070094B1 (ko) 저항 전극을 갖는 반도체 소자
US9831119B2 (en) Semiconductor device and method of fabricating the same
US20160020205A1 (en) Semiconductor Devices and Methods of Fabricating the Same
CN220106519U (zh) 半导体器件
CN117135923B (zh) 半导体结构及其制备方法、电子设备
US20240074155A1 (en) Semiconductor device
KR20140052763A (ko) 게이트 구조체를 갖는 반도체 소자 및 그 제조 방법들
CN116884945A (zh) 半导体器件及其制作方法
CN114649333A (zh) 半导体器件