CN107527909A - 垂直鳍式场效晶体管及其制造方法与具有其的半导体装置 - Google Patents

垂直鳍式场效晶体管及其制造方法与具有其的半导体装置 Download PDF

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CN107527909A
CN107527909A CN201710368685.9A CN201710368685A CN107527909A CN 107527909 A CN107527909 A CN 107527909A CN 201710368685 A CN201710368685 A CN 201710368685A CN 107527909 A CN107527909 A CN 107527909A
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effect transistor
gate electrode
primary
fin field
vertical fin
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CN107527909B (zh
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郑修然
姜明吉
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明提供一种垂直鳍式场效晶体管(V‑FinFET)及其制造方法与具有其的半导体装置如下。衬底具有下部源极/漏极(S/D)。鳍式结构从下部源极/漏极的上表面垂直地延伸。鳍式结构包含具有上侧壁部分、下侧壁部分以及位于其间的中心侧壁部分的侧壁。上部S/D安置于鳍式结构的上表面上。上部间隔物安置于上侧壁部分上。下部间隔物安置于下侧壁部分上。包含栅氧化物层以及第一栅电极的堆叠结构安置于下部间隔物的上表面、中心侧壁部分以及上部间隔物的下表面上。第二栅电极安置于第一栅电极上。所述垂直鳍式场效晶体管可减小泄漏电流。

Description

垂直鳍式场效晶体管及其制造方法与具有其的半导体装置
相关申请案的交叉参考
本申请案主张于2016年6月16日在美国专利商标局申请的美国临时专利申请案第62/351,010号及于2016年10月11日在美国专利商标局申请的美国非临时专利申请案第15/290,456号的权益，所述申请案的公开内容在此以全文引用的方式并入本文中。
技术领域
本发明概念涉及垂直鳍式场效晶体管(V-FinFET)，具有V-FinFET的半导体装置以及制造所述V-FinFET的方法。
背景技术
晶体管一直是平面的。随着晶体管的缩小(shrink)，泄漏电流增大，耗尽电池组并且加热半导体芯片。为了减小泄漏电流，已经提出各种晶体管结构。
发明内容
根据本发明概念的示范性实施例，提供一种垂直鳍式场效晶体管(V-FinFET)如下。衬底具有下部源极/漏极(S/D)。鳍式结构从下部S/D的上表面垂直地延伸。鳍式结构包含具有上侧壁部分、下侧壁部分以及定位于其间的中心侧壁部分的侧壁。上部S/D安置于鳍式结构的上表面上。上部间隔物安置于上侧壁部分上。下部间隔物安置于下侧壁部分上。包含栅氧化物层以及第一栅电极的堆叠结构安置于下部间隔物的上表面、中心侧壁部分以及上部间隔物的下表面上。第二栅电极安置于第一栅电极上。
根据本发明概念的示范性实施例，提供一种半导体装置如下。半导体装置包含第一垂直鳍式场效晶体管(V-FinFET)。第一V-FinFET包含具有下部源极/漏极(S/D)的衬底以及安置于下部S/D的上表面上的第一鳍式结构。第一鳍式结构包含具有下侧壁部分、上侧壁部分以及定位于其间的中心侧壁部分的侧壁。第一V-FinFET还包含安置于第一鳍式结构的上表面上的上部S/D、安置于下侧壁部分上的下部间隔物以及安置于上侧壁部分上的上部间隔物。上部间隔物包含第一侧壁以及第二侧壁，上部间隔物的第一侧壁与上侧壁部分接触。第一V-FinFET还包含堆叠结构，所述堆叠结构包含栅氧化物层以及第一栅电极。堆叠结构插入于上部间隔物与下部间隔物之间。堆叠结构的第一侧壁与第一鳍式结构的侧壁相接触。堆叠结构的第二侧壁与上部间隔物的第二侧壁垂直对准。
根据本发明概念的示范性实施例，提供制造垂直鳍式场效晶体管(V-FinFET)的方法如下。下部S/D形成于衬底中。初级堆叠结构形成于衬底上。初级堆叠结构包含堆叠于彼此上的初级下部间隔物层、牺牲层以及初级上部间隔物层。穿过初级堆叠结构的第一沟槽经形成以暴露下部S/D。鳍式结构形成于第一沟槽中且形成于下部S/D上。上部S/D形成于鳍式结构以及初级堆叠结构上。鳍式结构从下部S/D外延生长(epitaxially grown)。
附图说明
通过参考本发明概念的附图详细描述其示范性实施例，本发明概念的这些以及其它特征将变得更加显而易见：
图1绘示根据本发明概念的示范性实施例的包含垂直鳍式场效晶体管(V-FinFET)的半导体装置的横截面图；
图1A绘示根据本发明概念的示范性实施例的包含垂直鳍式场效晶体管(V-FinFET)的半导体装置的横截面图；
图2绘示根据本发明概念的示范性实施例的制造图1的V-FinFET以及图1A的V-FinFET的流程图；
图3至16绘示根据图2的流程图所形成的图1的V-FinFET的横截面图；
图11A绘示根据图2的步骤S190所形成的图1的V-FinFET的横截面图；
图12A至13A绘示根据图2的流程图的图1A的V-FinFET的横截面图；
图17为具有根据本发明概念的示范性实施例所制造的V-FinFET的半导体模块；
图18为根据本发明概念的示范性实施例的具有V-FinFET的电子系统的框图；
图19为具有根据本发明概念的示范性实施例所制造的V-FinFET的电子系统的框图。
应了解，为了说明的简单和清晰起见，图中说明的元件未必按比例绘制。举例来说，为了清楚起见，可相对于其它元件夸大一些元件的尺寸。另外，在认为适当时已在图式中重复参考标号以指示对应或类似元件。
虽然可能未能示出一些横截面图的对应平面图和/或透视图，但是本文中所说明的的装置结构的横截面图提供对于沿着两个不同方向(如将在平面图中所说明)和/或在三个不同方向上(如将在透视图中所说明)延伸的多个装置结构的支持。两个不同方向可或可不相互正交。三个不同方向可包含可与两个不同方向正交的第三方向。多个装置结构可集成于同一电子装置中。举例来说，当以横截面图说明装置结构(例如，存储器单元结构或晶体管结构)时，电子装置可包含多个装置结构(例如，存储器单元结构或晶体管结构)，如将由电子装置的平面图说明。多个装置结构可布置成阵列和/或二维图案。
附图标号说明
100、100'：半导体装置
100A、100B：垂直鳍式场效晶体管；
110：衬底；
120：下部源极/漏极；
130：上部源极/漏极；
140：下部间隔物；
140P：初级下部间隔物层；
140-S1、150-S1：第一侧壁；
140-S2、150-S2：第二侧壁；
150：上部间隔物；
150P：初级上部间隔物层；
160、160'：鳍式结构；
160-S：侧壁；
170：栅氧化物层；
170P：初级栅氧化物层；
180：第一栅电极；
180P：初级第一栅电极；
190：第二栅电极；
190P：初级第二栅电极层；
190-P：部分；
200：衬里；
200'：第一保持衬里；
200"：第二保持衬里；
210、210'：罩盖层；
220A、220B：接触电极；
300：绝缘层；
500：半导体模块；
510：半导体模块衬底；
520：微处理器；
530：半导体装置；
540：输入/输出终端；
600：电子系统；
610：主体；
620：微处理器单元；
630：电源供应器；
640：功能单元；
650：显示控制器单元；
660：显示单元；
670：外部装置；
680：有线或无线通信单元；
700：电子系统；
712：存储器系统；
714：微处理器；
716：随机存取存储器；
718：用户界面；
720：总线；
H1：高度；
P150：初级上部间隔物；
PSL：经图案化牺牲层；
PSS：初级堆叠结构；
RTR：凹陷沟槽；
RTR-G、TR3-G：间隙；
S100、S110、S120、S130、S140、S150、S160、S170、S180、S190、S200、S210、S220、S230、S240、S250：步骤；
SL：牺牲层；
SS：堆叠结构；
SS'：堆叠结构；
TR1：第一沟槽；
TR2：第二沟槽；
TR3、TR3'：第三沟槽；
TSL：厚度。
具体实施方式
下文将参考附图来详细描述本发明概念的示范性实施例。然而，本发明概念可以不同形式实施，并且不应被解释为受限于本文所阐述的实施例。还将理解，当元件被称作在另一元件或衬底“上”时，其可直接地在另一元件或衬底上，或也可以存在介入层。还将理解，当元件被称作“耦接”到另一元件或“连接”到另一元件时，其可直接耦接到另一元件或连接到另一元件，或者也可以存在介入元件。
图1绘示根据本发明概念的示范性实施例的包含第一垂直鳍式场效晶体管(V-FinFET)100A以及第二垂直鳍式场效晶体管(V-FinFET)100B的半导体装置100的横截面图。第一V-FinFET 100A和第二V-FinFET 100B可为N型晶体管或P型晶体管。举例来说，第一V-FinFET 100A和第二V-FinFET 100B具有相同类型的半导体或不同类型的半导体。
第一V-FinFET 100A与第二V-FinFET 100B实质上类似，且因此为了方便描述，下文将描述第一V-FinFET 100A且将其称为V-FinFET 100A。第一V-FinFET 100A的描述可适用于第二V-FinFET 100B。如果第二V-FinFET 100B为不同类型的晶体管，那么经掺入源极/漏极中的杂质将不同。
V-FinFET 100A包含鳍式结构160、下部源极/漏极(S/D)120以及上部源极/漏极(S/D)130。鳍式结构160安置于下部S/D 120的上表面上且安置于上部S/D 130的下表面之下。举例来说，从下部S/D 120的上表面垂直地延伸的鳍式结构160插入于下部S/D 120与上部S/D 130之间。在此情形下，鳍式结构160的高度H1与沿上部S/D 130与下部S/D 120之间的鳍式结构160的侧壁160-S测量的V-FinFET 100A的栅长度相等。
经由使用离子植入工艺或扩散工艺将杂质掺入衬底110中而形成下部S/D 120。衬底110可由硅(Si)或硅和锗的合金(SiGe)形成。如果V-FinFET 100A为N型晶体管，那么杂质可为N型杂质，例如，磷(P)、砷(As)或锑(Sb)。如果V-FinFET 100A为P型晶体管，那么杂质可为P型杂质，例如，硼(B)、铝(Al)或镓(Ga)。
V-FinFET 100A可具有鳍式结构160中的通道。举例来说，当V-FinFET 100A接通时，可沿鳍式结构160的侧壁160-S形成通道且晶体管接通电流(turn-on current)可沿所述通道流动。
V-FinFET 100A还包含栅氧化物层170、第一栅电极180、下部间隔物140以及上部间隔物150。栅氧化物层170和第一栅电极180插入于上部间隔物150与下部间隔物140之间。举例来说，栅氧化物层170和第一栅电极180的堆叠结构插入于上部间隔物150与下部间隔物140之间。
上部间隔物150和下部间隔物140形成于鳍式结构160的侧壁160-S上。上部间隔物150包含第一侧壁150-S1和第二侧壁150-S2。下部间隔物140包含第一侧壁140-S1和第二侧壁140-S2。鳍式结构160的侧壁160-S包含上侧壁部分、下侧壁部分以及定位于上侧壁部分与下侧壁部分之间的中心侧壁部分。
举例来说，上部间隔物150的第一侧壁150-S1安置于鳍式结构160的上侧壁部分上。在示范性实施例中，上部间隔物150的第一侧壁150-S1可与鳍式结构160的上侧壁部分相接触。
举例来说，下部间隔物140的第一侧壁140-S1安置于鳍式结构160的下侧壁部分上。在示范性实施例中，下部间隔物140的第一侧壁140-S1可与鳍式结构160的下侧壁部分相接触。
下部间隔物140由两个相邻的第一V-FinFET 100A及第二V-FinFET 100B共享。在此情形下，下部间隔物140也安置于第二V-FinFET 100B的鳍式结构160'的侧壁上。在示范性实施例中，第二侧壁140-S2可与第二V-FinFET 100B的鳍式结构160'的侧壁相接触。
上部间隔物150可由使用化学气相沉积(CVD)工艺或等离子增强型CVD(PECVD)工艺沉积的氮化硅而形成。上部间隔物150和下部间隔物140可具有包含氮化硅的实质上相同的材料。
根据示范性实施例，鳍式结构160形成于初级上部间隔物层、牺牲层以及初级下部间隔物层的初级堆叠结构内且因此可经由控制初级堆叠结构的厚度而确定V-FinFET 100A的栅长度。可针对图4描述初级堆叠结构。
栅氧化物层170形成于上部间隔物150的下表面和下部间隔物140的上表面上。栅氧化物层170也形成于在上部间隔物150与下部间隔物140之间暴露的鳍式结构160的中心侧壁部分上。因此，栅氧化物层170为C形。
栅氧化物层170可由包含HfO2或HfSiO的高介电常数电介质材料(high-kdielectric material)形成。可使用各种沉积工艺来形成栅氧化物层170，所述工艺包含化学气相沉积(CVD)工艺、等离子增强型CVD(PECVD)工艺、金属有机CVD(MOCVD)工艺或原子层沉积工艺(ALD)。
第一栅电极180安置于栅氧化物层170上。在此情形下，栅氧化物层170插入于第一栅电极180与鳍式结构160的侧壁160-S之间；栅氧化物层170插入于上部间隔物150与第一栅电极180之间；以及栅氧化物层170插入于下部间隔物140与第一栅电极180之间。在此情形下，第一栅电极180保形地(comformally)形成于栅氧化物层170上且为C形。因此，栅氧化物层170和第一栅电极180的堆叠结构SS以栅氧化物层170和第一栅电极180的堆叠结构SS的侧壁与鳍式结构160的侧壁160-S相接触且堆叠结构SS的另一侧壁与上部间隔物150的第二侧壁150-S2垂直对准的方式插入于上部间隔物150与下部间隔物140之间。
在示范性实施例中，第一栅电极180可完全填充C形的栅氧化物层170，如图1A中所示。图1A的其它元件与图1的其对应元件相同，且因此为了便于描述，在本文中将仅描述图1与图1A之间的差异且将省略相同元件的其它描述。
第一栅电极180可由包含TiN的氮化物形成。本发明概念不限于此。第一栅电极180可由至少两个不同材料层(例如，TiN(氮化钛)/TaN(氮化钽)/TiAlC(碳化钛铝)形成。
V-FinFET 100A包含安置于两个相邻鳍式结构160之间的第二栅电极190。当从V-FinFET100A的上方查看时，第二栅电极190可围绕鳍式结构160。第二栅电极190具有与栅氧化物层170与上部间隔物150之间的界面共面的上表面。本发明概念不限于此。举例来说，第二栅电极190的上表面可比栅氧化物层170与上部间隔物150之间的界面更高或更低。第二栅电极190与第一栅电极180彼此电连接。举例来说，第二栅电极190与第一栅电极180相接触。因此，无论第二栅电极190的上表面的位置如何，V-FinFET 100A的栅长度可由与第一栅电极180电容耦接的鳍式结构160的高度H1确定。
第二栅电极190由两个相邻的第一V-FinFET 100A及第二V-FinFET 100B共享。
第二栅电极190填充由上部间隔物150与下部间隔物140之间的第一栅电极180界定的间隙。举例来说，C形的第一栅电极180接收第二栅电极190的部分190-P以使得栅氧化物层170和第一栅电极180的堆叠结构SS还包含第二栅电极190的部分190-P。
第二栅电极190的部分190-P、第一栅电极180以及栅氧化物层170的堆叠结构SS插入于上部间隔物150与下部间隔物140之间。举例来说，堆叠结构SS填充上部间隔物150与下部间隔物140之间的空间。在此情形下，第二栅电极190的部分190-P突出至C形的第一栅电极180中。
在图1A的示范性实施例中，第二栅电极190不突出至C形的第一栅电极180中以使得第二栅电极190的侧壁与上部间隔物150的第二侧壁150-S2垂直对准。堆叠结构SS'包含栅氧化物层170和第一栅电极180。堆叠结构SS'插入于上部间隔物150与下部间隔物140之间。
返回参看图1，插入第二栅电极190与下部S/D 120之间的下部间隔物140可用以防止第二栅电极190与下部S/D 120的电性短路(electrical short)。
插入第二栅电极190与上部S/D 130之间的上部间隔物150可用以防止第二栅电极190与上部S/D 130的电性短路。
半导体装置100还包含绝缘层300、罩盖层210以及具有栅极接触电极220A和上部S/D接触电极220B的接触电极(contact electrode)。
栅极接触电极220A穿过绝缘层300以电连接到第二栅电极190。第一欧姆(ohmic)接触层(在此未图示)可插入第二栅电极190与栅极接触电极220A之间以减小其间的接触电阻。在此情形下，栅极接触电极220A可与第一欧姆接触层相接触。
上部S/D接触电极220B穿过绝缘层300及罩盖层210以电连接到上部S/D 130。第二欧姆接触层(在此未图示)可插入上部S/D 130与上部S/D接触电极220B之间。
在下文中，将参考图2至16描述制造V-FinFET 100A的方法。
图2为根据本发明概念的示范性实施例的制造图1的V-FinFET 100A的流程图。图3至16表示根据图2的流程图形成的V-FinFET 100A的横截面图。
图3表示根据本发明概念的示范性实施例的在执行图2的步骤S100之后形成的下部S/D 120。
在步骤S100中，执行掺杂过程以使用离子植入工艺或扩散工艺在衬底110中形成下部S/D 120。如果形成N型晶体管，那么衬底110中可掺入N型杂质，例如，磷(P)、砷(As)或锑(Sb)。对于P型晶体管，衬底中可掺入P型杂质，例如，硼(B)、铝(Al)或镓(Ga)。
衬底110可由硅(Si)或硅和锗的合金(SiGe)形成。
图4表示根据图2的步骤S110、步骤S120以及步骤S130的包含初级下部间隔物层140P、牺牲层SL以及初级上部间隔物层150P的初级堆叠结构PSS。在初级堆叠结构PSS中，初级下部间隔物层140P、牺牲层SL以及初级上部间隔物层150P从衬底110以所列次序堆叠于彼此上。举例来说，初级堆叠结构PSS形成于衬底110上。
初级下部间隔物层140P可由氮化硅形成。牺牲层SL可由硅或氧化硅形成。初级上部间隔物层150P可由氮化硅形成。在示范性实施例中，初级下部间隔物层140P和初级上部间隔物层150P可由包含氮化硅的实质上相同的材料形成。可根据图1的V-FinFET的目标栅长度确定牺牲层SL的厚度TSL。
图5表示根据本发明概念的示范性实施例的在执行图2的步骤S140之后形成于初级堆叠结构PSS中的第一沟槽TR1。
在步骤S140中，可执行光刻工艺以界定初级堆叠结构PSS中的第一沟槽TR1。举例来说，经图案化光刻胶层(在此未图示)可形成于图4的初级上部间隔物层150P上，暴露初级堆叠结构PSS的待形成为第一沟槽TR1的区域。
在形成经图案化光刻胶层之后，可在步骤S140中执行方向性蚀刻工艺(directional etching process)从而在初级堆叠结构PSS中形成第一沟槽TR1。经图案化光刻胶层可用作用于方向性蚀刻工艺的蚀刻掩模。第一沟槽TR1穿过初级堆叠结构PSS以暴露下部S/D 120。第一沟槽TR1界定来自初级下部间隔物层140P的下部间隔物140。第一沟槽TR1也界定来自牺牲层SL的经图案化牺牲层PSL。初级上部间隔物P150由第一沟槽TR1界定。初级上部间隔物P150经进一步图案化以形成图1的上部间隔物150。将参看图10描述上部间隔物150的形成。
方向性蚀刻工艺可包含使用含氟(F)气体(例如，CF4)作为蚀刻气体的反应性离子蚀刻(RIE)工艺。举例来说，含F气体可蚀刻硅、氧化硅或氮化硅。
图6表示根据本发明概念的示范性实施例的在执行图2的步骤S150之后形成的衬里200。
在步骤S150中，可在图5的结果结构上保形地形成初级衬里(在此未图示)。举例来说，初级衬里可形成于第一沟槽TR1内而不完全填充第一沟槽TR1；初级衬里也可形成于初级上部间隔物P150的上表面上。
在形成初级衬里之后，可对初级衬里执行包含RIE工艺的方向性蚀刻工艺从而形成衬里200。在方向性蚀刻工艺中移除形成于初级上部间隔物P150和下部S/D 120上的初级衬里的部分且在执行方向性蚀刻工艺之后保持形成于第一沟槽TR1的侧壁上的初级衬里的部分。初级衬里的剩余部分被称作衬里200。举例来说，衬里200形成于第一沟槽TR1的侧壁上。
可使用化学气相沉积(CVD)工艺、等离子增强型CVD(PECVD)工艺或原子层沉积(ALD)工艺来形成初级衬里。衬里200可由氮化硅形成。举例来说，衬里200可由与上部间隔物150及下部间隔物140实质上相同的材料形成。
衬里200遮盖经图案化牺牲层PSL以防止经图案化牺牲层PSL在下文所描述的图2的步骤S160中充当用于外延生长工艺的晶种层。
图7表示根据本发明概念的示范性实施例的在执行图2的步骤S160之后形成的鳍式结构160。
在步骤S160中，鳍式结构160可通过使用下部S/D 120作为晶种层外延地形成。衬里200可防止鳍式结构160从经图案化牺牲层PSL外延生长。在示范性实施例中，鳍式结构160可从下部S/D 120外延生长。本发明概念不限于此。举例来说，可省略衬里200且因此鳍式结构160可从经图案化牺牲层PSL外延生长。
图8表示根据本发明概念的示范性实施例的在执行图2的步骤S170之后形成的上部S/D 130。
在步骤S170中，上部S/D 130可从鳍式结构160外延地形成。在上部S/D 130的外延生长中，可掺入N型或P型杂质。对于N型晶体管，在上部S/D 130的外延生长中掺入N型杂质。对于P型晶体管，在上部S/D 130的外延生长中掺入P型杂质。
可原位地(in-situ)或连续地执行鳍式结构160的形成以及上部S/D 130的形成。举例来说，可使用外延生长工艺连续地形成鳍式结构160和上部S/D 130。鳍式结构160和上部S/D 130可由硅或硅和锗的合金形成。
图9表示根据本发明概念的示范性实施例的在执行图2的步骤S180之后形成的罩盖层210。
两个相邻的罩盖层210和210'可界定待形成为如下文所描述的图10中所示的第二沟槽TR2的区域。在鳍式结构160上形成罩盖层210，遮盖上部S/D 130。在另一鳍式结构160'上形成另一罩盖层210'。
在步骤S180中，可使用CVD工艺或PECVD工艺在图8的结果结构上形成初级罩盖层(在此未图示)。初级罩盖层可由TiN形成。在形成初级罩盖层之后，可执行热处理以使得初级罩盖层与上部S/D 130的硅反应。举例来说，初级罩盖层的硅化反应可发生于上部S/D130上。上部间隔物上的初级罩盖层不具有硅化反应。在蚀刻工艺中，上部间隔物上的初级罩盖层经移除且保持被称作罩盖层210的经硅化初级罩盖层。
图10表示根据本发明概念的示范性实施例的在执行图2的步骤S190之后形成的第二沟槽TR2。
在步骤S190中，可对图9的结果结构执行包含RIE工艺的方向性蚀刻工艺。罩盖层210和210'可充当蚀刻掩模以使得在两个相邻的罩盖层210与210'之间形成第二沟槽TR2。在步骤S190中，可执行方向性蚀刻工艺直到通过第二沟槽TR2暴露下部间隔物140为止。第二沟槽TR2穿过图9的初级上部间隔物P150以界定上部间隔物150。在示范性实施例中，可通过第一沟槽TR1和第二沟槽TR2形成上部间隔物150。第二沟槽TR2进一步图案化经图案化牺牲层PSL以使得通过第二沟槽TR2暴露经图案化牺牲层PSL。
图11表示根据本发明概念的示范性实施例的在执行图2的步骤S200之后形成的凹陷沟槽RTR。
在步骤S200中，使用包含湿式蚀刻工艺或干式蚀刻工艺的各向同性蚀刻(isotropic etching process)工艺经由第二沟槽TR2移除经图案化牺牲层PSL。也可在步骤S200的各向同性蚀刻工艺中移除衬里200。举例来说，图10的第二沟槽TR2侧向凹入以使得通过凹陷沟槽RTR暴露鳍式结构160的侧壁。在此情形下，插入上部间隔物150与鳍式结构160之间的衬里200可保持为第一保持衬里200'；及插入下部间隔物140与鳍式结构160之间的衬里200可保持为第二保持衬里200"。
在示范性实施例中，衬里200、下部间隔物140以及上部间隔物150可由包含氮化硅的实质上相同的材料形成。在此情形下，第一保持衬里200'和上部间隔物150可视为如图11A中所示的具有相同材料的单个元件。在此情形下，第一保持衬里200'可视为上部间隔物150的部分，如图11A中所示；及第二保持衬里200"和下部间隔物140可视为如图11A中所示的具有相同材料的单个元件。在此情形下，第二保持衬里200"可视为下部间隔物140的部分，如图11A中所示。
在下文中，为了便于描述，假设衬里200、下部间隔物140以及上部间隔物150由包含氮化硅的实质上相同的材料形成。因此，可参看图11A描述步骤S200的后续过程。本发明概念不限于此。举例来说，衬里200可由与上部间隔物150和下部间隔物140的材料不同的材料形成。在此情形下，可对图11的结果结构执行步骤S200的后续过程。
图12表示根据本发明概念的示范性实施例的在执行图2的步骤S210之后形成的初级栅氧化物层170P和初级第一栅电极180P。
可使用包含CVD工艺、PECVD工艺或MOCVD工艺的沉积工艺在凹陷沟槽RTR内保形地形成初级栅氧化物层170P。
初级栅氧化物层170P可具有凹陷沟槽RTR并不完全被填充之程度的预定厚度。举例来说，初级栅氧化物层170P形成于鳍式结构160的侧壁、上部间隔物150的下表面以及下部间隔物140的上表面上。初级栅氧化物层170P进一步形成于上部间隔物150的第二侧壁150-S2上。上部间隔物150还包含与鳍式结构160的侧壁相接触的第一侧壁150-S1。
初级栅氧化物层170P可由包含HfO2或HfSiO的高介电常数电介质材料形成。
初级第一栅电极180P保形地形成于凹陷沟槽RTR内而不完全填充凹陷沟槽RTR。举例来说，初级第一栅电极180P不完全填充凹陷沟槽RTR的间隙RTR-G。间隙RTR-G插入于上部间隔物150与下部间隔物140之间。
本发明概念不限于此。举例来说，如图12A中所示，初级第一栅电极180P完全填充凹陷沟槽RTR的间隙RTR-G，而不完全填充凹陷沟槽RTR或初级第一栅电极180P可完全填充凹陷沟槽RTR。
可使用CVD工艺形成初级第一栅电极180P。初级第一栅电极180P可由包含TiN的氮化物形成。本发明概念不限于此。举例来说，初级第一栅电极180P可包含两个或多于两个不同材料层，例如，TiN/TaN/TiAlC。
图13表示根据本发明概念的示范性实施例的在执行图2的步骤S220之后形成的第三沟槽TR3。步骤S220应用于图12的结果结构。
在步骤S220中，可对图12的结果结构执行包含RIE工艺的方向性蚀刻工艺以形成第三沟槽TR3。经由步骤S220的方向性蚀刻工艺，初级栅氧化物层170P和初级第一栅电极180P分别经图案化为栅氧化物层170和第一栅电极180。举例来说，可执行步骤S220的方向性蚀刻工艺直到第三沟槽TR3暴露下部间隔物140的上表面为止。在此情形下，罩盖层210和210'可充当蚀刻掩模以将初级栅氧化物层170P和初级第一栅电极180P分别图案化成栅氧化物层170和第一栅电极180。栅氧化物层170和第一栅电极180为C形以使得C形的栅氧化物层170和第一栅电极180部分围绕第三沟槽TR3的间隙TR3-G。
上部间隔物150也可在步骤S220的方向性蚀刻工艺中充当蚀刻掩模。
第三沟槽TR3的间隙TR3-G与上部间隔物150和下部间隔物140重叠。
可使用NH4OH/H2O2蚀刻初级第一栅电极180P。本发明概念不限于此。举例来说，可使用初级第一栅电极180P相对于由TiN形成的罩盖层210和210'具有蚀刻选择率的蚀刻化学(etch chemistry)。
可使用含有氯(Cl)的蚀刻剂气体(例如，CCl4)蚀刻初级栅氧化物层170P。本发明概念不限于此。举例来说，可使用初级栅氧化物层170P相对于罩盖层210和210'具有蚀刻选择率的蚀刻剂气体。
返回参看图12A，可对图12A的结果结构执行图2的步骤S220。在此情形下，图13A表示在执行步骤S220之后形成的第三沟槽TR3'。与图13的第三沟槽TR3不同，图13A的第三沟槽TR3'不具有图13的间隙TR3-G。
图14表示根据本发明概念的示范性实施例的在执行图2的步骤S230之后形成的初级第二栅电极层190P。
初级第二栅电极层190P保形地形成于第三沟槽TR3内，填充图13的第三沟槽TR3。初级第二栅电极层190P也形成于罩盖层210上。
可执行CVD工艺或MOCVD工艺形成初级第二栅电极层190P。初级第二栅电极层190P可由包含钨(W)或铜(Cu)的导电材料形成。
图15表示根据本发明概念的示范性实施例的在执行图2的步骤S240之后形成的第二栅电极190。
可使用回蚀工艺使图14的初级第二栅电极层190P凹入从而形成第二栅电极190。由于第一栅电极180经电连接到第二栅电极190且V-FinFET 100A的栅长度由与第一栅电极180电容耦接的鳍式结构160的高度确定，步骤S240的回蚀工艺可具有工艺裕度。取决于回蚀工艺的工艺变化，第二栅电极190的上表面可与栅氧化物层170与上部间隔物150的下表面之间的界面共面、比所述界面更高或更低。为了便于描述，图15表示其上表面与栅氧化物层170与上部间隔物150的下表面之间的界面共面的第二栅电极190。
图16表示根据本发明概念的示范性实施例的在执行图2的步骤S250之后形成的接触电极220A和220B。
在步骤S250中，绝缘层300形成于图15的结果结构上。举例来说，绝缘层300形成于罩盖层210和第二栅电极190上。接触电极220A和220B穿过绝缘层300。举例来说，栅极接触电极220A穿过绝缘层300以电连接到第二栅电极190；及上部S/D接触电极220B穿过绝缘层300及罩盖层210以电连接到上部S/D 130。栅极接触电极220A可使用罩盖层210和210'与第二栅电极190自对准。
欧姆接触层(在此未图示)可插入栅极接触电极220A与第二栅电极190之间及上部S/D接触电极220B与上部S/D 130之间。
下部S/D接触电极(在此未图示)可穿过绝缘层300和下部间隔物140以电连接到下部S/D 120。欧姆接触层(在此未图示)可插入下部S/D 120与下部S/D接触电极之间。当从上方查看时，下部间隔物140可围绕鳍式结构160。因此，下部S/D接触电极可穿过下部间隔物140以电连接到下部S/D 120。
根据本发明概念的示范性实施例，可在形成鳍式结构之前形成初级下部间隔物层、牺牲层以及初级上部间隔物层的初级堆叠结构以使得V-FinFET的目标栅长度由牺牲层的厚度确定。
应用于图13的结果结构的步骤S230至步骤S250可适用于图13A的结果结构以形成图1A的半导体装置100'。本文中为了便于描述而省略关于步骤S230至步骤250的重复描述。
图17为具有根据本发明概念的示范性实施例所制造的半导体装置的半导体模块。
参看图17，半导体模块500包含半导体装置530。可根据本发明概念的示范性实施例形成半导体装置530。半导体装置530安装在半导体模块衬底510上。半导体模块500还包含安装在半导体模块衬底510上的微处理器520。输入/输出终端540安置于半导体模块衬底510的至少一个侧面上。半导体模块500可包含于存储卡或固态硬盘(solid state drive，SSD)中。
图18为根据本发明概念的示范性实施例的具有半导体装置的电子系统的框图。
参看图18，根据本发明概念的示范性实施例所制造的半导体装置可包含于电子系统600中。电子系统600包含主体610、微处理器单元620、电源供应器630、功能单元640以及显示控制器单元650。主体610可包含具有印刷电路板(PCB)或类似物的系统板或主板。微处理器单元620、电源供应器630、功能单元640以及显示控制器单元650安装或安置于主体610上。显示单元660可堆叠在主体610的上表面上。举例来说，显示单元660安置于主体610的表面上，显示由显示控制器单元650处理的图像。电源供应器630接收来自外部电源供应器的恒定电压，并且产生不同的电压电平以将电压供应到微处理器单元620、功能单元640、显示控制器单元650等。微处理器单元620接收来自电源供应器630的电压以控制功能单元640和显示单元660。功能单元640可以执行电子系统600的各种功能。举例来说，当电子系统600为例如手机(cellular phone)或类似物的移动电子产品时，功能单元640可以包含不同组件以通过与外部装置670进行通信而执行无线通信功能，例如拨号、到显示单元660的视频输出或到扬声器的语音输出，并且当包含相机时，它可以充当图像处理器。在示范性实施例中，如果电子系统600连接到存储卡以扩展存储容量，那么功能单元640可以充当存储卡控制器。功能单元640可经由有线或无线通信单元680与外部装置670交换信号。另外，当电子系统600需要通用串行总线(Universal Serial Bus，USB)来扩展功能时，功能单元640可以充当接口控制器。功能单元640可包含根据本发明概念的示范性实施例制造的半导体装置。
图19为具有根据本发明概念的示范性实施例所制造的半导体装置的电子系统的框图。
参考图19，电子系统700可包含在移动装置或计算机(computer)中。举例来说，电子系统700包含存储器系统712、微处理器714、随机存取存储器(random access memory，RAM)716以及用户界面718，其经配置以使用总线720执行数据通信。微处理器714可对电子系统700进行编程(program)并且控制电子系统700。RAM 716可用作微处理器714的可操作存储器。举例来说，微处理器714或RAM 716可包含根据本发明概念的示范性实施例所制造的半导体装置。
微处理器714、RAM 716和/或其它组件可以装配在单个封装内。用户界面718可用于将数据输入到电子系统700或从电子系统700中输出数据。存储器系统712可以存储微处理器714的可操作代码(operational codes)、通过微处理器714处理的数据或从外部接收的数据。存储器系统712可包含控制器和存储器。
虽然已经参考本发明概念的示范性实施例示出和描述了本发明概念，但是对于本领域的一般技术人员显而易见的是在不脱离由所附权利要求书限定的本发明概念的精神和范围的前提下可以作出形式和细节中的不同变化。

Claims (20)

1.一种垂直鳍式场效晶体管，其特征在于，包括：
衬底，其具有下部源极/漏极；
鳍式结构，其从所述下部源极/漏极的上表面垂直地延伸，其中所述鳍式结构包含具有上侧壁部分、下侧壁部分以及定位于其间的中心侧壁部分的侧壁；
上部源极/漏极，其安置于所述鳍式结构的上表面上；
上部间隔物，其安置于所述上侧壁部分上；
下部间隔物，其安置于所述下侧壁部分上；
堆叠结构，其包含栅氧化物层和第一栅电极，其中所述堆叠结构安置于所述下部间隔物的上表面、所述中心侧壁部分以及所述上部间隔物的下表面上；以及
第二栅电极，其安置于所述第一栅电极上。
2.根据权利要求1所述的垂直鳍式场效晶体管，其特征在于，所述栅氧化物层与所述鳍式结构的所述中心侧壁部分相接触，以及所述下部间隔物与所述下侧壁部分相接触且插入所述下部源极/漏极与所述栅氧化物层之间。
3.根据权利要求1所述的垂直鳍式场效晶体管，其特征在于，所述上部间隔物与所述上侧壁部分相接触且插入所述上部源极/漏极与所述栅氧化物层之间。
4.根据权利要求1所述的垂直鳍式场效晶体管，其特征在于，所述第一栅电极为C形以使得所述第一栅电极接收所述第二栅电极的一部分，以及所述第二栅电极的所述部分突出到C形的所述第一栅电极中。
5.根据权利要求4所述的垂直鳍式场效晶体管，其特征在于，所述栅氧化物层为C形以使得所述栅氧化物层插入于C形的所述第一栅电极与所述中心侧壁部分之间、C形的所述第一栅电极与所述上部间隔物之间以及C形的所述第一栅电极与所述下部间隔物之间。
6.根据权利要求5所述的垂直鳍式场效晶体管，其特征在于，所述堆叠结构还包含所述第二栅电极的所述部分，以及所述堆叠结构插入于所述上部间隔物与所述下部间隔物之间。
7.根据权利要求5所述的垂直鳍式场效晶体管，其特征在于，所述上部间隔物和所述下部间隔物由包含氮化硅的相同的材料形成。
8.根据权利要求1所述的垂直鳍式场效晶体管，其特征在于，还包含：
罩盖层，其遮盖所述上部源极/漏极；以及
上部源极/漏极接触电极，其穿过所述罩盖层以使得所述上部源极/漏极接触电极电连接到所述上部源极/漏极。
9.根据权利要求8所述的垂直鳍式场效晶体管，其特征在于，还包含：
栅极接触电极，其安置于所述第二栅电极上，
其中所述栅极接触电极与所述罩盖层相接触。
10.根据权利要求1所述的垂直鳍式场效晶体管，其特征在于，所述第一栅电极包含氮化钛、氮化钽或碳化钛铝。
11.一种半导体装置，其特征在于，包括：
第一垂直鳍式场效晶体管，
其中所述第一垂直鳍式场效晶体管包含：
衬底，其具有下部源极/漏极；
第一鳍式结构，其安置于所述下部源极/漏极的上表面上，其中所述第一鳍式结构包含具有下侧壁部分、上侧壁部分以及定位于其间的中心侧壁部分的侧壁；
上部源极/漏极，其安置于所述第一鳍式结构的上表面上；
下部间隔物，其安置于所述下侧壁部分上；
第一上部间隔物，其安置于所述上侧壁部分上，其中所述第一上部间隔物包含第一侧壁和第二侧壁，所述第一上部间隔物的所述第一侧壁与所述上侧壁部分相接触；以及
堆叠结构，其包含栅氧化物层和第一栅电极，
其中所述堆叠结构插入于所述第一上部间隔物与所述下部间隔物之间，
其中所述堆叠结构的第一侧壁与所述第一鳍式结构的所述侧壁相接触，以及
其中所述堆叠结构的第二侧壁与所述第一上部间隔物的所述第二侧壁垂直对准。
12.根据权利要求11所述的半导体装置，其特征在于，还包含：
第二垂直鳍式场效晶体管，
其中所述第二垂直鳍式场效晶体管包含：
第二鳍式结构，其位在所述衬底上，
其中所述第一垂直鳍式场效晶体管的第二栅电极插入于所述第一鳍式结构与所述第二鳍式结构之间以使得所述第一垂直鳍式场效晶体管和所述第二垂直鳍式场效晶体管共享所述第二栅电极。
13.根据权利要求11所述的半导体装置，其特征在于，所述第一垂直鳍式场效晶体管的所述栅氧化物层与所述中心侧壁部分相接触。
14.根据权利要求12所述的半导体装置，其特征在于，所述第一垂直鳍式场效晶体管的所述下部间隔物与所述第一鳍式结构的所述下侧壁部分及所述第二鳍式结构的侧壁相接触以使得所述第一垂直鳍式场效晶体管与所述第二垂直鳍式场效晶体管共享所述下部间隔物。
15.根据权利要求12所述的半导体装置，其特征在于，所述第二垂直鳍式场效晶体管还包含：
第二上部间隔物，其安置于所述第二鳍式结构的侧壁上，
其中所述第二上部间隔物与所述第一上部间隔物间隔开。
16.一种制造垂直鳍式场效晶体管的方法，其特征在于，包括：
在衬底中形成下部源极/漏极；
在所述衬底上形成初级堆叠结构，所述初级堆叠结构包含堆叠于彼此上的初级下部间隔物层、牺牲层以及初级上部间隔物层；
形成穿过所述初级堆叠结构的第一沟槽以暴露所述下部源极/漏极；
在所述第一沟槽中及在所述下部源极/漏极上形成鳍式结构；以及
在所述鳍式结构和所述初级堆叠结构上形成上部源极/漏极，
其中所述鳍式结构从所述下部源极/漏极外延生长。
17.根据权利要求16所述的制造垂直鳍式场效晶体管的方法，其特征在于，形成所述初级堆叠结构包含：
在所述衬底上形成所述初级下部间隔物层；
在所述初级下部间隔物层上形成所述牺牲层；以及
在所述牺牲层上形成所述初级上部间隔物层，
其中所述牺牲层插入于所述初级下部间隔物层与所述初级上部间隔物层之间。
18.根据权利要求17所述的制造垂直鳍式场效晶体管的方法，其特征在于，所述牺牲层由与所述初级下部间隔物层和所述初级上部间隔物层的材料不同的材料形成。
19.根据权利要求18所述的制造垂直鳍式场效晶体管的方法，其特征在于，所述牺牲层由硅或氧化硅形成，以及所述初级下部间隔物层和所述初级上部间隔物层由氮化硅形成。
20.根据权利要求16所述的制造垂直鳍式场效晶体管的方法，其特征在于，还包含：
形成穿过所述初级上部间隔物层和所述牺牲层的第二沟槽；
移除通过所述第二沟槽暴露的所述牺牲层以使得暴露所述鳍式结构的侧壁；以及
在所述鳍式结构的所述侧壁上形成栅氧化物层和第一栅电极，
其中所述第一栅电极包含氮化钛、氮化钽或碳化钛铝。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11917806B2 (en) 2021-08-12 2024-02-27 Changxin Memory Technologies, Inc. Method of manufacturing semiconductor structure and semiconductor structure
US12029026B2 (en) 2021-08-12 2024-07-02 Changxin Memory Technologies, Inc. Method of manufacturing semiconductor structure and semiconductor structure

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11088033B2 (en) * 2016-09-08 2021-08-10 International Business Machines Corporation Low resistance source-drain contacts using high temperature silicides
US10840354B2 (en) * 2017-02-06 2020-11-17 International Business Machines Corporation Approach to bottom dielectric isolation for vertical transport fin field effect transistors
US10608114B2 (en) 2018-06-15 2020-03-31 International Business Machines Corporation Vertical nano-wire complimentary metal-oxide-semiconductor transistor with cylindrical III-V compound and germanium channel
US10559686B2 (en) * 2018-06-26 2020-02-11 Globalfoundries Inc. Methods of forming gate contact over active region for vertical FinFET, and structures formed thereby
US10957781B2 (en) 2018-07-31 2021-03-23 International Business Machines Corporation Uniform horizontal spacer
US10930758B2 (en) 2018-08-13 2021-02-23 International Business Machines Corporation Space deposition between source/drain and sacrificial layers
US10916638B2 (en) * 2018-09-18 2021-02-09 International Business Machines Corporation Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistance
EP3748683A1 (en) * 2019-06-05 2020-12-09 IMEC vzw A method for forming a verical field-effect transistor device
US11094798B2 (en) * 2019-06-14 2021-08-17 International Business Machines Corporation Vertical FET with symmetric junctions
US20230061683A1 (en) * 2021-09-01 2023-03-02 Tokyo Electron Limited. Method of Forming 3-Dimensional Spacer

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050156203A1 (en) * 2003-06-14 2005-07-21 Samsung Electronics Co., Ltd. Vertical carbon nanotube-field effect transistor and method of manufacturing the same
US20090200604A1 (en) * 2004-01-22 2009-08-13 International Business Machines Corporation Vertical fin-fet mos devices
US20120052640A1 (en) * 2010-08-31 2012-03-01 Mark Fischer Methods Of Forming Pluralities Of Vertical Transistors, And Methods Of Forming Memory Arrays
US20140038402A1 (en) * 2012-07-31 2014-02-06 Globalfoundries Inc. Dual work function finfet structures and methods for fabricating the same
US20150069458A1 (en) * 2013-09-09 2015-03-12 Qualcomm Incorporated Vertical tunnel field effect transistor
US20150236092A1 (en) * 2014-02-19 2015-08-20 Taiwan Semiconductor Manufacturing Company Limited Semiconductor structures and methods for multi-level work function and multi-valued channel doping of nanowire transistors to improve drive current
US20150236086A1 (en) * 2014-02-19 2015-08-20 Taiwan Semiconductor Manufacturing Company Limited Semiconductor structures and methods for multi-level work function
US20160020180A1 (en) * 2014-07-18 2016-01-21 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and method of forming vertical structure

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6798017B2 (en) * 2001-08-31 2004-09-28 International Business Machines Corporation Vertical dual gate field effect transistor
KR100906282B1 (ko) * 2004-01-22 2009-07-06 인터내셔널 비지네스 머신즈 코포레이션 수직 ｆｉｎ－ｆｅｔ ｍｏｓ 디바이스
KR100994710B1 (ko) 2007-12-21 2010-11-17 주식회사 하이닉스반도체 수직채널트랜지스터의 제조 방법
US7759729B2 (en) * 2008-02-07 2010-07-20 International Business Machines Corporation Metal-oxide-semiconductor device including an energy filter
KR101026486B1 (ko) 2008-10-22 2011-04-01 주식회사 하이닉스반도체 반도체 소자 및 그의 제조방법
KR101802220B1 (ko) 2010-12-20 2017-11-29 삼성전자주식회사 수직형 채널 트랜지스터를 포함하는 반도체 소자 및 그 제조 방법
KR20130134813A (ko) 2012-05-31 2013-12-10 에스케이하이닉스 주식회사 자기정렬된 게이트전극을 구비한 수직채널트랜지스터 및 그 제조 방법
KR20140106903A (ko) 2013-02-27 2014-09-04 에스케이하이닉스 주식회사 트랜지스터, 이를 구비하는 가변 저항 메모리 장치 및 그의 제조방법
US20140264607A1 (en) * 2013-03-13 2014-09-18 International Business Machines Corporation Iii-v finfets on silicon substrate
KR20150037168A (ko) 2013-09-30 2015-04-08 에스케이하이닉스 주식회사 수직 채널 트랜지스터를 갖는 반도체 소자 및 그의 제조방법
KR20150101726A (ko) 2014-02-27 2015-09-04 에스케이하이닉스 주식회사 터널링 트랜지스터, 그를 포함하는 저항 변화 메모리 장치 및 그 제조방법
US9570288B2 (en) * 2014-03-19 2017-02-14 Ecole Polytechnique Federale De Lausanne (Epfl) Method to fabricate FinFET sensors, in particular, FinFET sensors for ionic, chemical and biological applications on Si-Bulk
KR20160000294A (ko) 2014-06-24 2016-01-04 에스케이하이닉스 주식회사 수직 채널을 갖는 반도체 장치, 그를 포함하는 저항 메모리 장치 및 그 제조방법
US9911848B2 (en) 2014-08-29 2018-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical transistor and method of manufacturing the same
US9368572B1 (en) * 2015-11-21 2016-06-14 International Business Machines Corporation Vertical transistor with air-gap spacer
US9525064B1 (en) * 2015-12-16 2016-12-20 International Business Machines Corporation Channel-last replacement metal-gate vertical field effect transistor
US9754933B2 (en) * 2015-12-30 2017-09-05 International Business Machines Corporation Large area diode co-integrated with vertical field-effect-transistors
US9614087B1 (en) * 2016-05-17 2017-04-04 International Business Machines Corporation Strained vertical field-effect transistor (FET) and method of forming the same
US9640667B1 (en) * 2016-05-17 2017-05-02 International Business Machines Corporation III-V vertical field effect transistors with tunable bandgap source/drain regions

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050156203A1 (en) * 2003-06-14 2005-07-21 Samsung Electronics Co., Ltd. Vertical carbon nanotube-field effect transistor and method of manufacturing the same
US20090200604A1 (en) * 2004-01-22 2009-08-13 International Business Machines Corporation Vertical fin-fet mos devices
US20120052640A1 (en) * 2010-08-31 2012-03-01 Mark Fischer Methods Of Forming Pluralities Of Vertical Transistors, And Methods Of Forming Memory Arrays
US20140038402A1 (en) * 2012-07-31 2014-02-06 Globalfoundries Inc. Dual work function finfet structures and methods for fabricating the same
US20150069458A1 (en) * 2013-09-09 2015-03-12 Qualcomm Incorporated Vertical tunnel field effect transistor
US20150236092A1 (en) * 2014-02-19 2015-08-20 Taiwan Semiconductor Manufacturing Company Limited Semiconductor structures and methods for multi-level work function and multi-valued channel doping of nanowire transistors to improve drive current
US20150236086A1 (en) * 2014-02-19 2015-08-20 Taiwan Semiconductor Manufacturing Company Limited Semiconductor structures and methods for multi-level work function
US20160020180A1 (en) * 2014-07-18 2016-01-21 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and method of forming vertical structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11917806B2 (en) 2021-08-12 2024-02-27 Changxin Memory Technologies, Inc. Method of manufacturing semiconductor structure and semiconductor structure
US12029026B2 (en) 2021-08-12 2024-07-02 Changxin Memory Technologies, Inc. Method of manufacturing semiconductor structure and semiconductor structure

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