TW201736947A - 用於橫向硬光罩凹槽減小的混合碳硬光罩 - Google Patents

用於橫向硬光罩凹槽減小的混合碳硬光罩 Download PDF

Info

Publication number
TW201736947A
TW201736947A TW106100691A TW106100691A TW201736947A TW 201736947 A TW201736947 A TW 201736947A TW 106100691 A TW106100691 A TW 106100691A TW 106100691 A TW106100691 A TW 106100691A TW 201736947 A TW201736947 A TW 201736947A
Authority
TW
Taiwan
Prior art keywords
hard mask
layers
nitrogen
oxygen
carbon
Prior art date
Application number
TW106100691A
Other languages
English (en)
Other versions
TWI726034B (zh
Inventor
湯姆士容萬 鄺
程睿
亞伯希吉特巴蘇 馬禮克
爾萱 平
安在洙
Original Assignee
應用材料股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 應用材料股份有限公司 filed Critical 應用材料股份有限公司
Publication of TW201736947A publication Critical patent/TW201736947A/zh
Application granted granted Critical
Publication of TWI726034B publication Critical patent/TWI726034B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/80—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Abstract

本申請案之實施與改善之用於基板之圖案化及蝕刻的硬光罩材料及方法相關。複數個硬光罩可與圖案化及蝕刻處理結合使用以實現進階的裝置架構。在一實施中，第一硬光罩及第二硬光罩經設置於基板上，該基板具有各種設置於該基板上的材料層。在第一蝕刻處理期間可使用第二硬光罩以圖案化第一硬光罩。可在第一硬光罩上及第二硬光罩上沉積第三硬光罩，且可使用第二蝕刻處理以形成溝槽於材料層中。

Description

用於橫向硬光罩凹槽減小的混合碳硬光罩
本申請案之實施大體上係與基板之圖案化及蝕刻中所利用的方法及材料相關。更確切地說，本文所描述之實施係與混合碳硬光罩相關。
積體電路已發展成可在單一晶片上包含數百萬個電晶體、電容器及電阻器的複雜裝置。晶片設計的發展持續需要更快的電路及更大的電路密度。對具有更大電路密度的更快電路之需求施加相應要求於用來製造此類積體電路的材料上。尤其是隨著積體電路元件的尺寸減小到亞微米級，通常需要使用低電阻率導電材料及低介電常數絕緣材料以獲得用於此類元件的合適電性。
隨著積體裝置圖案的特徵尺寸減小，特徵的臨界尺寸(CD)要求變成用於穩定及可重複裝置效能的越來越重要的標準。跨越基板之可允許的CD變化也隨著特徵CD的縮放而縮放。由於橫向縮放比縱向縮放快及因裝置電容問題，高長寬比(HAR)目前在半導體工業內是普遍的。
當此類要求的長寬比及CD控制與高蝕刻選擇性、側壁平滑度及高工具產量的要求相結合時，用於任何硬體配置的處理裕度可變得非常小。在眾多情況下，當將多個處理氣體結合至與極端的硬體設定(如非常高的RF偏壓功率)結合之複雜的蝕刻劑氣體混合物時，小的處理裕度出現，以實現側壁鈍化、蝕刻速度及光罩選擇性間的脆弱平衡。然而，此種小的處理裕度通常遭受到性能限制，該等性能限制係不能使用當前可用的處理及材料來調整蝕刻處理。
因此，本領域需要改善的硬光罩材料及方法。
在一實施中，提供基板處理方法。方法包含以下步驟：沉積第一硬光罩於經設置於基板上的一或多個材料層上，及沉積第二硬光罩於該第一硬光罩上。可圖案化該第二硬光罩，及可執行第一蝕刻處理以蝕刻該第一硬光罩及該第二硬光罩。保形地沉積第三硬光罩於該一或多個材料層、該第一硬光罩及該第二硬光罩上，及執行第二蝕刻處理以蝕刻該一或多個材料層以形成溝槽於該一或多個材料層中。
在另一實施中，提供基板處理方法。方法包含以下步驟：沉積第一硬光罩於經設置在基板上的一或多個含氧及氮材料層上，及沉積第二硬光罩於該第一硬光罩上。執行第一蝕刻處理以蝕刻該第一硬光罩及該第二硬光罩，及保形地沉積碳氮化硼硬光罩於該一或多個含氧及氮材料層、該第一硬光罩及該第二硬光罩上。執行第二蝕刻處理以蝕刻該一或多個含氧及氮材料層以形成溝槽於該一或多個含氧及氮材料層中，及該第二蝕刻處理為使用由CH4 、N2 及O2 組成的群組所選出的先驅物及富含氟的先驅物的基於電漿的蝕刻處理。
在另一實施中，提供基板處理方法。方法包含以下步驟：沉積碳質硬光罩於經設置在基板上的一或多個含氧及氮材料層上，及沉積含矽的介電硬光罩於該碳質硬光罩上。執行第一蝕刻處理以蝕刻該碳質硬光罩及該含矽的介電硬光罩，及保形地沉積碳氮化硼硬光罩於該一或多個含氧及氮材料層、該碳質硬光罩及該含矽的介電硬光罩上。執行第二蝕刻處理以蝕刻該一或多個含氧及氮材料層以形成溝槽於該一或多個含氧及氮材料層中，及該第二蝕刻處理為使用由CH4 、N2 及O2 組成的群組所選出的先驅物及富含氟的先驅物的基於電漿的蝕刻處理。
本申請案之實施與改善之用於基板之圖案化及蝕刻的硬光罩材料及方法相關。複數個硬光罩可與圖案化及蝕刻處理結合使用以實現進階的裝置架構。在一實施中，第一硬光罩及第二硬光罩經設置於基板上，該基板具有各種設置於該基板上的材料層。在第一蝕刻處理期間可使用第二硬光罩以圖案化第一硬光罩。可在第一硬光罩上及第二硬光罩上沉積第三硬光罩，且可使用第二蝕刻處理以形成溝槽於材料層中。
圖1圖示說明基板102之部分之示意性的橫截面圖，該基板具有各種根據本文所描述之實施而在該基板上形成的材料。基板102通常可被認為是下層，該下層係具有沉積於該下層上或以其他方式形成於該下層上的各種材料。基板102的合適範例包含矽基板、碳摻雜氧化矽絕緣層上矽(SOI)基板、氮化矽、碳化矽、摻雜矽、鍺、砷化鎵、玻璃、藍寶石及如金屬、金屬氮化物、金屬碳化物、金屬合金及其它導電材料的任何其它材料(取決於應用)。材料層104可沉積於基板102上。材料層104可包含一或多個第一材料層106及一或多個第二材料層108。第一材料層106及第二材料層108可沉積於替代布置中以形成層堆疊。可自各種氧化物材料及氮化物材料(如氧化矽材料及氮化矽材料)形成第一材料層106及第二材料層108。在一實施中，第一材料層106可為氮化矽材料及第二材料層108可為氧化矽材料。在另一實施中，第一材料層106可為氧化矽材料及第二材料層108可為氮化矽材料。
材料層104通常由適於形成三維(3D)NAND裝置之布置中的材料製成。在一實施中，材料層104可包含大於約24個材料層、大於約32個材料層、大於約48個材料層、大於約54個材料層或大於約64個材料層。在某些實施中，本文所提供的揭示內容可針對具有大於約48個材料層的先進3D NAND裝置來實施。
第一硬光罩110可沉積於材料層104上。第一硬光罩110可包含碳質材料，該等碳質材料適於藉由各種基於電漿的蝕刻處理的蝕刻。可用於第一硬光罩110的合適材料包含摻雜及未摻雜的無定形碳材料，該等摻雜及未摻雜的無定形碳材料可從加州聖塔克拉拉市的應用材料公司購得，其商品名稱為先進曝光圖樣薄膜(Advanced Patterning FilmTM ，APF)。第一硬光罩110的厚度114可為約1 µm 與約 2 µm之間(如約1.5µm)。然而，可以設想到厚度114可取決於利用下層材料層104的所期望的蝕刻及圖案化特徵。舉例而言，第一硬光罩110可形成或沉積的厚度取決於材料對處理化學及條件的抵抗力，該等處理化學及條件係用於隨後蝕刻材料層104且同時保持第一硬光罩110及/或材料層104之合適的結構完整性的處理化學及條件。
第二硬光罩112可沉積於第一硬光罩110上。第二硬光罩112可為介電材料及可具有約20 µm 與約 200 µm之間的厚度116；例如，約50µm 與約 100 µm之間(如約80µm)。與第一硬光罩110相似，在隨後的蝕刻處理期間，可取決於期望效能來選擇第二硬光罩112的厚度116。在一實施中，第二硬光罩112可作為介電抗反射層(DARC)及/或改善由旋塗技術施加的隨後施加的有機膜的黏著性，否則該等隨後施加的有機膜可能不會良好地黏著至第一硬光罩110。第二硬光罩112可為單一膜或由至少一矽材料組成的多層膜堆疊。第二硬光罩112亦可包含氮及/或氧以形成二氧化矽材料、氮化矽材料或氮氧化矽材料。亦可調整第二硬光罩112的組成及厚度以為在裝置特徵的光刻圖案化期間採用的期望波長提供最小反射及高對比度。
光阻劑層118可沉積在第二硬光罩112上。光阻劑層118經圖示為預先圖案化。取決於將在基板102上形成的裝置特徵的期望間距及CD，合適的圖案化技術包含193nm光刻、193nm浸潤式微影術及極紫外光(EUV)微影術。亦可設想可利用如自對準雙圖案法(SADP)及自對準四重圖案法(SAQP)處理的雙圖案處理來圖案化光阻劑層118。可用於光阻劑層118的合適材料包含聚合物及諸如此類，如有機聚合物等。
圖2圖示說明根據本文所描述之實施之在第一蝕刻處理後之基板102之部分之示意性的橫截面圖。預先圖案化的光阻劑層118通常提供由第一蝕刻處理所利用的圖案。在經圖示說明的實施中，第一蝕刻處理可蝕刻第二硬光罩112及第一硬光罩110以形成第一硬光罩110之相鄰部分間的凹槽202。第一蝕刻處理可為使用適於蝕刻第一硬光罩110及第二硬光罩112的化學物質的電漿蝕刻處理。舉例而言，如任何已知的CX HY FZ (例如，CHF3 、CH2 F2 及CHF3 等)及/或任何已知的CX FY (例如，CF4 、C2 F6 、C4 F8 、C4 F6 及C5 F8 等)之碳氟化合物先驅物可被激發成電漿以移除第一光罩110及第二光罩112的部分以形成凹槽202。可在電漿形成期間提供如N2 之攜帶氣體或惰性氣體。
取決於期望的電漿特性及硬體實施，可藉由電感耦合電漿技術、電容耦合電漿技術及/或遠端電漿技術來形成電漿。通常來說，可用低頻偏壓功率RF產生器來激發先驅物，該低頻偏壓功率RF產生器具有低於約50MHz的頻率(如約13.56MHz)。設想到第一蝕刻處理可為時間相依的，且可執行該第一蝕刻處理足以用於凹槽和暴露材料層104的時間量。
圖3圖示說明根據本文所描述之實施之在保形地沉積第三硬光罩302後之基板102之部分之示意性的橫截面圖。在某些實施中，第三硬光罩302可沉積有大於約98%的保形性。如本文所使用地，術語「保形」或「保形地」係意指黏著至及均勻地覆蓋具有厚度304之暴露表面的層，該厚度304係具有相對於膜的平均厚度而言小於1%的變化。舉例而言，1000□厚的膜的厚度變化小於10□。此厚度及變化包含凹槽的邊緣、角、側面及底部。
在某些實施中，第三硬光罩302的厚度304可在約5nm與約15nm間(如約10nm)。因第三硬光罩302的保形性，第三硬光罩302可沉積於不同的材料上，如第二硬光罩112、第一硬光罩110及材料層104。由凹槽202所定義的第一硬光罩特徵及第二硬光罩特徵的結果CD 306可在約20nm與約100nm間(如約50nm與約80nm間)。因此，可藉由將第一硬光罩110及第二硬光罩112與第三硬光罩302結合使用來實現減小的CD。
在某些實施中，第三硬光罩302可為摻雜硼的無定形碳材料。如本文所使用地，摻雜硼的無定形碳材料包含由至少1 wt%的硼及至少20 wt%的碳所組成的材料。此類材料中包含富含硼的無定形碳，該富含硼的無定形碳通常由大於約25wt%的硼及約50 wt%的碳所組成。
可用熱沉積處理(CVD)或電漿增強沉積處理(PECVD)利用噴塗/旋塗方法來形成第三硬光罩302。在一實施中，給定膜特性為那些典型的熱解石墨、石墨及類金剛石碳的混合物，則第三硬光罩302用CVD或PECVD沉積，以形成由至少50 wt%之具有sp1、sp2及sp3鍵結狀態的碳所組成的碳材料。在某些實施中，可用使用烴先驅物的PECVD處理來形成第三硬光罩302，該等烴先驅物如甲烷、丙烯、丙炔、丙烷、丁烷、丁烯、丁二烯、乙炔、甲苯及上述與硼源(如乙硼烷)的混合物及諸如此類。在某些實施中，第三硬光罩302亦可包含氮或其他添加物。示例性的第三硬光罩材料可從加州聖塔克拉拉市的應用材料公司購得，其商品名稱為先進曝光圖樣薄膜(Advanced Patterning FilmTM ，APF)；更具體來說，係為稱為APFc之APF所屬材料的一種材料，該材料摻雜硼。
在第三硬光罩302包含氮的實施中，材料可被稱作碳氮化硼材料。如本文中所使用地，術語「碳氮化硼」係意指包含硼、碳及氮的膜。在一些實施中，碳氮化硼膜基本上由硼、碳及氮組成，其係意謂硼、碳及氮組構成膜的至少約80原子百分比。在一些實施中，碳氮化硼膜基本上由硼、碳及氮(及可選地，與氫原子)組成。
在一範例中，可藉由熱CVD處理來沉積碳氮化硼材料，該熱CVD處理係使用二甲胺基硼烷[（CH3 ）2 NH·BH3 ]（DMAB）先驅物。可在熱罐中加熱DMAB以提高蒸氣壓，且可使用超高純度(UHP)Ar攜帶氣體將該DMAB輸送到處理腔室。熱罐溫度可在室溫至約150℃的範圍內。Ar攜帶氣體可在約100 sccm至約20000 sccm的範圍內。為了控制碳氮化硼膜的元素組成，可將NH3 、H2 及C3 H6 共反應物氣體輸送到CVD腔室。腔室溫度可在約300℃至約550℃的範圍內。處理腔室的壓力可以在約100 mTorr至約100 Torr的範圍內。用於沉積第三硬光罩302的合適處理腔室之範例為可從加州聖塔克拉拉市的應用材料公司獲得的處理設備的PRODUCER□ 家族。然而，可以設想到來自其他製造商之經配置來沉積APF膜的其他腔室亦可用於保形地沉積第三硬光罩302。
圖4圖示說明根據本文所描述之實施之在執行第二蝕刻處理後之基板102之部分之示意性的橫截面圖。一般來說，第二蝕刻經配置以蝕刻材料層104，以在材料層104中形成溝槽402。亦可在第二蝕刻處理期間或在該第二蝕刻處理後移除第二硬光罩112及第三硬光罩302。亦可藉由將第一硬光罩110與第三硬光罩302結合使用來實現在第二蝕刻處理期間改善材料蝕刻選擇性。相信亦可藉由將光罩彼此結合使用來維持硬光罩移除特性。
舉例而言，由於將材料層104的蝕刻速度與第三硬光罩302的蝕刻速度相比較，故可改善溝槽402的垂直度分布以用於先進特徵堆疊。在某些實施中，可以設想到材料層104的蝕刻速度可比第三硬光罩302的蝕刻速度大於約3.5倍至約4.0倍。因此，在移除第三硬光罩302時，可實現溝槽402之適當深度及垂直度分布。
第二蝕刻處理可為基於電漿的蝕刻處理，該基於電漿的蝕刻處理可具有CH4 /N2 /O2 先驅物之結合及富含氟的先驅物，如CHF、CF4 、SF6 及C2 F6 等諸如此類。添加富含氟的源可助於移除第三硬光罩302中的硼，而CH4 （及一定程度的碳氟化合物先驅物）先驅物可主要地促進材料層104之氧化物材料/氮化物材料的移除。N2 及O2 先驅物亦可助於第三硬光罩302的灰化，使得不需要隨後的灰化處理。換句話說，第三硬光罩302(及第二硬光罩112)的灰化可在形成材料層104中之溝槽402之第二蝕刻處理期間原位進行。用於執行第二蝕刻處理之合適設備包含ENABLER□ 蝕刻腔室、AdvantEdge G3蝕刻腔室及C3蝕刻腔室，上述之所有腔室皆可自加州聖塔克拉拉市的應用材料公司獲得。可以設想到來自其他製造商之其他經合適配置的腔室亦可用於執行如本文所描述的第二蝕刻處理。
總之，可利用圖案化處理來圖案化第二硬光罩112，且可利用第一蝕刻處理來蝕刻第一硬光罩110及第二硬光罩112之一者或兩者。在第一蝕刻處理期間在形成凹槽202於第一硬光罩110後，第三硬光罩302可保形地沉積在材料層104、第一硬光罩110及第二硬光罩112上。然後可執行第二蝕刻處理以在材料層104中形成通道402，以從基板102移除第二硬光罩112及第三硬光罩302。因此，可藉由利用本文所述之實施來實現經改善的溝槽特性，如CD及垂直度分布及如選擇性的蝕刻特性。
儘管上述內容係針對本申請案的實施，但在不脫離本申請案之基本範疇的情況下係可設計本申請案之其他及進一步的實施，及本申請案之範疇係由後文的申請專利範圍所決定。
102‧‧‧基板
104‧‧‧材料層
106‧‧‧第一材料層
108‧‧‧第二材料層
110‧‧‧第一硬光罩
112‧‧‧第二硬光罩
114‧‧‧厚度
116‧‧‧厚度
118‧‧‧光阻劑層
202‧‧‧凹槽
302‧‧‧第三硬光罩
304‧‧‧厚度
306‧‧‧CD
402‧‧‧溝槽
上文所簡短總結之本申請案之更具體的描述可參考實施(該等實施中的一些實施係經圖示說明於附加圖式中)，以可更詳細地理解本申請案之上述特徵所述的方法。然而，應注意到附加圖式僅圖示說明示例性的實施，因而不該被視為是對其範圍的限制；可允許其他等效的實施。
圖1圖示說明基板之部分之示意性的橫截面圖，該基板具有各種根據本文所描述之實施而在該基板上形成的材料。
圖2圖示說明根據本文所描述之實施之在第一蝕刻處理後之基板之部分之示意性的橫截面圖。
圖3圖示說明根據本文所描述之實施之在保形地沉積硬光罩後之基板之部分之示意性的橫截面圖。
圖4圖示說明根據本文所描述之實施之在執行第二蝕刻處理後之基板之部分之示意性的橫截面圖。
為了助於理解，已盡可能地使用相同的元件符號，以指派圖式中共同的相同元素。預期一實施之元素及特徵可有利地併入至其他實施中而無須進一步的敘述。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
(請換頁單獨記載) 無
102‧‧‧基板
104‧‧‧材料層
106‧‧‧第一材料層
108‧‧‧第二材料層
110‧‧‧第一硬光罩
112‧‧‧第二硬光罩
202‧‧‧凹槽

Claims (20)

  1. 一種基板處理方法，包含以下步驟： 沉積一第一硬光罩於經設置於一基板上的一或多個材料層上；沉積一第二硬光罩於該第一硬光罩上； 圖案化該第二硬光罩；執行一第一蝕刻處理以蝕刻該第一硬光罩及該第二硬光罩；保形地沉積一第三硬光罩於該一或多個材料層、該第一硬光罩及該第二硬光罩上；及執行一第二蝕刻處理以蝕刻該一或多個材料層以形成溝槽於該一或多個材料層中。
  2. 如請求項1所述之方法，其中該一或多個材料層包含氮化矽材料及氧化矽材料。
  3. 如請求項1所述之方法，其中該氮化矽材料及該氧化矽材料經沉積於替代層中以形成一層堆疊。
  4. 如請求項3所述之方法，其中該層堆疊具有大於48個材料層。
  5. 如請求項1所述之方法，其中該第一硬光罩為一含碳材料。
  6. 如請求項5所述之方法，其中沉積該第一硬光罩至1 µm 與 2 µm之間的一厚度。
  7. 如請求項1所述之方法，其中該第二硬光罩為一介電材料。
  8. 如請求項7所述之方法，其中該介電材料為一含矽材料。
  9. 如請求項8所述之方法，其中該含矽材料為一二氧化矽材料、一氮化矽材料、一氮氧化矽材料或上述之結合。
  10. 如請求項7所述之方法，其中沉積該第二硬光罩至50 µm 與 200 µm之間的一厚度。
  11. 如請求項1所述之方法，其中該第一蝕刻處理為使用碳氟化合物先驅物的一電漿蝕刻處理。
  12. 如請求項1所述之方法，其中保形地沉積該第三硬光罩至5 nm 與 15 nm之間的一厚度。
  13. 如請求項1所述之方法，其中該第三硬光罩由一摻雜硼的碳質材料組成，該摻雜硼的碳質材料由大於25 wt%的硼及50 wt%的碳組成。
  14. 如請求項13所述之方法，其中該摻雜硼的碳質材料為一包括氮的碳氮化硼材料。
  15. 如請求項14所述之方法，其中自硼、碳及氮形成該碳氮化硼材料的至少80%。
  16. 如請求項15所述之方法，其中透過使用二甲胺基硼烷作為先驅物的熱化學氣相沉積處理來沉積該碳氮化硼材料。
  17. 一種基板處理方法，包含以下步驟： 沉積一第一硬光罩於經設置在一基板上的一或多個含氧及氮材料層上； 沉積一第二硬光罩於該第一硬光罩上； 執行一第一蝕刻處理以蝕刻該第一硬光罩及該第二硬光罩； 保形地沉積一碳氮化硼硬光罩於該一或多個含氧及氮材料層、該第一硬光罩及該第二硬光罩上；及 執行一第二蝕刻處理以蝕刻該一或多個含氧及氮材料層以形成溝槽於該一或多個含氧及氮材料層中，其中該第二蝕刻處理為使用由CH4 、N2 及O2 組成的群組所選出的先驅物及一富含氟的先驅物的一基於電漿的蝕刻處理。
  18. 如請求項17所述之方法，其中該第二蝕刻處理移除該第二硬光罩及該第三硬光罩。
  19. 一基板處理方法，包含以下步驟： 沉積一碳質硬光罩於經設置在一基板上的一或多個含氧及氮材料層上； 沉積一含矽的介電硬光罩於該碳質硬光罩上； 執行一第一蝕刻處理以蝕刻該碳質硬光罩及該含矽的介電硬光罩； 保形地沉積一碳氮化硼硬光罩於該一或多個含氧及氮材料層、該碳質硬光罩及該含矽的介電硬光罩上；及 執行一第二蝕刻處理以蝕刻該一或多個含氧及氮材料層以形成溝槽於該一或多個含氧及氮材料層中，其中該第二蝕刻處理為使用由CH4 、N2 及O2 組成的群組所選出的先驅物及一富含氟的先驅物的一基於電漿的蝕刻處理。
  20. 如請求項19所述之方法，其中在該第二蝕刻處理期間，該等含氧及氮材料層之一蝕刻速度比該碳氮化硼硬光罩的一蝕刻速度大3.5倍至4.0倍。
TW106100691A 2016-01-20 2017-01-10 基板處理方法 TWI726034B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662281046P 2016-01-20 2016-01-20
US62/281,046 2016-01-20

Publications (2)

Publication Number Publication Date
TW201736947A true TW201736947A (zh) 2017-10-16
TWI726034B TWI726034B (zh) 2021-05-01

Family

ID=59313885

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106100691A TWI726034B (zh) 2016-01-20 2017-01-10 基板處理方法

Country Status (6)

Country Link
US (2) US9991118B2 (zh)
JP (2) JP6907217B2 (zh)
KR (1) KR20180097763A (zh)
CN (2) CN108475640B (zh)
TW (1) TWI726034B (zh)
WO (1) WO2017127233A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI781678B (zh) * 2020-07-30 2022-10-21 日商芝浦機械電子裝置股份有限公司 基板處理方法及基板處理裝置
TWI806337B (zh) * 2021-01-08 2023-06-21 美商應用材料股份有限公司 低k碳氮化硼薄膜

Families Citing this family (77)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US9355922B2 (en) 2014-10-14 2016-05-31 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US11637002B2 (en) 2014-11-26 2023-04-25 Applied Materials, Inc. Methods and systems to enhance process uniformity
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US20160225652A1 (en) 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10790140B2 (en) * 2017-02-14 2020-09-29 Applied Materials, Inc. High deposition rate and high quality nitride
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US10497579B2 (en) 2017-05-31 2019-12-03 Applied Materials, Inc. Water-free etching methods
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10424487B2 (en) 2017-10-24 2019-09-24 Applied Materials, Inc. Atomic layer etching processes
US10283324B1 (en) * 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
TWI716818B (zh) 2018-02-28 2021-01-21 美商應用材料股份有限公司 形成氣隙的系統及方法
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
WO2019199822A2 (en) * 2018-04-10 2019-10-17 Applied Materials, Inc. Resolving spontaneous arcing during thick film deposition of high temperature amorphous carbon deposition
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US11437238B2 (en) 2018-07-09 2022-09-06 Applied Materials, Inc. Patterning scheme to improve EUV resist and hard mask selectivity
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
CN109545790B (zh) * 2018-11-02 2021-08-31 长江存储科技有限责任公司 三维存储器的沟道孔的形成方法
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes
KR20200143605A (ko) 2019-06-14 2020-12-24 삼성전자주식회사 열분해막을 이용한 반도체 소자의 제조 방법, 반도체 제조 장비 및 이를 이용하여 제조된 반도체 소자
US11658040B2 (en) 2019-06-26 2023-05-23 Hitachi High-Tech Corporation Plasma processing method
US11384428B2 (en) * 2019-07-19 2022-07-12 Applied Materials, Inc. Carbon layer covered mask in 3D applications
US11276573B2 (en) 2019-12-04 2022-03-15 Applied Materials, Inc. Methods of forming high boron-content hard mask materials
JP7370943B2 (ja) 2020-07-15 2023-10-30 Hoya株式会社 マスクブランク、転写用マスクの製造方法及び半導体デバイスの製造方法
US11715640B2 (en) * 2020-09-30 2023-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Patterning material including silicon-containing layer and method for semiconductor device fabrication
US20220102200A1 (en) * 2020-09-30 2022-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Patterning material including carbon-containing layer and method for semiconductor device fabrication
US20240014039A1 (en) * 2022-07-11 2024-01-11 Applied Materials, Inc. Carbon hardmask opening using boron nitride mask
WO2024091323A1 (en) * 2022-10-26 2024-05-02 Applied Materials, Inc. Aluminum oxide carbon hybrid hardmasks and methods for making the same

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11350110A (ja) * 1998-06-11 1999-12-21 Mitsubishi Heavy Ind Ltd 炭窒化ホウ素膜の製造方法
WO2001043176A1 (en) * 1999-12-08 2001-06-14 Samsung Electronics Co., Ltd. Semiconductor device having a self-aligned contact structure and methods of forming the same
US6774033B1 (en) * 2002-11-04 2004-08-10 Cypress Semiconductor Corporation Metal stack for local interconnect layer
US7144803B2 (en) * 2003-04-17 2006-12-05 Semiconductor Research Corporation Methods of forming boron carbo-nitride layers for integrated circuit devices
US6939794B2 (en) * 2003-06-17 2005-09-06 Micron Technology, Inc. Boron-doped amorphous carbon film for use as a hard etch mask during the formation of a semiconductor device
JP2005019054A (ja) * 2003-06-24 2005-01-20 Sony Corp 薄膜デバイス、薄膜デバイスの製造方法、液晶表示装置およびエレクトロルミネッセンス表示装置
US7105431B2 (en) 2003-08-22 2006-09-12 Micron Technology, Inc. Masking methods
US7052972B2 (en) 2003-12-19 2006-05-30 Micron Technology, Inc. Method for forming sublithographic features during the manufacture of a semiconductor device and a resulting in-process apparatus
US7829262B2 (en) * 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
KR100780944B1 (ko) * 2005-10-12 2007-12-03 삼성전자주식회사 탄소함유막 식각 방법 및 이를 이용한 반도체 소자의 제조방법
KR100801315B1 (ko) * 2006-09-29 2008-02-05 주식회사 하이닉스반도체 돌기형트랜지스터가 구비된 반도체소자의 제조 방법
US20100327413A1 (en) * 2007-05-03 2010-12-30 Lam Research Corporation Hardmask open and etch profile control with hardmask open
US7615447B2 (en) 2007-12-19 2009-11-10 Sandisk Corporation Composite charge storage structure formation in non-volatile memory using etch stop technologies
US20090286402A1 (en) * 2008-05-13 2009-11-19 Applied Materials, Inc Method for critical dimension shrink using conformal pecvd films
US8105465B2 (en) 2008-10-14 2012-01-31 Applied Materials, Inc. Method for depositing conformal amorphous carbon film by plasma-enhanced chemical vapor deposition (PECVD)
CN101800174A (zh) * 2010-02-11 2010-08-11 中微半导体设备(上海)有限公司 一种含碳层的等离子刻蚀方法
TW201216331A (en) 2010-10-05 2012-04-16 Applied Materials Inc Ultra high selectivity doped amorphous carbon strippable hardmask development and integration
US8778207B2 (en) * 2011-10-27 2014-07-15 Applied Materials, Inc. Plasma etch processes for boron-doped carbonaceous mask layers
KR20130075158A (ko) 2011-12-27 2013-07-05 삼성전자주식회사 반도체 소자의 제조 방법
US9396960B2 (en) 2012-11-01 2016-07-19 Tokyo Electron Limited Plasma processing method and plasma processing apparatus
US9129911B2 (en) * 2013-01-31 2015-09-08 Applied Materials, Inc. Boron-doped carbon-based hardmask etch processing
US8946076B2 (en) * 2013-03-15 2015-02-03 Micron Technology, Inc. Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells
JP6140575B2 (ja) * 2013-08-26 2017-05-31 東京エレクトロン株式会社 半導体装置の製造方法
US9296922B2 (en) * 2013-08-30 2016-03-29 Az Electronic Materials (Luxembourg) S.A.R.L. Stable metal compounds as hardmasks and filling materials, their compositions and methods of use
US20150118832A1 (en) * 2013-10-24 2015-04-30 Applied Materials, Inc. Methods for patterning a hardmask layer for an ion implantation process
US9418867B2 (en) * 2014-01-10 2016-08-16 Applied Materials, Inc. Mask passivation using plasma
JP6200849B2 (ja) * 2014-04-25 2017-09-20 株式会社日立ハイテクノロジーズ プラズマ処理装置およびドライエッチング方法
KR102171265B1 (ko) * 2014-07-08 2020-10-28 삼성전자 주식회사 금속 마스크를 이용한 패터닝 방법 및 그 패터닝 방법을 포함한 반도체 소자 제조방법
US10246772B2 (en) 2015-04-01 2019-04-02 Applied Materials, Inc. Plasma enhanced chemical vapor deposition of films for improved vertical etch performance in 3D NAND memory devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI781678B (zh) * 2020-07-30 2022-10-21 日商芝浦機械電子裝置股份有限公司 基板處理方法及基板處理裝置
TWI806337B (zh) * 2021-01-08 2023-06-21 美商應用材料股份有限公司 低k碳氮化硼薄膜

Also Published As

Publication number Publication date
TWI726034B (zh) 2021-05-01
JP6907217B2 (ja) 2021-07-21
JP2019503082A (ja) 2019-01-31
US20170207088A1 (en) 2017-07-20
US10410864B2 (en) 2019-09-10
JP2021177557A (ja) 2021-11-11
US20180277370A1 (en) 2018-09-27
CN108475640A (zh) 2018-08-31
JP7266068B2 (ja) 2023-04-27
KR20180097763A (ko) 2018-08-31
CN108475640B (zh) 2023-06-06
CN116631865A (zh) 2023-08-22
WO2017127233A1 (en) 2017-07-27
US9991118B2 (en) 2018-06-05

Similar Documents

Publication Publication Date Title
JP7266068B2 (ja) 横方向ハードマスク凹部縮小のためのハイブリッドカーボンハードマスク
US10954129B2 (en) Diamond-like carbon as mandrel
US9570303B2 (en) Conformal amorphous carbon for spacer and spacer protection applications
US10014174B2 (en) Conformal strippable carbon film for line-edge-roughness reduction for advanced patterning
TWI671795B (zh) 利用共形碳薄膜減低臨界尺寸之方法
CN102939641A (zh) 改良堆迭缺陷率的非晶碳沉积方法
US11495454B2 (en) Deposition of low-stress boron-containing layers
TW202212256A (zh) 低應力含碳層的沉積