TW201733076A - Semiconductor device and manufacturing method thereof capable of raising the production rate of semiconductor devices constituting a lower part of a PoP-type semiconductor device - Google Patents

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof, which raise the production rate of semiconductor devices constituting a lower part of a PoP-type semiconductor device. An upper surface of a wiring substrate (2) are disposed with a plurality of wires (4), welding leads (5) acting as ends of the wires (4), and pads acting as the other ends of the wires (4). The center of the wiring substrate (2) is mounted with a semiconductor chip (3). A soldering wire is used to electrically connect electrode pads (11) of the semiconductor chip (3) to the welding leads (5). Each pad (6) is provided thereon with a soldering ball (13). The upper surface of the wiring substrate (2) is provided thereon with sealing resin (14) which covers the semiconductor chip (3), the plurality of wires (4), welding wires (12), the soldering balls (13), etc. The sealing resin (14) is provided therein with a continuous slot (15) exposing the upper parts of the soldering balls (13). By electrically connecting the soldering balls (13) set on a lower side of a semiconductor device (1) with the soldering balls set on an upper side of the semiconductor device, a PoP-type semiconductor device is therefore fabricated.

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same.

In recent years, with the miniaturization and high functionality of electronic devices, further miniaturization and high integration of semiconductor devices used in electronic devices have been sought. In response to such a demand, development of a three-dimensionally mounted semiconductor device is being promoted in the packaging technology of a semiconductor package. For example, a (laminated type) semiconductor device called a package on package (PoP) in which a three-dimensional structure of a semiconductor package is laminated in a height direction is attracting attention.

In the present invention, the term "lamination" in the phrase "laminated with a semiconductor package" is used in the following sense. This meaning means a state in which these semiconductor packages are stacked in a state in which the connection terminals respectively provided in the plurality of semiconductor packages are electrically connected to each other. Moreover, suitably, "A and B are electrically connected" are simply referred to as "A and B are connected".

The PoP type semiconductor device is a laminated semiconductor device in which a lower semiconductor device (lower semiconductor package) and an upper semiconductor device (upper semiconductor package) are laminated. The PoP type semiconductor device is manufactured by electrically connecting a plurality of electrodes provided on a circuit board of a lower semiconductor device and a plurality of electrodes provided on the back surface of the upper semiconductor device by using a bonding member such as a solder ball.

As a laminated semiconductor device, a semiconductor element in which a sealing material is disposed on the upper surface of the lower semiconductor package to cover at least the upper surface of the wiring substrate on the lower side and a lower side is provided. The bumper electrode that is electrically connected to the semiconductor package of the semiconductor package and the semiconductor package of the upper side (omitted) can prevent a laminated semiconductor device with reduced reliability (for example, refer to paragraph [0011] of Patent Document 1 and FIG. 1 to image 3).

Patent Document 1: Japanese Patent Publication No. 2008-171904

However, the conventional laminate type semiconductor device disclosed in Patent Document 1 has the following problems. As shown in FIG. 1 to FIG. 3 of the patent document 1, the lower semiconductor package 1 includes a wiring board 2 and a pad portion 7 provided outside the semiconductor mounting portion on the upper surface of the wiring board 2. The upper semiconductor package 10 includes a wiring substrate 11 in which a substrate wiring is spread, a pad portion 13 provided on a lower surface of the wiring substrate 11 , and a bump electrode 14 bonded to the pad portion 13 . The tip end portion of the bump electrode 14 is bonded to the pad portion 7 of the lower semiconductor package 1 to electrically connect the semiconductor package 1 and the semiconductor package 10.

In such a laminate type semiconductor device, in order to electrically connect the lower semiconductor package 1 and the upper semiconductor package 10 by the bump electrodes 14, the bump electrodes 14 corresponding to the height of the lower semiconductor package 1 are required. the size of. This means that the size of the solder ball forming the bump electrode 14 is increased to the same level as the thickness of the semiconductor package 1 on the lower side. When the solder balls become large, it is necessary to increase the center-to-center spacing between adjacent solder balls and solder balls. When the interval between centers between adjacent solder balls becomes large, there arises a problem that the laminated type semiconductor device becomes large.

The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor device capable of miniaturizing a semiconductor device and a method of manufacturing the same.

In order to solve the above problems, the semiconductor device disclosed in the present invention includes:

Wiring substrate

a wafer component mounted on one side of the wiring substrate;

a plurality of connecting members electrically connecting a plurality of wafer electrodes formed on the wafer member and a plurality of substrate electrodes formed on one surface of the wiring substrate;

a plurality of external electrodes are formed on one surface of the wiring substrate and connected to the plurality of substrate electrodes to form a periphery of the wafer member;

a plurality of first protruding electrodes are respectively formed on the plurality of external electrodes;

a sealing resin formed on one surface of the wiring substrate covering at least the wafer member and the plurality of first protruding electrodes;

The opening is formed in the sealing resin to expose at least an upper portion of the plurality of first protruding electrodes.

In the semiconductor device disclosed in the present invention, the following aspects are also obtained:

The semiconductor device includes: a first protruding electrode group formed of a plurality of first protruding electrodes, surrounding a periphery of the wafer member in plan view;

The first protruding electrode group is formed in plural;

The plurality of first protruding electrode groups are formed in a plurality of shapes by surrounding the wafer members in plan view.

In the semiconductor device disclosed in the present invention, the following aspects are also obtained:

The opening is formed by any one of physical processing or chemical processing.

In the semiconductor device disclosed in the present invention, the following aspects are also obtained:

The opening is a continuous groove.

The invention further discloses a semiconductor device comprising:

The first semiconductor device is composed of the above-described semiconductor device, and the second semiconductor device has a plurality of the plurality of first semiconductor electrodes. Two protruding electrodes;

A plurality of first protruding electrodes and a plurality of second protruding electrodes are electrically connected, respectively.

In the semiconductor device disclosed in the present invention, the following aspects are also obtained:

The semiconductor device includes a filling material formed around a plurality of first protruding electrodes and a plurality of second protruding electrodes in the opening.

In order to solve the above problems, a method of fabricating a semiconductor device according to the present invention includes the following steps:

a step of preparing a wiring substrate having: one surface; a mounting region for mounting a wafer member having a plurality of wafer electrodes on one surface; and a plurality of substrate electrodes formed on one surface around the mounting region; And a plurality of external electrodes formed on one surface and connected to the plurality of substrate electrodes;

a step of mounting a wafer component in a mounting area;

a step of electrically connecting a plurality of wafer electrodes and a plurality of substrate electrodes;

a step of forming a plurality of first protruding electrodes on a plurality of external electrodes;

Forming a sealing resin covering at least the wafer member and the plurality of first protruding electrodes on one surface of the wiring substrate;

A step of forming an opening in the sealing resin for the purpose of exposing at least an upper portion of the plurality of first protruding electrodes.

In the method of fabricating the semiconductor device disclosed in the present invention, the method further has the following features:

In the step of preparing the wiring substrate, a wiring substrate having a first protruding electrode group is prepared, and the first protruding electrode group has the following features:

(1) The first protruding electrode group is formed of a plurality of first protruding electrodes, and surrounds the periphery of the wafer member in plan view;

(2) The first projecting electrode group is formed of a plurality of groups, and is formed in a plurality of layers by surrounding the wafer members in plan view.

In the method of fabricating the semiconductor device disclosed in the present invention, the method further has the following features:

In the step of forming the opening, the opening is formed by any one of physical processing or chemical processing.

In the method of fabricating the semiconductor device disclosed in the present invention, the method further has the following features:

In the step of forming the opening, a continuous groove is formed as an opening.

The present invention further discloses a method of fabricating a semiconductor device, comprising the steps of:

a step of preparing a first semiconductor device composed of a semiconductor device manufactured by the above-described method of manufacturing a semiconductor device;

a step of preparing a second semiconductor device having a plurality of second protruding electrodes formed at positions corresponding to the plurality of first protruding electrodes of the first semiconductor device;

a step of arranging the second semiconductor device by positioning the plurality of first protruding electrodes and the plurality of second protruding electrodes opposite to each other over the first semiconductor device;

a step of overlapping the first semiconductor device and the second semiconductor device;

A step of electrically connecting a plurality of first protruding electrodes and a plurality of second protruding electrodes.

In the method of fabricating the semiconductor device disclosed by the present invention, the method further has the following steps:

The method of fabricating a semiconductor device further includes the step of forming a filling material that fills a periphery of the plurality of first protruding electrodes and the plurality of second protruding electrodes in the opening of the first semiconductor device.

According to the invention, a semiconductor device includes: a wiring substrate; a plurality of external electrodes formed on one surface of the wiring substrate; a plurality of first protruding electrodes respectively formed on the plurality of external electrodes; and a sealing resin formed On one side of the wiring substrate, the wafer member and the plurality of first protruding electrodes are covered. An opening that exposes an upper portion of the first protruding electrode is formed in the sealing resin. In order to form the opening, the sealing resin is removed until the upper portion of the first protruding electrode is exposed. Thereby, first, since the upper portion of the first protruding electrode can be exposed, the upper end of the first protruding electrode can be provided at a position lower than the upper surface of the wafer member. Therefore, since the first protruding electrode can be miniaturized, the semiconductor device can be downsized. Second, the time to form the opening can be shortened. Therefore, the productivity at the time of producing a semiconductor device can be improved.

As shown in FIG. 1, a plurality of wirings 4, soldering leads 5 (such as substrate electrodes) corresponding to one end of the wiring 4, and pads 6 corresponding to the other end of the wiring 4 (such as external electrodes) are provided on the upper surface of the wiring board 2. ). The semiconductor wafer 3 is mounted on the central portion of the wiring board 2. The electrode pads 11 (such as wafer electrodes) of the semiconductor wafer 3 and the solder leads 5 are electrically connected using a bonding wire. Solder balls 13 (such as first protruding electrodes) are respectively disposed on the respective pads 6. A sealing resin 14 is provided on the upper surface of the wiring board 2, and the sealing resin 14 covers the semiconductor wafer 3, the plurality of wirings 4, the bonding wires 12, the solder balls 13, and the like. A continuous groove 15 (such as an opening) for exposing the upper portion of the solder ball 13 is provided in the sealing resin 14. A PoP type semiconductor device is manufactured by electrically connecting the solder balls 13 provided on the lower semiconductor device 1 and the solder balls provided on the upper semiconductor device.

(Example 1)

Embodiment 1 of the semiconductor device disclosed in the present invention will be described with reference to Figs. 1 to 2 . For the sake of easy understanding, any of the drawings in the present invention will be appropriately omitted or exaggerated and schematically depicted. The same components are denoted by the same reference numerals, and the description is omitted as appropriate.

The present invention is applied to both a semiconductor device and a PoP-type semiconductor device in the lower side of a semiconductor device constituting a PoP-type semiconductor device.

As shown in FIG. 1, a semiconductor device 1 (such as a first semiconductor device) is a semiconductor device on the lower side of a semiconductor device constituting a PoP-type semiconductor device. The semiconductor device 1 includes a wiring board 2 and a semiconductor wafer 3 mounted on the wiring board 2 . As the wiring board 2, for example, a printed board, a metal base board, a ceramic board, a film base board, or the like is used. On the upper surface of the wiring board 2, a wafer-shaped electronic component, that is, a semiconductor wafer 3 which is a type of wafer component, is mounted.

As the semiconductor wafer 3 (for example, a wafer component), a component for digital control such as a complementary metal oxide semiconductor (CMOS), a component for power, and the like are mounted. In the first embodiment, the semiconductor wafer 3 is mounted on the upper surface of the wiring substrate 2 so that the surface side of the semiconductor wafer 3 (the side on which one surface of the electrode pad is formed) faces upward. A plurality of wafer members (wafer-shaped electronic components) may be mounted on the upper surface of one wiring board 2, and a wafer component of a passive component may be included in a plurality of wafer components. The wafer component mounted on the upper surface of the wiring board 2 is the same in other embodiments.

As shown in FIG. 1(b), on the upper surface of the wiring board 2 (one surface on which the semiconductor wafer 3 is mounted), a plurality of wirings 4 are provided corresponding to the product. As a material of the wiring 4, copper (Cu) or the like having a small electrical resistivity is preferably used. As shown on the right side of FIG. 1(b), one end (inside) of the plurality of wirings 4 constitutes a soldering lead 5 connected to the semiconductor wafer 3. The other end (outer side) of the plurality of wirings 4 constitutes a pad 6 corresponding to a connection electrode connected to the upper semiconductor device (refer to FIG. 3). Each of the pads 6 is provided to surround the periphery of the semiconductor wafer 3. In FIG. 1, for the sake of convenience, 24 pads 6 are provided around the semiconductor wafer 3. The solder leads 5 and the pads 6 are preferably arranged such that the wiring length on the wiring board 2 is the shortest.

On the lower surface (the other surface) of the wiring board 2, a pad 7 corresponding to an external electrode electrically connected to an external device is provided. The plurality of wirings 4 provided on the upper surface of the wiring board 2 are connected to the pads 7 via via wirings 8 and internal wirings (not shown) provided inside the wiring board 2. The pad 7 is provided in a grid-like manner on the lower surface of the wiring substrate 2.

In a region other than the surfaces of the bonding wires 5 and the pads 6 of the upper surface of the wiring substrate 2, a solder resist film 9 for protecting a plurality of wirings 4 is provided. The solder resist film 9 is an insulating resin film. The semiconductor wafer 3 is mounted on the solder resist film 9 formed on the central portion of the wiring substrate 2 by the adhesive 10 . On the surface side of the semiconductor wafer 3, a plurality of electrode pads 11 are provided around the semiconductor wafer 3. The plurality of electrode pads 11 are electrically connected to the solder leads 5 via bonding wires 12 (such as connecting members) made of gold wires, copper wires, or the like.

On the wiring substrate 2, solder balls 13 (such as protruding electrodes) are respectively provided on the respective pads 6 which are not covered by the solder resist film 9. The solder ball 13 is a connection terminal for connecting the semiconductor device on the upper side (refer to FIG. 3). A thin layer of flux exists between each of the pads 6 and each of the solder balls 13. The flux has a function of activating the surface of the pad 6 and the surface of the solder ball 13, and a function of temporarily fixing the solder ball 13 to the pad 6 by an adhesive force.

The solder ball 13 is made of, for example, a tin (Sn) element or a Sn alloy obtained by adding a small amount of bismuth (Bi), zinc (Zn), silver (Ag), copper (Cu) or the like to Sn or after adding a plurality of the above metals. The obtained Sn alloy or the like is composed. The material of the solder ball 13 is preferably lead-free solder. As the protruding electrode, instead of the solder ball 13, a bump formed by, for example, plating, wire bonding, or the like can be used. In this regard, the same is true in other embodiments.

In the first embodiment, the size of the solder ball 13 is set to a height which is approximately half of the height of the sealing resin 14 of the semiconductor device 1. The upper end position of the solder ball 13 is preferably set to a position lower than the upper surface of the wafer member. In this regard, the same is true in other embodiments.

A sealing resin 14 is provided on the upper surface of the wiring board 2 to cover the semiconductor wafer 3, the plurality of wirings 4, the bonding wires 12, the solder resist film 9, and the solder balls 13. As the sealing resin 14, for example, a thermosetting epoxy resin or an fluorenone resin is used.

As shown in FIG. 1(a), a continuous groove 15 (opening) is formed in the sealing resin 14 so that the upper portion of the solder ball 13 is exposed from the sealing resin 14. In order to connect the semiconductor device 1 and the upper semiconductor device (refer to FIG. 3), the upper portion of the solder ball 13 is exposed from the sealing resin 14. The continuous groove 15 is provided around the semiconductor device 1 so as to overlap the solder ball 13 in plan view. In the case of (a) of FIG. 1, as shown by a broken line, a continuous groove 15 reaching the side surface (outer peripheral surface) of the sealing resin 14 can be formed. Thereby, the opening OP is formed in the side surface of the sealing resin 14. It is also possible to form the continuous groove 15 reaching the side surface of the sealing resin 14, which is the same in other embodiments.

A solder resist film 16 is provided in a region other than the surface of each of the pads 7 on the lower surface of the wiring substrate 2. Solder balls 17 are provided on the respective pads 7 via a flux layer. The solder ball 17 corresponds to an external terminal that is connected to an external device in the PoP type semiconductor device.

The process of manufacturing the semiconductor device 1 as the lower semiconductor device in the PoP type semiconductor device will be described with reference to FIG. First, as shown in FIG. 2(a), the wiring board 2 corresponding to the lower semiconductor device 1 is prepared in advance. A wiring 4 made of Cu having the bonding wires 5 and the pads 6 is formed on the upper surface of the wiring substrate 2. The wiring 4 is connected to the pad 7 on the lower surface of the wiring board 2 via the via wiring 8 and the internal wiring (not shown) formed inside the wiring board 2. A plating layer (not shown) is formed on the surfaces of the wiring 4, the bonding leads 5, the pads 6, and the pads 7 by a plating process. The plating layer is preferably a lead-free plating layer.

Next, a solder resist film 9 as an insulating resin film is formed on the surface of the wiring board 2. The solder resist film 9 formed in the regions of the solder leads 5 and the pads 6 is removed by photolithography. By the steps up to here, openings are formed in the solder leads 5 and the pads 6, and the surface layer (Cu or plating layer) of the wiring 4 is exposed. Next, the photoresist film for solder bumps is patterned to open the region of the pad 6. Next, for example, the solder balls 13 are implanted, and the solder balls 13 are mounted on the respective pads 6 via the flux layer.

Next, a reflow process is performed in a nitrogen atmosphere to melt the solder ball 13 and bond it to the pad 6. Thereafter, the photoresist film for the solder bumps is removed.

Then, as shown in FIG. 2(b), for example, the semiconductor wafer 3 is mounted on the center portion of the wiring board 2 so that the surface side of the semiconductor wafer 3 faces upward by using a wafer bonding machine. Next, each of the electrode pads 11 provided on the surface side of the semiconductor wafer 3 and the respective solder leads 5 provided on the wiring substrate 2 are electrically connected via a bonding wire 12 using a wire bonder. In order to prevent the bonding wires 12 from coming into contact with the corner portions of the semiconductor wafer 3, the bonding wires 12 are formed in such a manner that the bonding wires 12 form a loop shape.

Next, as shown in FIG. 2(c), the sealing resin 14 is molded on the wiring board 2, for example, using a resin molding apparatus using a transfer molding method or a compression molding method. By the steps up to this point, the upper surface of the wiring substrate 2 including the semiconductor wafer 3, the wiring 4, the bonding wires 12, the solder resist film 9, the solder balls 13, and the like is covered with the sealing resin 14.

Next, as shown in FIG. 2(d), a solder resist film 16 is formed on the lower surface of the wiring substrate 2. The solder resist film 16 formed in the region of the pad 7 is removed by photolithography. Next, the photoresist film for the solder bump is patterned to open the region of the pad 7. Next, the solder balls 17 are implanted, and the solder balls 17 are collectively mounted on the pads 7. Next, a reflow process is performed to melt the solder ball 17 and bond it to the pad 7. Further, after the step of forming the solder balls 13 on the upper surface of the wiring substrate 2 shown in (a) of FIG. 2, the solder balls 17 formed on the lower surface of the wiring substrate 2 shown in (d) of FIG. 2 may be formed. A step of.

Next, as shown in FIG. 2(e), in the semiconductor device 1, a continuous groove 15 (opening) is formed in the sealing resin 14 so that at least an upper portion of the solder ball 13 is exposed from the sealing resin 14. The continuous groove 15 is formed around the semiconductor device 1 so as to overlap the plurality of solder balls 13 in plan view (refer to (a) of FIG. 1). For example, a continuous groove 15 is formed in the sealing resin 14 by physical processing such as laser, rotary blade, grinding abrasive, or ion beam. It is also possible to form the continuous groove 15 in the sealing resin 14 by chemical processing such as etching. By the steps up to this point, the semiconductor device 1 as the semiconductor device constituting the lower side of the PoP type semiconductor device is completed.

According to the present embodiment, in the semiconductor device 1 constituting the lower side of the PoP type semiconductor device, a continuous groove 15 (opening) is formed in the upper portion of the sealing resin 14 to expose the upper portion of the solder ball 13. The continuous groove 15 is formed by removing the sealing resin 14 having a thickness of about half of the thickness of the sealing resin 14 of the semiconductor device 1. According to this, the opening can be formed shallower. Therefore, the man-hour for forming the continuous groove 15 can be shortened. Thereby, the productivity at the time of producing the semiconductor device 1 which is a semiconductor device of the lower side of a PoP type semiconductor device can be improved.

Moreover, since four continuous grooves 15 are continuously formed on the solder balls 13, the number of man-hours for forming the openings can be shortened. Therefore, the productivity at the time of producing the semiconductor device 1 as the semiconductor device of the lower side of the PoP type semiconductor device can be improved.

The following modifications can also be employed. In the first modification, instead of forming the continuous grooves 15 on the solder balls 13, separate openings are formed in the sealing resin 14 on each of the solder balls 13 by using laser, grinding abrasive grains, ion beams, etching, or the like. As these separate openings, in the lower left portion in (a) of Fig. 1, three openings H are shown by broken lines for convenience. When a plurality of individual openings are collectively formed in the sealing resin 14 by etching, the man-hour for forming the opening can be shortened.

In the second modification, the upper surface of the sealing resin 14 is polished (including grinding, the same applies hereinafter) from the state shown in FIG. 1(b) (which may be the state before the solder ball 17 is formed). In (b) of FIG. 1, the upper surface of the sealing resin 14 after polishing is shown by a broken line. For the grinding, abrasive grains, grinding wheels, and the like are used. The polishing is preferably performed while controlling or measuring the thickness of the polishing to prevent the wire 12 having the loop shape from being exposed. By polishing the upper surface of the sealing resin 14, first, the man-hour for performing the opening can be shortened. Second, the thickness of the PoP-type semiconductor device (refer to (c) of FIG. 5) can be reduced. The upper surface of the sealing resin 14 included in the lower semiconductor device may be polished, and the same applies to the other embodiments.

(Example 2)

Embodiment 2 of the semiconductor device disclosed in the present invention will be described with reference to Figs. 3 to 5 . In the second embodiment and the third embodiment, the same components as those in the first embodiment or the portions having the same functions as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be appropriately omitted. For the portions having different structures and functions from Embodiment 1, additional symbols are given.

As shown in FIG. 3, the semiconductor device 18 (such as the second semiconductor device) is a semiconductor device constituting the upper side of the PoP type semiconductor device. The semiconductor device 18 includes a wiring substrate 19 and a semiconductor wafer 20 mounted on the wiring substrate 19. As the semiconductor wafer 20, a dynamic random access memory (DRAM), a flash memory, a logic component, an analog component, a micro electro mechanical system (MEMS), a sensor, etc. are mounted. The wafer component, and the components obtained by stacking the wafer components in the vertical direction or in the horizontal direction. The semiconductor wafer 20 is mounted on the wiring board 19 with the front side facing upward.

As shown in FIG. 3(b), a plurality of wirings 4 are provided on the upper surface of the wiring board 19. Solder leads 5 connected to the semiconductor wafer 20 are provided at one end (inner side) of the plurality of wirings 4. The other end (outer side) of the plurality of wirings 4 is connected to the pads 21 provided on the lower surface of the wiring board 19 via via wirings 8 and internal wirings (not shown) provided inside the wiring board 19. The pad 21 provided on the upper semiconductor device 18 is a connection electrode connected to the lower semiconductor device 1 (refer to FIG. 1). On the lower surface of the wiring board 19, each of the pads 21 is provided at a position corresponding to each of the pads 6 provided on the wiring board 2 of the semiconductor device 1 on the lower side.

A solder resist film 9 is provided in a region other than the surface of the bonding lead 5 on the upper surface of the wiring substrate 19. The semiconductor wafer 20 is mounted on the solder resist film 9 formed on the central portion of the wiring substrate 19 by the adhesive 10 . On the surface side of the semiconductor wafer 20, a plurality of electrode pads 11 are provided around the semiconductor wafer 20. A plurality of electrode pads 11 are electrically connected to the solder leads 5 via bonding wires 12, respectively.

A sealing resin 14 is provided on the upper surface of the wiring substrate 19 to cover the semiconductor wafer 20, the plurality of wirings 4, the bonding wires 12, and the solder resist film 9.

A solder resist film 16 is provided in a region other than the surface of each of the pads 21 on the lower surface of the wiring substrate 19. Solder balls 22 (e.g., second protruding electrodes) are provided on the respective pads 21 via a flux layer. The solder ball 22 corresponds to a connection terminal that is connected to the lower semiconductor device 1 (refer to FIG. 1). In the second embodiment, the size of the solder ball 22 is set to a height which is approximately half of the height of the sealing resin of the semiconductor device 1 on the lower side. Accordingly, the size of the solder balls 13 provided on the lower semiconductor device 1 is substantially the same as the size of the solder balls 22 provided on the upper semiconductor device 18.

A process for manufacturing the semiconductor device 18 as the upper semiconductor device in the PoP type semiconductor device will be described with reference to FIG. First, as shown in FIG. 4(a), the wiring board 19 corresponding to the upper semiconductor device 18 is prepared in advance. A wiring 4 made of Cu having soldered leads 5 is formed on the upper surface of the wiring board 19. The wiring 4 is connected to the pad 21 on the lower surface of the wiring substrate 19 via the via wiring 8 and the internal wiring (not shown) formed inside the wiring substrate 19. A lead-free plating layer (not shown) is formed on the surface of the wiring 4, the bonding leads 5, and the pads 21 by plating.

Next, a solder resist film 9 is formed on the surface of the wiring substrate 19. The solder resist film 9 formed in the region of the soldered lead 5 is removed by photolithography. By the steps up to this point, an opening is formed in the soldering lead 5, and the surface layer (plating layer) of the bonding lead 5 is exposed.

Next, as shown in FIG. 4(b), the semiconductor wafer 20 is mounted on the central portion of the wiring substrate 19 so that the surface side of the semiconductor wafer 20 faces upward by using a wafer bonding machine. Next, the electrode pad 11 provided on the surface side of the semiconductor wafer 20 is connected to the soldering lead 5 provided on the wiring substrate 19 by using a wire bonder and using the bonding wire 12. The bonding wires 12 are formed in such a manner that the bonding wires 12 form a loop shape.

Next, as shown in FIG. 4(c), the sealing resin 14 is molded on the wiring substrate 19 by using a resin molding apparatus using a transfer molding method or a compression molding method. By the steps up to here, the upper surface of the wiring substrate 19 including the semiconductor wafer 20, the wiring 4, the bonding wires 12, the solder resist film 9, and the like is covered with the sealing resin 14.

Next, as shown in FIG. 4(d), a solder resist film 16 is formed on the lower surface of the wiring substrate 19. The solder resist film 16 formed in the region of the pad 21 is removed by photolithography. Next, the photoresist film for the solder bump is patterned to open the region of the pad 21. Next, the solder balls 22 are implanted, and the solder balls 22 are collectively mounted on the pads 21. Next, a reflow process is performed to melt the solder balls 22 and bond them to the pads 21. Thereafter, the photoresist film for the solder bumps is removed. By the steps up to this point, the semiconductor device 18 which is the upper semiconductor device constituting the PoP type semiconductor device is completed.

Referring to Fig. 5, a process of manufacturing a PoP type semiconductor device by laminating a semiconductor device 1 as a semiconductor device on the lower side and a semiconductor device 18 as a semiconductor device on the upper side will be described. First, as shown in FIG. 5(a), the upper semiconductor device 18 is moved above the lower semiconductor device 1 and aligned. A plurality of solder balls 22, which are connection terminals provided on the lower surface of the wiring board 19 of the upper semiconductor device 18, and a plurality of solder balls 13 which are provided on the upper surface of the wiring board 2 of the lower semiconductor device 1 Position the position.

Next, as shown in FIG. 5(b), the upper semiconductor device 18 is lowered, and the upper semiconductor device 18 is superposed on the lower semiconductor device 1. By the steps up to this point, a plurality of solder balls 22 provided on the upper semiconductor device 18 are inserted into the continuous grooves 15 provided in the lower semiconductor device 1. The solder balls 13 provided on the lower semiconductor device 1 and the solder balls 22 provided on the upper semiconductor device 18 have approximately half the height of the sealing resin 14 of the lower semiconductor device 1. Therefore, in the continuous groove 15 of the lower semiconductor device 1, the lower solder ball 13 is in contact with the upper solder ball 22.

Next, as shown in FIG. 5(c), the semiconductor device 1 on the lower side and the semiconductor device 18 on the upper side are superposed in a nitrogen atmosphere. By performing the reflow process, the lower solder ball 13 and the upper solder ball 22 are melted and joined to each other. Accordingly, the solder ball 13 and the solder ball 22 are connected to each other between the pad 6 of the lower semiconductor device 1 and the pad 21 of the upper semiconductor device 18. The solder ball 13 and the solder ball 22 are laminated with the semiconductor device 1 on the lower side and the semiconductor device 18 on the upper side. The PoP type semiconductor device 23 can be manufactured by the steps up to this point.

According to the present embodiment, the semiconductor device 1 on the lower side and the semiconductor device on the upper side are laminated by electrically connecting the solder balls 13 provided on the lower semiconductor device 1 and the solder balls 22 provided on the upper semiconductor device 18. 18. Therefore, the size of the upper solder ball 22 and the lower side can be compared with the case where the semiconductor device on the lower side is laminated only by the solder ball provided on the upper semiconductor device as compared with the case of the upper semiconductor device. The diameter of both of the sizes of the solder balls 13 is set to about half. Specifically, both the size of the solder ball 13 and the size of the solder ball 22 are set to be approximately half the height of the sealing resin 14 provided on the lower semiconductor device 1. According to this, it is possible to reduce both the center-to-center spacing between adjacent solder balls 13 and the center-to-center spacing between adjacent solder balls 22. In the PoP type semiconductor device 23, even when the number of the solder balls 13 and 22 is extremely large, the small-diameter solder balls 13 and 22 can be disposed at a small center-to-center interval. Therefore, the PoP type semiconductor device 23 can be miniaturized.

According to the present embodiment, the open continuous groove 15 can be formed shallowly. According to this, the man-hour for forming the opening can be shortened. Therefore, the productivity at the time of producing the semiconductor device 1 as the semiconductor device of the lower side of the PoP type semiconductor device can be improved.

According to the present embodiment, since four continuous grooves 15 are continuously formed on the solder balls 13, the number of man-hours for forming the openings can be shortened. Therefore, the productivity at the time of producing the semiconductor device 1 as the semiconductor device of the lower side of the PoP type semiconductor device can be improved.

According to the present embodiment, a plurality of solder balls 22 provided on the upper semiconductor device 18 are inserted into the continuous grooves 15 provided on the lower semiconductor device 1. According to this, it is possible to easily perform the alignment when the upper semiconductor device 18 is stacked on the lower semiconductor device 1. Therefore, the productivity at the time of producing the PoP type semiconductor device 23 can be improved.

(Example 3)

Embodiment 3 of the semiconductor device disclosed in the present invention will be described with reference to Figs. 6 to 8 . As shown in FIG. 6, the semiconductor device 24 (such as the first semiconductor device) is a semiconductor device constituting the lower side of the PoP-type semiconductor device. The semiconductor device 24 includes a wiring substrate 25 and a semiconductor wafer 26 mounted on the wiring substrate 25. In the third embodiment, the surface side of the semiconductor wafer 26 (such as a wafer member) (the side on which the electrode pad 11 is formed) is mounted on the wiring board 25 (surface-down mounting). The semiconductor wafer 26 is flip-chip mounted on the wiring substrate 25 using bumps 27 (such as connecting members).

As shown in FIG. 6(b), a plurality of wirings 4 are provided on the upper surface of the wiring board 25. One end (inner side) of the plurality of wirings 4 constitutes a substrate electrode 28 that is connected to the electrode pads 11 of the semiconductor wafer 26 via the bumps 27. The other end (outer side) of the plurality of wirings 4 constitutes a pad 6 corresponding to a connection electrode connected to the upper semiconductor device (refer to FIG. 7). In Embodiment 3, each of the pads 6 is provided in a double shape so as to surround the periphery of the semiconductor wafer 26. In FIG. 6, 32 pads 6 are provided on the outermost periphery of the semiconductor wafer 26, and 24 pads 6 are provided inside, and a total of 56 pads 6 are provided on the wiring substrate 25. Not limited to this, the pads 6 surrounding the periphery of the semiconductor wafer 26 may be set to be three or more.

A pad 7 corresponding to an external electrode electrically connected to an external device is provided on the lower surface of the wiring substrate 25. The plurality of wirings 4 provided on the upper surface of the wiring board 25 are connected to the respective pads 7 via via wirings 8 and internal wirings (not shown) provided inside the wiring substrate 25. The pad 7 is provided in a mesh shape on the lower surface of the wiring substrate 25.

A solder resist film 9 is provided in a region other than the surfaces of the substrate electrode 28 and the pad 6 on the upper surface of the wiring substrate 25. Each of the substrate electrodes 28 is connected to each of the electrode pads 11 provided on the semiconductor wafer 26 via the bumps 27. Solder balls 13 (first protruding electrodes) are provided on the respective pads 6 . The solder ball 13 is a connection terminal for connection to the upper semiconductor device (refer to FIG. 7). The solder balls 13 are set to double in such a manner as to surround the periphery of the semiconductor wafer 26 in such a manner that the pads 6 are disposed to double around the periphery of the semiconductor wafer 26.

A sealing resin 14 is provided on the upper surface of the wiring board 25 to cover the semiconductor wafer 26, the plurality of wirings 4, the substrate electrodes 28, the solder resist film 9, and the solder balls 13. In the third embodiment, the semiconductor wafer 26 is flip-chip mounted on the wiring substrate 25 by using the bumps 27. In the present embodiment, the bonding wire is not used as compared with the case where the bonding wire is used in the embodiment 1. Thereby, the height of the sealing resin 14 which resin-seals the semiconductor wafer 26 can be reduced. Therefore, the size of the solder ball 13 can be reduced. In this case, the size of the solder ball 13 is also set to a height which is approximately half of the height of the sealing resin 14 constituting the semiconductor device 24.

As shown in (b) of FIG. 6, the respective bumps 27 connecting the semiconductor wafer 26 and the substrate electrode 28 are also filled with the sealing resin 14. Without being limited thereto, the underfill (sealing material) may be previously flowed between the semiconductor wafer 26 and the substrate electrode 28 to electrically insulate the bumps 27 in advance.

As shown in FIG. 6(a), in order to laminate the semiconductor device 24 as the lower semiconductor device and the upper semiconductor device, it is necessary to expose the upper portion of the solder ball 13. In order to expose the upper portion of the solder ball 13, continuous grooves 15a, 15b (e.g., openings) are provided in the sealing resin 14, respectively. Each of the continuous grooves 15a and 15b is provided in a double shape around the semiconductor wafer 26 so as to overlap the solder ball 13 in plan view.

A solder resist film 16 is provided in a region other than the surface of each of the pads 7 on the lower surface of the wiring substrate 25. Solder balls 17 corresponding to external terminals of a PoP type semiconductor device electrically connected to an external device are provided on each of the pads 7.

As shown in FIG. 7, the semiconductor device 29 (such as the second semiconductor device) is a semiconductor device constituting the upper side of the PoP type semiconductor device. The semiconductor device 29 includes a wiring board 30 and a semiconductor wafer 31 mounted on the wiring board 30. As the semiconductor wafer 31, a wafer component on which a DRAM, a flash memory, a logic component, an analog component, a MEMS, a sensor, or the like is mounted, and which are obtained by stacking these wafer components in a vertical direction or in a horizontal direction are used. Components, etc. The semiconductor wafer 31 is mounted on the wiring board 30 with the front side facing downward. The semiconductor wafer 31 is flip-chip mounted on the wiring substrate 30 via the bumps 27.

As shown in FIG. 7(b), a plurality of wirings 4 are provided on the upper surface of the wiring board 30. One end (inside) of the plurality of wirings 4 constitutes the substrate electrode 28. The substrate electrode 28 is connected to the electrode pad 11 of the semiconductor wafer 31 via the bump 27 . The other end (outer side) of the plurality of wirings 4 is connected to the pads 21 provided on the lower surface of the wiring board 30 via via wirings 8 and internal wirings (not shown) provided inside the wiring board 30, respectively. The pad 21 provided on the upper semiconductor device 29 is a connection electrode connected to the lower semiconductor device 24 (refer to FIG. 6). Each of the pads 21 is provided in a double shape so as to surround the periphery of the semiconductor wafer 31. On the lower surface of the wiring substrate 30, each of the pads 21 is provided at a position corresponding to each of the pads 6 provided on the wiring substrate 25 of the semiconductor device 24 on the lower side.

A solder resist film 16 is provided in a region other than the surface of each of the pads 21 on the lower surface of the wiring substrate 30. Solder balls 22 corresponding to connection terminals connected to the lower semiconductor device 24 (refer to FIG. 6) are provided on the respective pads 21, respectively. In the third embodiment, the size of the solder ball 22 is set to a height which is approximately half of the height of the sealing resin of the semiconductor device 24 on the lower side. Therefore, the size of the solder balls 13 provided on the lower semiconductor device 24 and the size of the solder balls 22 provided on the upper semiconductor device 29 are substantially the same size.

A sealing resin 14 is provided on the upper surface of the wiring substrate 30 to cover the semiconductor wafer 31, the plurality of wirings 4, the substrate electrodes 28, and the solder resist film 9.

Referring to Fig. 8, a process of manufacturing a PoP type semiconductor device by laminating a semiconductor device 24 as a semiconductor device on the lower side and a semiconductor device 29 as a semiconductor device on the upper side will be described. First, as shown in FIG. 8(a), the upper semiconductor device 29 is moved above the lower semiconductor device 25 and aligned. The plurality of solder balls 22 provided on the outermost circumference of the upper semiconductor device 29 are aligned with the positions of the plurality of solder balls 13 provided on the outermost periphery of the lower semiconductor device 24, respectively. Similarly, the plurality of solder balls 22 provided on the innermost periphery of the upper semiconductor device 29 are aligned with the positions of the plurality of solder balls 13 provided on the innermost periphery of the lower semiconductor device 24, respectively.

Next, as shown in FIG. 8(b), the upper semiconductor device 18 is lowered, and the upper semiconductor device 29 is superposed on the lower semiconductor device 25. By the steps up to this point, a plurality of solder balls 22 provided on the upper semiconductor device 29 are inserted into the continuous grooves 15a and 15b provided in the lower semiconductor device 24, respectively. The solder balls 13 provided on the lower semiconductor device 24 and the solder balls 22 provided on the upper semiconductor device 29 have approximately half the height of the sealing resin 14 of the lower semiconductor device 24. Therefore, in the continuous grooves 15a and 15b of the lower semiconductor device 24, the lower solder balls 13 are in contact with the upper solder balls 2.

Next, the semiconductor device 24 on the lower side and the semiconductor device 29 on the upper side are subjected to a reflow process in a nitrogen atmosphere. By performing the reflow process, the lower solder ball 13 and the upper solder ball 22 are melted and joined to each other. Accordingly, the pad 6 of the lower semiconductor device 24 and the pad 21 of the upper semiconductor device 29 are connected via the solder ball 13 and the solder ball 22. The lower semiconductor device 24 and the upper semiconductor device 29 are laminated via solder balls 13 and solder balls 22. The PoP type semiconductor device 32 can be manufactured by the steps up to this point.

According to the present embodiment, in the semiconductor devices 24, 29, the semiconductor wafers 26, 31 are flip-chip mounted on the wiring substrates 25, 30, respectively, using the bumps 27. According to this, it is not necessary to form a loop shape for preventing the wire from being short-circuited as compared with the case of using the bonding wire. Therefore, the height of the sealing resin 14 can be made small, so that the size of the solder balls 13 and the solder balls 22 can be reduced. According to this, it is possible to reduce both the center-to-center spacing between adjacent solder balls 13 and the center-to-center spacing between adjacent solder balls 22. In the PoP type semiconductor device 23, even when the number of the solder balls 13 and 22 is extremely large, the small-diameter solder balls 13 and 22 can be disposed at a small center-to-center interval. Therefore, the PoP type semiconductor device 23 can be miniaturized.

The following modifications can also be employed. In the first modification, in addition to polishing from the state shown in FIG. 6(b), the upper surface of the sealing resin 14 is polished, and the upper surface of the semiconductor wafer 26 is polished. In this case, the semiconductor wafer 26 can be polished until the thickness of the semiconductor wafer 26 is not hindered. In (b) of FIG. 6, the upper surface of the polished semiconductor device 24 is shown by a broken line. Therefore, the thickness of the PoP type semiconductor device 24 can be further reduced. Further, the number of man-hours for forming the continuous grooves 15a and 15b in the sealing resin 14 can be reduced.

In the second modification, instead of forming the continuous grooves 15a and 15b in the sealing resin 14, the upper surface of the sealing resin 14 and the upper surface of the semiconductor wafer 26 may be sequentially polished until the upper portion of the solder ball 13 is exposed. In this case, the step of sequentially polishing the upper surface of the sealing resin 14 and the upper surface of the semiconductor wafer 26 corresponds to a step of forming an opening in the sealing resin 14 for the purpose of exposing the upper portion of the solder ball 13.

According to each of the embodiments described so far, a plurality of solder balls 22 provided on the upper semiconductor device are inserted into the continuous grooves provided in the lower semiconductor device, and then the reflow process is performed. Accordingly, the lower solder ball 13 and the upper solder ball 22 are electrically connected. The PoP type semiconductor device 32 can be manufactured by the steps up to this point.

The following modifications can also be employed. First, a predetermined amount of resin material is supplied to a continuous groove provided on the lower semiconductor device immediately before the lower semiconductor device and the upper semiconductor device are laminated. As the resin material, a solid shape resin or a semi-solid shape resin such as a pellet, a powder, a paste or a gel is used. As the resin material, a liquid resin (a resin which is liquid at normal temperature) can also be used. In the case of a solid-shaped resin or a semi-solid shape resin, it is preferred that in the step of performing the reflow process, the fluid resin easily flows in a state where the resin material is melted to form a fluid resin. In the case of a liquid resin, it is preferred to easily flow at a temperature at which the reflow process is performed. As the resin material, any of a thermosetting resin and a thermoplastic resin can also be used.

Next, a plurality of solder balls 22 provided on the upper semiconductor device are inserted into the continuous grooves provided on the lower semiconductor device. The resin material is extruded around the solder balls 22 by inserting the solder balls 22 into the continuous grooves. In this state, the reflow process is performed.

In the reflow processing step, the lower solder ball 13 and the upper solder ball 22 are melted and joined, and the resin material is melted to form a fluid resin. Accordingly, the space around the solder balls 13 and the solder balls 22 is filled with a fluid resin. In the space around the solder balls 13, 22, the fluid resin is cured. Thereby, the space around the solder ball 13 on the lower side and the solder ball 22 on the upper side is filled by the cured resin. Therefore, the solder balls 13 and the solder balls 22 can be insulated from the surroundings. According to this, first, it is possible to prevent moisture or the like from entering the periphery of the solder ball 13 on the lower side and the solder ball 22 on the upper side from the outside of the PoP type semiconductor device. Second, the mechanical strength of the PoP type semiconductor device is improved. Therefore, the reliability of the PoP type semiconductor device can be improved.

The following other modifications can also be employed. After laminating the semiconductor device on the lower side and the semiconductor device on the upper side, a predetermined amount of the resin material is supplied into the continuous groove provided on the lower semiconductor device. In this case, in the step of forming the continuous groove 15 (refer to (a) of FIG. 1) and the continuous groove 15a (refer to (a) of FIG. 6), the continuous groove 15 which reaches each outer peripheral surface of the sealing resin 14 is formed. And a continuous groove 15a. Thereby, an opening portion is formed on the side surface (outer peripheral surface) of the sealing resin 14. In a state in which the lower solder ball 13 and the upper solder ball 22 are joined (refer to FIG. 5( b )), the resin material is injected from the outside of the sealing resin 14 into the continuous groove through the opening. For example, a liquid resin is injected into a continuous tank using a dispenser. In this case, it is preferable to suck the inside of the continuous groove 15 and the continuous groove 15a from the opening on the side opposite to the opening into which the liquid resin is injected. According to this, the liquid resin can be filled into the inside of the continuous groove 15 and the continuous groove 15a in a short time. The width of the groove is preferably enlarged to form the continuous groove 15 and the continuous groove 15a as compared with the case where the resin material is not supplied into the continuous groove.

Further, regarding the PoP type semiconductor device, there are two modes in which the semiconductor device is shipped. The first embodiment is a method of laminating a laminated semiconductor device (a semiconductor device functioning as a final product) in which a lower semiconductor device and an upper semiconductor device are laminated. The second mode is a method in which only the lower semiconductor device is shipped as a semi-finished product. The semi-finished product is a semiconductor device on the lower side, and the semi-finished product itself can function. Moreover, the final product is completed by combining the semi-finished product with another semiconductor device (the upper semiconductor device). In this case, the user who purchased the semiconductor device on the lower side laminates the semiconductor device on the upper side by itself and uses it as a laminated semiconductor device. The present invention is applicable to either method.

In Fig. 1, only one set of solder balls 13 surrounding the semiconductor wafer 3 is shown. The group of solder balls 13 shown in FIG. 1 has a rectangular shape in plan view. In FIG. 6, only two sets of solder balls 13 surrounding the semiconductor wafer 26 are shown. The number of sets of the solder balls 13 surrounding the semiconductor wafer 26 may be three or more. In the case where the number of sets of the solder balls 13 surrounding the semiconductor wafer 26 is plural, each group of the solder balls 13 is formed in order from the far side to the near side of the semiconductor wafer 26 in plan view.

The plan view shape of the inner solder balls 13 shown in FIG. 6 is similar to the plan view shape of the outer solder balls 13 in a plan view. The shape of the group of solder balls 13 surrounding the semiconductor wafer 26 may be a rectangle (including a square), may be an ellipse (including a perfect circle), or may be a combination of a line segment and a curved line.

The planar shape of the group of solder balls 13 surrounding the semiconductor wafer 26 is not limited to a closed line segment shape and a closed curve shape. The shape of the plan view may be, for example, an "L" shape of a Latin character or a "Π" shape of a Greek character. The group of the solder balls 13 having the Latin character "L" shape or the group of the solder balls 13 having the Greek character "Π" shape may be two or more sets.

The shape of the solder ball 13 surrounding the semiconductor wafer 26 may be a spiral shape formed by a continuous curve, or may be a spiral shape similar to a spiral (a shape in which a plurality of line segments are connected). In these cases, one turn of the solder balls 13 surrounding the semiconductor wafer 26 corresponds to one set of solder balls 13. Each of the solder balls 13 is formed in order from the far side to the near side of the semiconductor wafer 26 in plan view.

The present invention is not limited to the above-described embodiments, and may be combined, modified, or selectively employed as needed, without departing from the spirit and scope of the invention.

1, 24‧‧‧ semiconductor devices
2, 25‧‧‧ wiring substrate
3, 26‧‧‧ semiconductor wafer
4‧‧‧Wiring
5‧‧‧ soldering leads
6‧‧‧ pads
7‧‧‧ pads
8‧‧‧Through hole wiring
9‧‧‧ solder mask
10‧‧‧Adhesive
11‧‧‧electrode pads
12‧‧‧welding line
13‧‧‧ solder balls
14‧‧‧ Sealing resin
15, 15a, 15b‧‧‧ continuous slots
16‧‧‧ solder mask
17‧‧‧ solder balls
18, 29‧‧‧ semiconductor devices
19, 30‧‧‧ wiring substrate
20, 31‧‧‧ semiconductor wafer
21‧‧‧ pads
22‧‧‧ solder balls
23‧‧‧PoP type semiconductor device
27‧‧‧Bumps
28‧‧‧Substrate electrode
32‧‧‧PoP type semiconductor device
H‧‧‧ openings
OP‧‧‧ openings

1 is a schematic view showing a configuration of a semiconductor device on the lower side in a first embodiment of a semiconductor device according to the present invention, wherein (a) is a plan view and (b) is a cross-sectional view taken along line A-A. (a) to (e) of FIG. 2 are schematic cross-sectional views showing a process of manufacturing a semiconductor device on the lower side in the first embodiment of the present invention. 3 is a schematic view showing a configuration of an upper semiconductor device corresponding to a lower semiconductor device in a second embodiment of the semiconductor device disclosed in the present invention, wherein (a) is a plan view and (b) is a BB. Line cutaway view. (a) to (d) of FIG. 4 are schematic cross-sectional views showing a process of manufacturing the upper semiconductor device in the second embodiment of the present invention. (a) to (c) of FIG. 5 are schematic cross-sectional views showing a process in which the semiconductor device on the lower side and the upper semiconductor device are laminated in the second embodiment of the present invention. FIG. 6 is a schematic view showing a configuration of a semiconductor device on the lower side in a third embodiment of the semiconductor device disclosed in the present invention, wherein (a) is a plan view and (b) is a cross-sectional view taken along line C-C. FIG. 7 is a schematic view showing a configuration of a semiconductor device on the upper side in a third embodiment of the semiconductor device disclosed in the present invention, wherein (a) is a plan view and (b) is a cross-sectional view taken along line D-D. (a) to (b) of FIG. 8 are schematic cross-sectional views showing a process in which the semiconductor device on the lower side and the upper semiconductor device are laminated in the third embodiment.

1‧‧‧Semiconductor device

2‧‧‧ wiring substrate

3‧‧‧Semiconductor wafer

4‧‧‧Wiring

5‧‧‧ soldering leads

6‧‧‧ pads

7‧‧‧ pads

8‧‧‧Through hole wiring

9‧‧‧ solder mask

10‧‧‧Adhesive

11‧‧‧electrode pads

12‧‧‧welding line

13‧‧‧ solder balls

14‧‧‧ Sealing resin

15‧‧‧Continuous slot

16‧‧‧ solder mask

17‧‧‧ solder balls

H‧‧‧ openings

OP‧‧‧ openings

Claims (12)

A semiconductor device comprising: a wiring substrate; a wafer component mounted on one surface of the wiring substrate; a plurality of connection members, a plurality of wafer electrodes formed on the wafer component and a plurality of surfaces formed on one surface of the wiring substrate The substrate electrodes are electrically connected to each other; a plurality of external electrodes are respectively connected to the plurality of substrate electrodes on one surface of the wiring substrate to form around the wafer member; and a plurality of first protruding electrodes are respectively formed on the plurality of electrodes a sealing resin formed on one surface of the wiring substrate covering at least the wafer member and the plurality of first protruding electrodes; and an opening formed in the sealing resin to cause the plurality of first protruding electrodes At least the upper part of it is exposed. The semiconductor device according to claim 1, further comprising: a first protruding electrode group formed of the plurality of first protruding electrodes, surrounding the periphery of the wafer member in plan view; the first protruding shape The electrode group is formed in plural numbers; the plurality of first protruding electrode groups are formed to be multiplexed by surrounding the wafer member in plan view. The semiconductor device according to claim 1, wherein the opening is formed by any one of physical processing or chemical processing. The semiconductor device of claim 1, wherein the opening is a continuous groove. A semiconductor device comprising: a first semiconductor device formed by laminating a second semiconductor device, wherein the first semiconductor device is constituted by the semiconductor device according to claim 1, wherein the second semiconductor device has a plurality of second protruding electrodes formed at positions corresponding to the plurality of first protruding electrodes; wherein the plurality of first protruding electrodes and the plurality of second protruding electrodes are electrically connected. The semiconductor device of claim 5, comprising: a filling material around the plurality of first protruding electrodes and the plurality of second protruding electrodes formed in the opening. A manufacturing method of a semiconductor device, comprising the steps of: preparing a wiring substrate, the wiring substrate having: a surface; a mounting region for mounting a wafer component having a plurality of wafer electrodes on the one surface; and a plurality of substrates An electrode formed on the one surface around the mounting region; and a plurality of external electrodes formed on the one surface and connected to the plurality of substrate electrodes; a step of mounting the wafer component in the mounting region; a step of electrically connecting the plurality of wafer electrodes and the plurality of substrate electrodes; forming a plurality of first protruding electrodes on the plurality of external electrodes; forming at least the wafer component on one side of the wiring substrate and the a step of sealing the sealing resin of the plurality of first protruding electrodes; and a step of forming an opening in the sealing resin for the purpose of exposing at least an upper portion of the plurality of first protruding electrodes. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of preparing the wiring substrate, the wiring substrate having the first protruding electrode group is prepared, the first protruding electrode group having the following features (1) the first protruding electrode group is formed by the plurality of first protruding electrodes, and surrounds the periphery of the wafer member in a plan view; (2) the first protruding electrode group is formed of a plurality of groups, and The wafer member is surrounded by a plurality of layers in a plan view. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of forming the opening, the opening is formed by any one of physical processing or chemical processing. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of forming the opening, a continuous groove is formed as the opening. A method of manufacturing a semiconductor device, comprising the steps of: preparing a first semiconductor device, the first semiconductor device being constituted by the semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 7 a step of preparing a second semiconductor device having a plurality of second protruding electrodes formed at positions corresponding to the plurality of first protruding electrodes of the first semiconductor device; a step of arranging the second semiconductor device above the semiconductor device, positioning the plurality of first protruding electrodes and the plurality of second protruding electrodes to face each other; and causing the first semiconductor device and a step of superposing the second semiconductor device; and electrically connecting the plurality of first protruding electrodes and the plurality of second protruding electrodes. The method of manufacturing a semiconductor device according to claim 10, comprising the steps of: forming a filling material, the filling material filling the plurality of first protrusions in the opening of the first semiconductor device An electrode and a periphery of the plurality of second protruding electrodes.