JP2008171904A - Laminated semiconductor device and its manufacturing method - Google Patents

Laminated semiconductor device and its manufacturing method Download PDF

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Publication number
JP2008171904A
JP2008171904A JP2007001881A JP2007001881A JP2008171904A JP 2008171904 A JP2008171904 A JP 2008171904A JP 2007001881 A JP2007001881 A JP 2007001881A JP 2007001881 A JP2007001881 A JP 2007001881A JP 2008171904 A JP2008171904 A JP 2008171904A
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semiconductor
semiconductor package
stacked
semiconductor device
package
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Japanese (ja)
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Kumiko Nomura
久美子 野村
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2007001881A priority Critical patent/JP2008171904A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated semiconductor device that can protect a semiconductor element, a wiring substrate or a projection electrode from impact from the outside, stress or thermal stress during or after a step for laminating an upper semiconductor package and prevent the degradation of reliability. <P>SOLUTION: A sealing resin 15 is arranged in a manner to cover the entire upper surface of a lower semiconductor package 1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体パッケージを積層した積層型半導体装置、及びその製造方法に関する。   The present invention relates to a stacked semiconductor device in which semiconductor packages are stacked and a manufacturing method thereof.

従来より、半導体パッケージを積層することで半導体素子を三次元実装した積層型半導体装置が提供されている。以下、従来の積層型半導体装置について説明する。図９に従来の積層型半導体装置の断面図を示す。   Conventionally, there has been provided a stacked semiconductor device in which semiconductor elements are three-dimensionally mounted by stacking semiconductor packages. Hereinafter, a conventional stacked semiconductor device will be described. FIG. 9 shows a cross-sectional view of a conventional stacked semiconductor device.

図９において、下側の半導体パッケージ１００の配線基板１０１の両面にはランド部１０２ａ、１０２ｂがそれぞれ形成されている。また、配線基板１０１の上面には半導体素子１０３がフリップチップ実装されている。半導体素子１０３には、フリップチップ実装するための突起電極１０４が設けられており、その突起電極１０４が異方性導電シート１０５を介して、図示しないランド部１０２ｂ上にＡＣＦ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）接合されている。また、配線基板１０１の下面のランド部１０２ａには突起電極１０６が設けられている。   In FIG. 9, land portions 102a and 102b are formed on both surfaces of the wiring substrate 101 of the lower semiconductor package 100, respectively. A semiconductor element 103 is flip-chip mounted on the upper surface of the wiring substrate 101. The semiconductor element 103 is provided with a protruding electrode 104 for flip-chip mounting, and the protruding electrode 104 is bonded to an unillustrated land portion 102b via an anisotropic conductive sheet 105 by an ACF (Anisotropic Conductive Film). Has been. A protruding electrode 106 is provided on the land portion 102 a on the lower surface of the wiring substrate 101.

一方、上側の半導体パッケージ１１０の配線基板１１１の下面にはランド部１１２が形成されており、そのランド部１１２には突起電極１１３が設けられている。また、配線基板１１１上には半導体素子（不図示）が実装され、その半導体素子が実装された配線基板１１１は、封止樹脂１１４で封止されている。   On the other hand, a land portion 112 is formed on the lower surface of the wiring substrate 111 of the upper semiconductor package 110, and a protruding electrode 113 is provided on the land portion 112. Further, a semiconductor element (not shown) is mounted on the wiring substrate 111, and the wiring substrate 111 on which the semiconductor element is mounted is sealed with a sealing resin 114.

そして、下側の配線基板１０１の上面に設けられたランド部１０２ｂに突起電極１１３を接合させることで、上側の配線基板１１１が半導体素子１０３上に配置されるようにして、半導体パッケージ１１０が半導体パッケージ１００の上部に積層されている。   Then, the bump electrode 113 is bonded to the land portion 102b provided on the upper surface of the lower wiring board 101, so that the upper wiring board 111 is disposed on the semiconductor element 103, and the semiconductor package 110 is a semiconductor. It is stacked on top of the package 100.

また、半導体素子１０３上には、上側の半導体パッケージ１１０との対向面（上面）にのみ樹脂１１５が配置され、上側の半導体パッケージ１１０は樹脂１１５を介して半導体素子１０３に固着されている。   Further, on the semiconductor element 103, the resin 115 is disposed only on the surface (upper surface) facing the upper semiconductor package 110, and the upper semiconductor package 110 is fixed to the semiconductor element 103 via the resin 115.

続いて、従来の積層型半導体装置の製造方法について説明する。図１０は、図９に示す従来の積層型半導体装置の製造方法を示す断面図である。まず、図１０（ａ）に示すように、上側の半導体パッケージ１１０のランド部１１２上に突起電極１１３としてハンダボールを形成するとともに、下側の半導体パッケージ１００のランド部１０２ｂ上にフラックス１０７を供給する。また、ディスペンサなどを用いることにより、半導体素子１０３上に樹脂１１５を供給する。   Next, a conventional method for manufacturing a stacked semiconductor device will be described. FIG. 10 is a cross-sectional view showing a method of manufacturing the conventional stacked semiconductor device shown in FIG. First, as shown in FIG. 10A, solder balls are formed as protruding electrodes 113 on the land portion 112 of the upper semiconductor package 110, and a flux 107 is supplied onto the land portion 102b of the lower semiconductor package 100. To do. Further, the resin 115 is supplied onto the semiconductor element 103 by using a dispenser or the like.

次に、図１０（ｂ）に示すように、半導体パッケージ１００の上部に半導体パッケージ１１０を積層する。すなわち、半導体パッケージ１００上に半導体パッケージ１１０をマウントし、突起電極１１３のリフロー処理を行うことにより、突起電極１１３を溶融させ、突起電極１１３をランド部１０２ｂ上に接合させた後、樹脂１１５を硬化させる。次に、図１０（ｃ）に示すように、下側の配線基板１０１の下面に設けられたランド部１０２ａ上に突起電極１０６を設ける。   Next, as shown in FIG. 10B, the semiconductor package 110 is stacked on the semiconductor package 100. That is, by mounting the semiconductor package 110 on the semiconductor package 100 and performing a reflow process on the bump electrode 113, the bump electrode 113 is melted and the bump electrode 113 is bonded onto the land portion 102 b, and then the resin 115 is cured. Let Next, as illustrated in FIG. 10C, the protruding electrode 106 is provided on the land portion 102 a provided on the lower surface of the lower wiring substrate 101.

このように、従来は、半導体素子１０３の上面にのみ樹脂１１５を配置し、この樹脂１１５を介して下側の半導体パッケージ１００と上側の半導体パッケージ１１０とを固着させていた（例えば、特許文献１参照。）。
特開２００４−３３５６０３号公報 As described above, conventionally, the resin 115 is disposed only on the upper surface of the semiconductor element 103, and the lower semiconductor package 100 and the upper semiconductor package 110 are fixed via the resin 115 (for example, Patent Document 1). reference.).
JP 2004-335603 A

しかしながら、従来の積層型半導体装置においては、上側の半導体パッケージを積層する工程途中あるいは工程後の外からの衝撃や、応力、熱ストレスにより、下側の配線基板の表層に形成された基板配線が切断されるおそれがあった。また、半導体素子の上面にのみ樹脂を配置し、下側の半導体パッケージと上側の半導体パッケージとを固着させているため、下側の半導体パッケージと上側の半導体パッケージとの電気的接続を図るための突起電極が露出しており、上述したような外部からの応力を受けて、その突起電極にクラック等が発生し、安定した電気的接続を図ることが困難であった。   However, in the conventional stacked semiconductor device, the substrate wiring formed on the surface layer of the lower wiring board is not affected by an impact, stress, or thermal stress from outside during or after the process of stacking the upper semiconductor package. There was a risk of being cut. Further, since the resin is disposed only on the upper surface of the semiconductor element and the lower semiconductor package and the upper semiconductor package are fixed, the electrical connection between the lower semiconductor package and the upper semiconductor package is achieved. Since the protruding electrode is exposed and receives external stress as described above, a crack or the like is generated in the protruding electrode, making it difficult to achieve stable electrical connection.

本発明は、上記問題点に鑑み、下側の半導体パッケージの上面に、少なくとも下側の配線基板の上面に実装された半導体素子と、下側の半導体パッケージと上側の半導体パッケージとの電気的接続を図るための突起電極とを被覆するように封止材を配置することにより、外からの衝撃や応力、熱ストレスから脆弱な半導体素子や、配線基板、下側の半導体パッケージと上側の半導体パッケージとの電気的接続を図るための突起電極を保護することができ、信頼性低下を防ぐことができる積層型半導体装置を提供することを目的とする。   In view of the above problems, the present invention provides an electrical connection between a semiconductor element mounted on at least the upper surface of a lower wiring substrate and an upper semiconductor package on the upper surface of a lower semiconductor package. By disposing a sealing material so as to cover the protruding electrodes for the purpose of semiconductor devices, semiconductor elements, wiring boards, lower semiconductor packages, and upper semiconductor packages that are vulnerable to external impacts, stresses, and thermal stresses It is an object of the present invention to provide a stacked semiconductor device that can protect a protruding electrode for electrical connection with the semiconductor device and prevent a decrease in reliability.

本発明の請求項１記載の積層型半導体装置は、第１の基板と、前記第１の基板の上面に実装された半導体素子と、前記第１の基板の上面の前記半導体素子が搭載された部分より外側に設けられた第１のランド部とからなる第１の半導体パッケージと、第２の基板と、前記第２の基板の下面に設けられた第２のランド部とからなる第２の半導体パッケージと、を備え、前記第１のランド部と前記第２のランド部との間に突起電極を配置して、前記第１の半導体パッケージの上に前記第２の半導体パッケージを積層した積層型半導体装置であって、前記第１の半導体パッケージの上面に少なくとも前記半導体素子と前記突起電極とを被覆するように封止材を配置したことを特徴とする。   According to a first aspect of the present invention, a stacked semiconductor device includes a first substrate, a semiconductor element mounted on the upper surface of the first substrate, and the semiconductor element on the upper surface of the first substrate. A first semiconductor package comprising a first land portion provided outside the portion, a second substrate, and a second land portion comprising a second land portion provided on the lower surface of the second substrate. A semiconductor package, wherein a projecting electrode is disposed between the first land portion and the second land portion, and the second semiconductor package is stacked on the first semiconductor package. In the semiconductor device, a sealing material is disposed on an upper surface of the first semiconductor package so as to cover at least the semiconductor element and the protruding electrode.

また、本発明の請求項２記載の積層型半導体装置は、請求項１記載の積層型半導体装置であって、前記封止材は、前記第１の半導体パッケージの上面全体または前記突起電極より外側の上面周辺部を除いた部分を覆うように配置されていることを特徴とする。   The stacked semiconductor device according to claim 2 of the present invention is the stacked semiconductor device according to claim 1, wherein the sealing material is outside the entire upper surface of the first semiconductor package or the protruding electrode. It arrange | positions so that the part except the upper surface periphery part of may be covered.

また、本発明の請求項３記載の積層型半導体装置は、請求項１もしくは２のいずれかに記載の積層型半導体装置であって、前記封止材は、前記半導体素子の上部では、前記半導体素子の上面から前記第２の半導体パッケージの下面までの高さ未満の厚みを有し、前記半導体素子が搭載されている領域外の領域では、前記第１の半導体パッケージの上面から前記半導体素子の上面までの高さ以上、前記第１の半導体パッケージの上面から前記第２の半導体パッケージの下面までの高さ未満の厚みを有することを特徴とする。   The stacked semiconductor device according to claim 3 of the present invention is the stacked semiconductor device according to claim 1, wherein the sealing material is formed on the semiconductor element above the semiconductor element. In a region outside the region where the semiconductor element is mounted, the thickness is less than the height from the upper surface of the device to the lower surface of the second semiconductor package. It has a thickness not less than the height from the upper surface to the upper surface of the first semiconductor package and less than the height from the lower surface of the second semiconductor package.

また、本発明の請求項４記載の積層型半導体装置は、請求項１もしくは２のいずれかに記載の積層型半導体装置であって、前記封止材は、前記半導体素子の上部では、前記半導体素子と前記第２の半導体パッケージの間を充填する厚みを有し、前記半導体素子が搭載されている領域外の領域では、前記第１の半導体パッケージの上面から前記半導体素子の上面までの高さ以上、前記第１の半導体パッケージの上面から前記第２の半導体パッケージの下面までの高さ未満の厚みを有することを特徴とする。   The stacked semiconductor device according to claim 4 of the present invention is the stacked semiconductor device according to claim 1, wherein the sealing material is formed on the semiconductor element above the semiconductor element. In a region outside the region where the semiconductor element is mounted, the height from the upper surface of the first semiconductor package to the upper surface of the semiconductor element has a thickness that fills a space between the element and the second semiconductor package. As described above, the first semiconductor package has a thickness less than the height from the upper surface of the first semiconductor package to the lower surface of the second semiconductor package.

また、本発明の請求項５記載の積層型半導体装置は、請求項１もしくは２のいずれかに記載の積層型半導体装置であって、前記封止材は、前記第１と第２の半導体パッケージの間を充填するとともに、前記第２の半導体パッケージよりも外側では、前記第１の半導体パッケージの上面から前記第２の半導体パッケージの下面までの高さ以上、前記第１の半導体パッケージの上面から前記第２の半導体パッケージの上面までの高さ未満の厚みを有することを特徴とする。   A stacked semiconductor device according to claim 5 of the present invention is the stacked semiconductor device according to claim 1, wherein the sealing material is the first and second semiconductor packages. Between the upper surface of the first semiconductor package and at least the height from the upper surface of the first semiconductor package to the lower surface of the second semiconductor package outside the second semiconductor package. The second semiconductor package has a thickness less than a height to the upper surface.

また、本発明の請求項６記載の積層型半導体装置は、請求項１もしくは２のいずれかに記載の積層型半導体装置であって、前記第１の基板は上面に凹部を有し、前記凹部に前記半導体素子を搭載することを特徴とする。   A stacked semiconductor device according to claim 6 of the present invention is the stacked semiconductor device according to claim 1, wherein the first substrate has a recess on an upper surface, and the recess The semiconductor element is mounted on the board.

また、本発明の請求項７記載の積層型半導体装置の製造方法は、第１の基板と、前記第１の基板の上面に実装された半導体素子と、前記第１の基板の上面の前記半導体素子が搭載された部分より外側に設けられた第１のランド部とからなる第１の半導体パッケージと、第２の基板と、前記第２の基板の下面に設けられた第２のランド部とからなる第２の半導体パッケージと、を備え、前記第１のランド部と前記第２のランド部との間に突起電極を配置して、前記第１の半導体パッケージの上に前記第２の半導体パッケージを積層した積層型半導体装置を製造する方法であって、前記第１の基板の上面に前記半導体素子を実装する工程と、前記第１の半導体パッケージの上面に少なくとも前記半導体素子と前記突起電極とが被覆されるように封止材を配置する工程と、前記第２の半導体パッケージを前記封止材を介して第１の半導体パッケージの上面に積層する工程と、前記封止材を硬化させる工程と、を含むことを特徴とする。   According to a seventh aspect of the present invention, there is provided a method for manufacturing a stacked semiconductor device comprising: a first substrate; a semiconductor element mounted on the upper surface of the first substrate; and the semiconductor on the upper surface of the first substrate. A first semiconductor package including a first land portion provided outside a portion on which the element is mounted, a second substrate, and a second land portion provided on the lower surface of the second substrate; A second semiconductor package comprising: a protruding electrode disposed between the first land portion and the second land portion; and the second semiconductor package on the first semiconductor package. A method of manufacturing a stacked semiconductor device in which packages are stacked, the step of mounting the semiconductor element on an upper surface of the first substrate, and at least the semiconductor element and the protruding electrode on an upper surface of the first semiconductor package And sealed so that A step of disposing a material, a step of laminating the second semiconductor package on the upper surface of the first semiconductor package via the sealing material, and a step of curing the sealing material. To do.

また、本発明の請求項８記載の積層型半導体装置の製造方法は、請求項７記載の積層型半導体装置の製造方法であって、前記第１の半導体パッケージの上面に配置する前記封止材はシート状であって、前記封止材を配置する工程の前に、前記封止材の前記第１のランド部に対応する箇所を開口する工程を含み、前記半導体素子を実装する工程の前に、前記封止材を配置する工程を行うことを特徴とする。   The manufacturing method of the stacked semiconductor device according to claim 8 of the present invention is the manufacturing method of the stacked semiconductor device according to claim 7, wherein the sealing material disposed on the upper surface of the first semiconductor package. Is in the form of a sheet, and includes a step of opening a portion corresponding to the first land portion of the sealing material before the step of disposing the sealing material, and before the step of mounting the semiconductor element. In addition, a step of arranging the sealing material is performed.

本発明によれば、上側の半導体パッケージを積層する工程途中あるいは工程後の外からの衝撃や応力、熱ストレスから脆弱な半導体素子や、配線基板、下側の半導体パッケージと上側の半導体パッケージとの電気的接続を図るための突起電極を保護することができ、半導体素子の破壊や、配線基板表層の基板配線の切断、下側の半導体パッケージと上側の半導体パッケージとの電気的接続を図るための突起電極のクラック等を回避して、信頼性低下を防ぐことができる。   According to the present invention, a semiconductor element vulnerable to impact, stress, or thermal stress from the outside during or after the process of laminating the upper semiconductor package, the wiring board, the lower semiconductor package, and the upper semiconductor package Protruding electrodes for electrical connection can be protected, and destruction of semiconductor elements, cutting of substrate wiring on the surface layer of a wiring board, and electrical connection between a lower semiconductor package and an upper semiconductor package It is possible to prevent a decrease in reliability by avoiding cracks and the like of the protruding electrodes.

（実施の形態１）
本発明の実施の形態１における積層型半導体装置、及びその製造方法について、以下、図面を参照しながら説明する。 (Embodiment 1)
A stacked semiconductor device and a manufacturing method thereof according to Embodiment 1 of the present invention will be described below with reference to the drawings.

図１は本実施の形態１における積層型半導体装置の一例を示す断面図である。
図１において、下側の半導体パッケージ（第１の半導体パッケージ）１はフリップチップ実装型であり、配線基板（第１の基板）２と、配線基板２の上面に予め設けられた半導体搭載部（不図示）にフリップチップ実装された薄型の半導体素子３と、半導体搭載部に設けられたランド部４と、半導体素子３の下面に設けられたランド部（不図示）と半導体搭載部に設けられたランド部４に接合し、配線基板２と半導体素子３を電気的に接続する突起電極５と、配線基板２と半導体素子３との間を封止する封止樹脂６と、配線基板２の上面の半導体搭載部より外側に設けられたランド部（第１のランド部）７と、配線基板２の下面に設けられたランド部８と、ランド部８に接合する突起電極９を具備する。また、図示しないが、配線基板２には、上面側のランド部と下面側のランド部を電気的に接続する基板配線が引き回されている。 FIG. 1 is a cross-sectional view showing an example of a stacked semiconductor device according to the first embodiment.
In FIG. 1, a lower semiconductor package (first semiconductor package) 1 is a flip chip mounting type, and includes a wiring substrate (first substrate) 2 and a semiconductor mounting portion (provided in advance on the upper surface of the wiring substrate 2). A thin semiconductor element 3 flip-chip mounted on a semiconductor chip 3, a land part 4 provided on the semiconductor mounting part, a land part (not shown) provided on the lower surface of the semiconductor element 3, and a semiconductor mounting part. A protruding electrode 5 that is joined to the land portion 4 and electrically connects the wiring substrate 2 and the semiconductor element 3; a sealing resin 6 that seals between the wiring substrate 2 and the semiconductor element 3; A land portion (first land portion) 7 provided outside the semiconductor mounting portion on the upper surface, a land portion 8 provided on the lower surface of the wiring substrate 2, and a protruding electrode 9 bonded to the land portion 8 are provided. Although not shown, the wiring board 2 is provided with board wiring that electrically connects the land portion on the upper surface side and the land portion on the lower surface side.

一方、下面を半導体パッケージ１の上面に対向させて、半導体パッケージ１の上部に積層された上側の半導体パッケージ（第２の半導体パッケージ）１０はボールグリッドアレイ型パッケージであり、基板配線が引き回された配線基板（第２の基板）１１と、その配線基板上に実装された半導体素子（不図示）と、その半導体素子が実装された配線基板１１を封止する封止樹脂１２と、配線基板１１の下面に設けられたランド部（第２のランド部）１３と、そのランド部１３に接合された突起電極１４を具備する。突起電極１４は、先端部が下側の半導体パッケージ１のランド部７に接合しており、半導体パッケージ１と半導体パッケージ１０を電気的に接続する。   On the other hand, the upper semiconductor package (second semiconductor package) 10 stacked on top of the semiconductor package 1 with the lower surface facing the upper surface of the semiconductor package 1 is a ball grid array type package, and the substrate wiring is routed around. A wiring board (second board) 11, a semiconductor element (not shown) mounted on the wiring board, a sealing resin 12 for sealing the wiring board 11 on which the semiconductor element is mounted, and a wiring board 11 is provided with a land portion (second land portion) 13 provided on the lower surface of 11, and a protruding electrode 14 joined to the land portion 13. The protruding electrode 14 is joined to the land portion 7 of the lower semiconductor package 1 at the tip, and electrically connects the semiconductor package 1 and the semiconductor package 10.

また、下側の半導体パッケージ１の上面全体は封止樹脂（封止材）１５で封止されている。この封止樹脂１５は、上側の半導体パッケージ１０を積層する前に、下側の半導体パッケージ１の上面全体を覆うように貼り付けた所定の厚み（所定の断面形状）を有するシート状の封止樹脂（以下、封止シート１５ａと称す。）を、上側の半導体パッケージ１０の積層時に硬化させて形成したものである。   The entire upper surface of the lower semiconductor package 1 is sealed with a sealing resin (sealing material) 15. The sealing resin 15 is a sheet-like sealing having a predetermined thickness (predetermined cross-sectional shape) attached so as to cover the entire upper surface of the lower semiconductor package 1 before the upper semiconductor package 10 is stacked. A resin (hereinafter referred to as a sealing sheet 15 a) is formed by curing when the upper semiconductor package 10 is stacked.

配線基板２と半導体素子３との間に充填された封止樹脂６は、液状樹脂あるいはＡＣＦ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）あるいはＮＣＦ（Ｎｏｎｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）のいずれでもよい。また、下側の半導体パッケージ１の上面を覆う封止樹脂１５は、ＡＣＦあるいはＮＣＦのいずれでもよいが、当該積層型半導体装置全体の反り低減が可能な物性値を持つものが好適である。また、封止樹脂６と封止樹脂１５は同一の材料であっても、異なる材料であってもよい。   The sealing resin 6 filled between the wiring substrate 2 and the semiconductor element 3 may be a liquid resin, an ACF (Anisotropic Conductive Film), or an NCF (Nonconductive Film). The sealing resin 15 covering the upper surface of the lower semiconductor package 1 may be either ACF or NCF, but preferably has a physical property value that can reduce the warpage of the entire stacked semiconductor device. Further, the sealing resin 6 and the sealing resin 15 may be the same material or different materials.

封止シート１５ａは、半導体パッケージ１の外形サイズに合わせて、同一の形状にカットして、半導体パッケージ１の上面に貼り付ける。なお、封止シート１５ａを半導体パッケージ１の外形サイズに合わせてカットしても、封止シート１５ａの厚みや、貼り付け時あるいは硬化時の熱や加圧による封止シート１５ａの変形により、半導体素子３の厚み（段差）分だけ配線基板の端部が封止樹脂１５により覆われないという事態を回避できる。また、通常、基板配線は配線基板の端部（数μｍ程度の幅）にまでは引き回されていないので、その端部が封止樹脂１５により覆われていなくとも、封止樹脂１５による基板配線の保護は可能である。   The sealing sheet 15 a is cut into the same shape according to the outer size of the semiconductor package 1 and is attached to the upper surface of the semiconductor package 1. Even if the sealing sheet 15a is cut in accordance with the external size of the semiconductor package 1, the thickness of the sealing sheet 15a, the deformation of the sealing sheet 15a due to heat or pressure at the time of pasting or curing, the semiconductor A situation in which the end portion of the wiring substrate is not covered with the sealing resin 15 by the thickness (step) of the element 3 can be avoided. Further, since the substrate wiring is not usually routed to the end portion (width of about several μm) of the wiring substrate, even if the end portion is not covered with the sealing resin 15, the substrate made of the sealing resin 15 is used. Wiring protection is possible.

このように、上側の半導体パッケージ１０の積層前に、下側の半導体パッケージ１の上面全体を封止シート１５ａで覆うことにより、半導体パッケージ１０を積層する工程途中あるいは工程後の外からの衝撃や、応力、熱ストレスから半導体素子３や、配線基板２、突起電極１４を保護することができ、積層型半導体装置全体の信頼性低下を防ぐことができる。また、図１に示すように半導体パッケージ１、１０間を封止樹脂１５で充填することにより、パッケージ間の応力を緩和することができる。また半導体素子や基板配線が露出しないので、積層型半導体装置の外観不良を防ぐことができる。さらに、下側の半導体パッケージ１に用いる配線基板２においては、封止樹脂１５（封止シート１５ａ）により反りを抑えることができるため、表層にソルダーレジストを設けずにすむ。   As described above, before the upper semiconductor package 10 is stacked, the entire upper surface of the lower semiconductor package 1 is covered with the sealing sheet 15a. Therefore, the semiconductor element 3, the wiring board 2, and the protruding electrode 14 can be protected from stress and thermal stress, and the reliability of the entire stacked semiconductor device can be prevented from being lowered. In addition, as shown in FIG. 1, by filling the space between the semiconductor packages 1 and 10 with the sealing resin 15, the stress between the packages can be relieved. Further, since the semiconductor element and the substrate wiring are not exposed, it is possible to prevent the appearance defect of the stacked semiconductor device. Further, in the wiring substrate 2 used for the lower semiconductor package 1, since the warpage can be suppressed by the sealing resin 15 (sealing sheet 15a), it is not necessary to provide a solder resist on the surface layer.

なお、半導体パッケージ１、１０に用いる配線基板には、高密度配線を引き回すことが可能な有機基板を用いるのが好適である。また、半導体パッケージ１と半導体パッケージ１０を電気的に接続する突起電極１４には半田や金などいずれの材料を用いてもよい。   It is preferable to use an organic substrate capable of routing high-density wiring as the wiring substrate used for the semiconductor packages 1 and 10. Further, any material such as solder or gold may be used for the protruding electrode 14 that electrically connects the semiconductor package 1 and the semiconductor package 10.

続いて、上記した積層型半導体装置の製造方法の一例について説明する。図２は本実施の形態１における積層型半導体装置の製造工程の一例を示す断面図である。なお、図１を用いて説明した部材と同一の部材には同一符号を付して、説明を省略する。   Subsequently, an example of a manufacturing method of the above-described stacked semiconductor device will be described. FIG. 2 is a cross-sectional view showing an example of the manufacturing process of the stacked semiconductor device according to the first embodiment. In addition, the same code | symbol is attached | subjected to the member same as the member demonstrated using FIG. 1, and description is abbreviate | omitted.

まず、図２（ａ）に示すように、両面にランド部４、７、８が設けられた配線基板２を用意する。次に、図２（ｂ）に示すように、配線基板２の半導体搭載部（不図示）の上部に半導体素子３を配置するとともに、その半導体素子３の上部に封止シート１５ａを配置する。封止シート１５ａは、上述したように、半導体パッケージ１の外形サイズに合わせて同一の形状にカットされており、所定の厚み（所定の断面形状）を有する。また、後述するように封止シート１５ａには開口部１６が設けられている。また、半導体搭載部には、フリップチップ実装前に予め封止樹脂６が設けられている。   First, as shown in FIG. 2A, a wiring board 2 provided with lands 4, 7, and 8 on both sides is prepared. Next, as shown in FIG. 2B, the semiconductor element 3 is disposed on the upper portion of the semiconductor mounting portion (not shown) of the wiring board 2, and the sealing sheet 15 a is disposed on the upper portion of the semiconductor element 3. As described above, the sealing sheet 15a is cut into the same shape according to the outer size of the semiconductor package 1, and has a predetermined thickness (a predetermined cross-sectional shape). Moreover, the opening part 16 is provided in the sealing sheet 15a so that it may mention later. The semiconductor mounting portion is provided with a sealing resin 6 in advance before flip chip mounting.

次に、図２（ｃ）に示すように、ツール１７を用いて、半導体搭載部に半導体素子３をフリップチップ実装すると同時に、配線基板２の半導体素子３を含めた上面全体を覆うように封止シート１５ａを貼り付けた後、配線基板２のランド部８上に突起電極９を設けて、図２（ｄ）に示す半導体パッケージ１を得る。このようにフリップチップ実装時に封止シート１５ａを同時に設けるので、積層型半導体装置の製造の工程数を削減することができる。   Next, as shown in FIG. 2C, using the tool 17, the semiconductor element 3 is flip-chip mounted on the semiconductor mounting portion, and at the same time, the entire upper surface including the semiconductor element 3 of the wiring board 2 is sealed so as to cover. After affixing the stop sheet 15a, the protruding electrode 9 is provided on the land portion 8 of the wiring board 2 to obtain the semiconductor package 1 shown in FIG. Thus, since the sealing sheet 15a is provided simultaneously at the time of flip chip mounting, the number of manufacturing steps of the stacked semiconductor device can be reduced.

なお、フリップチップ実装方法は、特に限定されるものではなく、一般的な圧接法あるいは超音波法を採用することができるが、封止シート１５ａを貼り付けるための温度・荷重は必要とする。但し、接合温度については、この時点で封止シート１５ａが硬化しないようにするために、封止シート１５ａの硬化温度以下とする。このように接合温度の低温化を図ることができ、半導体素子３及び配線基板２にかかる熱ストレスやダメージを低減することができる。また、ツール１７の下部側の面は、半導体素子３のサイズ以上、半導体パッケージ１のサイズ以下であり、形状・材質は特に限定されるものではない。   The flip chip mounting method is not particularly limited, and a general pressure welding method or an ultrasonic method can be adopted, but a temperature and a load for attaching the sealing sheet 15a are required. However, the bonding temperature is set to be equal to or lower than the curing temperature of the sealing sheet 15a so that the sealing sheet 15a is not cured at this time. In this way, the bonding temperature can be lowered, and thermal stress and damage applied to the semiconductor element 3 and the wiring board 2 can be reduced. The lower surface of the tool 17 is not less than the size of the semiconductor element 3 and not more than the size of the semiconductor package 1, and the shape and material are not particularly limited.

ここで、封止シート１５ａには、半導体パッケージ１の上面に貼り付ける前に、あらかじめ図３に示すように、半導体パッケージ１のランド部７に対応する箇所に開口部１６を設けておく。開口部１６は、封止シート１５ａの厚み・材料に応じて、ドリルや、レーザー、パンチなどの治工具のいずれか、あるいはこれらを組み合わせて用いて穴加工することで形成する。開口部１６の形状は丸や多角形など、上側の半導体パッケージ１０の突起電極１４と下側の半導体パッケージ１のランド部７が接合できる形状であればよい。このように穴を開けておくことで、半導体パッケージ１０の突起電極１４と半導体パッケージ１のランド部７を接合させる際に、封止シート１５ａの厚み分の段差により突起電極１４の位置合わせがしやすくなる。   Here, before adhering to the upper surface of the semiconductor package 1, the sealing sheet 15 a is provided with an opening 16 at a location corresponding to the land portion 7 of the semiconductor package 1 in advance as shown in FIG. 3. The opening 16 is formed by drilling using a jig, a tool such as a laser, a punch, or a combination thereof according to the thickness and material of the sealing sheet 15a. The shape of the opening 16 may be any shape that can join the protruding electrode 14 of the upper semiconductor package 10 and the land portion 7 of the lower semiconductor package 1 such as a circle or a polygon. By forming the holes in this way, when the protruding electrode 14 of the semiconductor package 10 and the land portion 7 of the semiconductor package 1 are joined, the protruding electrode 14 is aligned by the step corresponding to the thickness of the sealing sheet 15a. It becomes easy.

次に、図２（ｅ）に示すように、半導体パッケージ１の上部に半導体パッケージ１０を配置し、上側の半導体パッケージ１０の突起電極１４と下側の半導体パッケージ１のランド部７の位置を合わせた後、図２（ｆ）に示すように、半導体パッケージ１の上部に半導体パッケージ１０を積層する。すなわち、温度・荷重をかけて突起電極１４とランド部７を接合し、半導体パッケージ１、１０を電気的に接続する。この接合時の温度で、封止樹脂６及び封止シート１５ａを硬化させる。したがって、接合温度は封止樹脂６及び封止シート１５ａの硬化温度以上とする。このとき既に下側の半導体パッケージ１の上面は封止シート１５ａで覆われており、突起電極１４の接合時に外から加わる衝撃や、応力、熱ストレスから配線基板２や、半導体素子３、突起電極１４が保護されているため、パッケージ単体での信頼性低下を防ぐことができる。   Next, as shown in FIG. 2 (e), the semiconductor package 10 is arranged on the upper part of the semiconductor package 1, and the protruding electrodes 14 of the upper semiconductor package 10 and the land portions 7 of the lower semiconductor package 1 are aligned. After that, as shown in FIG. 2F, the semiconductor package 10 is stacked on the semiconductor package 1. That is, the bumps 14 and the land portions 7 are joined by applying temperature and load, and the semiconductor packages 1 and 10 are electrically connected. The sealing resin 6 and the sealing sheet 15a are cured at the bonding temperature. Therefore, the bonding temperature is set to be equal to or higher than the curing temperature of the sealing resin 6 and the sealing sheet 15a. At this time, the upper surface of the lower semiconductor package 1 is already covered with the sealing sheet 15a, and the wiring substrate 2, the semiconductor element 3, and the protruding electrode are subjected to impact, stress, and thermal stress applied from the outside when the protruding electrode 14 is joined. Since 14 is protected, it is possible to prevent a decrease in reliability of the package alone.

以上のように、下側の配線基板２へ半導体素子３をフリップチップ実装すると同時に封止シート１５ａを貼り付け、上側の半導体パッケージ１０を積層すると同時に、その封止シート１５ａを硬化させるので、積層型半導体装置の製造工程数を抑制することができる。また、下側の半導体パッケージ１のランド部７と上側の半導体パッケージ１０の突起電極１４を接合させるときに封止シート１５ａを本硬化させるので、フリップチップ実装時に封止シート１５ａを硬化させなくてもよい。よって、フリップチップ実装時の圧着温度を低くし、フリップチップ実装時に半導体素子にかかる熱ストレスを低減することができる。   As described above, the semiconductor element 3 is flip-chip mounted on the lower wiring substrate 2 and the sealing sheet 15a is attached at the same time, and the upper semiconductor package 10 is stacked and the sealing sheet 15a is cured at the same time. The number of manufacturing steps of the type semiconductor device can be suppressed. Further, since the sealing sheet 15a is fully cured when the land portion 7 of the lower semiconductor package 1 and the protruding electrode 14 of the upper semiconductor package 10 are joined, the sealing sheet 15a need not be cured at the time of flip chip mounting. Also good. Therefore, the pressure bonding temperature at the time of flip chip mounting can be lowered, and the thermal stress applied to the semiconductor element at the time of flip chip mounting can be reduced.

なお、上側の半導体パッケージは、ワイヤボンド接続された半導体素子を実装するタイプでもよいし、フリップチップ実装型でもよい。また、半導体素子の積層構造を実装するタイプでもよい。また、ここでは、上側の半導体パッケージ１０のランド部１３に突起電極１４を予め設けた場合について説明したが、下側の半導体パッケージ１のランド部７に予め設けてもよい。   Note that the upper semiconductor package may be a type in which a semiconductor element connected by wire bonding is mounted or a flip chip mounting type. Moreover, the type which mounts the laminated structure of a semiconductor element may be sufficient. Although the case where the protruding electrode 14 is provided in advance in the land portion 13 of the upper semiconductor package 10 has been described here, it may be provided in advance in the land portion 7 of the lower semiconductor package 1.

また、ここでは、下側の半導体パッケージ１の上面全体を封止樹脂１５で覆う場合について説明したが、封止樹脂１５は、少なくとも半導体素子３と突起電極１４を被覆するように配置すればよく、突起電極１４より外側の上面周辺部を除いた部分を覆うように配置してもよい。   Although the case where the entire upper surface of the lower semiconductor package 1 is covered with the sealing resin 15 has been described here, the sealing resin 15 may be disposed so as to cover at least the semiconductor element 3 and the protruding electrode 14. Alternatively, it may be arranged so as to cover a portion excluding the peripheral portion of the upper surface outside the protruding electrode 14.

また、上側の半導体パッケージ１０を積層する前に、下側の半導体パッケージ１の上面全体を覆うように封止シート１５ａを貼り付ける場合について説明したが、上側の半導体パッケージ１０を積層する前に液状の封止樹脂を下側の半導体パッケージ１の上面に塗布してもよい。この場合であっても、半導体パッケージ１０を積層する工程途中あるいは工程後の外からの衝撃や、応力、熱ストレスから半導体素子３や、配線基板２、突起電極１４を保護することができ、積層型半導体装置全体の信頼性低下を防ぐことができる。また、上側の半導体パッケージ１０を下側の半導体パッケージ１の上面に載置した後、液状の封止樹脂を下側の半導体パッケージ１の上面に塗布し、その後、突起電極１４とランド部７を接合するようにしてもよい。この場合であっても、突起電極１４とランド部７の接合時および半導体パッケージ１０の積層工程後の外からの衝撃や、応力、熱ストレスから半導体素子３や、配線基板２、突起電極１４を保護することができ、積層型半導体装置全体の信頼性低下を防ぐことができる。   Further, the case where the sealing sheet 15a is pasted so as to cover the entire upper surface of the lower semiconductor package 1 before the upper semiconductor package 10 is stacked has been described. The sealing resin may be applied to the upper surface of the lower semiconductor package 1. Even in this case, the semiconductor element 3, the wiring board 2, and the protruding electrode 14 can be protected from impact, stress, and thermal stress from outside or after the process of laminating the semiconductor package 10. The reliability of the entire semiconductor device can be prevented from being lowered. Further, after the upper semiconductor package 10 is placed on the upper surface of the lower semiconductor package 1, a liquid sealing resin is applied to the upper surface of the lower semiconductor package 1, and then the protruding electrodes 14 and the land portions 7 are applied. You may make it join. Even in this case, the semiconductor element 3, the wiring substrate 2, and the protruding electrode 14 are removed from external impact, stress, and thermal stress when the protruding electrode 14 and the land portion 7 are joined and after the stacking process of the semiconductor package 10. Therefore, it is possible to prevent the deterioration of the reliability of the entire stacked semiconductor device.

（実施の形態２）
図４は、本実施の形態２における積層型半導体装置の一例を示す断面図である。但し、前述した実施の形態１で説明した部材と同一の部材には同一符号を付して、説明を省略する。 (Embodiment 2)
FIG. 4 is a cross-sectional view showing an example of the stacked semiconductor device according to the second embodiment. However, the same members as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

図４に示す積層型半導体装置は、封止樹脂１５の厚み（断面形状）が前述の実施の形態１と異なる。具体的には、前述の実施の形態１では、封止樹脂１５は半導体パッケージ１、１０間に充填されていたが（図１参照）、図４に示す積層型半導体装置の封止樹脂１５は、半導体素子３の上部では、半導体素子３の上面から上側の半導体パッケージ１０の下面までの高さ未満の厚みを有し、半導体素子３が搭載されている領域外の領域では、下側の半導体パッケージ１の上面から半導体素子３の上面までの高さ以上、下側の半導体パッケージ１の上面から上側の半導体パッケージ１０の下面までの高さ未満の厚みを有する。これにより、半導体パッケージ１、１０間に空間ができるため、積層型半導体装置の放熱性を向上させることができる。   In the stacked semiconductor device shown in FIG. 4, the thickness (cross-sectional shape) of the sealing resin 15 is different from that of the first embodiment. Specifically, in the first embodiment, the sealing resin 15 is filled between the semiconductor packages 1 and 10 (see FIG. 1), but the sealing resin 15 of the stacked semiconductor device shown in FIG. The upper portion of the semiconductor element 3 has a thickness less than the height from the upper surface of the semiconductor element 3 to the lower surface of the upper semiconductor package 10, and the lower semiconductor in a region outside the region where the semiconductor element 3 is mounted. The thickness is not less than the height from the upper surface of the package 1 to the upper surface of the semiconductor element 3 and less than the height from the upper surface of the lower semiconductor package 1 to the lower surface of the upper semiconductor package 10. Thereby, since a space is formed between the semiconductor packages 1 and 10, the heat dissipation of the stacked semiconductor device can be improved.

また、図５は本実施の形態２における積層型半導体装置の他の例を示す断面図である。この図５に示す積層型半導体装置は、半導体素子３の上部における封止樹脂１５の厚みが、半導体素子３と半導体パッケージ１０との間を充填する厚みとなっている点が図４に示す積層型半導体装置と異なる。これにより、突起電極１４付近における放熱性を向上させると同時に、半導体素子３の上面を封止樹脂１５を介して上側の半導体パッケージ１０に接着させて、半導体パッケージ１、１０間の応力を緩和することができ、積層型半導体装置全体の反り抑制をすることができる。   FIG. 5 is a sectional view showing another example of the stacked semiconductor device according to the second embodiment. In the stacked semiconductor device shown in FIG. 5, the thickness of the sealing resin 15 in the upper part of the semiconductor element 3 is such that the gap between the semiconductor element 3 and the semiconductor package 10 is filled. Different from type semiconductor devices. As a result, the heat dissipation in the vicinity of the protruding electrode 14 is improved, and at the same time, the upper surface of the semiconductor element 3 is bonded to the upper semiconductor package 10 via the sealing resin 15 to relieve the stress between the semiconductor packages 1 and 10. Therefore, warpage of the entire stacked semiconductor device can be suppressed.

また、図６は本実施の形態２における積層型半導体装置の他の例を示す断面図である。この図６に示す積層型半導体装置は、上側の半導体パッケージ１０のサイズが下側の半導体パッケージ１のサイズよりも小さく、上側の半導体パッケージ１０よりも外側の領域における封止樹脂１５の厚みが、下側の半導体パッケージ１の上面から上側の半導体パッケージ１０の下面までの高さ以上、下側の半導体パッケージ１の上面から上側の半導体パッケージ１０の上面までの高さ未満である点が前述の実施の形態１と異なる。   FIG. 6 is a sectional view showing another example of the stacked semiconductor device according to the second embodiment. In the stacked semiconductor device shown in FIG. 6, the size of the upper semiconductor package 10 is smaller than the size of the lower semiconductor package 1, and the thickness of the sealing resin 15 in the region outside the upper semiconductor package 10 is The above-described implementation is that the height from the upper surface of the lower semiconductor package 1 to the lower surface of the upper semiconductor package 10 is not less than the height from the upper surface of the lower semiconductor package 1 to the upper surface of the upper semiconductor package 10. This is different from Form 1.

このように上側の半導体パッケージ１０まで封止樹脂１５で覆う構造にすることで、積層型半導体装置が反って、上側の半導体パッケージの下面のコーナー部から封止樹脂１５へ応力がかかり、封止樹脂１５に亀裂が入ることを防ぐことができる。   As described above, the structure in which the upper semiconductor package 10 is covered with the sealing resin 15 causes the stacked semiconductor device to warp, and stress is applied to the sealing resin 15 from the corner portion on the lower surface of the upper semiconductor package. It is possible to prevent the resin 15 from cracking.

以上のように、本実施の形態２によれば、積層型半導体装置の反りに応じて封止樹脂１５の厚みを上記した範囲内で変化させることにより、積層型半導体装置の反りを低減させることができる。   As described above, according to the second embodiment, it is possible to reduce the warpage of the stacked semiconductor device by changing the thickness of the sealing resin 15 within the above-described range in accordance with the warp of the stacked semiconductor device. Can do.

（実施の形態３）
図７は、本実施の形態３における積層型半導体装置の一例を示す断面図である。但し、前述した実施の形態１で説明した部材と同一の部材には同一符号を付して、説明を省略する。 (Embodiment 3)
FIG. 7 is a cross-sectional view showing an example of the stacked semiconductor device according to the third embodiment. However, the same members as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

図７に示す積層型半導体装置は、下側の配線基板２（半導体パッケージ１）の半導体搭載部１８が半導体素子３の高さ分凹んだ形状をしている点が前述の実施の形態１と異なる。このように、配線基板２の上面に凹部を設け、該凹部に半導体素子３を搭載することにより、積層型半導体装置全体の厚みを小さくすることが可能となる。   The stacked semiconductor device shown in FIG. 7 is different from the above-described first embodiment in that the semiconductor mounting portion 18 of the lower wiring board 2 (semiconductor package 1) has a shape recessed by the height of the semiconductor element 3. Different. Thus, by providing a recess on the upper surface of the wiring board 2 and mounting the semiconductor element 3 in the recess, the thickness of the entire stacked semiconductor device can be reduced.

（実施の形態４）
図８は、本実施の形態４における積層型半導体装置の一例を示す断面図である。但し、前述した実施の形態１、２で説明した部材と同一の部材には同一符号を付して、説明を省略する。 (Embodiment 4)
FIG. 8 is a cross-sectional view showing an example of the stacked semiconductor device according to the fourth embodiment. However, the same members as those described in the first and second embodiments are denoted by the same reference numerals, and description thereof is omitted.

図８に示す積層型半導体装置は、前述の実施の形態１で説明した下側の半導体パッケージ１を複数段（ここでは３段）積層した構成となっている。すなわち、図８に示すように、各半導体パッケージ１の下面に設けられたランド部（下側ランド部）８に接合する突起電極９が、下側の半導体パッケージ１の上面に設けられたランド部（上側ランド部）７に接合して上側と下側の半導体パッケージ１を電気的に接続する構成となっている。これにより、半導体素子の高密度実装が容易に可能となる。   The stacked semiconductor device shown in FIG. 8 has a configuration in which the lower semiconductor package 1 described in the first embodiment is stacked in a plurality of stages (here, three stages). That is, as shown in FIG. 8, the protruding electrode 9 joined to the land portion (lower land portion) 8 provided on the lower surface of each semiconductor package 1 has the land portion provided on the upper surface of the lower semiconductor package 1. The upper and lower semiconductor packages 1 are electrically connected to each other by being joined to the (upper land portion) 7. As a result, high-density mounting of semiconductor elements can be easily performed.

また、前述の実施の形態１、２と同様に、各半導体パッケージ１の上面には封止樹脂１５が設けられており、封止樹脂１５の厚みは、図５に示す積層型半導体装置と同様に、半導体素子３の上部では、半導体素子３と上側の半導体パッケージ１との間を充填する厚みとなっており、半導体素子３が搭載されている領域外の領域では、下側の半導体パッケージ１の上面から半導体素子３の上面までの高さ以上、下側の半導体パッケージ１の上面から上側の半導体パッケージ１の下面までの高さ未満の厚みとなっている。   Further, as in the first and second embodiments, a sealing resin 15 is provided on the upper surface of each semiconductor package 1, and the thickness of the sealing resin 15 is the same as that of the stacked semiconductor device shown in FIG. In addition, the upper portion of the semiconductor element 3 has a thickness that fills the space between the semiconductor element 3 and the upper semiconductor package 1, and the lower semiconductor package 1 in a region outside the region where the semiconductor element 3 is mounted. The thickness is not less than the height from the upper surface of the semiconductor element 3 to the upper surface of the semiconductor element 3 and less than the height from the upper surface of the lower semiconductor package 1 to the lower surface of the upper semiconductor package 1.

本発明にかかる積層型半導体装置、およびその製造方法は、上側の半導体パッケージを積層する工程途中あるいは工程後の外からの衝撃や応力、熱ストレスから脆弱な半導体素子や、配線基板、突起電極を保護して、積層型半導体装置の信頼性低下を防ぐことができ、半導体素子の三次元実装に有用である。   A stacked semiconductor device and a manufacturing method thereof according to the present invention include a semiconductor element, a wiring board, and a protruding electrode that are vulnerable to external impact, stress, and thermal stress during or after the process of stacking an upper semiconductor package. It is possible to prevent the deterioration of the reliability of the stacked semiconductor device by protecting it, which is useful for three-dimensional mounting of semiconductor elements.

本発明の実施の形態１における積層型半導体装置の一例を示す断面図Sectional drawing which shows an example of the laminated semiconductor device in Embodiment 1 of this invention 同実施の形態１における積層型半導体装置の製造工程の一例を示す断面図Sectional drawing which shows an example of the manufacturing process of the laminated semiconductor device in the same Embodiment 1 同実施の形態１における封止シートの穴加工を説明するための図であり、（ａ）は断面図、（ｂ）は平面図It is a figure for demonstrating the hole processing of the sealing sheet in the same Embodiment 1, (a) is sectional drawing, (b) is a top view 本発明の実施の形態２における積層型半導体装置の一例を示す断面図Sectional drawing which shows an example of the laminated semiconductor device in Embodiment 2 of this invention 同実施の形態２における積層型半導体装置の他の例を示す断面図Sectional drawing which shows the other example of the laminated semiconductor device in Embodiment 2 同実施の形態２における積層型半導体装置の他の例を示す断面図Sectional drawing which shows the other example of the laminated semiconductor device in Embodiment 2 本発明の実施の形態３における積層型半導体装置の一例を示す断面図Sectional drawing which shows an example of the laminated semiconductor device in Embodiment 3 of this invention 本発明の実施の形態４における積層型半導体装置の一例を示す断面図Sectional drawing which shows an example of the laminated semiconductor device in Embodiment 4 of this invention 従来の積層型半導体装置の断面図Sectional view of a conventional stacked semiconductor device 従来の積層型半導体装置の製造方法を示す断面図Sectional drawing which shows the manufacturing method of the conventional laminated semiconductor device

符号の説明Explanation of symbols

１ 半導体パッケージ
２ 配線基板
３ 半導体素子
４ ランド部
５ 突起電極
６ 封止樹脂
７ ランド部
８ ランド部
９ 突起電極
１０ 半導体パッケージ
１１ 配線基板
１２ 封止樹脂
１３ ランド部
１４ 突起電極
１５ 封止樹脂
１５ａ 封止シート
１６ 開口部
１７ ツール
１８ 半導体搭載部
１００ 半導体パッケージ
１０１ 配線基板
１０２ａ、１０２ｂ ランド部
１０３ 半導体素子
１０４ 突起電極
１０５ 異方性導電シート
１０６ 突起電極
１０７ フラックス
１１０ 半導体パッケージ
１１１ 配線基板
１１２ ランド部
１１３ 突起電極
１１４ 封止樹脂
１１５ 樹脂 DESCRIPTION OF SYMBOLS 1 Semiconductor package 2 Wiring board 3 Semiconductor element 4 Land part 5 Protruding electrode 6 Sealing resin 7 Land part 8 Land part 9 Protruding electrode 10 Semiconductor package 11 Wiring board 12 Sealing resin 13 Land part 14 Protruding electrode 15 Sealing resin 15a Sealing Stop sheet 16 Opening 17 Tool 18 Semiconductor mounting part 100 Semiconductor package 101 Wiring board 102a, 102b Land part 103 Semiconductor element 104 Protruding electrode 105 Anisotropic conductive sheet 106 Protruding electrode 107 Flux 110 Semiconductor package 111 Wiring board 112 Land part 113 Protrusion Electrode 114 Sealing resin 115 Resin

Claims (8)

第１の基板と、前記第１の基板の上面に実装された半導体素子と、前記第１の基板の上面の前記半導体素子が搭載された部分より外側に設けられた第１のランド部とからなる第１の半導体パッケージと、
第２の基板と、前記第２の基板の下面に設けられた第２のランド部とからなる第２の半導体パッケージと、
を備え、前記第１のランド部と前記第２のランド部との間に突起電極を配置して、前記第１の半導体パッケージの上に前記第２の半導体パッケージを積層した積層型半導体装置であって、
前記第１の半導体パッケージの上面に少なくとも前記半導体素子と前記突起電極とを被覆するように封止材を配置したことを特徴とする積層型半導体装置。 A first substrate; a semiconductor element mounted on the upper surface of the first substrate; and a first land portion provided outside the portion of the upper surface of the first substrate on which the semiconductor element is mounted. A first semiconductor package comprising:
A second semiconductor package comprising a second substrate and a second land portion provided on the lower surface of the second substrate;
A stacked semiconductor device in which a protruding electrode is disposed between the first land portion and the second land portion, and the second semiconductor package is stacked on the first semiconductor package. There,
A stacked semiconductor device, wherein a sealing material is disposed on an upper surface of the first semiconductor package so as to cover at least the semiconductor element and the protruding electrode. 前記封止材は、前記第１の半導体パッケージの上面全体または前記突起電極より外側の上面周辺部を除いた部分を覆うように配置されていることを特徴とする請求項１記載の積層型半導体装置。   2. The stacked semiconductor according to claim 1, wherein the sealing material is disposed so as to cover the entire top surface of the first semiconductor package or a portion excluding the peripheral portion of the top surface outside the protruding electrode. apparatus. 前記封止材は、前記半導体素子の上部では、前記半導体素子の上面から前記第２の半導体パッケージの下面までの高さ未満の厚みを有し、前記半導体素子が搭載されている領域外の領域では、前記第１の半導体パッケージの上面から前記半導体素子の上面までの高さ以上、前記第１の半導体パッケージの上面から前記第２の半導体パッケージの下面までの高さ未満の厚みを有することを特徴とする請求項１もしくは２のいずれかに記載の積層型半導体装置。   The sealing material has a thickness less than a height from an upper surface of the semiconductor element to a lower surface of the second semiconductor package at an upper portion of the semiconductor element, and a region outside the region where the semiconductor element is mounted Then, it has a thickness not less than the height from the upper surface of the first semiconductor package to the upper surface of the semiconductor element and less than the height from the upper surface of the first semiconductor package to the lower surface of the second semiconductor package. The stacked semiconductor device according to claim 1, wherein the stacked semiconductor device is a stacked semiconductor device. 前記封止材は、前記半導体素子の上部では、前記半導体素子と前記第２の半導体パッケージの間を充填する厚みを有し、前記半導体素子が搭載されている領域外の領域では、前記第１の半導体パッケージの上面から前記半導体素子の上面までの高さ以上、前記第１の半導体パッケージの上面から前記第２の半導体パッケージの下面までの高さ未満の厚みを有することを特徴とする請求項１もしくは２のいずれかに記載の積層型半導体装置。   The sealing material has a thickness that fills a space between the semiconductor element and the second semiconductor package above the semiconductor element, and the first sealing element has a thickness outside the area where the semiconductor element is mounted. The semiconductor device has a thickness not less than a height from an upper surface of the semiconductor package to an upper surface of the semiconductor element and less than a height from an upper surface of the first semiconductor package to a lower surface of the second semiconductor package. 3. A stacked semiconductor device according to either 1 or 2. 前記封止材は、前記第１と第２の半導体パッケージの間を充填するとともに、前記第２の半導体パッケージよりも外側では、前記第１の半導体パッケージの上面から前記第２の半導体パッケージの下面までの高さ以上、前記第１の半導体パッケージの上面から前記第２の半導体パッケージの上面までの高さ未満の厚みを有することを特徴とする請求項１もしくは２のいずれかに記載の積層型半導体装置。   The sealing material fills a space between the first and second semiconductor packages, and outside the second semiconductor package, from the upper surface of the first semiconductor package to the lower surface of the second semiconductor package. 3. The stacked type according to claim 1, wherein the stacked type has a thickness not less than a height of less than a height from an upper surface of the first semiconductor package to an upper surface of the second semiconductor package. Semiconductor device. 前記第１の基板は上面に凹部を有し、前記凹部に前記半導体素子を搭載することを特徴とする請求項１もしくは２のいずれかに記載の積層型半導体装置。   3. The stacked semiconductor device according to claim 1, wherein the first substrate has a concave portion on an upper surface, and the semiconductor element is mounted in the concave portion. 第１の基板と、前記第１の基板の上面に実装された半導体素子と、前記第１の基板の上面の前記半導体素子が搭載された部分より外側に設けられた第１のランド部とからなる第１の半導体パッケージと、
第２の基板と、前記第２の基板の下面に設けられた第２のランド部とからなる第２の半導体パッケージと、
を備え、前記第１のランド部と前記第２のランド部との間に突起電極を配置して、前記第１の半導体パッケージの上に前記第２の半導体パッケージを積層した積層型半導体装置を製造する方法であって、
前記第１の基板の上面に前記半導体素子を実装する工程と、
前記第１の半導体パッケージの上面に少なくとも前記半導体素子と前記突起電極とが被覆されるように封止材を配置する工程と、
前記第２の半導体パッケージを前記封止材を介して第１の半導体パッケージの上面に積層する工程と、
前記封止材を硬化させる工程と、
を含むことを特徴とする積層型半導体装置の製造方法。 A first substrate; a semiconductor element mounted on the upper surface of the first substrate; and a first land portion provided outside the portion of the upper surface of the first substrate on which the semiconductor element is mounted. A first semiconductor package comprising:
A second semiconductor package comprising a second substrate and a second land portion provided on the lower surface of the second substrate;
A stacked semiconductor device in which a protruding electrode is disposed between the first land portion and the second land portion, and the second semiconductor package is stacked on the first semiconductor package. A method of manufacturing comprising:
Mounting the semiconductor element on the upper surface of the first substrate;
Disposing a sealing material on the upper surface of the first semiconductor package so as to cover at least the semiconductor element and the protruding electrode;
Laminating the second semiconductor package on the upper surface of the first semiconductor package via the sealing material;
Curing the sealing material;
A method for manufacturing a stacked semiconductor device, comprising: 前記第１の半導体パッケージの上面に配置する前記封止材はシート状であって、前記封止材を配置する工程の前に、前記封止材の前記第１のランド部に対応する箇所を開口する工程を含み、前記半導体素子を実装する工程の前に、前記封止材を配置する工程を行うことを特徴とする請求項７記載の積層型半導体装置の製造方法。   The sealing material to be disposed on the upper surface of the first semiconductor package is in a sheet form, and a position corresponding to the first land portion of the sealing material is provided before the step of disposing the sealing material. 8. The method of manufacturing a stacked semiconductor device according to claim 7, further comprising a step of arranging the sealing material before the step of mounting the semiconductor element, including a step of opening.
JP2007001881A 2007-01-10 2007-01-10 Laminated semiconductor device and its manufacturing method Withdrawn JP2008171904A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8569114B2 (en) 2009-06-01 2013-10-29 Samsung Electronics Co. Ltd. Method of forming a semiconductor device package
KR20170073476A (en) 2015-12-18 2017-06-28 토와 가부시기가이샤 Semiconductor device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8569114B2 (en) 2009-06-01 2013-10-29 Samsung Electronics Co. Ltd. Method of forming a semiconductor device package
KR20170073476A (en) 2015-12-18 2017-06-28 토와 가부시기가이샤 Semiconductor device and method for manufacturing the same

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