JP2015041743A - Semiconductor chip, semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable inhibition of the occurrence of positional deviation of a bump electrode without increasing manufacturing cost when semiconductor chips are laminated.SOLUTION: A semiconductor chip of the present embodiment is a semiconductor chip to compose a semiconductor device by lamination of a plurality of semiconductor chips and composes: a substrate; a first bump electrode formed on one surface of the substrate; a first positioning bump electrode which is formed on the one surface of the substrate and is higher than the first bump electrode; a second bump electrode which is formed on the other surface of the substrate and electrically connected with the first bump electrode; and a second positioning bump electrode which is formed on the other surface of the substrate and is higher than the second bump electrode. The semiconductor chip is positioned with respect to another semiconductor chip by setting the first bump electrode at a contact state with a second bump electrode of the other semiconductor chip and laminated to maintain a fit state where the first positioning bump electrode fits a second positioning bump electrode of the other semiconductor chip without collision.

Description

  The present invention relates to a semiconductor chip, a semiconductor device, and a method for manufacturing a semiconductor device.

  In recent years, with the miniaturization and high functionality of electronic equipment, high-density mounting of semiconductor chips is required. In response to such demands, CoC (Chip on Chip) type semiconductor devices in which a plurality of semiconductor chips having through electrodes are stacked are being studied.

  In Patent Document 1 (Japanese Patent Laid-Open No. 2010-251347) and Patent Document 2 (Japanese Patent Laid-Open No. 2011-129684), a plurality of semiconductor chips having bump electrodes protruding from the substrate surface that are connected to the through electrodes are provided. The semiconductor chip is stacked so that the bump electrodes are connected to each other (flip chip mounting), the chip stack is formed by filling the underfill between the stacked semiconductor chips, and the formed chip stack is mounted on the wiring board. Techniques to do this are disclosed.

  In general, the tops of the bump electrodes are formed to be substantially flat. However, displacement may occur between the corresponding bump electrodes of the stacked semiconductor chips due to a load applied during flip chip mounting. When the positional deviation between the bump electrodes occurs, a short circuit occurs between adjacent bump electrodes, or the connection reliability between the bump electrodes is lowered.

  Therefore, in Patent Document 3 (Japanese Patent Laid-Open No. 2012-248732), in order to prevent the bump electrode from slipping, a bump electrode having a concave top portion on one surface of the substrate of the semiconductor chip is provided on the other surface of the substrate. A technique is disclosed in which bump electrodes having convex top portions are provided by different production means. According to this technique, a semiconductor chip is formed such that a bump electrode whose concave portion is provided on one surface of the semiconductor chip and a bump electrode whose convex portion is provided on the other surface of the other semiconductor chip are engaged. By laminating, it is possible to prevent displacement (side slip) between the bump electrodes.

JP 2010-251347 A JP 2011-129684 A JP 2012-248732 A

  In the techniques disclosed in Patent Document 1 and Patent Document 2, misalignment may occur between corresponding bump electrodes of stacked semiconductor chips. When the positional deviation between the bump electrodes occurs, there is a problem that the adjacent bump electrodes are short-circuited or the connection reliability between the bump electrodes is lowered.

  In the technique disclosed in Patent Document 3, bump electrodes having two shapes, a concave shape and a convex shape, are used for one semiconductor chip. The procedure for manufacturing the bump electrode having such a shape is complicated, and there is a problem that the manufacturing cost of the semiconductor chip increases.

The semiconductor chip of the present invention is
A plurality of semiconductor chips that are stacked to form a semiconductor device,
A substrate,
A first bump electrode formed on one surface of the substrate;
A first positioning bump electrode formed on one surface of the substrate, wherein a height from the one surface of the substrate is higher than a height from the one surface of the substrate of the first bump electrode;
A second bump electrode formed on the other surface of the substrate and electrically connected to the first bump electrode;
A second positioning bump electrode formed on the other surface of the substrate, wherein a height from the other surface of the substrate is higher than a height of the second bump electrode from the other surface of the substrate; Have
The first bump electrode is in contact with the second bump electrode of another semiconductor chip, and the first positioning bump electrode is the second positioning bump electrode of the other semiconductor chip. By being stacked in a fitted state without colliding with each other, positioning is performed with the other semiconductor chip.

The semiconductor device of the present invention is
A semiconductor device configured by stacking a plurality of semiconductor chips,
The semiconductor chip is formed on a substrate, a first bump electrode formed on one surface of the substrate, and on one surface of the substrate, and a height from the one surface of the substrate is the first surface. A first positioning bump electrode higher than the height of the bump electrode from one surface of the substrate, and a second electrode formed on the other surface of the substrate and electrically connected to the first bump electrode. A bump electrode and a second positioning formed on the other surface of the substrate, wherein a height from the other surface of the substrate is higher than a height of the second bump electrode from the other surface of the substrate. A bump electrode, and
The first and second semiconductor chips of the plurality of semiconductor chips are stacked,
The first bump electrode of the first semiconductor chip is brought into contact with the second bump electrode of the second semiconductor chip, and the first positioning bump electrode of the first semiconductor chip Are stacked in a fitted state without colliding with the second positioning bump electrode of the second semiconductor chip, whereby the first and second semiconductor chips are positioned.

A method for manufacturing a semiconductor device of the present invention includes:
A method of manufacturing a semiconductor device in which a plurality of semiconductor chips are stacked,
A first bump electrode on a first surface of the substrate and a first positioning electrode having a height higher than the first surface of the first bump electrode than a height of the first bump electrode from the first surface of the substrate. A bump electrode is formed, a second bump electrode electrically connected to the first bump electrode on the other surface of the substrate, and a height from the other surface of the substrate is the second surface. Forming a plurality of semiconductor chips by forming a second positioning bump electrode higher than the height of the bump electrode from the other surface of the substrate;
Placing the second semiconductor chip of the plurality of semiconductor chips on the first semiconductor chip of the plurality of semiconductor chips;
Bringing the first bump electrode of the first semiconductor chip into contact with the second bump electrode of the second semiconductor chip;
By engaging the first positioning bump electrode of the first semiconductor chip without colliding with the second positioning bump electrode of the second semiconductor chip, the first and the first The semiconductor chip of 2 has the process of positioning.

  According to the present invention, the stacked semiconductor chips are positioned by bringing the positioning bump electrodes into a fitted state. The positioning bump electrodes are formed higher than the bump electrodes, but the bump electrodes formed low can be brought into contact with each other by being fitted without colliding. Thus, since positioning is performed using bump electrodes having different heights, a highly reliable product can be manufactured without an increase in manufacturing cost.

1 is a top view of a semiconductor chip according to a first embodiment of the present invention. It is sectional drawing along the A-A 'line | wire shown to FIG. 1A. FIG. 1B is a cross-sectional view taken along line B-B ′ shown in FIG. 1A. It is a figure which shows the arrangement pattern of the bump electrode for positioning of the semiconductor chip shown to FIG. 1A. It is sectional drawing of the semiconductor chip of the area | region C shown to FIG. 1B. It is sectional drawing which shows the formation process of the semiconductor chip shown to FIG. 1A. It is sectional drawing which shows the formation process of the semiconductor chip shown to FIG. 1A. It is sectional drawing which shows the formation process of the semiconductor chip shown to FIG. 1A. It is sectional drawing which shows the formation process of the semiconductor chip shown to FIG. 1A. It is sectional drawing which shows the formation process of the semiconductor chip shown to FIG. 1A. It is sectional drawing which shows the formation process of the semiconductor chip shown to FIG. 1A. It is sectional drawing which shows the formation process of the semiconductor chip shown to FIG. 1A. It is sectional drawing which shows the formation process of the bump electrode in the surface of the semiconductor chip shown to FIG. 1A. It is sectional drawing which shows the formation process of the bump electrode in the surface of the semiconductor chip shown to FIG. 1A. It is sectional drawing which shows the formation process of the bump electrode in the surface of the semiconductor chip shown to FIG. 1A. It is sectional drawing which shows the formation process of the bump electrode in the surface of the semiconductor chip shown to FIG. 1A. It is sectional drawing which shows the lamination | stacking process of the semiconductor chip shown to FIG. 1A. It is sectional drawing which shows the lamination | stacking process of the semiconductor chip shown to FIG. 1A. It is sectional drawing which shows the lamination | stacking process of the semiconductor chip shown to FIG. 1A. It is sectional drawing which shows the lamination | stacking process of the semiconductor chip shown to FIG. 1A. It is sectional drawing which shows the formation process of bump connection of the chip laminated body shown to FIG. 5D. It is sectional drawing which shows the formation process of bump connection of the chip laminated body shown to FIG. 5D. It is a block diagram of the semiconductor device which has a chip laminated body shown to FIG. 5D. FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 7. FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 7. FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 7. FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 7. FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 7. FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 7. It is a top view of the semiconductor chip of the 2nd Embodiment of this invention. It is sectional drawing along the D-D 'line | wire shown to FIG. 9A. It is a figure which shows the arrangement pattern of the bump electrode for positioning of the semiconductor chip shown to FIG. 9A. It is a top view of the semiconductor chip of the 3rd Embodiment of this invention. It is sectional drawing along the E-E 'line | wire shown to FIG. 10A. It is a figure which shows the arrangement pattern of the bump electrode for positioning of the semiconductor chip shown to FIG. 10A. It is a figure which shows the other arrangement pattern of the bump electrode for positioning. It is a figure which shows the bump electrode for positioning further another arrangement pattern. It is a figure which shows the further another arrangement pattern of the bump electrode for positioning.

  EMBODIMENT OF THE INVENTION Below, the form for implementing this invention is demonstrated with reference to drawings.

(First embodiment)
First, a schematic configuration of the semiconductor chip 100 according to the first embodiment of the present invention will be described with reference to FIGS. 1A to 1D.

  FIG. 1A is a top view of the semiconductor chip 100. 1B is a cross-sectional view taken along the line A-A ′ of FIG. 1A. 1C is a cross-sectional view taken along line B-B ′ of FIG. 1A.

  The semiconductor chip 100 has a silicon substrate 101.

  The silicon substrate 101 is, for example, a substrate formed of silicon having a thickness of about 50 μm, and a circuit forming layer 101A is formed on one surface. Hereinafter, the surface of the silicon substrate 101 on which the circuit formation layer 101A is provided is referred to as the front surface, and the surface on which the circuit formation layer 101A is not provided is referred to as the back surface.

  As shown in FIG. 1A, a surface bump electrode 102A, a positioning surface bump electrode 103A, and a reinforcing surface bump electrode 104A are formed on the surface of the silicon substrate 101A.

  The surface bump electrodes 102A as the first bump electrodes are provided so as to form a plurality of rows in a predetermined direction at predetermined pitch intervals. Hereinafter, the direction of the row of surface bump electrodes 102A is referred to as a Y-axis direction, and the direction orthogonal to the Y-axis direction on the surface is referred to as an X-axis direction. The surface bump electrode 102A is a columnar electrode connected to a circuit provided in the circuit formation layer 101A, and is used as a signal input / output terminal, a power supply terminal, a ground (ground) terminal, or the like. The height of the surface bump electrode 102A is, for example, about 20 μm.

  The positioning surface bump electrodes 103A, which are the first positioning bump electrodes, are formed in a predetermined arrangement pattern at the four corners of the surface of the silicon substrate 101. The positioning surface bump electrode 103A is a columnar dummy electrode insulated from the circuit provided in the circuit forming layer 101A.

  As shown in FIGS. 1A and 1C, the reinforcing surface bump electrode 104A is formed at both ends in the X-axis direction along the Y-axis direction. The reinforcing surface bump electrode 104A is provided for the purpose of reinforcing the connection of the stacked semiconductor chips, and is insulated from the circuit provided on the circuit forming layer 101A in the same manner as the positioning surface bump electrode 103A. It is a columnar dummy electrode. In this case, it may be connected to the ground potential for the purpose of reinforcing the power supply.

  On the back surface of the silicon substrate 101, as shown in FIGS. 1B and 1C, a back surface bump electrode 102B, a positioning back surface bump electrode 103B, a reinforcing back surface bump electrode 104B, and a resin layer 106 are formed.

  As shown in FIG. 1B, the back bump electrode 102B, which is the second bump electrode, is a columnar electrode provided corresponding to the front bump electrode 102A, and the surface of the back bump electrode 102B through the through electrode 105 penetrating the silicon substrate 101. Connected to the bump electrode 102A.

  The positioning back surface bump electrode 103B, which is the second positioning bump electrode, is a columnar dummy electrode, and the arrangement pattern thereof corresponds to the arrangement pattern of the positioning surface bump electrode 103A. It is formed in an arrangement pattern that fits without colliding with the positioning surface bump electrode 103A.

  As shown in FIG. 1C, the reinforcing back surface bump electrode 104B is a columnar electrode provided corresponding to the reinforcing surface bump electrode 104A, and is connected to the reinforcing surface bump electrode 104A through the through electrode 105. .

  The resin layer 106 is formed using a resin such as NCF (Non Conductive Film) and seals each bump electrode provided on the back surface of the silicon substrate 101. By forming the resin layer 106, warpage of the silicon substrate 101 is reduced. The thickness of the resin layer 106 is, for example, about 50 μm.

  The height of the positioning surface bump electrode 103A from the surface of the silicon substrate 101 is higher than the height of the surface bump electrode 102A from the surface of the silicon substrate 101, and the height of the surface bump electrode 102A from the surface of the silicon substrate 101 is higher. And the height of the back surface bump electrode 102B from the back surface of the silicon substrate 101 is lower. Further, the width (diameter) of the positioning surface bump electrode 103A is smaller than that of the surface bump electrode 102A.

  Further, the height of the positioning back bump electrode 103B from the back surface of the silicon substrate 101 is higher than the height of the back bump electrode 102B from the back surface of the silicon substrate 101, and the height of the front bump electrode 102A from the surface of the silicon substrate 101 is high. And the height of the back surface bump electrode 102B from the back surface of the silicon substrate 101 is lower. In addition, the width (diameter) of the positioning back surface bump electrode 103B is smaller than that of the back surface bump electrode 102 due to a manufacturing process described later.

  Next, the relationship between the arrangement pattern of the positioning front surface bump electrode 103A and the arrangement pattern of the positioning back surface bump electrode 103B will be described.

  FIG. 1D is a top view seen from the front surface side showing an example of an arrangement pattern of the positioning front surface bump electrode 103A and the positioning back surface bump electrode 103B. In the following description, in the Y-axis direction, the upper (lower) direction in the drawing is defined as upper (lower), and in the X-axis direction, the left (right) direction in the drawing is described as left (right).

  FIG. 1D shows an arrangement pattern of the positioning front surface bump electrode 103A and the positioning back surface bump electrode 103B disposed in the lower right corner of the silicon substrate 100, and the positioning surface bump electrodes 103A (103A-1, 103A-2). ) Is indicated by a solid line, and the positioning rear surface bump electrode 103B (103B-1, 103B-2) is indicated by a dotted line.

  As shown in FIG. 1D, when the semiconductor chips 100 are stacked, at the bonding portion of each semiconductor chip 100, the positioning surface bump electrode 103A of one semiconductor chip 100 and the positioning back surface of another semiconductor chip 100 facing each other. The bump electrode 103B is in a fitted state without colliding.

  Specifically, at the bonding portion of each semiconductor chip 100, the positioning back surface bump electrode 103B-1 is adjacent to the lower side of the positioning surface bump electrode 103A-1, and the right side of the positioning surface bump electrode 103A-1. Is adjacent to the positioning rear surface bump electrode 103B-2. Further, the positioning back surface bump electrode 103B-1 is adjacent to the left side of the positioning surface bump electrode 103A-2, and the positioning back surface bump electrode 103B-2 is adjacent to the upper side of the positioning surface bump electrode 103A-2. Yes. Note that, in the other three corners of the silicon substrate 100, the positioning front bump electrode 103A and the positioning rear bump electrode 103B are brought into a fitted state without colliding.

  As described above, the positioning back (front) surface bump electrode is adjacent to the positioning back (front) surface bump electrode in each of the X-axis direction and the Y-axis direction. For example, for the positioning front surface bump electrode 103A-1, the positioning back surface bump electrode 103B-1 and the positioning back surface bump electrode 103B-2 are adjacent to each other. With such a configuration, movement in each of the X-axis direction and the Y-axis direction is restricted and positioning is performed.

  FIG. 2 is an enlarged sectional view showing the configuration of the region C in FIG. 1B in more detail. The structure will be described below with reference to FIG.

  A predetermined circuit, for example, a memory circuit is formed in the circuit formation layer 101A. In the circuit formation layer 101A, a plurality of stacked insulating layers, wirings provided in the plurality of insulating layers, contact plugs, and the like are formed.

  On the circuit formation layer 101A, a plurality of electrode pads 201 and 202 are provided in a predetermined arrangement. At the position where the electrode pads 201 and 202 are provided, the wiring provided in the uppermost layer of the circuit formation layer 101A is exposed from the surface of the circuit formation layer 101A and is electrically connected to the electrode pads 201 and 202. . The circuit forming layer 101A is covered with an insulating film 203 in order to protect the circuit forming surface except for the region where the electrode pads 201 and 202 are provided.

  On the electrode pads 201 and 202, columnar surface pillar portions 206 and 207 made of Cu are formed via surface seed layers 204 and 205, respectively.

  Ni plating layers 208 and 209 are formed on the surface pillar portions 206 and 207 to prevent Cu diffusion. On the Ni plating layers 208 and 209, Au plating layers 210 and 211 are formed for preventing oxidation.

  The electrode pad 201, the surface seed layer 204, the surface pillar portion 206, the Ni plating layer 208, and the Au plating layer 210 constitute the surface bump electrode 102A. In addition, the electrode pad 202, the seed layer 205, the surface pillar portion 207, the Ni plating layer 209, and the Au plating layer 211 constitute the positioning surface bump electrode 103A.

  A through hole is formed in the silicon substrate 101 at a position corresponding to the electrode pads 201 and 202, and the through hole is filled with a conductor layer, for example, Cu, through the back surface seed layers 214 and 215. An electrode 105 is formed.

  In addition, the silicon substrate 101 includes an insulating member that is embedded in a cylindrical shape around the through electrode 105 so as to surround the through electrode 105 in order to provide insulation between the silicon substrate 101 and the through electrode 105. Insulating rings 212 and 213 are formed.

  On the back surface of the silicon substrate 101, back pillar portions 216 and 217 made of Cu are formed via seed layers 214 and 215. The back pillar portion 216 is formed corresponding to the front surface bump electrode 102 </ b> A, and is electrically connected to the corresponding front surface bump electrode 102 </ b> A via the through electrode 105. The back pillar portion 217 is formed in an arrangement pattern corresponding to the arrangement pattern of the positioning front surface bump electrode 103 </ b> A and is electrically connected to the through electrode 105.

  On the back pillar portions 216 and 217, hemispherical back solder layers 218 and 219 made of Sn / Ag are formed.

  The back surface seed layer 214, the back surface pillar portion 216, and the back surface solder layer 218 constitute the back surface bump electrode 102B. The back surface seed layer 215, the back surface pillar portion 217, and the back surface solder layer 219 constitute the positioning back surface bump electrode 103B.

  Next, a process of forming the semiconductor chip 100 will be described with reference to FIGS. 3A to 3F. Normally, a plurality of semiconductor chips 100 are formed on a semiconductor wafer, and each semiconductor chip 100 formed on the semiconductor wafer is singulated to obtain a semiconductor chip. Below, the process of forming the semiconductor chip 100 on the semiconductor wafer will be described in order.

  3A to 3F are cross-sectional views sequentially showing the process of forming the semiconductor chip 100 shown in FIG. 1A.

  First, in the process shown in FIG. 3A, a semiconductor wafer 300 having a plurality of chip formation regions 301 in which the semiconductor chips 100 are formed and a dicing line 302 that partitions the plurality of chip formation regions 301 is prepared. The semiconductor substrate 300 has a first surface 300A that is a flat surface and a second surface 300B that is located on the opposite side of the first surface 300A and is a flat surface. As the semiconductor wafer 300, for example, a single crystal silicon wafer can be used.

  A circuit formation layer 101A is formed in a plurality of chip formation regions 301 on the first surface 300A of the semiconductor wafer 300. The circuit formation layer 101A has a multilayer wiring structure including transistor elements, a plurality of stacked interlayer insulating layers, a wiring pattern (such as wiring and vias) formed in the plurality of interlayer insulating layers, and the like.

  Next, an insulating film 203 (passivation film) having an opening exposing the formation region of the surface bump electrode 102A and the positioning surface bump electrode 103A is formed on the circuit formation layer 101A.

  The insulating film 203 is a film for protecting the circuit formation layer 101A and is formed using an insulating resin (for example, polyimide resin).

  Next, the surface bump electrode 102A and the positioning surface bump electrode 103A are formed on the circuit formation layer 101A exposed through the opening. At this time, the surface bump electrode 102 </ b> A and the positioning surface bump electrode 103 </ b> A are formed so as to protrude from the surface of the insulating film 203.

  Next, a plating film (not shown) is formed on the surface bump electrode 102A and the positioning surface bump electrode 103A.

  3B, after the silicon wafer 300 shown in FIG. 3A is turned upside down, the support substrate 304 is bonded to the first surface 300A of the semiconductor wafer 300 via the bonding member 303.

  As the material of the adhesive member 303, a material whose foaming or adhesive strength is reduced by reacting with a specific light source (for example, laser light or UV (Ultra Violet) light) is used.

  As the support substrate 304, for example, a light transmissive substrate (for example, a glass substrate) is used.

  The adhesive member 303 is formed to have a thickness capable of completely embedding the surface bump electrode 102A and the positioning surface bump electrode 103A.

  In this way, by completely embedding the surface bump electrode 102A and the positioning surface bump electrode 103A in the adhesive member 303, the support substrate 304 is not damaged without damaging the surface bump electrode 102A and the positioning surface bump electrode 103A. Thus, the semiconductor wafer 300 can be supported.

  3C, the semiconductor wafer 300 is thinned by grinding or polishing the semiconductor wafer 300 from the second surface 300B side of the semiconductor wafer 300. At this time, for example, the semiconductor wafer 300 is thinned so that the thickness of the semiconductor wafer 300 is 50 μm or less.

  Since the thinned semiconductor wafer 300 is supported by the support substrate 304, the thinned semiconductor wafer 300 can be easily handled (for example, transported between semiconductor manufacturing apparatuses).

  Next, through holes are formed in the semiconductor wafer 300 from the second surface 300B side toward the electrode pads formed in the circuit formation layer 101A. The through hole is formed so that the electrode pad is exposed.

  Next, an insulating film (not shown) that covers the side surface of the through hole and the second surface 300B of the semiconductor wafer 300 is formed, and a resist film for plating having an opening that exposes the through hole on the insulating film. (Mask) is formed.

  Next, a back seed layer is formed to cover the inner surface of the through hole, the surface of the plating resist film (including the side surface of the opening), and the upper surface of the insulating film exposed in the opening, and the back seed layer As a power feeding layer, a Cu plating film is formed by embedding through holes and openings by an electrolytic plating method using Cu.

  Next, by removing the plating resist film, and then removing the back surface seed layer not covered with the Cu plating film, the through electrode 105 disposed in the through hole and connected to the front surface bump electrode 102A, A back surface bump electrode 102B that is integrated with the through electrode 105 and protrudes from the insulating film, and a positioning back surface bump electrode 103B that is integrated with the through electrode 105 and protrudes from the insulating film are collectively formed.

  The surface bump electrode 102A and the positioning surface bump electrode 103A are electrically insulated from the semiconductor wafer 300 by the insulating film 203 covering the first surface 300A of the semiconductor wafer 300. Further, the back surface bump electrode 102B and the positioning back surface bump electrode 103B are electrically insulated from the semiconductor wafer 300 by an insulating film covering the second surface 300B of the semiconductor wafer 300.

  Next, in the step shown in FIG. 3D, a resin layer 106 (insulating resin layer having adhesiveness) covering the back surface bump electrode 102B and the positioning back surface bump electrode 103B is formed on the second surface 300B of the semiconductor wafer 300. Form.

  Specifically, NCF (Non Conductive Film) is attached as the resin layer 106 to the second surface 300 </ b> B of the semiconductor wafer 300.

  Thus, by forming the resin layer 106 on the second surface 300B of the semiconductor wafer 300, warpage of the semiconductor wafer 300 due to the insulating film 203 can be reduced.

  3A to 3D, the circuit forming layer 101A, the insulating film 203, the surface bump electrode 102A, the back surface bump electrode 102B, the positioning surface bump electrode 103A, the positioning back surface bump electrode 103B, the through electrode 105, and The semiconductor chip 100 having the resin layer 106 is formed on the plurality of chip formation regions 301 of the semiconductor wafer 300.

  Next, in a step shown in FIG. 3E, a dicing tape 305 including a dicing tape main body and an adhesive layer is prepared, and the dicing tape main body is attached to the resin layer 106 via the adhesive layer of the dicing tape 305.

  Thus, after forming the resin layer 106 so that the back surface bump electrode 102B and the positioning back surface bump electrode 103B may be covered, the dicing tape 305 is adhered to the resin layer 106, whereby the back surface bump electrode 102B and the positioning surface are positioned. The back bump electrode 103B for use is not embedded in the adhesive layer of the dicing tape 305.

  Thus, when the semiconductor chip 100 is picked up from the dicing tape 305 after the plurality of semiconductor chips 100 formed on the semiconductor wafer 300 are singulated, the back surface bump electrode 102B and the positioning back surface bump electrode 103B are connected to the dicing tape 305. Therefore, unnecessary stress is not applied to the thinned semiconductor chip 100.

  Therefore, when the semiconductor chip 100 is picked up from the dicing tape 305, it is possible to suppress the breakage of the semiconductor chip 100 (for example, chip crack starting from the through electrode 105) or the pick-up mistake of the semiconductor chip 100.

  Further, when the semiconductor chip 100 is picked up from the dicing tape 305, the resin layer 106 is attached to the semiconductor chip 100, so that the resin layer 106 functions as a support plate for the semiconductor chip 100 and the picked-up semiconductor chip 100. The occurrence of warpage is suppressed. Thereby, it can suppress that the semiconductor chip 100 is damaged.

  As the adhesive layer constituting the dicing tape 305, for example, a layer having a characteristic that a chemical reaction is caused in the component of the adhesive material by ultraviolet (UV) irradiation and the adhesive force is reduced.

  Alternatively, the resin layer 106 may be attached to the adhesive layer of the dicing tape 305, and the resin layer 106 to which the dicing tape 305 is attached may be attached to the second surface 300B of the semiconductor wafer 300.

  In this way, by applying the dicing tape 305, the stress applied to the semiconductor wafer 300 as compared with the case where the resin layer 106 is formed on the second surface 300B of the semiconductor wafer 300 using the spinner method. Can be reduced.

  Next, in the step shown in FIG. 3F, the structure shown in FIG. 3E is turned upside down and then irradiated with light from a specific light source via the support substrate 304 (for example, laser light or UV light (ultraviolet light)). By irradiating the adhesive member 303, the adhesive member 303 is foamed or the adhesive force is reduced, and the adhesive member 303 and the support substrate 304 are removed.

  As a result, the insulating film 203, the surface bump electrode 102A, and the positioning surface bump electrode 103A constituting the semiconductor chip 100 are exposed.

  Next, in the process shown in FIG. 3G, the semiconductor wafer 300 shown in FIG. 3F is held on a stage of a dicing apparatus (not shown), and then the semiconductor wafer adhered to the dicing tape 305 by a dicing blade (not shown). 300 and the resin layer 106 are cut into a plurality of semiconductor chips 100 by cutting along the dicing line 302 from the resin layer 106 side. At this time, a part of the dicing tape 305 corresponding to the dicing area is cut.

  As a result, the resin layer 106 has a shape corresponding to the outer shape of the semiconductor chip 100 (separated semiconductor chip 100) constituting the semiconductor wafer 300.

  In this manner, by cutting the semiconductor wafer 300 attached to the dicing tape 305 and the resin layer 106 in a state where the resin layer 106 that reduces warpage of the semiconductor wafer 300 due to the insulating film 203 is formed, The plurality of semiconductor chips 100 can be separated into pieces with high accuracy.

  Further, by cutting the semiconductor wafer 300 from the side on which the circuit forming layer 101A is formed, the dicing area can be recognized with high accuracy without using a special recognition means such as an infrared camera.

  Next, by irradiating UV light to the adhesive layer of the dicing tape 305 from the second surface 300B side of the semiconductor wafer 300 through the main body of the dicing tape 305 by an unillustrated ultraviolet (UV) irradiation mechanism, Reduce the adhesive strength of the adhesive layer.

  Thereby, the resin layer 106 can be easily peeled off from the adhesive layer of the dicing tape 305.

  Next, the process of forming the surface bump electrode 102A and the positioning surface bump electrode 103A will be described in detail with reference to FIGS. 4A to 4D.

  4A, an unillustrated UBM (Under Bump Metal) film is formed on the insulating film 203, and a seed layer is formed on the formed UBM layer. Note that the seed layers become the surface seed layers 204 and 205 depending on the positions where they are formed. The seed layer is, for example, a Ti / Cu film and is formed by a sputtering film forming method or the like.

  Subsequently, a photoresist layer 401 is applied to the seed layer. The photoresist layer 401 is a plating mask and has a thickness of 30 μm, for example. Further, the coated photoresist layer 401 is covered so as to have an opening of a predetermined pattern, and exposed and developed to form openings 402 and 403.

  Here, the seed layer located in the opening 402 becomes the surface seed layer 204, and the seed layer located in the opening 403 becomes the surface seed layer 205. The openings 402 and 403 are substantially circular openings, and a part of the electrode pad 201 is exposed. Note that the opening width (W1) that is the diameter of the opening 402 is larger than the opening width (W2) that is the diameter of the opening 403.

  Next, in the step shown in FIG. 4B, the surface pillar portions 206, 403 are formed in the openings 402, 403 on the surface seed layers 204, 205 by an electrolytic plating process using Cu using the surface seed layers 204, 205 as a power feeding layer. 207 is formed.

  Here, in general, the growth rate of the plating film in the openings having two different sizes when the electrolytic plating process is used is higher in the growth rate in the small opening than in the large opening. Since the opening width (W2) of the opening 403 is smaller than the opening width (W1) of the opening 402, the height (H2) of the positioning surface bump electrode 103A is higher than the height (H1) of the surface bump electrode 102A. Also gets higher. In this manner, bump electrodes having different heights can be formed according to the opening width of the opening of the photoresist layer 401.

  Next, in the step shown in FIG. 4C, Ni plating layers 208 and 209 are formed on the surface pillar portions 206 and 207 by an electrolytic plating process using the surface seed layers 204 and 205 as power feeding layers, and the Ni plating layer 208 is further formed. , 209, Au plating layers 210 and 211 are formed.

  Next, in the step shown in FIG. 4D, the surface seed layers 204 and 205 and the photoresist layer 401 formed on the insulating film 203 are removed by etching.

  In this manner, the surface bump electrode 102A including the electrode pad 201, the surface seed layer 204, the surface pillar portion 206, the Ni plating layer 208, and the Au plating layer 210 is formed at a position corresponding to the opening 402. . In addition, a positioning surface bump electrode 103 </ b> A including the electrode pad 202, the surface seed layer 205, the surface pillar portion 207, the Ni plating layer 209, and the Au plating layer 211 is formed at a position corresponding to the opening 403.

  The positioning back surface bump electrode 103B has an opening formed by providing a plating mask having an opening smaller than the opening in which the back surface bump electrode 102B is formed on the back surface of the silicon substrate 101, and forming a plating film. Formed in the part. The positioning back surface bump electrode 103B formed in this way is higher than the height of the back surface bump electrode 102B.

  Next, with reference to FIGS. 5A to 5D, a process of forming a chip stacked body in which a plurality of semiconductor chips 100 are stacked will be described.

  5A to 5D are cross-sectional views illustrating the stacking process of the semiconductor chips 100 (100-1 to 100-4).

  In the step shown in FIG. 5A, the semiconductor chip 100-1 is placed on the bonding stage 501.

  As shown in FIG. 5A, the semiconductor chip 100-1 has bump electrodes formed only on the front surface and no bump electrodes formed on the back surface.

  The bonding stage 501 is provided with a plurality of first suction holes 502 on the mounting surface on which the semiconductor chip 100-1 is mounted. The first suction hole 502 is connected to a vacuum pump (not shown). The semiconductor chip 100-1 is fixed to the bonding stage 501 by being mounted on the mounting surface of the bonding stage 501 and then sucked by a vacuum pump through the first suction hole 502. Here, the semiconductor chip 100-1 is fixed so that the back surface on which the front surface bump electrode 102A is not formed is in contact with the bonding stage 501. Since the bump electrode such as the bump electrode 102B is not formed on the back surface of the semiconductor chip 100-1, the semiconductor chip 100-1 can be satisfactorily fixed on the bonding stage 501. The bonding stage 501 can heat the fixed semiconductor chip 100-1.

  Next, in the step shown in FIG. 5B, the surface of the semiconductor chip 100-2 is fixed by the bonding tool 503 so that the back surface of the semiconductor chip 100-2 faces the surface of the semiconductor chip 100-1. The bonding tool 503 is provided with a recess, and the bump electrode formed on the surface of the semiconductor chip 100-2 is stored in the recess.

  The bonding tool 503 is provided with a plurality of second suction holes 504 on the surface to which the semiconductor chip 100-2 is fixed. The second suction hole 504 is connected to a vacuum pump (not shown). The semiconductor chip 100-2 is fixed to the bonding tool 503 by being sucked by a vacuum pump through the second suction hole 504. The bonding tool 503 can heat the fixed semiconductor chip 100-2.

  The bonding stage 501 and the bonding tool 503 constitute a bonding apparatus.

  The bonding tool 503 for fixing the semiconductor chip 100-2 moves toward the bonding stage 501 for fixing the semiconductor chip 100-1, so that the bump electrode formed on the surface of the semiconductor chip 100-1 and the semiconductor chip 100-1 The semiconductor chip 100-2 is stacked on the semiconductor chip 100-1 so that the resin layer 106 of -2.

  Next, the semiconductor chips 100-1 and 100-2 are heated by the bonding apparatus to a first temperature (for example, about 150 ° C.) at which the resin layer 106 is melted, and the surface bump electrode 102A of the semiconductor chip 100-1 is obtained. Are connected to the back bump electrode 102B of the semiconductor chip 100-2. Further, the semiconductor chips 100-1 and 100-2 are heated to a second temperature (for example, about 260 ° C.) at which the back surface solder layer 218 provided on the top of the back surface bump electrode 102B of the semiconductor chip 100-1 reflows. Then, the front surface bump electrode 102A of the semiconductor chip 100-1 and the rear surface bump electrode 102B of the semiconductor chip 100-2 are bump-connected and fixed via the reflowed back surface solder layer 218.

  Next, in the process shown in FIG. 5C, the third-stage semiconductor chip 100-3 is connected and fixed on the second-stage semiconductor chip 100-2 by the same process as the process shown in FIG. 5B. The fourth-stage semiconductor chip 100-4 is connected and fixed on the semiconductor chip 100-3.

  Through the steps described above, as shown in FIG. 5D, a semiconductor chip stacked body 505 in which the semiconductor chips 100-1, 100-2, 100-3, and 100-4 are stacked is configured.

  Next, the bump connection forming process will be described in detail.

  6A and 6B are cross-sectional views showing a bump connection forming process when the semiconductor chip 100 is stacked. 6A and 6B show a bump connection forming process between the front surface bump electrode 102A of the semiconductor chip 100-1 shown in FIG. 5 and the rear surface bump electrode 102B of the semiconductor chip 100-2 shown in FIG. Yes.

  6A, the bonding stage 501 sucks and holds the back surface of the semiconductor chip 100-1, and the bonding tool 503 sucks and holds the surface of the semiconductor chip 100-2.

  The semiconductor chips 100-1 and 100-2 are provided with recognition marks (not shown) corresponding to the positions of the bump electrodes. The recognition marks correspond to the semiconductor chips 100-1 and 100-2, respectively. The semiconductor chips 100-1 and 100-2 can be arranged so that the bump electrodes to be opposed to each other.

  Next, in the step shown in FIG. 6B, the semiconductor chip 100-2 is arranged so that the bump electrode formed on the surface of the semiconductor chip 100-1 and the resin layer 106 of the semiconductor chip 100-2 are in contact with each other. 1 is laminated.

  Next, the bonding apparatus heats the semiconductor chips 100-1 and 100-2 while applying a load to the semiconductor chips 100-1 and 100-2. Specifically, for example, the bonding apparatus heats up to 150 ° C. and applies a load of 10N. At such a temperature, the resin layer 106 melts, but the back solder layer 218 does not melt.

  When the resin layer 106 of the semiconductor chip 100-2 is melted with a load applied by the bonding apparatus, the bump electrodes formed on the surface of the semiconductor chip 100-1 enter the resin layer 106 of the semiconductor chip 100-2. . Then, the top of the front surface bump electrode 102A of the semiconductor chip 100-1 and the top of the back surface solder layer 218 provided on the back surface bump electrode 102B of the semiconductor chip 100-2 are in contact. Further, the positioning front surface bump electrode 103A of the semiconductor chip 100-1 and the positioning back surface bump electrode 103B of the semiconductor chip 100-2 are adjacent to each other and are in a combined state.

  Next, the bonding apparatus further heats the semiconductor chips 100-1 and 100-2 while applying a load. Specifically, for example, the bonding apparatus heats up to 260 ° C. At such a temperature, the back solder layer 218 melts and spreads between the top of the front bump electrode 102A of the semiconductor chip 100-1 and the top of the back bump electrode 102B of the semiconductor chip 100-2.

  Subsequently, the bonding apparatus reduces the temperatures of the semiconductor chips 100-1 and 100-2. For example, the bonding apparatus reduces the temperature to 100 ° C. At such a temperature, the back surface solder layer 218 is cured, and the front surface bump electrode 102A of the semiconductor chip 100-1 and the back surface bump electrode 102B of the semiconductor chip 100-2 are satisfactorily connected via the cured back surface solder layer 218. Is done. In addition, the resin layer 106 extends into the gap between the semiconductor chips 100-1 and 100-2 and fills the gap.

  Next, the configuration of the semiconductor device 700 on which the chip stack 505 is mounted will be described with reference to FIG.

  The semiconductor device 700 has a configuration in which a chip stack 505 is connected to a wiring substrate 710 via a logic chip 720.

  The wiring substrate 710 includes an insulating substrate 711, connection pads 712, lands 713, and an insulating film 714.

  The insulating substrate 711 is a plate-like substrate made of an insulating member.

  The connection pad 712 is provided on one surface of the wiring board 710 (the surface to which the logic chip 720 is connected). Note that a surface of the wiring board 710 where the connection pads 712 are provided is referred to as a front surface.

  The land 713 is provided on the back surface of the wiring board 710 and is connected to the solder ball 750.

  The insulating film 714 is a protective film that covers the front surface or the back surface of the wiring substrate 710, for example, using a solder resist. In addition, the insulating film 714 has an opening that exposes the land 713, the stacked region of the logic chip 720, and the like.

  The logic chip 720 is a semiconductor chip that has a front surface bump electrode 721, a front surface solder layer 722, a back surface bump electrode 723, and a through electrode 724, and drives the chip stack 505.

  The surface bump electrode 721 is an electrode formed on one surface of the logic chip 720 (the surface to which the wiring board 710 is connected), and is connected to a circuit formed in the logic chip 720, the through electrode 724, or the like. Hereinafter, in the logic chip 720, a surface on which the surface bump electrode 721 is formed is referred to as a surface.

  The surface solder layer 722 is formed in a hemispherical shape on the surface bump electrode 721 by reflowing a Sn / Ag plating layer generated by electrolytic plating.

  The back bump electrode 723 is an electrode formed on the back surface of the logic chip 720 at a position corresponding to the front bump electrode 721.

  The through electrode 724 penetrates the logic chip 720, one end is connected to the front surface bump electrode 721, and the other end is connected to the back surface bump electrode 723.

  The logic chip 720 having the above-described configuration is mounted on the wiring board 710 so that the surface bump electrodes 721 are connected to the connection pads 712 formed on the surface of the wiring board 710. On the logic chip 720, the chip stack 505 is mounted such that the back bump electrode 723 and the front bump electrode 102A of the lowermost semiconductor chip 100 of the chip stack 505 are connected.

  The resin member 730 is a resin such as NCP (Non Conductive Paste), and bonds and fixes the chip stack 505 and the wiring board 710 or the wiring board 710 and the logic chip 720.

  The sealing resin 740 is, for example, a thermosetting epoxy resin, and is fixed by molding the chip stack 505 and the logic chip 720 mounted on the wiring board 710.

  The solder ball 750 is a terminal that is connected to the land 713 of the wiring board 710 and performs input / output of signals to / from the outside of the semiconductor device 700.

  Next, an assembly process of the semiconductor device 700 shown in FIG. 7 will be described with reference to FIGS. 8A to 8F.

  8A to 8F are cross-sectional views showing manufacturing steps of the semiconductor device 700 shown in FIG.

  When assembling the semiconductor device 700, first, a wiring substrate 710 having a plurality of product forming portions 801 arranged in a matrix is prepared. Each of the product forming portions 801 is a portion that becomes the wiring substrate 710 of the semiconductor device 700. Each product forming portion 801 has a predetermined pattern of wiring, and each wiring is a solder except for the connection pads 711 and the lands 713. An insulating film 714 such as a resist film is covered. Between each of the product forming portions 801 is a dicing line 802 for separating each semiconductor device 700 individually.

  A plurality of connection pads 712 for connecting to the logic chip 720 are formed on the surface of the wiring substrate 710, and a plurality of lands 713 for connecting conductive solder balls 750 serving as external terminals are formed on the back surface. ing. The connection pad 712 is connected to a predetermined land 713 by wiring.

  When the preparation of the wiring board 710 is completed, as shown in FIG. 8A, an insulating resin member 730 is applied on each product forming portion 801 by a dispenser.

  Next, the surface of the logic chip 720 is sucked and held with a bonding tool or the like, and as shown in FIG. 8B, the logic chip 720 is mounted on the product formation portion 801, and the connection pads 712 of the wiring board 710 and the logic chip 720 The surface bump electrode 721 is bonded using, for example, a thermocompression bonding method. At this time, the resin member 730 is filled between the wiring board 710 and the logic chip 720, and the wiring board 710 and the logic chip 720 are bonded and fixed. Further, a resin member 730 is applied on the logic chip 720 with a dispenser.

  Next, the back surface of the uppermost semiconductor chip 100 of the chip stack 505 is sucked and held with a bonding tool or the like, and the chip stack 505 is mounted on the logic chip 720 as shown in FIG. The front surface bump electrode 102A of the lowermost semiconductor chip 100 and the back surface bump electrode 723 of the logic chip 720 are bonded using, for example, a thermocompression bonding method. At this time, the resin member 730 is filled between the chip stack 505 and the logic chip 720, and the chip stack 505 and the logic chip 720 are bonded and fixed.

  The wiring board 710 on which the chip stack 505 and the logic chip 720 are mounted is set in a molding die including an upper mold and a lower mold (not shown), and the process proceeds to a molding process.

  A cavity (not shown) that collectively covers the chip stack 505 and the logic chip 720 is formed in the upper mold of the molding die, and a plurality of chip stacks 505 mounted on the wiring board 710 in the cavity, and A logic chip 720 is accommodated.

  Next, the sealing resin 740 heated and melted is injected into the cavity provided in the upper mold of the molding die, and the cavity is filled with the sealing resin 740 so as to cover the entire chip stack 505 and the logic chip 720. To do.

  Subsequently, in a state where the cavity is filled with the sealing resin, the sealing resin 740 is cured by curing at a predetermined temperature, for example, about 180 ° C., thereby forming a plurality of products as shown in FIG. 8D. A sealing resin 740 is formed that collectively covers each chip stack 505 and each logic chip 720 mounted on the portion 801. Further, the sealing resin 740 is completely cured by baking at a predetermined temperature.

  As described above, since the semiconductor chip 100 between the chip stacks 505 is sealed with the resin member 108, the entire chip stack 505 is covered with the resin member 740, so that voids are generated in the gaps between the semiconductor chips 100. Can be suppressed.

  When the sealing resin 740 is formed, the process proceeds to a ball mounting process, and the solder ball 750 is connected to the land 713 formed on the other surface of the wiring board 710.

  In the ball mounting process, a plurality of solder balls 750 are sucked and held using a mounting tool having a plurality of suction holes arranged so as to correspond to the arrangement of the plurality of lands 713 of the wiring board 710, as shown in FIG. 8E. In addition, after the flux is transferred to each solder ball 750, each solder ball 750 is collectively connected to the land 713 of the wiring board 710.

  After the connection of the solder balls 750 to all the product forming portions 801 is completed, the solder balls 750 and the lands 713 are connected by reflowing the wiring board 710.

  When the connection of the solder balls 750 is completed, the process proceeds to a substrate dicing process, and the individual product forming portions 801 are cut and separated by the dicing lines 812, thereby forming the semiconductor device 700.

  In the substrate dicing process, the product forming portion 801 is supported by sticking a dicing tape (not shown) to the sealing resin 740. Then, as shown in FIG. 8F, the product forming portion 801 is separated by a dicing line 812 by a dicing blade provided in a dicing device (not shown). After cutting and separating, by picking up each product forming portion 801 from the dicing tape, the CoC type semiconductor device 700 shown in FIG. 7 is obtained.

  As described above, in order to connect and fix the chip stack 505 to the wiring substrate 710 via the logic chip 720, the chip stack 505 on which the plurality of semiconductor chips 100 are stacked is first configured. The thermal stress applied to the connection part between the semiconductor chips 100 and the semiconductor chip 100 due to the heat treatment at the time of manufacture is reduced due to the difference in thermal expansion coefficient and rigidity of the wiring board 710 and the logic chip 720. Therefore, it is possible to suppress the breakage of the connection portion between the semiconductor chips 100 and the occurrence of cracks in the semiconductor chip 100.

  As described above, when the semiconductor chip 100 is stacked, the front surface bump electrode 102A and the rear surface bump electrode 102B are in contact with each other, and the positioning front surface bump electrode 103A and the positioning rear surface bump electrode 103B are in a combined state. The position where 100 is laminated is determined.

  Further, when the semiconductor chips 100 are stacked, the positioning front bump electrodes 103A and the positioning back bump electrodes 103B are brought into a combined state at the joint portion of the semiconductor chips 100, and the stack positions of the semiconductor chips are fixed. For this reason, even if a force in a direction orthogonal to the stacking direction is applied, the stacking position of the semiconductor chip 100 is not shifted. The positioning front surface bump electrode 103A and the positioning back surface bump electrode 103B are restricted from moving in the plane of the semiconductor chip 100 even if they are brought into a combined state at one location by their arrangement pattern.

  Therefore, when the semiconductor chip 100 is stacked, it is possible to suppress the displacement between the front surface bump electrode 102A and the rear surface bump electrode 102B.

  Further, in this manner, the positioning surface bump electrode 103A higher than the surface bump electrode 102A is combined with the opening 402 in which the surface bump electrode 102A is manufactured in the plating mask in the manufacturing procedure of the surface bump electrode 102A. An opening 403 smaller than the opening 402 is provided and a plating film is formed, whereby the opening 403 can be manufactured.

  Similarly, the positioning rear surface bump electrode 103B higher than the rear surface bump electrode 102B is provided with an opening smaller than the opening in the plating mask together with the opening where the rear surface bump electrode 102B is formed. Can be produced.

Therefore, the positioning front bump electrode 103A higher than the front bump electrode 102A and the positioning rear bump electrode 103B higher than the rear bump electrode 102B can be manufactured without complicating the manufacturing procedure.
(Second Embodiment)
Next, the configuration of the semiconductor chip 900 according to the second embodiment of the present invention will be described with reference to FIGS. 9A to 9C. In the semiconductor chip 900 of this embodiment, the arrangement pattern of the positioning front surface bump electrode and the positioning back surface bump electrode is different from that of the semiconductor chip 100 of the first embodiment. Hereinafter, an arrangement pattern of the positioning front surface bump electrode and the positioning back surface bump electrode in the semiconductor chip 900 of this embodiment will be mainly described.

  FIG. 9A is a top view of the semiconductor chip 900. FIG. 9B is a cross-sectional view taken along line D-D ′ shown in FIG. 9A. FIG. 9C is a diagram illustrating an example of an arrangement pattern of the positioning front surface bump electrode 901A and the positioning back surface bump electrode 901B of the semiconductor chip 900 illustrated in FIG. 9A. In FIG. 9C, positioning bump electrodes 901A (901A-1 to 901A-4) are indicated by solid lines, and positioning bump electrodes 901B are indicated by dotted lines.

  As shown in FIGS. 9A and 9C, the positioning bump electrode 901A and the positioning bump electrode 901B are provided at different positions at the four corners of the silicon substrate 101, respectively. In the bonding portion of the chip 900, at the four corners of the substrate surface of each semiconductor chip 900, the positioning front surface bump electrode 901A of one semiconductor chip 900 has the rear surface bump electrode 901B for positioning of the other semiconductor chip 900 vertically and horizontally. Enclosed without any collision.

  As described above, when the semiconductor chips 900 are stacked, the positioning front surface bump electrodes 901A are adjacent to each other so as to surround the positioning back surface bump electrodes 901B at a plurality of locations in the joint portion of each semiconductor chip 900.

  Here, when the positioning front surface bump electrode 901A and the positioning back surface bump electrode 901B are in a combined state at one location, the semiconductor chip 900 is restricted from moving in the vertical and horizontal directions in the plane. However, the movement in the in-plane rotational direction is not restricted. However, since the positioning front surface bump electrode 901A and the positioning back surface bump electrode 901B are combined at a plurality of locations, movement in the rotational direction within the surface of the semiconductor chip 900 is also restricted. That is, the positioning front surface bump electrode 901A and the positioning back surface bump electrode 901B are brought into a combined state at two or more locations, thereby restricting in-plane movement of the semiconductor chip 900.

Therefore, when the semiconductor chip 900 is stacked, it is possible to suppress positional deviation between the front surface bump electrode 102A and the rear surface bump electrode 102B.
(Third embodiment)
Next, the configuration of the semiconductor chip 1000 according to the third embodiment of the present invention will be described with reference to FIGS. 10A to 10C. In the semiconductor chip 1000 of this embodiment, the arrangement pattern of the positioning front surface bump electrode and the positioning back surface bump electrode is different from that of the semiconductor chip 100 of the first embodiment. Hereinafter, an arrangement pattern of the positioning front surface bump electrode and the positioning back surface bump electrode in the semiconductor chip 1000 of the present embodiment will be mainly described.

  FIG. 10A is a top view of the semiconductor chip 1000. FIG. 10B is a cross-sectional view taken along line E-E ′ shown in FIG. 10A. FIG. 10C is a diagram illustrating an example of an arrangement pattern of the positioning front surface bump electrode 1001A and the positioning back surface bump electrode 1001B of the semiconductor chip 1000 illustrated in FIG. 10A. In FIG. 10C, positioning bump electrodes 1001A (1001A-1 to 1001A-8) are indicated by solid lines, and positioning bump electrodes 1001B (1001B-1 to 1001B-4) are indicated by dotted lines.

  As shown in FIGS. 10A and 10C, when the semiconductor chips 1000 are stacked, the positioning surface bump electrode 1001 </ b> A of one semiconductor chip 1000 is the back surface for positioning of the other semiconductor chip 1000 at the joint portion of each semiconductor chip 1000. The bump electrodes 1001B (1001B-1 to 1001B-4) and the rear surface bump electrodes for positioning 1001B-1 to 1001B-4 are adjacent to each other so as to surround a rectangle, and are brought into a fitted state without colliding.

  Specifically, at the bonding portion of each semiconductor chip, a positioning back surface bump electrode 1001B-1 is adjacent to the right side in the X-axis direction of the positioning surface bump electrode 1001A-1, and the positioning surface bump electrode 1001A-2 A positioning back surface bump electrode 1001B-1 is adjacent to the lower side in the Y-axis direction. Also, a positioning back surface bump electrode 1001B-2 is adjacent to the positioning surface bump electrode 1001A-3 on the lower side in the Y-axis direction, and a positioning back surface bump electrode 1001A-4 is positioned on the left side in the X-axis direction. 1001B-2 is adjacent. Further, a positioning back surface bump electrode 1001B-3 is adjacent to the positioning surface bump electrode 1001A-5 on the right side in the X-axis direction, and a positioning back surface bump electrode 1001B is positioned on the upper side in the Y axis direction of the positioning surface bump electrode 1001A-6. -3 are adjacent. Further, a positioning back surface bump electrode 1001B-4 is adjacent to the positioning surface bump electrode 1001A-7 on the upper side in the Y axis direction, and a positioning back surface bump electrode 1001B is positioned on the left side in the X axis direction of the positioning surface bump electrode 1001A-8. -4 is adjacent.

  As described above, when the semiconductor chips 1000 are stacked, the positioning surface bump electrode 1001A is adjacent to the positioning back surface bump electrode 1001B at a plurality of positions in the joint portion of each semiconductor chip 1000, and the positioning surface bump electrode 1001A. In addition, the positioning back surface bump electrode 1001B is brought into a combined state, and movement in the surface of the semiconductor chip 1000 is restricted.

  Therefore, when the semiconductor chip 1000 is stacked, it is possible to suppress positional deviation between the front surface bump electrode 102A and the rear surface bump electrode 102B.

  Next, another arrangement pattern of the positioning front surface bump electrode and the positioning back surface bump electrode will be described with reference to FIGS.

  In FIG. 11, the positioning front surface bump electrodes 1101A (1101A-1, 1101A-2) are indicated by solid lines, and the positioning rear surface bump electrodes 1101B (1101B-1, 1101B-2) are indicated by dotted lines.

  As shown in FIG. 11, the positioning front surface bump electrode 1101A and the positioning back surface bump electrode 1101B have a substantially square pillar shape with a substantially square bottom surface, and have a positioning surface bump electrode 1101A and a positioning back surface bump electrode 1101B. At the time of stacking the chips, at the bonding portion of each semiconductor chip, the front surface bump electrode 1101A for positioning of one semiconductor chip and the back surface bump electrode 1101B for positioning of another semiconductor chip are adjacent to each other and collide with each other. It will be in a fitting state, without.

  Specifically, at the bonding portion of each semiconductor chip, one side of the positioning back surface bump electrode 1101B-1 is adjacent to one side of the positioning surface bump electrode 1101A-1 on the lower side in the Y-axis direction. One side of the positioning rear surface bump electrode 1101B-2 is adjacent to the other side on the right side in the X-axis direction of the electrode 1101A-1. Further, the other side of the positioning back surface bump electrode 1101A-2 is adjacent to the left side of the positioning surface bump electrode 1101A-2 on the left side in the X axis direction, and the other side of the positioning surface bump electrode 1101A-2 on the upper side in the Y axis direction. Is adjacent to the other side of the positioning rear surface bump electrode 1101B-2.

  As described above, the positioning surface bump electrode 1101A and the positioning back surface bump electrode 1101B have a regular quadrangular prism shape. When the semiconductor chips are stacked, the positioning surface bump electrodes 1101A and 1101A and The positioning back surface bump electrodes 1101B have adjacent side surfaces adjacent to each other, and movement in the surface of the semiconductor chip is restricted. That is, even if the positioning front bump electrode 1101A and the positioning back bump electrode 1101B are in a combined state at one place, the movement in the surface of the semiconductor chip is restricted.

  For this reason, it is possible to suppress displacement between the front surface and back surface bump electrodes when the semiconductor chips are stacked.

  Next, in FIG. 12, the positioning surface bump electrodes 1201A (1201A-1, 1201A-2) are indicated by solid lines, and the positioning back surface bump electrodes 1201B are indicated by dotted lines.

  As shown in FIG. 12, the positioning surface bump electrode 1201A (1201A-1, 1201A-2) has an L-shaped columnar bottom surface, and L-shaped bent portions are provided to face each other. One back bump electrode 1201B is provided in a rectangular parallelepiped shape. At the time of stacking the semiconductor chips having the positioning front surface bump electrode 1201A and the positioning back surface bump electrode 1201B, the positioning front bump electrode 1201A of one semiconductor chip is used for positioning of another semiconductor chip at the junction of each semiconductor chip. It adjoins so that each of the side surface of the back surface bump electrode 1201B may be enclosed, and it will be in a fitting state, without colliding.

  Specifically, at the bonding portion of each semiconductor chip, the positioning surface bump electrode 1201A-1 includes the positioning back surface bump electrode 1201B, one surface in the Y axis direction of the positioning back surface bump electrode 1201B, and the X axis direction. It adjoins in one side of. The positioning surface bump electrode 1201A-2 is adjacent to the positioning back surface bump electrode 1201B and the other surface in the Y-axis direction and the other surface in the X-axis direction of the positioning back surface bump electrode 1201B.

  As described above, at the time of stacking the semiconductor chips, the positioning front bump electrode 1201A is adjacent to each of the side surfaces of the rectangular parallelepiped positioning back bump electrode 1201B at the bonding portion of each semiconductor chip, and within the surface of the semiconductor chip. Movement is restricted. That is, the positioning front bump electrode 1201A and the positioning back bump electrode 1201B are restricted from moving in the plane of the semiconductor chip even if they are in a combined state at one location due to their shapes.

  For this reason, it is possible to suppress displacement between the front surface and back surface bump electrodes when the semiconductor chips are stacked.

  In the present embodiment, the positioning bump electrode 1201B has a substantially rectangular parallelepiped shape, but is not limited thereto. The positioning bump electrode 1201B may have a polygonal column shape with a polygonal bottom surface.

  Next, in FIG. 13, the positioning front bump electrode 1301A is indicated by a solid line, and the positioning back bump electrode 1301B is indicated by a dotted line.

  As shown in FIG. 13, the positioning surface bump electrode 1301A has a substantially C-shaped column shape with a bottom portion cut off in an annular shape, and the positioning back surface bump electrode 1301B has a columnar shape. Each is provided at a plurality of different positions on the silicon substrate. At the time of stacking the semiconductor chips having the positioning front surface bump electrode 1301A and the positioning back surface bump electrode 1301B, the side surface inside the positioning surface bump electrode 1301A of one semiconductor chip and the other semiconductors are joined at the bonding portion of each semiconductor chip. The side surface of the positioning rear surface bump electrode 1301B of the chip is adjacent to each other, and the positioning surface bump electrode 1301A and the positioning surface bump electrode 1301B are brought into a fitted state without colliding.

  Thus, when the semiconductor chips are stacked, the positioning front bump electrode 1301A is adjacent to surround the positioning back bump electrode 1301B at the bonding portion of each semiconductor chip. Even if the positioning surface bump electrode 1301B is in an integrated state at one location, movement in the rotational direction within the surface of the semiconductor chip is not limited. Movement including the in-plane rotation direction is restricted. That is, the positioning front surface bump electrode 1301A and the positioning back surface bump electrode 1301B are brought into a combined state at two or more locations, thereby restricting movement of the semiconductor chip within the surface.

  For this reason, it is possible to suppress displacement between the front surface and back surface bump electrodes when the semiconductor chips are stacked.

  In the above-described embodiment, the height of the positioning surface bump electrode is higher than the height of the front surface bump electrode, and the height of the positioning back surface bump electrode is higher than the height of the back surface bump electrode. It is not limited to this. The height of any one of the positioning front surface bump electrode and the positioning back surface bump electrode only needs to be higher than the height of the bump electrode formed on the same surface.

100, 900, 1000 Semiconductor chip 101 Silicon substrate 101A Circuit forming layer 102A, 721 Surface bump electrode 102B, 723 Back surface bump electrode 103A, 901A, 1001A, 1101A, 1201A, 1301A Positioning surface bump electrode 103B, 901B, 1001B, 1101B, 1201B, 1301B Positioning rear surface bump electrode 104A Reinforcing surface bump electrode 104B Reinforcing rear surface bump electrode 105, 724 Through electrode 106 Resin layer 201, 202 Electrode pad 203, 714 Insulating film 204, 205 Surface seed layer 206, 207 Surface pillar portion 208, 209 Ni plating layer 210, 211 Au plating layer 212, 213 Insulating ring 214, 215 Back surface seed layer 216, 217 Back surface pillar portion 218, 219 Back surface solder layer 300 Semiconductor wafer 301 Chip formation region 302, 802 Dicing line 303 Adhesive member 304 Support substrate 305 Dicing tape 401 Photoresist layer 402, 403 Opening 501 Bonding stage 502, 504 Adsorption hole 503 Bonding tool 505 Chip stack 700 Semiconductor Device 710 Wiring board 711 Insulating board 712 Connection pad 713 Land 720 Logic chip 722 Surface solder layer 730 Resin member 740 Sealing resin 750 Solder ball 801 Product formation part

Claims (5)

A plurality of semiconductor chips that are stacked to form a semiconductor device,
A substrate,
A first bump electrode formed on one surface of the substrate;
A first positioning bump electrode formed on one surface of the substrate, wherein a height from the one surface of the substrate is higher than a height from the one surface of the substrate of the first bump electrode;
A second bump electrode formed on the other surface of the substrate and electrically connected to the first bump electrode;
A second positioning bump electrode formed on the other surface of the substrate, wherein a height from the other surface of the substrate is higher than a height of the second bump electrode from the other surface of the substrate; Have
The first bump electrode is in contact with the second bump electrode of another semiconductor chip, and the first positioning bump electrode is the second positioning bump electrode of the other semiconductor chip. The semiconductor chip is positioned with the other semiconductor chip by being stacked in a fitted state without colliding with the other semiconductor chip. The semiconductor chip according to claim 1,
At the time of the lamination, at least one of the first positioning bump electrode and the second positioning bump electrode is provided in the bonding portion of each semiconductor chip, and the first positioning bump electrode and the other semiconductor are provided. A semiconductor chip characterized in that the second positioning bump electrode of the chip is positioned with the other semiconductor chip by being brought into a mating state at least at one place. The semiconductor chip according to claim 1,
At the time of stacking, at each semiconductor chip bonding portion, at least two of the first positioning bump electrode and the second positioning bump electrode are provided, and the first positioning bump electrode and the other positioning bump electrodes are provided. A semiconductor chip characterized in that the second positioning bump electrode of the semiconductor chip is positioned with another semiconductor chip by being brought into the combined state at two or more locations. A semiconductor device configured by stacking a plurality of semiconductor chips,
The semiconductor chip is formed on a substrate, a first bump electrode formed on one surface of the substrate, and on one surface of the substrate, and a height from the one surface of the substrate is the first surface. A first positioning bump electrode higher than the height of the bump electrode from one surface of the substrate, and a second electrode formed on the other surface of the substrate and electrically connected to the first bump electrode. A bump electrode and a second positioning formed on the other surface of the substrate, wherein a height from the other surface of the substrate is higher than a height of the second bump electrode from the other surface of the substrate. A bump electrode, and
The first and second semiconductor chips of the plurality of semiconductor chips are stacked,
The first bump electrode of the first semiconductor chip is brought into contact with the second bump electrode of the second semiconductor chip, and the first positioning bump electrode of the first semiconductor chip The first and second semiconductor chips are positioned by being stacked in a fitted state without colliding with the second positioning bump electrode of the second semiconductor chip. A semiconductor device. A method of manufacturing a semiconductor device in which a plurality of semiconductor chips are stacked,
A first bump electrode on a first surface of the substrate and a first positioning electrode having a height higher than the first surface of the first bump electrode than a height of the first bump electrode from the first surface of the substrate. A bump electrode is formed, a second bump electrode electrically connected to the first bump electrode on the other surface of the substrate, and a height from the other surface of the substrate is the second surface. Forming a plurality of semiconductor chips by forming a second positioning bump electrode higher than the height of the bump electrode from the other surface of the substrate;
Placing the second semiconductor chip of the plurality of semiconductor chips on the first semiconductor chip of the plurality of semiconductor chips;
Bringing the first bump electrode of the first semiconductor chip into contact with the second bump electrode of the second semiconductor chip;
By engaging the first positioning bump electrode of the first semiconductor chip without colliding with the second positioning bump electrode of the second semiconductor chip, the first and the first And a step of positioning the semiconductor chip of 2.

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