TW201730996A - 銅柱側壁保護 - Google Patents

銅柱側壁保護 Download PDF

Info

Publication number
TW201730996A
TW201730996A TW106115964A TW106115964A TW201730996A TW 201730996 A TW201730996 A TW 201730996A TW 106115964 A TW106115964 A TW 106115964A TW 106115964 A TW106115964 A TW 106115964A TW 201730996 A TW201730996 A TW 201730996A
Authority
TW
Taiwan
Prior art keywords
passivation layer
metal
conformal passivation
layer
sidewall
Prior art date
Application number
TW106115964A
Other languages
English (en)
Other versions
TWI631635B (zh
Inventor
格蘭 瑞訥
迪安 策恩德
克里斯托佛Ｊ 貝瑞
羅伯特 蘭左訥
路多維科 班寇德
Original Assignee
艾馬克科技公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 艾馬克科技公司 filed Critical 艾馬克科技公司
Publication of TW201730996A publication Critical patent/TW201730996A/zh
Application granted granted Critical
Publication of TWI631635B publication Critical patent/TWI631635B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10145—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11474—Multilayer masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/11831—Reworking, e.g. shaping involving a chemical process, e.g. etching the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H01L2224/11903—Multiple masking steps using different masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13565—Only outside the bonding interface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1357—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/1369—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32238—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/36—Material effects
    • H01L2924/365—Metallurgical effects
    • H01L2924/3651—Formation of intermetallics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

保護銅柱的方法可以包括在半導體晶粒上的接觸上形成金屬柱，其中金屬柱包括側壁。金屬蓋可以形成在金屬柱上並且可以比金屬柱的寬度還寬。焊料凸塊可以形成在金屬蓋上，並且保形鈍化層可以形成在金屬柱的至少側壁上。金屬蓋的截面可以塑形成圓化或矩形。金屬柱和金屬蓋可以包括銅。金屬蓋可以包括銅層和鎳層。種子金屬層可以包括鈦、鎢、銅當中一或更多者。保形鈍化層可以包括不可溼潤的聚合物。保形鈍化層的水平部分可以利用異向性蝕刻(例如電漿蝕刻)而移除。

Description

銅柱側壁保護
本揭示的特定實施例關於半導體晶片封裝。更特定而言，本揭示的特定實施例關於銅柱側壁保護的方法和系統。
半導體封裝保護積體電路或晶片以免於實體損傷和外部應力。附帶而言，它可以提供熱傳導路徑以有效率的移除晶片中所產生的熱，並且舉例而言也提供對其他構件(例如印刷電路板)的電連接。用於半導體封裝的材料典型而言包括陶瓷或塑膠，並且形式因素尤其已經從陶瓷扁平包裝和雙行直插封裝進展到針腳格柵陣列和無引線晶片載體封裝。
熟於此技藝的人士透過習用和傳統做法與如列於本案其他參考圖式的揭示來比較，則此種習用和傳統系統的進一步限制和缺點將變得明顯。
本發明的一方面關於封裝半導體的方法，該方法包括：在半導體晶粒上的接觸上形成金屬柱，該金屬柱包括側壁；在金屬柱上形成焊料凸塊；以及在金屬柱的至少側壁上形成保形鈍化層。
本發明的另一方面關於包括鈍化之側壁柱連接的電子裝置，該鈍化的側壁柱連接包括：金屬柱，其形成在半導體晶粒上的接觸上， 該金屬柱包括側壁；保形鈍化層，其覆蓋金屬柱的至少側壁；以及焊料凸塊，其在金屬柱上。
本發明的另一方面關於半導體封裝的方法，該方法包括：至少藉由以下來形成鈍化的側壁柱連接：在金屬接觸上和在覆蓋部分之金屬接觸的鈍化層上形成種子金屬層；在種子金屬層上形成光阻層；在光阻層中而在部分的金屬接觸上方形成開口；在開口中形成金屬柱，其中金屬柱的高度緊密關聯於光阻層的厚度；在金屬柱上形成焊料凸塊；移除光阻和種子金屬層的暴露部分，其中暴露部分包括未被金屬柱所覆蓋的種子金屬層；在鈍化層、金屬柱、焊料凸塊、金屬接觸之未被金屬種子層之剩餘部分或未被鈍化層所覆蓋的部分上形成保形鈍化層；移除保形鈍化層的水平部分，如此則僅金屬柱的側壁由保形鈍化層所覆蓋；以及包括：藉由在基板上的金屬導線上形成第二保形鈍化層，而形成鈍化的側壁基板導線；使用異向性蝕刻而移除第二保形層的水平部分；以及利用焊料凸塊而將鈍化的側壁柱連接結合到鈍化的側壁基板導線。
本發明的另一方面關於半導體封裝的方法，該方法包括至少藉由以下來形成具有鈍化環的柱連接：在基板上形成光阻層；在光阻層中而在基板上之部分的金屬接觸上方形成開口；在金屬接觸上的開口中形成金屬柱，其中金屬柱的高度小於光阻層的厚度；在光阻層和金屬柱上形成保形鈍化層；移除部分的保形鈍化層，如此則僅鈍化層的環維持在光阻和金屬柱之間的介面；在金屬柱上形成焊料凸塊；以及移除光阻。
本發明的另一方面關於包括鈍化之側壁柱連接的電子裝置，該鈍化的側壁柱連接包括：金屬柱，其形成在半導體晶粒上的接觸上， 該金屬柱包括側壁；焊料凸塊，其在金屬柱上；以及保形鈍化層，其覆蓋金屬柱的至少側壁和部分的焊料凸塊。
本發明的另一方面關於包括鈍化之側壁柱連接的電子裝置，該鈍化的側壁柱連接包括：金屬柱，其形成在半導體晶粒上的接觸上，該金屬柱包括側壁；焊料凸塊，其在金屬柱上；以及保形鈍化層，其在金屬柱和焊料凸塊之間而呈環形。
101‧‧‧晶粒
103‧‧‧囊封劑材料
105‧‧‧柱
107‧‧‧焊料凸塊
109‧‧‧襯墊/導線
111‧‧‧底填材料
113‧‧‧基板
115‧‧‧焊球
117‧‧‧線路後端(BEOL)層
119‧‧‧鈍化層
120‧‧‧結合接面
121‧‧‧BEOL鈍化
123‧‧‧晶粒襯墊
125‧‧‧非導電膏(NCP)
200‧‧‧鈍化的側壁柱
201‧‧‧晶粒/基板
203‧‧‧柱
205‧‧‧凸塊
207‧‧‧保形層
207A‧‧‧腳
300‧‧‧鈍化的側壁柱
301‧‧‧晶粒/基板
303‧‧‧柱
305‧‧‧凸塊
307‧‧‧保形層
307A‧‧‧腳
400‧‧‧鈍化的側壁柱
401‧‧‧晶粒/基板
403‧‧‧桶形柱
405‧‧‧凸塊
407‧‧‧保形層
409‧‧‧光阻層
500‧‧‧鈍化的側壁柱
501‧‧‧晶粒/基板
503‧‧‧柱
505‧‧‧凸塊
507‧‧‧保形層
507A‧‧‧環
509‧‧‧光阻層
600‧‧‧鈍化柱
603‧‧‧柱
605‧‧‧凸塊
607‧‧‧柱側壁鈍化
609‧‧‧蕈菇形頭或蓋子
611‧‧‧接觸
613‧‧‧接觸鈍化
615‧‧‧導線
617‧‧‧導線鈍化
619‧‧‧基板或晶粒
700‧‧‧蕈菇頭之鈍化的側壁柱連接
701‧‧‧接觸
702‧‧‧鈍化層
703‧‧‧柱
704‧‧‧種子層
705‧‧‧凸塊
707‧‧‧光阻層
709‧‧‧蕈菇形蓋子
711‧‧‧保形層
801‧‧‧基板/晶粒
803‧‧‧保形層
815‧‧‧導線
900‧‧‧鈍化側壁釘頭結構
901‧‧‧接觸
902‧‧‧鈍化層
903‧‧‧柱
904‧‧‧種子層
905‧‧‧凸塊
907‧‧‧光阻層
907B‧‧‧第二光阻層
909‧‧‧頭
909A、909B‧‧‧金屬
910‧‧‧鈍化側壁釘頭結構
1001~1019‧‧‧步驟
1101~1121‧‧‧步驟
w1、w2‧‧‧柱的寬度
圖1A是示意圖，其示範依據本揭示的範例性實施例而包括覆晶結合晶粒的模製晶片尺寸封裝。
圖1B和1C顯示關於本揭示的範例性實施例而形成結合接面。
圖2A~2D示範依據本揭示的範例性實施例之鈍化的側壁柱連接之製造步驟。
圖3A~3D示範依據本揭示的範例性實施例之鈍化的側壁柱連接之替代性製造步驟。
圖4A~4C示範依據本揭示的範例性實施例而在柱形成之前的保形層沉積過程。
圖5A~5D示範依據本揭示的範例性實施例之形成具有焊料壩堤的柱結構之步驟。
圖6A~6C示範依據本揭示的範例性實施例之鈍化的側壁柱連接。
圖7A~7N示範依據本揭示的範例性實施例之蕈菇頭鈍化的 側壁柱連接之處理步驟。
圖8A~8D示範依據本揭示的範例性實施例之形成鈍化的側壁導線之過程步驟。
圖9A~9H示範依據本揭示的範例性實施例之釘頭鈍化的側壁柱連接之處理步驟。
圖10是流程圖，其示範依據本揭示的範例性實施例之蕈菇頭鈍化的側壁柱連接之範例性步驟。
圖11是流程圖，其示範依據本揭示的範例性實施例之釘頭鈍化的側壁柱連接之範例性步驟。
本揭示的特定方面可以於銅柱保護中發現。本揭示的範例性方面可以包括：在半導體晶粒上的接觸上形成金屬柱，其中金屬柱包括側壁；在金屬柱上形成金屬蓋，其中金屬蓋比金屬柱的寬度還寬；在金屬蓋上形成焊料凸塊；以及在金屬柱的至少側壁上形成保形鈍化層。金屬蓋可以包括圓化或矩形的截面。焊料凸塊可以接受回焊過程。金屬柱和金屬蓋可以包括銅。金屬蓋可以包括銅層和鎳層。種子金屬層可以包括鈦、鎢、銅當中一或更多者。保形鈍化層可以包括不可溼潤的聚合物。保形鈍化層的水平部分可以利用異向性蝕刻而移除。異向性蝕刻可以包括電漿蝕刻。具有鈍化環的柱連接可以藉由以下而形成：在基板上形成光阻層；在光阻層中而在基板上之部分的金屬接觸上方形成開口；在金屬接觸上的開口中形成金屬柱。金屬柱的高度可以小於光阻層的厚度。保形鈍化層可以形成在光阻層和金屬柱上。可以移除部分的保形鈍化層，如此則僅鈍化層的環 維持在光阻和金屬柱之間的介面。焊料凸塊可以形成在金屬柱上，並且可以移除光阻。
本揭示的其他範例性方面可以包括：在金屬接觸和覆蓋部分之接觸的鈍化層上形成種子金屬層；在種子金屬層上形成光阻層；在光阻層中而在部分的金屬接觸上方形成開口；以及在開口中形成金屬柱，其中金屬柱的高度緊密關聯於光阻層的厚度。金屬蓋可以形成在金屬柱上，其中金屬蓋可以比柱的寬度還寬。焊料凸塊可以形成在金屬蓋上。可以移除光阻和種子金屬層的暴露部分，其中暴露部分可以包括未被金屬柱所覆蓋的種子金屬層。保形鈍化層可以形成在鈍化層、金屬柱、焊料凸塊、金屬蓋之未被焊料凸塊所覆蓋的部分、金屬接觸之未被金屬種子層之剩餘部分或未被鈍化層所覆蓋的部分上。可以移除保形鈍化層的水平部分，如此則僅金屬柱的側壁由保形鈍化層所覆蓋。金屬蓋的截面可以是圓化或矩形。焊料凸塊可以接受回焊過程。金屬柱和金屬蓋可以包括銅。金屬蓋可以包括銅層和鎳層。種子金屬層可以包括鈦、鎢、銅當中一或更多者。保形鈍化層可以包括不可溼潤的聚合物。保形鈍化層的水平部分可以利用異向性蝕刻(其可以包括電漿蝕刻)而移除。
圖1A是示意圖，其示範依據本揭示的範例性實施例而包括覆晶結合晶粒的模製晶片尺寸封裝。參見圖1A，顯示的是晶粒101，其使用多個結合接面120而覆晶結合到基板113。也顯示的是在晶粒101上的囊封劑材料103、柱105、焊料凸塊107、襯墊/導線109、底填材料111、基板113、焊球115、線路後端(back end of line，BEOL)層117。
晶粒101可以包括積體電路晶粒，其已經從半導體晶圓所分 離並且可以包括電路，舉例而言譬如數位訊號處理器(digital signal processor，DSP)、網路處理器、電力管理單元、音訊處理器、射頻(RF)電路、無線基頻單晶片系統(system-on-chip，SoC)處理器、感測器、特殊應用積體電路。
基板113可以包括多層的層合結構，其舉例而言有或沒有核心和焊球115以電連接到外部結構(例如印刷電路板)。基板113也可以包括嵌埋在基板113之中和之上的多個通孔、襯墊、電導線，以在頂面和底面之間提供電連接性，而鈍化層119可以提供電隔離和實體保護給基板113的頂面和底面。
結合接面120可以包括柱105、焊料凸塊107、襯墊/導線109。柱105可以包括形成在晶粒101上的銅柱，以經由基板113而在晶粒101上的裝置和外部結構之間提供電連接性。柱105可以形成在BEOL層117上，其可以包括形成晶粒101之中和之上的導電層和介電層以在晶粒101上的裝置和柱105之間分別提供電連接性和隔離。焊料凸塊107可以包括焊料，其在比柱105和襯墊109還低的溫度下熔化。因此，當壓在一起和加熱時，焊料凸塊107可以在柱105和襯墊109之間形成電和實體結合。
然而，當凸塊107的焊料溼潤到柱105的側邊時，可以發生有關形成結合接面120的問題，如圖1示意圖上方的顯微照片所示。溼潤到側壁可以引起焊料欠缺而造成空洞，這減少結合接面120的可靠度。附帶而言，金屬間化合物的形成可以是非均勻的，其也可以減少接面的可靠度。焊料凸塊107中的錫可以與柱105中的銅反應，藉此窄化柱105。
於範例性情境，柱105的側壁舉例而言可以例如用沉積的鈍 化層或保形的聚合物來保護，如此則來自焊料凸塊107的焊料不溼潤到側壁，而導致柱105和襯墊109之間有均勻的焊料接面，如結合接面120中之幾乎球形的焊料接面所示，這與圖1A示意圖上面的顯微照片成對比。
圖1B和1C關於本揭示的範例性實施例而顯示結合接面的形成。參見圖1B，顯示的是柱105、焊料凸塊107、襯墊109、基板113、BEOL鈍化121、晶粒襯墊123、非導電膏(non-conductive paste，NCP)125。柱105、焊料凸塊107、基板113可以實質類似於相對於圖1A所述的元件。
晶粒襯墊123可以包括形成在晶粒101上的導電襯墊而作為BEOL 117的一部分，其可以藉由BEOL鈍化121而與其他的導電襯墊和導線呈電隔離，該BEOL鈍化舉例而言可以包括氧化物或其他介電材料。
NCP 125可以包括預先施加的底填材料，其幫助形成結合並且當結合時可以填充晶粒和基板之間的剩餘空洞。然而，當壓在一起和加熱時，NCP 125也可以增進焊料凸塊107中的焊料對於柱105之側壁的溼潤，舉例而言由於非均勻的金屬間化合物和形成空洞而導致劣化的接面，如圖1B和1C右邊的顯微照片所示。
目前細微間距的覆晶柱互連乃使用極小體積的焊料來形成對於匹配導線或襯墊的接面。這可以源自於接面之間的極小間隔和在要使用較大體積焊料的地方有短路的危險。前述小體積接面連同焊料對於襯墊和導線的自然溼潤行為則在這些接面引起特定的可靠度問題。特定而言，於接合期間，當焊料熔化並且接觸襯墊或導線時，它將在它所碰觸的表面上自然溼潤(或散開)，如圖1B和1C的顯微照片所示。如果在可以形成無空洞和適當的金屬間化合物之前有太多的小體積從接面分散開來，則這可以 使緊鄰的接面區域變成「極缺焊料的」(solder starved)。這可以導致大致有缺陷的接面，其在例如溫度循環或高溫儲存的應力測試下表現不良，這轉而可以避免產品合格或限制產品的服務壽命。
習用的過程可能嘗試使NCP 125的使用最佳化以避免焊料溼潤，但這是沒有產生結構貢獻以正面免除流出可能性的被動做法。於本揭示的範例性實施例，鈍化的側壁柱連接可以利用一層可識別的鈍化材料，其添加到柱連接的側壁，而可以顯著的要比NCP最佳化或表面處理還有效。
圖2A~2D示範依據本揭示的範例性實施例之鈍化的側壁柱連接的製造步驟。參見圖2A，顯示的是製造在晶粒/基板201上之鈍化的側壁柱200，其包括柱203和凸塊205而具有保形層207。柱203可以包括銅柱，舉例而言類似於圖1A~1C的柱103，以提供對晶粒/基板201中之裝置的電接觸。晶粒/基板201舉例而言可以包括半導體晶粒或基板，例如矽互補金屬氧化物半導體(CMOS)晶粒/基板，而具有積體電路和/或裝置。
凸塊205舉例而言可以包括焊料，其在比柱203還低的溫度下熔化，並且提供對另一柱或其他接觸的電和實體連接。
保形層207舉例而言可以包括不可溼潤的聚合物，例如聚對二甲苯，其可以保形的沉積在柱203和凸塊205的所有表面上。以此方式，晶粒/基板201的頂面與柱203和凸塊205的暴露表面可以由聚合物所覆蓋。保形層207可以沉積在完成的柱結構上或在稍早階段(例如在凸塊205回焊之前)就沉積。
乾淨的銅表面與一類的化學品反應，該類化學品例如唑化合 物，其常常稱為有機可焊性保存劑(organic solderability preservative，OSP)。OSP藉由形成層化的有機/離子性Cu表面而保護銅來抵抗氧化。最早的OSP是苯并三唑，其提供有限的溫度抵抗性和保護來抵抗氧化。現代的OSP配方來自取代的苯并咪唑(烷基苯并咪唑)和取代的咪唑(芳苯基咪唑)的化學家族，其在銅上形成明確的層化膜，而允許暴露在較高溫度而不分解，並且可以使用於無鉛焊料。OSP可以阻礙或避免錫在柱表面做表面擴散，並且可以阻礙或避免錫擴散到柱表面上之未反應的銅。
雖然暴露的銅於銅柱處理期間形成氧化銅，不過這些氧化物於回焊期間由助熔劑所剝除。於範例性情境，無機的銅表面化合物可以由保形層207所形成，其不被助熔劑或非導電膏的助熔成分所剝除。這無機銅表面保護舉例而言可以與其他結構(例如銅釘頭結構或鎳阻障)組合，以使焊料擴散和消耗減到最少。
於範例性情境，柱203的側壁除外，可以利用異向性蝕刻而從每個表面來移除保形層207。異向性蝕刻舉例而言可以包括乾式蝕刻，例如氧電漿蝕刻過程，其在垂直方向蝕刻而不在側向蝕刻，或者至少在低很多的速率下做側向蝕刻。溼式化學蝕刻可以用於保形層對於給定的蝕刻劑展現異向性蝕刻之例子。
蝕刻過程可以導致圖2B所示的結構，其中已經剝除保形層207的水平表面而留下聚合物在柱203的側壁上，也留下「腳」(feet)207A在柱203的基底以及柱203和凸塊205的接面。腳207A可以於後續種子金屬蝕刻期間保護抵抗底切。
一旦熔化和結合到另一接觸，則剩餘的保形層207可以免除 柱203上有側壁溼潤，而導致有想要的柱連接，如圖1C所示，而不需要NCP，雖然如果想要的話NCP可以用於結合過程。
圖2C和2D是依據本揭示的範例性實施例之鈍化側壁柱的顯微照片。參見圖2C，顯示的是鈍化之側壁柱200的俯視圖，其顯示暴露的凸塊205。圖2D顯示鈍化之側壁柱200的斜視圖，其顯示暴露的凸塊205，其中已經移除保形層207並且剩餘的保形層207在柱205的側壁上。附帶而言，在保形層的底部看到腳207A。
圖3A~3D示範依據本揭示的範例性實施例之鈍化的側壁柱連接的替代性製造步驟。參見圖3A，顯示的是製造在晶粒/基板301上之鈍化的側壁柱300，其包括柱303和凸塊205而具有保形層307。柱303和晶粒/基板301可以類似於相對於圖2A~2D所述的柱203和晶粒/基板301。凸塊305可以類似於圖2的凸塊205，但是在造成圓化形狀的回焊過程之前。
凸塊305舉例而言可以包括焊料，其在比柱303還低的溫度下熔化，並且提供對於另一柱或其他接觸的電和實體連接。
保形層307舉例而言可以包括不可溼潤的聚合物，例如聚對二甲苯，其可以保形的沉積在柱303和凸塊305的所有表面上。以此方式，晶粒/基板301的頂面以及柱303和凸塊305的暴露表面可以由聚合物所覆蓋。保形層307可以在用於形成凸塊305的鍍覆和光阻剝除步驟之後但在回焊步驟之前而沉積在柱303和凸塊305上，這就是為何凸塊在這階段顯示成矩形截面。
於範例性情境，柱303的側壁除外，可以利用異向性蝕刻而 從每個表面移除保形層307。異向性蝕刻舉例而言可以包括溼式化學蝕刻或乾式蝕刻(例如電漿蝕刻過程)。
蝕刻過程可以導致圖3B所示的結構，其中已經剝除保形層307的水平表面而留下聚合物在柱303的側壁上，也留下腳307A在柱303的基底以及柱303和凸塊305的接面。腳307A可以於後續種子金屬蝕刻期間保護抵抗底切。
圖3C和3D示範依據本揭示的範例性情境而在回焊之後的鈍化側壁柱。在圖3B所示的異向性蝕刻之後的柱結構可以接受回焊過程，其熔化凸塊而導致圓化的形狀，如圖3C所示。保形層307維持在柱303的垂直側壁上。在回焊時，接觸凸塊305的聚合物可以維持成附著於凸塊305中的氧化錫，其因此避免被後續助熔過程所減少並且符合熔化焊料的形狀。
一旦熔化和結合到另一接觸，剩餘的保形層307可以免除柱303上的側壁溼潤，而造成想要的柱連接，如圖1C所示，但不需要NCP，雖然如果想要的話NCP可以用於結合過程。
圖3D是顯微照片，其顯示在回焊之後所得的鈍化側壁柱300，其具有回焊後的凸塊305和已符合凸塊形狀的剩餘保形層307。剩餘的保形層307可以於後續對於另一接觸的結合過程期間作為側壁溼潤的阻礙。
圖4A~4C示範依據本揭示的範例性實施例而在柱形成之前的保形層沉積過程。參見圖4A，顯示的是晶粒/基板401、光阻層409、保形層407。晶粒/基板401和保形層407可以類似於之前所述的晶粒/基板301和保形層307。
光阻層409可以包括光阻，其已經形成在晶粒/基板401上、圖案化、顯影、在要形成鈍化側壁柱的區域加以移除。保形層407然後可以沉積在圖案化的光阻層409上，而導致圖4A所示的結構。異向性蝕刻可以進行在保形層407上，藉此移除聚合物的水平表面，而在光阻層409裡僅留下垂直側壁。
圖案化的光阻層409可以提供圓柱形體積，其中舉例而言可以利用鍍覆過程而形成金屬以在該體體裡形成柱。舉例而言，可以利用鍍覆銅和焊料鍍覆過程以在圖案化的光阻層409中形成柱和凸塊，使得剩餘的保形層部分延伸到沉積之凸塊金屬的側面，接著再做回焊過程和光阻剝除，而造成鈍化的側壁柱，如圖4C所示。也可以利用其他適合的金屬形成過程，例如蒸鍍、化學氣相沉積……。於另一範例性情境，圖4A~4C所述的過程可以導致「桶」(barrel)形柱403，其在柱的中間較寬而在頂部和底部較窄。
圖4C顯示依據本揭示的範例性實施例而形成有保形層之鈍化的側壁柱，該保形層在柱形成之前就沉積。如圖4C所示，保形層407維持在柱403的垂直側壁上並且部分上到凸塊405的側面。亦類似於圖3C和3D，保形層407可以附著於凸塊405中的氧化錫，因此符合回焊焊料的形狀，而導致類似於圖3C和3D所示的結構。
圖5A~5D示範依據本揭示的範例性實施例來形成具有焊料壩堤之柱結構的步驟。參見圖5A，顯示的是晶粒/基板501、柱503、保形層507、光阻層509。晶粒/基板501、柱503、保形層507可以類似於之前討論的晶粒/基板、柱、保形層。
圖5A顯示的結構是在光阻已經沉積在晶粒/基板501上並且圖案化成具有要形成柱的開口之後。而且，已經進行金屬鍍覆過程以填充光阻層509中的暴露區域，而造成柱503。舉例而言，金屬可以包括銅或其他想要的接觸金屬。
最後，保形層507可以沉積在光阻層509和柱503上，而導致圖5A所示的結構。可以進行(溼式或乾式)異向性蝕刻過程以從水平表面移除保形層507。因為蝕刻離子的軌跡不都是垂直的，所以靠近光阻層509之側壁的聚合物可以受到一些保護而蝕刻得較慢，故角落最後才清除。因此，角落可以保持原封不動，而在柱503的頂部留下保形層507的環507A。
焊料可以鍍覆在暴露的柱503和保形層環507A上以形成焊料凸塊，在此之後可以移除光阻層509，並且鍍覆的焊料金屬可以接受回焊過程，而導致如圖5C所示的凸塊505。環507A中剩餘的保形層可以維持經過這些過程，而形成柱503上的焊料溼潤之阻障，而不必完全覆蓋柱503的側壁。
圖6A~6C示範依據本揭示的範例性實施例之鈍化的側壁柱連接。參見圖6A、顯示的是鈍化柱600，其包括柱603、凸塊605、柱側壁鈍化607、「蕈菇形頭」(mushroom shaped head)或蓋子609、接觸611、接觸鈍化613。鈍化柱600的「蕈菇頭」形狀源自圖7A~7H所示的過程步驟，其中圓柱603要比蓋子609窄，而蓋子當從結構上方來看時是圓形。應注意蓋子609是可選用的，並且凸塊605可以直接形成在柱603上。
接觸611可以包括形成在積體電路晶粒或基板上的金屬襯墊，而鈍化柱600對此提供接觸；鈍化層613可以包括介電材料而提供電隔 離和實體保護給接觸611。
柱側壁鈍化607可以包括保形鈍化層，例如相對於圖2~5所述者，並且舉例而言可以包括聚合物材料。當鈍化柱600結合於另一接觸(例如圖6B和6C所示的導線615，其舉例而言可以包括在基板或晶粒619上的銅導線)，柱側壁鈍化607可以免除側壁溼潤。
圖6B示範鈍化柱600結合於沒有側壁鈍化的導線615。雖然柱側壁鈍化607避免焊料於結合期間溼潤到柱603，如回焊之後在柱603和導線615之間所良好形成的凸塊605所示，不過仍有可能溼潤到導線615的側邊。
凸塊605對導線615的溼潤可以藉由添加鈍化層到導線而避免，如此則接觸的二側都會具有鈍化側壁，並且僅有蓋子609和導線615的暴露金屬會於回焊期間被凸塊605所溼潤，如圖6C的所得結構所示。
圖7A~7N示範依據本揭示的範例性實施例之蕈菇頭鈍化側壁柱連接的處理步驟。參見圖7A，顯示的是要形成柱連接的接觸701以及電隔離和提供實體保護給接觸701的鈍化層702。
於圖7B，種子層可以沉積在接觸701的暴露部分上和在鈍化層702上。種子層704可以包括金屬合金，其增進柱(例如銅柱)對接觸701的電接觸。於範例性情境，種子層704可以包括薄層的濺鍍鈦、鎢、銅(譬如TiW層和Cu層)，雖然可以利用其他的金屬和沉積技術。
圖7C示範的結構是在已經施加光阻層707並且圖案化而做出暴露部分的接觸701之後。光阻層707可以旋塗上去、透過遮罩圖案而暴露於紫外光(UV)、顯影以提供所示的圖案化光阻層707。然後可以進行金屬 鍍覆過程，而填充圖案化光阻層707並且在接觸701的暴露部分上形成柱703，如圖7D所示。據此，光阻層707的厚度可以建構成控制所得柱703的高度。
蕈菇鍍覆可以進行在圖7D所示的結構上，其中銅舉例而言可以鍍覆在柱703的暴露表面和部分的光阻層707上，而在圓柱703的頂部上形成圓化的「蕈菇形」蓋子709，如圖7E所示。可以進行第二蕈菇鍍覆，而導致如圖7F所示範的凸塊705。凸塊705舉例而言可以包括焊料，其在比柱703和蓋子709還低的溫度下熔化。應注意蓋子709是可選用的，並且凸塊705可以直接形成在柱703上。
可以移除光阻層707以暴露未被柱703所覆蓋的種子層704，並且也暴露柱703的側壁以及凸塊705和蓋子709的底側，如圖7G所示。其次，種子層704的暴露部分舉例而言可以經由蝕刻來移除，而暴露接觸701之未被柱703和剩餘種子層704所覆蓋的頂面，並且也暴露鈍化層702的頂面，如圖7H所示範。附帶而言，種子層704可以可選用的被過度蝕刻，藉此減少柱703的寬度，如此則w2<w1。
回焊過程可以圓化蓋子709上之凸塊705的形狀，而導致圖7I所示的結構。接觸701、鈍化702、柱703、凸塊705、蓋子709的暴露表面然後可以用保形層711來披覆，其可以類似於之前所述的保形層，並且舉例而言可以包括聚合物。所得的結構顯示於圖7J。
然後可以利用異向性蝕刻以移除保形層711的水平表面，如圖7K所示範而導致圖7L所示的結構。異向性蝕刻舉例而言可以包括溼式化學蝕刻或乾式蝕刻(例如電漿蝕刻)，其在垂直方向蝕刻而不在側向蝕刻， 或者至少在低很多的速率下做側向蝕刻。於另一範例性情境，可以跳過上面圖7H所述的種子層蝕刻，直到圖7K所示的保形鈍化做蝕刻之後才為之，藉此留下部分的種子層704，如圖7M所示。在柱703之直徑外的剩餘種子層704可以導致有較大的表面積而改善電接觸和增加所得結合的實體強度。
於又一範例性情境，保形鈍化層711可以比蓋子709在柱703上延伸的寬度還窄，使得該層遵循蓋子709和種子層704之水平表面的輪廓，如圖7N所示。於這範例，因為蓋子709的高度要比其他所示的實施例還高，所以保形層711也覆蓋蓋子709的側表面。
此外，圖7N所示的保形層可以在不同於之前所述的沉積/異向性蝕刻過程中形成。於替代性過程，保形層711可以利用之前所述的OSP和相關的化合物而直接形成在柱703和/或蓋子709的暴露銅表面上，例如這是當結構是如圖7I所示時。
圖8A~8D示範依據本揭示的範例性實施例之形成鈍化側壁導線的過程步驟。參見圖8A，顯示的是在基板/晶粒801上的導線815。導線815舉例而言可以包括銅導線以提供對於上面形成了它之基板或晶粒的電連接。基板/晶粒801舉例而言可以包括封裝基板、半導體晶粒、插置晶粒或晶圓、或印刷電路板，其包括導線815所要耦合的裝置和/或互連而要連接到外部裝置。
導線815和基板/晶粒801的暴露部分可以由保形層803所覆蓋，如圖8B所示。保形層803可以類似於之前所述的保形層，並且於範例性情境，其包括聚合物層而避免焊料溼潤它所覆蓋的表面。
然後可以利用異向性蝕刻以移除保形層803的水平表面，如 圖8C所示範，而導致圖8D所示的結構。異向性蝕刻舉例而言可以包括溼式化學蝕刻或乾式蝕刻(例如電漿蝕刻)，其在垂直方向蝕刻而不在側向蝕刻，或者至少在低很多的速率下做側向蝕刻。圖8D之剩餘的保形層803覆蓋導線815的側壁，而避免當結合於焊料凸塊和接受回焊過程時造成側壁溼潤。
圖9A~9H示範依據本揭示的範例性實施例之釘頭鈍化側壁柱連接的處理步驟。參見圖9A，顯示的是要形成柱連接的接觸901以及電隔離和提供實體保護給接觸901的鈍化層902。
於圖9B，種子層可以沉積在接觸901的暴露部分上和在鈍化層902上。種子層904可以包括金屬合金，其增進柱(例如銅柱)對於接觸901的電接觸。於範例性情境，種子層904可以包括薄層的濺鍍鈦、鎢、銅(譬如TiW層和Cu層)，雖然可以利用其他的金屬和沉積技術。
圖9C示範的結構是在已經施加光阻層907並且圖案化成暴露部分的接觸901之後。光阻層907可以旋塗上去、透過遮罩圖案而暴露於UV光、顯影以提供所示的圖案化光阻層907。然後可以進行金屬鍍覆過程，譬如銅或錫/銀，其填充圖案化的光阻層907並且在接觸901的暴露部分上形成柱903，如圖9D所示。據此，光阻層907的厚度可以建構成控制所得柱903的高度。
第二光阻層907B可以形成在光阻層907上，並且圖案化以在柱903上留下開口，其寬度比柱還寬，如圖9E所示。可以進行一或更多個鍍覆步驟，而填充在柱上方和部分在光阻層907上的區域。圖9F~9H顯示二個平行的過程，左邊的結構具有單一鍍覆步驟(例如銅鍍覆)，而導致圖 9F左方所示的「釘頭」(nail head)結構，其中頭909的截面可以是矩形並且當往下看時是圓形。類似而言，二步驟的鍍覆過程(例如銅/鎳鍍覆過程)也可以填充在柱903和光阻層907上的區域，而導致圖9F右方所示的釘頭或金屬蓋結構，但其具有二個金屬909A和909B。應注意蓋金屬909和909A/909B是可選用的，並且凸塊905可以直接形成在柱903上。
可以在圖9F的釘頭結構上進行焊料鍍覆過程，而導致如圖9G所示範的凸塊905。凸塊905舉例而言可以包括焊料，其在比柱903和蓋子909/909A/909B還低的溫度下熔化。
可以移除光阻層907以暴露未被柱903所覆蓋的種子層904，並且也暴露柱903的側壁以及凸塊905和蓋子909/909B的底側，其類似於圖7G。其次，種子層904的暴露部分舉例而言可以經由蝕刻來移除，而暴露接觸901之未被柱903和剩餘種子層904所覆蓋的頂面，並且也暴露鈍化層902的頂面，其類似於圖7H所示的結構。附帶而言，種子層904可以可選用的被過度蝕刻，藉此減少柱903的寬度。
回焊過程可以圓化在蓋子909/909A/909B上之凸塊905的形狀。接觸901、鈍化902、柱903、凸塊905、蓋子909/909A/909B的暴露表面然後可以用保形層來披覆，其可以類似於之前所述的保形層，並且舉例而言可以包括聚合物。所得的結構可以類似於圖7J所示者。
然後可以利用異向性蝕刻以移除保形層的水平表面，而導致圖9H所示的鈍化側壁釘頭結構900和910。異向性蝕刻舉例而言可以包括溼式化學蝕刻或乾式蝕刻(例如電漿蝕刻)，其在垂直方向蝕刻而不在側向蝕刻，或者至少在低很多的速率下做側向蝕刻。
圖10是流程圖，其示範依據本揭示的範例性實施例之蕈菇頭鈍化側壁柱連接的範例性步驟。圖10所述的過程舉例而言可以對應於相對於圖7A~7L所述的過程。於第一步驟1001，種子層可以沉積在接觸和部分覆蓋接觸的鈍化層上。於步驟1103，光阻圖案可以形成在種子層上，而開口形成在部分的接觸上。
於步驟1005，金屬鍍覆過程(例如銅鍍覆)可以填充光阻圖案中的開口以形成柱，使得柱的高度可以緊密關聯於光阻厚度。於步驟1007，另一鍍覆步驟可以在柱上形成蕈菇形狀的蓋子；而於步驟1009，焊料鍍覆可以在形成的柱和蕈菇頭上形成焊料凸塊。
於步驟1011，可以移除光阻層並且可以蝕刻暴露的種子層。於範例性情境，種子層可以過度蝕刻，導致柱有較小的直徑，而增加蕈菇頭和柱直徑之間的高寬比。
於步驟1013，焊料可以接受回焊過程，而導致在柱的頂部上有更圓化的結構；接著在步驟1015做保形層沉積，該保形層包括聚合物或類似的材料以避免焊料溼潤在柱側壁上。保形層可以覆蓋光阻剝除和種子層蝕刻所暴露的所有表面，例如蕈菇頭、柱、接觸、鈍化層。
於步驟1017，然後可以利用異向性蝕刻以移除保形層的水平表面，而導致鈍化側壁之蕈菇頭形的柱結構。異向性蝕刻舉例而言可以包括溼式化學蝕刻或乾式蝕刻(例如電漿蝕刻)，其在垂直方向蝕刻而不在側向蝕刻，或者至少在低很多的速率下做側向蝕刻。
於步驟1019，鈍化側壁之蕈菇形狀的柱可以結合到另一接觸，例如基板導線，其中在柱側壁上的保形層避免焊料於回焊期間溼潤。
圖11是流程圖，其示範依據本揭示的範例性實施例之釘頭鈍化側壁柱連接的範例性步驟。圖11所述的過程舉例而言可以對應於相對於圖9A~9H所述的過程。於第一步驟1101，種子層可以沉積在接觸和部分覆蓋接觸的鈍化層上。於步驟1103，光阻圖案可以形成在種子層上，而開口形成在部分的接觸上。
於步驟1105，金屬鍍覆過程(例如銅鍍覆)可以填充光阻圖案中的開口以形成柱，使得柱的高度可以緊密關聯於光阻厚度。於步驟1107，另一光阻圖案可以形成在第一光阻層上，而柱上方有開口並且延伸於第一光阻層上。
於步驟1109，第二鍍覆步驟可以在柱上形成「釘頭」，其中釘頭可以包括如之前所述的二層；而於步驟1111，焊料鍍覆可以在形成的柱和釘頭上形成焊料凸塊。
於步驟1113，可以移除光阻層並且可以蝕刻暴露的種子層。於範例性情境，種子層可以過度蝕刻，導致柱有較小的直徑，而增加釘頭和柱直徑之間的高寬比。
於步驟1115，焊料可以接受回焊過程，而導致在柱的頂部上有更圓化的結構；接著在步驟1117做保形層沉積，該保形層包括聚合物或類似的材料以避免焊料溼潤在柱側壁上。保形層可以覆蓋光阻剝除和種子層蝕刻所暴露的所有表面，例如釘頭、柱、接觸、鈍化層。
於步驟1119，然後可以利用異向性蝕刻以移除保形層的水平表面，而導致鈍化側壁之釘頭形的柱結構。異向性蝕刻舉例而言可以包括溼式化學蝕刻或乾式蝕刻(例如電漿蝕刻)，其在垂直方向蝕刻而不在側向 蝕刻，或者至少在低很多的速率下做側向蝕刻。
於步驟1121，鈍化側壁釘頭柱可以結合到另一接觸，例如基板導線，其中柱側壁上的保形層避免焊料於回焊期間溼潤。
於本揭示的實施例，方法和系統乃針對銅柱保護來揭示。就此而言，本揭示的諸多方面可以包括：在半導體晶粒上的接觸上形成金屬柱，其中金屬柱包括側壁；在金屬柱上形成金屬蓋，其中金屬蓋比金屬柱的寬度還寬；在金屬蓋上形成焊料凸塊；以及在金屬柱的至少側壁上形成保形鈍化層。金屬蓋可以包括圓化的矩形截面。焊料凸塊可以接受回焊過程。金屬柱和金屬蓋可以包括銅。金屬蓋可以包括銅層和鎳層。種子金屬層可以包括鈦、鎢、銅當中一或更多者。保形鈍化層可以包括不可溼潤的聚合物。保形鈍化層的水平部分可以利用異向性蝕刻而移除。異向性蝕刻可以包括電漿蝕刻。
於本揭示的實施例，方法和系統乃針對銅柱保護來揭示。就此而言，本揭示的諸多方面可以包括：在金屬接觸和覆蓋部分之接觸的鈍化層上形成種子金屬層；在種子金屬層上形成光阻層；在光阻層中而在部分的金屬接觸上方形成開口；以及在開口中形成金屬柱。金屬柱的高度可以緊密關聯於光阻層的厚度。金屬蓋可以形成在金屬柱上，其中金屬蓋可以比柱的寬度還寬。
焊料凸塊可以形成在金屬蓋上。可以移除光阻和種子金屬層的暴露部分，其中暴露部分可以包括未被金屬柱所覆蓋的種子金屬層。保形鈍化層可以形成在鈍化層、金屬柱、焊料凸塊、金屬蓋之未被焊料凸塊所覆蓋的部分、金屬接觸之未被金屬種子層的剩餘部分或未被鈍化層所覆 蓋的部分上。可以移除保形鈍化層的水平部分，如此則僅金屬柱的側壁由保形鈍化層所覆蓋。
金屬蓋的截面可以是圓形或矩形。焊料凸塊可以接受回焊過程。金屬柱和金屬蓋可以包括銅。金屬蓋可以包括銅層和鎳層。種子金屬層可以包括鈦、鎢、銅當中一或更多者。保形鈍化層可以包括不可溼潤的聚合物。保形鈍化層的水平部分可以利用異向性蝕刻(其可以包括電漿蝕刻)而移除。
具有鈍化環的柱連接可以藉由以下而形成：在基板上形成光阻層；在光阻層中而在基板上之部分的金屬接觸上方形成開口；在金屬接觸上的開口中形成金屬柱。金屬柱的高度可以小於光阻層的厚度。保形鈍化層可以形成在光阻層和金屬柱上。可以移除部分的保形鈍化層，如此則僅鈍化層的環維持在光阻和金屬柱之間的介面。焊料凸塊可以形成在金屬柱上，並且可以移除光阻。
雖然本揭示已經參考特定的實施例來描述，不過熟於此技藝者將了解可以做出多樣的改變並且可以用等同者來取代，而不偏離本揭示的範圍。附帶而言，可以做出許多修改以使特殊的情況或材料適合本揭示的教導，而不偏離其範圍。因此，本揭示打算不限於所揭示的特殊實施例，本揭示而是將包括落於所附請求項範圍裡的所有實施例。
600‧‧‧鈍化柱
603‧‧‧柱
605‧‧‧凸塊
607‧‧‧柱側壁鈍化
609‧‧‧蕈菇形頭或蓋子
611‧‧‧接觸
613‧‧‧接觸鈍化

Claims (21)

  1. 一種用於半導體封裝的方法，該方法包括：在半導體晶粒上的接觸上形成金屬柱，該金屬柱包括側壁；在該金屬蓋上形成焊料凸塊使得該焊料凸塊直接地接觸該金屬柱；以及在該金屬柱的至少該側壁上形成保形鈍化層。
  2. 根據申請專利範圍第1項的方法，其中前述形成該保形鈍化層包含：在該焊料凸塊和該金屬柱的該側壁上沉積該保形鈍化層；以及從該焊料凸塊的上表面移除該保形鈍化層，而保留該保形鈍化層於該金屬柱的該側壁上。
  3. 根據申請專利範圍第1項的方法，其中前述形成該保形鈍化層包含：在該焊料凸塊和該金屬柱的該側壁上沉積該保形鈍化層；以及利用異向性蝕刻製程從該焊料凸塊的上表面移除該保形鈍化層，而保留該保形鈍化層於該金屬柱的該側壁上。
  4. 根據申請專利範圍第1項的方法，其中前述形成該保形鈍化層包含：在該焊料凸塊和該金屬柱的該側壁上沉積該保形鈍化層；以及從該焊料凸塊的上表面移除該保形鈍化層，然而保留該保形鈍化層於該金屬柱的該側壁上、於該焊料凸塊的至少一部份上以及於該金屬柱和該焊料凸塊之間的接合處上。
  5. 根據申請專利範圍第1項的方法，其中：前述形成該焊料凸塊包含回流焊料直接地接觸該金屬柱以形成該焊料凸塊；以及 前述形成該保形鈍化層包含在前述回流之後沉積該保形鈍化層於該焊料凸塊上以及於該金屬柱的該側壁上。
  6. 根據申請專利範圍第1項的方法，其中：前述形成該保形鈍化層包含沉積該保形鈍化層於焊料上直接地接觸該金屬柱並且於該金屬柱的該側壁上；以及前述形成該焊料凸塊包含在前述沉積之後回流該焊料以形成該焊料凸塊直接地在該金屬柱上。
  7. 根據申請專利範圍第1項的方法，其中前述形成該保形鈍化層包含：沉積該保形鈍化層於焊料上直接地接觸該金屬柱並且於該金屬柱的側壁上；從該焊料的上表面移除該保形鈍化層，而保留該保形鈍化層於該金屬柱的該側壁上；以及在前述沉積和移除之後，回流該焊料以形成該焊料凸塊直接地在該金屬柱上，使得該保形鈍化層附接至該焊料凸塊的一部份。
  8. 根據申請專利範圍第1項的方法，其中前述形成該保形鈍化層包含沉積不可溼潤的聚合物於該金屬柱的側壁上。
  9. 根據申請專利範圍第1項的方法，其中前述形成該保形鈍化層包含沉積聚對二甲苯於該金屬柱的側壁上。
  10. 根據申請專利範圍第1項的方法，其中前述形成該金屬柱包含由銅形成該金屬柱。
  11. 一種電子裝置，該電子裝置包含：半導體晶粒，其包含積體電路； 金屬柱，其包含下表面，該下表面經由該半導體晶粒的接觸而耦合到該積體電路；焊料凸塊，其直接地接觸該金屬柱的上表面；以及保形鈍化層，其覆蓋至少該金屬柱的側壁，其中該側壁鄰接該金屬柱的該上表面到該金屬柱的該下表面。
  12. 根據申請專利範圍第11項的裝置，其中該金屬柱包含銅。
  13. 根據申請專利範圍第11項的裝置，其中該保形鈍化層包含不可溼潤的聚合物。
  14. 根據申請專利範圍第11項的裝置，其中該保形鈍化層包含聚對二甲苯。
  15. 根據申請專利範圍第11項的裝置，其中該保形鈍化層覆蓋至少該焊料凸塊的一部份並且覆蓋該焊料凸塊和該金屬柱之間的接合處。
  16. 根據申請專利範圍第11項的裝置，其中該保形鈍化層覆蓋至少該焊料凸塊的一部份、該半導體晶粒的接觸以及該焊料凸塊和該金屬柱之間的接合處。
  17. 根據申請專利範圍第11項的裝置，其中該焊料凸塊包含凸出的上表面和平坦的下表面，該下表面直接地接觸該金屬柱的該上表面。
  18. 根據申請專利範圍第17項的裝置，其中該保形鈍化層沒有覆蓋該焊料凸塊的凸出的上表面。
  19. 根據申請專利範圍第17項的裝置，其中該保形鈍化層覆蓋該凸出的上表面的一部份。
  20. 根據申請專利範圍第11項的裝置，其中保形鈍化層包含有機可焊性 保存劑。
  21. 根據申請專利範圍第11項的裝置，其中：該焊料凸塊包含上表面和下表面，該下表面直接地接觸該金屬柱的上表面；以及該保形鈍化層接觸該焊料凸塊。
TW106115964A 2014-05-23 2015-04-27 銅柱側壁保護 TWI631635B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/286,263 US9875980B2 (en) 2014-05-23 2014-05-23 Copper pillar sidewall protection
US14/286,263 2014-05-23

Publications (2)

Publication Number Publication Date
TW201730996A true TW201730996A (zh) 2017-09-01
TWI631635B TWI631635B (zh) 2018-08-01

Family

ID=54556612

Family Applications (2)

Application Number Title Priority Date Filing Date
TW104113369A TWI595576B (zh) 2014-05-23 2015-04-27 銅柱側壁保護
TW106115964A TWI631635B (zh) 2014-05-23 2015-04-27 銅柱側壁保護

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW104113369A TWI595576B (zh) 2014-05-23 2015-04-27 銅柱側壁保護

Country Status (3)

Country Link
US (1) US9875980B2 (zh)
KR (2) KR20150135127A (zh)
TW (2) TWI595576B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI701791B (zh) * 2018-12-27 2020-08-11 南亞科技股份有限公司 半導體結構及其製造方法
US11127704B2 (en) 2017-11-28 2021-09-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with bump structure and method of making semiconductor device

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016064350A1 (en) * 2014-10-23 2016-04-28 Agency For Science, Technology And Research Method of bonding a first substrate and a second substrate
US9431335B2 (en) * 2014-10-24 2016-08-30 Dyi-chung Hu Molding compound supported RDL for IC package
US9564409B2 (en) * 2015-01-27 2017-02-07 Semiconductor Components Industries, Llc Methods of forming semiconductor packages with an intermetallic layer comprising tin and at least one of silver, copper or nickel
KR102462505B1 (ko) 2016-04-22 2022-11-02 삼성전자주식회사 인쇄회로기판 및 반도체 패키지
US10217712B2 (en) 2016-12-16 2019-02-26 Advanced Semiconductor Engineering, Inc. Semiconductor package and semiconductor process for manufacturing the same
US11014806B2 (en) * 2017-05-18 2021-05-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
US10636758B2 (en) * 2017-10-05 2020-04-28 Texas Instruments Incorporated Expanded head pillar for bump bonds
US10304697B2 (en) 2017-10-05 2019-05-28 Amkor Technology, Inc. Electronic device with top side pin array and manufacturing method thereof
CN110610916B (zh) * 2018-06-14 2021-12-24 通富微电子股份有限公司 封装结构
US10784222B2 (en) * 2018-10-31 2020-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-bump sidewall protection
US11094656B2 (en) * 2018-12-31 2021-08-17 Texas Instruments Incorporated Packaged semiconductor device with electroplated pillars
DE102019103355A1 (de) * 2019-02-11 2020-08-13 Infineon Technologies Ag Halbleitervorrichtung mit einer Kupfersäule-Zwischenverbindungsstruktur
KR20210024869A (ko) 2019-08-26 2021-03-08 삼성전자주식회사 반도체 칩 적층 구조, 반도체 패키지 및 이들의 제조 방법
US11417539B2 (en) 2020-02-27 2022-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Bump structure and method of making the same
DE102020129570A1 (de) * 2020-02-27 2021-09-02 Taiwan Semiconductor Manufacturing Co., Ltd. Bumpstruktur und verfahren zu deren herstellung
US11276659B2 (en) * 2020-02-28 2022-03-15 Micron Technology, Inc. Methods for forming elements for microelectronic components, related conductive elements, and microelectronic components, assemblies and electronic systems incorporating such conductive elements
US11380641B2 (en) 2020-11-04 2022-07-05 International Business Machines Corporation Pillar bump with noble metal seed layer for advanced heterogeneous integration
US11694982B2 (en) 2021-02-25 2023-07-04 Qualcomm Incorporated Sidewall wetting barrier for conductive pillars
US11978698B2 (en) * 2021-04-23 2024-05-07 Changxin Memory Technologies, Inc. Method for forming a semiconductor package structure
US20240096845A1 (en) * 2022-09-21 2024-03-21 Qualcomm Incorporated Circuit packages with bump interconnect polymer surround and method of manufacture

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3968554B2 (ja) * 2000-05-01 2007-08-29 セイコーエプソン株式会社 バンプの形成方法及び半導体装置の製造方法
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
JP3851607B2 (ja) * 2002-11-21 2006-11-29 ローム株式会社 半導体装置の製造方法
US20090233436A1 (en) * 2008-03-12 2009-09-17 Stats Chippac, Ltd. Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP Coating
WO2010075447A1 (en) 2008-12-26 2010-07-01 Megica Corporation Chip packages with power management integrated circuits and related techniques
US8592995B2 (en) 2009-07-02 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for adhesion of intermetallic compound (IMC) on Cu pillar bump
US8207453B2 (en) 2009-12-17 2012-06-26 Intel Corporation Glass core substrate for integrated circuit devices and methods of making the same
US8637392B2 (en) 2010-02-05 2014-01-28 International Business Machines Corporation Solder interconnect with non-wettable sidewall pillars and methods of manufacture
US8441124B2 (en) * 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8232193B2 (en) 2010-07-08 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming Cu pillar capped by barrier layer
US8664760B2 (en) * 2011-05-30 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Connector design for packaging integrated circuits
US9299680B2 (en) * 2013-03-14 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure having dies with connectors

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11127704B2 (en) 2017-11-28 2021-09-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with bump structure and method of making semiconductor device
TWI701791B (zh) * 2018-12-27 2020-08-11 南亞科技股份有限公司 半導體結構及其製造方法
US10777522B2 (en) 2018-12-27 2020-09-15 Nanya Technology Corporation Semiconductor structure and method of manufacturing the same

Also Published As

Publication number Publication date
KR20170123299A (ko) 2017-11-07
TWI631635B (zh) 2018-08-01
US20150340332A1 (en) 2015-11-26
TW201545251A (zh) 2015-12-01
KR20150135127A (ko) 2015-12-02
US9875980B2 (en) 2018-01-23
KR101905334B1 (ko) 2018-10-05
TWI595576B (zh) 2017-08-11

Similar Documents

Publication Publication Date Title
TWI595576B (zh) 銅柱側壁保護
TWI755389B (zh) 半導體裝置及其製造方法
US11031347B2 (en) Semiconductor packages
US12009289B2 (en) Semiconductor package and manufacturing method thereof
US9449931B2 (en) Pillar bumps and process for making same
US9799592B2 (en) Semicondutor device with through-silicon via-less deep wells
KR101423388B1 (ko) 패키지 온 패키지 소자와, 반도체 다이를 패키징하는 방법
TWI506711B (zh) 內連線結構與其製作方法
TWI590347B (zh) 形成圍繞基板之晶粒附接區域之相鄰的通道及屏障材料之半導體裝置及方法以控制向外流之底部填充材料
TWI720035B (zh) 半導體裝置與其製造方法
KR102591618B1 (ko) 반도체 패키지 및 반도체 패키지의 제조 방법
US10522476B2 (en) Package structure, integrated fan-out package and method of fabricating the same
CN106298684B (zh) 半导体装置及其制造方法
TW201836099A (zh) 半導體裝置及其製造方法
US20210296139A1 (en) Semiconductor device with tiered pillar and manufacturing method thereof
TWI792089B (zh) 半導體裝置和製造其之方法
CN117542836A (zh) 半导体器件及其形成方法
KR102674882B1 (ko) 반도체 디바이스 및 그 제조 방법
US9024439B2 (en) Substrates having bumps with holes, semiconductor chips having bumps with holes, semiconductor packages formed using the same, and methods of fabricating the same
KR20160016431A (ko) 반도체 디바이스, 반도체 패키지, 반도체 디바이스 및 반도체 패키지의 제조 방법
TWI842093B (zh) 半導體裝置及其製造方法
TWI844247B (zh) 半導體裝置和製造其之方法
TW202407917A (zh) 半導體封裝以及製造其之方法