TW201715671A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TW201715671A
TW201715671A TW105117131A TW105117131A TW201715671A TW 201715671 A TW201715671 A TW 201715671A TW 105117131 A TW105117131 A TW 105117131A TW 105117131 A TW105117131 A TW 105117131A TW 201715671 A TW201715671 A TW 201715671A
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Taiwan
Prior art keywords
reinforcing member
insert
interposer
semiconductor package
semiconductor
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TW105117131A
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TWI712123B (zh
Inventor
金陽瑞
杜旺朱
李吉弘
張民華
金東和
李旺求
黃金良
崔美京
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艾馬克科技公司
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Abstract

一種半導體封裝及一種其製造方法，所述半導體封裝及其製造方法能夠減小所述半導體封裝的大小並且提高產品可靠性。在非限制性實例實施例中，所述方法可以包括在晶圓上形成插入件，在所述插入件上形成至少一個加固部件，將至少一個半導體晶粒耦合且電連接到所述插入件，用底膠填充所述半導體晶粒與所述插入件之間的區域，並且使用囊封物囊封所述插入件上的所述加固部件、所述半導體晶粒和所述底膠。

Description

半導體裝置及其製造方法 【相關申請案的交叉參考/通過引用方式併入】
本申請引用、主張2015年10月22日在韓國智慧財產權局遞交的且標題為“用於製造半導體封裝的方法以及使用所述方法的半導體封裝(METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE USING THE SAME)，，的第10-2015-0147395號韓國專利申請的優先權並主張所述韓國專利申請的權益，所述韓國專利申請的內容在此以全文引入的方式併入本文中。
本發明涉及半導體裝置及其製造方法。
當前用於形成感測器裝置(例如，指紋感測器裝置)的半導體封裝和方法並不適當，例如，會導致感測準確性和/或裝置可靠性不足、可製造性問題、裝置比需要的更厚、裝置難以整合到其它產品中和/或整合到其它產品中的成本高、等等。通過比較常規和傳統方法與如在本申請的其餘部分中參考圖式闡述的本發明，所屬領域的技術人員將顯而易見此類方法的另外的限制和缺點。
本發明的各種態樣提供一種半導體封裝及一種其製造方法，所述半導體封裝及其製造方法能夠減小半導體封裝的大小並且能夠提高產品可靠性。在非限制性實例實施例中，所述方法可以包括在晶圓上形成插入件，在插入件上形成至少一個加固部件，將至少一個半導體晶粒耦合且電連接到插入件，用底膠填充半導體晶粒與插入件之間的區域，並且使用囊封物囊封插入件上的加固部件、半導體晶粒和底膠。
10‧‧‧晶圓
100‧‧‧半導體封裝
110‧‧‧插入件
111‧‧‧再分佈層
111a‧‧‧第一再分佈層
111b‧‧‧第二再分佈層
111c‧‧‧第三再分佈層
112‧‧‧鈍化層
112a‧‧‧第一鈍化層
112b‧‧‧第二鈍化層
112c‧‧‧第三鈍化層
120‧‧‧加固部件
130‧‧‧半導體晶粒
131‧‧‧導電墊
132‧‧‧導電凸塊
133‧‧‧焊料
140‧‧‧底膠
150‧‧‧囊封物
160‧‧‧導電凸塊
170‧‧‧屏蔽層
200‧‧‧半導體封裝
220‧‧‧加固部件
221‧‧‧第一加固部件部分
222‧‧‧第二加固部件部分
280‧‧‧模具直通孔
320‧‧‧加固部件
321‧‧‧第一加固部件部分
322‧‧‧第二加固部件部分
323‧‧‧第三加固部件部分
S‧‧‧接納空間
S1-S7‧‧‧步驟
S11-S17‧‧‧步驟
圖1是示出根據本發明的實施例的用於製造半導體封裝的方法的流程圖；圖2A到2K是示出圖1中所示的用於製造半導體封裝的方法的橫截面圖；圖3是示出根據本發明的另一實施例的用於製造半導體封裝的方法的流程圖；圖4A到4C是示出圖3中所示的用於製造半導體封裝的方法的橫截面圖；圖5是示出在根據本發明的用於製造半導體封裝的方法中形成加固部件的步驟的另一實施例的平面圖；以及圖6是示出在根據本發明的用於製造半導體封裝的方法中形成加固部件的步驟的又另一實施例的平面圖。
以下論述通過提供實例來呈現本發明的各種態樣。此類實例是非限制性的，並且由此本發明的各種方面的範圍應不必受所提供的實例 的任何特定特徵限制。在以下論述中，短語“例如”和“示例性”是非限制性的且通常與“借助於實例而非限制”、“例如且不加限制”等等同義。
如本文中所使用，“和/或”意指通過“和/或”聯結的列表中的項目中的任何一個或多個。作為一實例，“x和/或y”意指三元素集合{(x),(y),(x,y)}中的任何元素。換句話說，“x和/或y”意指“x和y中的一個或兩個”。作為另一實例，“x、y和/或z”意指七元素集合{(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}中的任何元素。換句話說，“x、y和/或z”意指“x、y和z中的一個或多個”。
本文中所使用的術語僅出於描述特定實例的目的，且並不意圖限制本發明。如本文中所使用，除非上下文另外明確指示，否則單數形式也意圖包含複數形式。將進一步理解，術語“包括”、“包含”、“具有”等等當在本說明書中使用時，表示所陳述特徵、整體、步驟、操作、元件和/或構件的存在，但是不排除一個或多個其它特徵、整體、步驟、操作、元件、構件和/或其群組的存在或添加。
將理解，雖然術語“第一”、“第二”等可在本文中用於描述各種元件，但這些元件不應受這些術語限制。這些術語僅用於將一個元件與另一元件區分開來。因此，例如，在不脫離本發明的教示內容的情況下，下文論述的第一元件、第一元件或第一部分可被稱為第二元件、第二元件或第二部分。類似地，各種空間術語，例如“上部”、“下部”、“側部”等等，可以用於以相對方式將一個元件與另一元件區分開來。然而，應理解，元件可以不同方式定向，例如，在不脫離本發明的教示內容的情況下，半導體裝置可以側向轉動使得其“頂部”表面水準地朝向且其“側 部，，表面垂直地朝向。
在圖式中，為了清楚起見可以放大層、區域和/或元件的厚度或大小。相應地，本發明的範圍應不受此類厚度或大小限制。另外，在圖式中，類似元件符號可以在整個論述中指代類似元件。
此外，應理解，當元件A被提及為“連接到”或“耦合到”元件B時，元件A可以直接連接到元件B或間接連接到元件B(例如，可以在元件A與元件B之間放置插入元件C(和/或其它元件))。
本發明的某些實施例涉及一種用於製造半導體封裝的方法以及一種使用所述方法的半導體封裝。
近來，例如行動電話或智慧型電話等移動通信終端，或例如平板電腦、MP3播放機或數位相機等小型電子裝置已經發展為尺寸更小且重量更輕。隨著這種趨勢，構成小型電子裝置的半導體封裝正變得更小且更輕。
為了適應各種半導體晶粒並且獲得高密度再分佈層(或結構)，半導體封裝採用插入件(或基板)。由於插入件通常包含穿過矽基板的矽直通孔(TSV)，因此製造過程可能變得複雜且可能增加製造成本。另外，由於插入件與半導體晶粒之間以及插入件與囊封物之間的熱膨脹係數差別可能導致出現翹曲現象。
本發明提供一種用於製造半導體封裝的方法以及使用所述方法的半導體封裝，其能夠減小半導體封裝的大小並且能夠提高產品可靠性。
將在優選實施例的以下描述中描述或從以下描述中清楚本 發明的上述和其它目的。
根據本發明的態樣，提供一種用於製造半導體封裝的方法，所述方法包含在晶圓上形成插入件，在插入件上形成至少一個加固部件，將至少一個半導體晶粒附接到插入件晶粒上以使所述至少一個半導體晶粒電連接到插入件，用底膠填充半導體晶粒與插入件之間的區域，並且使用囊封物囊封插入件上的加固部件、半導體晶粒和底膠。
根據本發明的態樣，提供一種半導體封裝，所述半導體封裝包含：插入件；在插入件上形成的至少一個加固部件；在插入件上形成的待電連接到插入件的至少一個半導體晶粒；填充半導體晶粒與插入件之間的區域的底膠；以及囊封插入件上的加固部件、半導體晶粒和底膠的囊封物。
如上文所描述，在根據本發明的用於製造半導體封裝的方法和使用所述方法的半導體封裝中，由於加固部件可以形成於插入件上以防止填充插入件與半導體晶粒之間的區域的底膠流至插入件的側面，由此減小了半導體封裝的大小並且提高了產品可靠性。
另外，在根據本發明的用於製造半導體封裝的方法和使用所述方法的半導體封裝中，由於加固部件和底膠形成於插入件上，因此有可能抑制由於插入件與半導體晶粒之間以及插入件與囊封物之間的熱膨脹係數差別而導致出現翹曲現象。
現將詳細參考本發明的當前實施例，在附圖中說明所述實施例的實例。
本發明的各種態樣可以許多不同形式實施且不應理解為受 限於在本文中所闡述的實例實施例。實際上，提供本發明的這些實例實施例是為了使本發明將為充分且完整的，並且將向所屬領域的技術人員傳達本發明的各種態樣。
在圖式中，為了清楚起見而放大了層和區域的厚度。此處，類似元件符號通篇指代類似元件。如本文中所使用，術語“和/或”包含相關聯的所列項目中的一個或多個的任何和所有組合。
另外，本文中所使用的術語僅僅是出於描述特定實施例的目的而並不意圖限制本發明。如本文中所使用，除非上下文另外明確指示，否則單數形式也意圖包含複數形式。將進一步理解，術語“包括”當在本說明書中使用時，表示所陳述特徵、數目、步驟、操作、元件和/或構件的存在，但是不排除一個或多個其它特徵、數目、步驟、操作、元件、構件和/或其群組的存在或添加。
圖1是示出根據本發明的實施例的用於製造半導體封裝的方法的流程圖，並且圖2A到2K是示出圖1中所示的用於製造半導體封裝的方法的橫截面圖。
如圖1所示，根據本發明的實施例的用於製造半導體封裝的方法包含以下步驟：形成插入件(S1)、形成加固部件(S2)、附接半導體晶粒(S3)、用底膠進行填充(S4)、囊封(S5)、形成導電凸塊(S6)以及形成屏蔽層(S7)。現將參考圖2A到2K詳細地描述圖1的各個步驟。
在形成插入件(S1)時，在晶圓10上形成插入件110。如圖2A所示，插入件110包含多層再分佈層111(或再分佈結構)和覆蓋再分佈層111的鈍化層112。具體來說，如圖2B(圖2B是圖2A的部分A的 放大視圖)所示，在形成插入件(S1)時，在晶圓10上形成第一再分佈層111a(或導電層)並且由第一鈍化層112a(或介電層)覆蓋第一再分佈層111a的一部分。接著，進一步形成電連接到第一再分佈層111a的第二再分佈層111b(或導電層)，並且由第二鈍化層112b(或介電層)覆蓋第二再分佈層111b的一部分。另外，進一步形成電連接到第二再分佈層111b的第三再分佈層111c(或導電層)，並且由第三鈍化層112c(或介電層)覆蓋第三再分佈層111c的一部分，由此完成實例插入件110。此處，第三再分佈層111c暴露於插入件110的頂表面。雖然在圖2A到2C中示出了具有三層的再分佈層111，但是再分佈層111的層的數目可以多於或少於三個。另外，晶圓10可以由矽(Si)、玻璃或金屬製成，但本發明的各態樣並不限於此。
可以通過無電電鍍、電鍍和/或濺鍍由選自由銅、鋁、金、銀、鈀及其等效物組成的群組中的一種材料製成再分佈層111(或其導電層)，但本發明的各態樣並不限於此。另外，可以使用一般光阻通過光微影執行再分佈層111(或其導電層)的圖案化或佈線，但本發明的各態樣並不限於此。
鈍化層112(或介電層)可以由選自由聚合物(例如聚醯亞胺、苯並環丁烯、或聚苯並惡唑，及其等效物)組成的群組的一種材料製成，但本發明的各態樣並不限於此。另外，可以通過選自由旋塗、噴塗、浸塗、棒塗及其等效物組成的群組的一種方法形成鈍化層112，但本發明的各態樣並不限於此。
另外，可以通過在晶圓10的製造過程(或工廠)期間供應形成於晶圓10上的再分佈層111的一部分並且在封裝過程(或工廠)期間 另外在所述一部分上形成再分佈層111來完成插入件110。因此，由於插入件110實現較細線寬(小於100μm)和較細間距互連，所以可以實現高密度互連。這種類型的插入件110可以(例如)被稱為無矽整合模組(silicon-less integrated module，SLIM)插入件。另外，可以通過在晶圓10的製造過程(或工廠)期間僅供應晶圓10並且在封裝過程(或工廠)期間在晶圓10上形成再分佈層111(或再分佈結構)來製造插入件110。這種類型的插入件110可以(例如)被稱為矽晶圓整合扇出技術(silicon wafer integrated fan-out technology，SWIFT)插入件。又例如，插入件110可以是印刷電路板(printed circuit board，PCB)。
在形成加固部件(S2)時，在插入件110上形成加固部件120。如圖2C所示，加固部件120為柱形或壁形，安置為大體上垂直於插入件110並且形成於插入件110的邊緣處。加固部件120可以由具有高電導率和熱導率的導電材料(例如，選自銅(Cu)或其等效物的一種材料)或具有高熱導率的塑膠材料製成，但本發明的各態樣並不限於此。
如圖2D所示，可以在使用晶圓10的過程期間以矩陣配置在晶圓10上形成加固部件120。具體來說，在用於鋸切晶圓10以形成單個的半導體封裝的鋸切線上形成加固部件120。因此，實例加固部件120形成為完全包圍插入件110的邊緣，由此形成安裝有(稍後將描述的)半導體晶粒130的接納空間S(或晶粒空間或元件空間)。
在附接半導體晶粒(S3)時，將半導體晶粒130附接到插入件110上。首先，如圖2E所示，在附接半導體晶粒(S3)時，在暴露於插入件110的頂表面的再分佈層111上形成導電墊131。因此，導電墊131電 連接到再分佈層111(或再分佈結構)。另外，可以在形成插入件(S1)之前形成導電墊131或可以在形成加固部件(S2)時與加固部件120一起形成導電墊131。導電墊131可以由選自由銅、鋁、金、銀、鈀及其等效物組成的群組中的一種材料製成，但本發明的各態樣並不限於此。另外導電墊131可以通過濺鍍、真空沉積或光微影形成，但本發明的各態樣並不限於此。
接著，如圖2F所示，在附接半導體晶粒(S3)時，將半導體晶粒130電連接到導電墊131。例如，將半導體晶粒130的導電凸塊132通過焊料133電連接到導電墊131。例如，可以使用質量回焊工藝、熱壓工藝或雷射黏結工藝將半導體晶粒130電連接到導電墊131。可以使用選自金屬材料(例如，鉛/錫(Pb/Sn)或無鉛Sn及其等效物)的一種材料形成焊料133，但本發明的各態樣並不限於此。
另外，半導體晶粒130可以包含(例如)電路，例如數位訊號處理器(digital signal processor，DSP)、微處理器、網路處理器、功率管理處理器、音訊處理器、RF電路、無線基帶系統單晶片(system-on-chip，SoC)處理器、感測器或特定應用積體電路(application specific integrated circuit，ASIC)。
在用底膠進行填充(S4)時，底膠140填充插入件110與半導體晶粒130之間的區域。如圖2G所示，底膠140填充插入件110的頂表面與半導體晶粒130的底表面之間的區域，接著進行固化。底膠140保護凸塊黏結部分在半導體封裝製造過程期間免受例如機械衝擊或腐蝕等外來因素影響。此處，底膠140可以由選自由以下組成的群組的一種材料製成：環氧樹脂、熱塑性材料、熱可固化材料、聚醯亞胺、聚氨酯、聚合材料、 填充環氧樹脂、填充熱塑性材料、填充熱可固化材料、填充聚醯亞胺、填充聚氨酯、填充聚合材料、熔劑底膠及其等效物，但本發明的各態樣並不限於此。
另外，底膠140完全覆蓋插入件110的頂表面並且被設置為與加固部件120的一個側表面接觸。因此，底膠140可以借助於加固部件120而不流至插入件110的側面。也就是說，加固部件120可以充當阻擋層以用於在用底膠140進行填充時防止底膠140流動。
另外，由於底膠140形成於插入件110與半導體晶粒130之間同時完全覆蓋插入件110的頂表面，因此有可能抑制由於插入件110與半導體晶粒130之間以及插入件110與囊封物150之間的熱膨脹係數差別而導致出現翹曲現象。
在囊封(S5)時，使用囊封物150囊封插入件110的頂部。如圖2H所示，在囊封(S5)時，使用囊封物150囊封安裝在插入件110上的加固部件120、半導體晶粒130和底膠140。囊封物150完全囊封加固部件120、半導體晶粒130和底膠140，由此保護加固部件120、半導體晶粒130和底膠140免受因外部衝擊和氧化而導致損壞。囊封物150可以由選自由以下組成的群組的一種材料製成：用於一般傳遞模塑的熱可固化環氧模塑化合物、用於調劑的室溫可固化囊封膠及其等效物，但本發明的各態樣並不限於此。此處，囊封物150與插入件110的頂表面間隔開而不與插入件110的頂表面直接接觸。
雖然未示出，但是可以通過磨削將囊封物150的頂表面的不必要的部分去除掉預定厚度。此處，可以使用例如金剛石磨削機或其等效 物執行磨削，但本發明的各態樣並不限於此。
在形成導電凸塊(S6)時，移除置於插入件110下的晶圓10並且在插入件110下形成導電凸塊160。首先，如圖2I所示，在形成導電凸塊(S6)時，移除置於插入件110下的晶圓10。例如，可以通過一般磨削過程移除晶圓10。因此，再分佈層111(例如，第一再分佈層或導電層)暴露於插入件110的底表面。接著，如圖2J所示，在形成導電凸塊(S6)時，在暴露於插入件110的底表面的再分佈層111上形成導電凸塊160。此處，可以在暴露於插入件110的底表面的再分佈層111上形成凸塊下金屬(under bump metal，UBM)並且可以在所述UBM上形成導電凸塊160。UBM可以通過防止在導電凸塊160與再分佈層111之間形成金屬間化合物來提高導電凸塊160的板級(board-level)可靠性。
導電凸塊160可以由選自但不限於以下的材料製成：共晶焊料(例如，Sn37Pb)、具有高熔點的高鉛焊料(例如，Sn95Pb)、無鉛焊料(例如，SnAg、SnCu、SnZn、SnZnBi、SnAgCu和SnAgBi)及其等效物。
接著，雖然未示出，但是執行鋸切過程以形成由至少一個半導體晶粒130和對應於安置在接納空間S(或晶粒空間或元件空間)中的所述至少一個半導體晶粒的加固部件120組成的單一單元，由此製造根據本發明的實施例的半導體封裝100。此處，可以使用鋸切設備(例如，鋼鋸條或雷射光束)執行鋸切過程。
在形成屏蔽層(S7)時，在囊封物150的表面上形成屏蔽層170。在形成屏蔽層(S7)時，如圖2K所示，形成屏蔽層170以覆蓋囊封物150的整個表面和加固部件120的至少一部分。例如，可以通過使用噴塗 或濺鍍在囊封物150的表面上塗布混合導電金屬粉末的導電漿料來形成屏蔽層170，但本發明的各態樣並不限於此。
此處，當形成屏蔽層170時，加固部件120可以由導電金屬製成，同時其一端優選地接地。因此，可以通過屏蔽層170屏蔽由囊封物150中的至少一個半導體晶粒130產生的電磁波以免散射到外部，並且也可以通過屏蔽層170屏蔽外部施加的電磁波以免穿透到囊封物150中的至少一個半導體晶粒130中。
圖3是示出根據本發明的另一實施例的用於製造半導體封裝的方法的流程圖，並且圖4A到4C是示出圖3中所示的用於製造半導體封裝的方法的橫截面圖。
參考圖3，根據本發明的另一實施例的用於製造半導體封裝的方法包含以下步驟：形成插入件(S11)、形成加固部件(S12)、附接半導體晶粒(S13)、用底膠進行填充(S14)、囊封(S15)、形成模具直通孔(through mold via)(S16)以及形成導電凸塊(S17)。現將參考圖4A到4C詳細地描述圖3的各個步驟。
步驟S11、S12、S13、S14和S15與圖1的步驟S1、S2、S3、S4和S5相同，並且示出對應的步驟S11、S12、S13、S14和S15的各圖與圖2A到2H相同，因此將不進行所述各圖的詳細描述。
在形成模具直通孔(S16)時，在囊封物150中形成模具直通孔(through mold via，TMV)280。如圖4A所示，在形成模具直通孔(TMV)(S16)時，TMV 280穿過介於囊封物150的頂表面到插入件110的頂表面的範圍內的區域。TMV 280形成於半導體晶粒130與加固部件120之間。具 體來說，通過以下步驟形成TMV 280：通過(例如)雷射鑽孔過程形成穿過囊封物150的通孔；在通孔的內壁表面上電鍍具有高電導率和熱導率的導熱金屬，例如鋁(Al)或銅(Cu)；且接著用例如金屬漿料等導電材料填充通孔。因此，根據本發明的半導體封裝可以容易地通過TMV 280散發由插入件110產生的熱量。另外，可以在TMV 280上進一步電堆疊半導體晶粒或半導體封裝。
在形成導電凸塊(S17)時，移除置於插入件110下的晶圓10並且在插入件110下形成導電凸塊160。首先，如圖4B所示，在形成導電凸塊(S17)時，移除置於插入件110下的晶圓10。例如，可以通過一般磨削過程移除晶圓10。因此，再分佈層111(例如，第一再分佈層或導電層)暴露於插入件110的底表面。接著，如圖4C所示，在形成導電凸塊(S17)時，在暴露於插入件110的底表面的再分佈層111上形成導電凸塊160。此處，可以在暴露於插入件110的底表面的再分佈層111上形成凸塊下金屬(UBM)並且可以在所述UBM上形成導電凸塊160。UBM可以通過防止在導電凸塊160與再分佈層111之間形成金屬間化合物來提高導電凸塊160的板級可靠性。
導電凸塊160可以由選自但不限於以下的材料製成：共晶焊料(例如，Sn37Pb)、具有高熔點的高鉛焊料(例如，Sn95Pb)、無鉛焊料(例如，SnAg、SnCu、SnZn、SnZnBi、SnAgCu和SnAgBi)及其等效物。
接著，雖然未示出，但是執行鋸切過程以形成由至少一個半導體晶粒130和對應於安置在接納空間S(或晶粒空間或元件空間)中的所述至少一個半導體晶粒的加固部件120組成的單一單元，由此製造根據本 發明的另一實施例的半導體封裝200。此處，可以使用鋸切設備(例如，鋼鋸條或雷射光束)執行鋸切過程。
圖5是示出在根據本發明的用於製造半導體封裝的方法中形成加固部件的步驟的另一實施例的平面圖。
參考圖5，在形成加固部件時，在晶圓10上形成加固部件220。在用於鋸切晶圓10以形成單個的半導體封裝的鋸切線的轉角處形成加固部件220。因此，加固部件220可以包含彼此間隔開的四個部件。加固部件220可以形成為大體上‘L’形配置，並且包含第一加固部件部分221和垂直於第一加固部件部分221的第二加固部件部分222。此處，第一加固部件部分221形成為垂直於鋸切線中的一條線。另外，加固部件220的對應部件形成為彼此間隔開以形成安裝有半導體晶粒的接納空間(或晶粒空間或元件空間)。在鋸切晶圓10之後，加固部件220在單一半導體封裝的每個轉角處支撐插入件的頂表面，由此防止在半導體製造過程期間出現扭動或翹曲。
圖6是示出在根據本發明的用於製造半導體封裝的方法中形成加固部件的步驟的又另一實施例的平面圖。
參考圖6，在形成加固部件時，在晶圓10上形成加固部件320。在用於通過鋸切晶圓10形成單一半導體封裝的鋸切線的每個轉角處形成加固部件320。因此，加固部件320可以包含彼此間隔開的四個部件。加固部件320可以形成為大體上箭頭形配置，並且包含第一加固部件部分321、垂直於第一加固部件部分321的第二加固部件部分322、以及置於第一加固部件部分321與第二加固部件部分322之間的第三加固部件部分 323。此處，第一加固部件部分321形成為垂直於鋸切線中的一條線。另外，加固部件320的對應部件形成為彼此間隔開以形成安裝有半導體晶粒的接納空間S(或晶粒空間或元件空間)。在鋸切晶圓10之後，加固部件320在單一半導體封裝的每個轉角處支撐插入件的頂表面，由此防止在半導體製造過程期間出現扭動或翹曲。
雖然已經參考某些支援實施例描述了根據本發明的各種態樣的用於製造半導體封裝的方法以及使用所述方法的半導體封裝，但是所屬領域的技術人員應理解，本發明不限於所公開的特定實施例，而是本發明將包含落入所附申請專利範圍的範疇內的所有實施例。
本文中的論述包含展示電子裝置的各個部分及其製造方法的眾多示意圖。為了清楚地示意，這些圖並未展示每個實例組合件的所有態樣。本文中提供的任何實例組合件和/或方法可以與本文中提供的任何或全部其它組合件和/或方法共用任何或全部特徵。
綜上所述，本發明的各種方面提供一種半導體封裝及一種其製造方法，所述半導體封裝及其製造方法能夠減小半導體封裝的大小並且能夠提高產品可靠性。在非限制性實例實施例中，所述方法可以包括在晶圓上形成插入件，在插入件上形成至少一個加固部件，將至少一個半導體晶粒耦合且電連接到插入件，用底膠填充半導體晶粒與插入件之間的區域，並且使用囊封物囊封插入件上的加固部件、半導體晶粒和底膠。雖然已經參考某些方面和實例描述了以上內容，但是所屬領域的技術人員應理解，在不脫離本發明的範圍的情況下，可以進行各種修改並可以替代等效物。另外，在不脫離本發明的範圍的情況下，可以進行許多修改以使特定 情況或材料適應本發明的教示。因此，希望本發明不限於所公開的特定實例，而是本發明將包含落入所附申請專利範圍的範疇內的所有實例。
100‧‧‧半導體封裝
110‧‧‧插入件
111‧‧‧再分佈層
112‧‧‧鈍化層
120‧‧‧加固部件
130‧‧‧半導體晶粒
131‧‧‧導電墊
132‧‧‧導電凸塊
133‧‧‧焊料
140‧‧‧底膠
150‧‧‧囊封物
160‧‧‧導電凸塊
170‧‧‧屏蔽層

Claims (20)

  1. 一種用於製造半導體封裝的方法，所述方法包括：在晶圓上形成插入件；在所述插入件上形成至少一個加固部件；將至少一個半導體晶粒耦合且電連接到所述插入件；用底膠填充所述半導體晶粒與所述插入件之間的區域；以及使用囊封物囊封所述插入件上的所述加固部件、所述半導體晶粒和所述底膠。
  2. 根據申請專利範圍第1項所述的方法，其中所述形成所述至少一個加固部件包括在所述插入件的邊緣處形成所述至少一個加固部件以形成安裝有所述半導體晶粒的元件空間的邊界。
  3. 根據申請專利範圍第2項所述的方法，其中所述至少一個加固部件中的每一個加固部件分別地形成在所述元件空間的對應轉角處，並且包括第一加固部件部分和垂直於所述第一加固部件部分的第二加固部件部分。
  4. 根據申請專利範圍第3項所述的方法，其中所述至少一個加固部件中的每一個加固部件包括置於所述第一加固部件部分與所述第二加固部件部分之間的第三加固部件部分。
  5. 根據申請專利範圍第1項所述的方法，其中所述至少一個加固部件中的每一個加固部件由導電材料製成。
  6. 根據申請專利範圍第1項所述的方法，其中對所述區域進行填充包括用所述底膠完全覆蓋所述插入件的頂表面，並且使所述至少一個加固部件的側表面與所述底膠接觸，其中所述至少一個加固部件防止所述底膠流 至所述插入件的外側。
  7. 根據申請專利範圍第1項所述的方法，其中所述囊封物並不直接接觸所述插入件的所述頂表面。
  8. 根據申請專利範圍第1項所述的方法，包括在所述囊封之後：將所述晶圓從所述插入件移除，並且在所述插入件的與所述半導體晶粒相對的一側上形成導電凸塊且將所述導電凸塊電連接到所述插入件；以及鋸切所述插入件以形成單個的半導體封裝。
  9. 根據申請專利範圍第8項所述的方法，包括在所述形成所述導電凸塊之後：形成包圍所述囊封物並且電連接到所述加固部件的屏蔽層。
  10. 根據申請專利範圍第1項所述的方法，包括在所述囊封之後形成模具直通孔(through mold via，TMV)，所述模具直通孔穿過介於所述囊封物的頂表面到所述插入件的所述頂表面的範圍內的區域。
  11. 一種半導體封裝，包括：插入件；至少一個加固部件，在所述插入件上形成；至少一個半導體晶粒，耦合到所述插入件且電連接到所述插入件；底膠，填充所述半導體晶粒與所述插入件之間的區域；以及囊封物，囊封所述插入件上的所述加固部件、所述半導體晶粒和所述底膠。
  12. 根據申請專利範圍第11項所述的半導體封裝，其中所述至少一個加固部件置於所述插入件的邊緣處以形成安裝有所述半導體晶粒的元件空間 的邊界。
  13. 根據申請專利範圍第12項所述的半導體封裝，其中所述至少一個加固部件中的每一個加固部件分別地形成在所述元件空間的對應轉角處，並且包括第一加固部件部分和垂直於所述第一加固部件部分的第二加固部件部分。
  14. 根據申請專利範圍第13項所述的半導體封裝，其中所述至少一個加固部件中的每一個加固部件包括置於所述第一加固部件部分與所述第二加固部件部分之間的第三加固部件部分。
  15. 根據申請專利範圍第11項所述的半導體封裝，其中所述至少一個加固部件中的每一個加固部件由導電材料製成。
  16. 根據申請專利範圍第11項所述的半導體封裝，其中所述底膠完全覆蓋所述插入件的頂表面並且接觸所述至少一個加固部件的側表面，其中所述至少一個加固部件防止所述底膠流至所述插入件的外側。
  17. 根據申請專利範圍第11項所述的半導體封裝，其包括包圍所述囊封物並且電連接到所述加固部件的屏蔽層。
  18. 根據申請專利範圍第11項所述的半導體封裝，其包括模具直通孔(TMV)，所述模具直通孔穿過介於所述囊封物的頂表面到所述插入件的所述頂表面的範圍內的區域，其中所述模具直通孔置於所述半導體晶粒與所述加固部件之間。
  19. 根據申請專利範圍第11項所述的半導體封裝，其進一步包括導電凸塊，所述導電凸塊在所述插入件的與所述半導體晶粒相對的一側上並且電連接到所述插入件。
  20. 一種用於製造半導體封裝的方法，所述方法包括：將至少一個半導體晶粒耦合且電連接到晶圓上的插入件，其中所述插入件包括至少一個加固部件；用底膠填充所述半導體晶粒與所述插入件之間的區域；以及使用囊封物囊封所述插入件上的所述加固部件、所述半導體晶粒和所述底膠。
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