TW201620136A - 高壓金氧半導體電晶體元件 - Google Patents

高壓金氧半導體電晶體元件 Download PDF

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TW201620136A
TW201620136A TW103141053A TW103141053A TW201620136A TW 201620136 A TW201620136 A TW 201620136A TW 103141053 A TW103141053 A TW 103141053A TW 103141053 A TW103141053 A TW 103141053A TW 201620136 A TW201620136 A TW 201620136A
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high voltage
mos transistor
transistor device
voltage mos
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TWI632683B (zh
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浦士杰
李明宗
楊承樺
李年中
李文芳
王智充
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聯華電子股份有限公司
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Priority to US14/590,957 priority patent/US9224859B1/en
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Abstract

本發明提供一種高壓金氧半導體電晶體元件，包含有：一基底，具有一第一導電型態，一閘極，設置於該基底上，一汲極區域，設置於該基底內，且該汲極區域具有一第二導電型態，以及一源極區域，設置於該基底內，其中該源極區域包含有至少一第一部分以及至少一第二部分，且該第一部分包含該第二導電型態，該第二部分包含有一第一導電型態，該第二導電型態與該第一導電型態互補。

Description

高壓金氧半導體電晶體元件
本發明有關於一種高壓金氧半導體(high voltage metal-oxide-semiconductor，以下簡稱為HV MOS)電晶體元件，尤指一種高壓橫向雙擴散金氧半導體(high voltage lateral double-diffused metal-oxide-semiconductor，HV-LDMOS)電晶體元件。
在具有高壓處理能力的功率元件中，雙擴散金氧半導體(double-diffused MOS，DMOS)電晶體元件係持續受到重視。常見的DMOS電晶體元件有垂直雙擴散金氧半導體(vertical double-diffused MOS，VDMOS)與橫向雙擴散金氧半導體(LDMOS)電晶體元件。而LDMOS電晶體元件因具有較高的操作頻寬與操作效率，以及易與其他積體電路整合之平面結構，現已廣泛地應用於高電壓操作環境中，如中央處理器電源供應(CPU power supply)、電源管理系統(power management system)、直流/交流轉換器(AC/DC converter)以及高功率或高頻段的功率放大器等等。LDMOS電晶體元件主要的特徵為源極端所設置之低摻雜濃度、大面積的橫向擴散漂移區域，其目的在於緩和源極端與汲極端之間的高電壓，因此可使LDMOS電晶體元件獲得較高的崩潰電壓(breakdown voltage)。
由於HV MOS電晶體元件所追求的兩個主要特性為低導 通電阻以及高崩潰電壓，且這兩個要求常常是彼此衝突難以權衡的。因此目前仍需要一種可在高電壓環境下正常運作，且同時滿足低導通電阻以及高崩潰電壓兩個要求的解決途徑。除此之外，HV MOS的靜電放電(electrostatic discharge,ESD)也會影響整體效能，因此降低HV MOS的ESD也是一個重要的課題。
因此，本發明之一目的係在於提供一提供低導通電阻與高崩潰電壓的HV MOS電晶體元件。同時可增進HV MOS的ESD效能。
本發明提供一種高壓金氧半導體電晶體元件，包含有：一基底，具有一第一導電型態，一閘極，設置於該基底上，一汲極區域，設置於該基底內，且該汲極區域具有一第二導電型態，以及一源極區域，設置於該基底內，其中該源極區域包含有至少一第一部分以及至少一第二部分，且該第一部分包含該第二導電型態，該第二部分包含有一第一導電型態，該第二導電型態與該第一導電型態互補。
比起習知的高壓金氧半導體，本發明的高壓金氧半導體之源極區域由兩種不同導電型態的部分所共同組成。更詳細說明，本發明的高壓金氧半導體之源極區域具有第一部分與第二部分，且第一部分與第二部分具有互補的導電型態，如此一來，由於從汲極區域流至源極區域的高壓訊號流量被分散，因此可以減少HV MOS高壓訊號的ESD電流流量直接經過源極，進而降低ESD損害發生的可能性，且增加HV MOS的穩定性。
100‧‧‧HV MOS電晶體元件
100’‧‧‧HV MOS電晶體元件
102‧‧‧基底
104‧‧‧絕緣層
105‧‧‧絕緣層
106‧‧‧深井區
110‧‧‧高壓井區
112‧‧‧汲極區域
112’‧‧‧汲極接觸區
114‧‧‧源極區域
114’‧‧‧源極接觸區
114A‧‧‧第一部分
114A’‧‧‧第一部分
114B‧‧‧第二部分
114B’‧‧‧第二部分
116‧‧‧基體區域
116’‧‧‧基體接觸區
120‧‧‧第一摻雜區
130‧‧‧閘極結構
A-A’‧‧‧剖面線
B-B’‧‧‧剖面線
G‧‧‧間隔
第1圖為本發明所提供之HV MOS電晶體元件之佈局圖案之第一較佳實施例之上視圖。
第2圖為第1圖中沿A-A’剖線所得之剖面示意圖。
第3圖為第1圖中沿B-B’剖線所得之剖面示意圖。
第4圖為本發明所提供之HV MOS電晶體元件之佈局圖案之第二較佳實施例之上視圖。
請參閱第1~3圖，其中第1圖為本發明所提供之HV MOS電晶體元件之佈局圖案之第一較佳實施例之上視圖，第2圖與第3圖為本發明所提供之HV MOS電晶體元件之第一較佳實施例之示意圖，且第2圖為第1圖中沿A-A’剖線所得之剖面示意圖，第3圖為第1圖中沿B-B’剖線所得之剖面示意圖。如第1~3圖所示，本較佳實施例所提供之HV MOS電晶體元件100係設置於一基底102，例如一矽基底上。基底102具有一第一導電型態，在本較佳實施例中該第一導電型態為p型。HV MOS電晶體元件100更包含至少一絕緣層104，例如為一場氧化層(field oxide，FOX)，但值得注意的是，為了清楚表現HV MOS電晶體元件100中某些特定摻雜區域的相對關係，第1圖中係將絕緣層104省略，然熟習該項技藝之人士應可根據第2圖與第3圖輕易瞭解絕緣層104設置之位置。
請繼續參閱第1~3圖。本較佳實施例所提供之HV MOS電晶體元件100尚包含一深井區106，深井區106係包含一第二導電型態，第二導電型態係與第一導電型態互補(complementary)，因此在本較佳實施例中第二導電型態為n型。在深井區106中，係形 成有一漂移區(圖未示)與一高壓井區110(示於第2圖與第3圖)。漂移區包含第二導電型態；而高壓井區110則包含第一導電型態。在n型漂移區中，係形成有一汲極區域112；而在p型高壓井區110中，則形成有一源極區域114與一基體(body)區域116。汲極區域112具有第二導電型態，故作為HVMOS電晶體元件100的n型汲極區域112。至於源極區域114在本發明中則包含有兩部分：第一部分114A與第二部分114B，其中第一部分114A具有第二導電型態，而第二部分114B則具有第一導電型態。以本實施例為例，第一部分114A為n型，第二部分114B為p型，關於本發明源極區域114的其他特徵，將會在後續段落中描述。基體摻雜區116係包含第一導電型態，故用以作為HV MOS電晶體元件100的p型基體摻雜區116。如第1~3圖所示，基體區域116係較佳與源極區域114不互相重疊，兩者之間有一絕緣層105存在，且彼此電性隔離，絕緣層105例如為場氧化層，或著是淺溝隔離(shallow trench isoaltion，STI)。此外，在汲極摻雜區112、源極摻雜區114與基體摻雜區116中更可分別設置汲極接觸區112’、源極接觸區114’與基體接觸區116’。
HV MOS電晶體元件100亦包含一閘極130，但值得注意的是，為了清楚表現HV MOS電晶體元件100中某些特定摻雜區域的相對關係，第1圖中亦將閘極130省略，然熟習該項技藝之人士亦可根據第2圖與第3圖之圖式輕易瞭解閘極130設置之位置。如第2圖與第3圖所示，閘極130係設置於基底102上，且覆蓋部分絕緣層104。
請仍然參閱第1~3圖。本較佳實施例所提供之HV MOS電晶體元件100更包含一第一摻雜區120。如第1~3圖所示，第一摻雜區120係設置於汲極區域112與源極區域114之間，且汲極區 域112、源極區域114、與第一摻雜區120彼此分隔設置，並利用深井區106與高壓井區110電性隔離汲極區域112、源極區域114與第一摻雜區120。第一摻雜區120包含該第一導電型態，因此本實施例中，係為一p型的第一摻雜區120。根據本較佳實施例所提供之HV MOS電晶體元件100，第一摻雜區120設置於絕緣層104下方，其中第一摻雜區120的寬度較佳小於絕緣層104的寬度，且第一摻雜區120的導電型態互補於n型源極區域的第一部分114A與n型汲極區域112，可用以提升HV MOS電晶體元件100的電阻值。當高壓訊號流經此一路徑時，會因為電阻值的增加使得本實施例的壓降能力有效提升，繼而使輸出的訊號成為低壓訊號。換句話說，藉由p型第一摻雜區120的設置，HV MOS電晶體元件100的崩潰電壓係可有效地提升。
本發明的特徵如第1圖所示，源極區域114包含有第一部分114A與第二部分114B。更詳細說明，本實施例中，源極區域114為一環狀結構，第一部分114A與第二部分114B皆為弧形結構，且第一部分114A與第二部分114B彼此並不直接接觸，兩者之間存在有至少兩個間隔(gaps)G。環狀的源極區域114主要由第一部分114A與第二部分114B共同組成，也就是說，第一部分114A與第二部分114B可以共同組成一環形結構，並具有至少兩個間隔G。另外，從上視圖來看，p型第二部分114B的總表面面積大於n型第一部分114A的總表面面積。
習知的HV MOS，其源極區域可能是一完整封閉環狀的n型摻雜區域，因此當高壓訊號從汲極區域流至源極區域時，大量的高壓電流將會容易產生靜電放電(electrostatic discharge,ESD)，進而 影響整體HV MOS的效能。本發明的源極區域114有超過一半的部分為p型第二部分114B，而僅留下相對較少部分的n型第一部分114A，該些n型第一部分114A才可作為高壓訊號的出口。如此一來，當高壓訊號從汲極區域112向外流出時，高壓訊號僅會從n型第一部分114A流出，而其餘p型第二部分114B則不會成為高壓訊號的出口，而此時高壓訊號則可由p型第二部分114B旁邊的基體區域116被導引至HV MOS外。如此一來，由於n型第一部分114A，也就是高壓訊號的流通路徑的出口佔有相對較小面積，因此將可有效控制HV MOS的高壓訊號流量，更可以有效減少因靜電放電(electrostatic discharge,ESD)而產生的不良影響。
本發明的源極區域114的第一部分114A與第二部分114B之面積，將直接影響HV MOS偵測到的訊號大小，因此若第一部分114A所佔的總表面積增加，對於抑制ESD的效果就不明顯，然而若第一部分114A所佔的總表面積愈小，則HV MOS偵測到的訊號就容易過小。因此本發明中，n型第二部分114B所佔的圓心角度介於180度~330度之間，也就是說，第二部分114B的總表面積與整個源極區域114的總表面積之比值較佳介於1/2~11/12之間，如此一來將可避免上述缺失。
上述第一實施例中，一個環狀源極區域114中僅包含有一個第一部分114A以及一個第二部分114B，然而在本發明的其他實施例可能包含有多個第一部分以及多個第二部分。請參考第4圖，其繪示本發明所提供之HV MOS電晶體元件之佈局圖案之第二較佳實施例之上視圖，在本實施例中，HV MOS電晶體元件100’的源極區域114為不連續摻雜區，可包含有多個第一部分114A’以及多個第二部 分114B’，同樣地，各個第一部分114A’以及第二部分114B’彼此不直接接觸，且包含多個間隔G位於第一部分114A’以及第二部分114B’之間，但本實施例仍須滿足第二部分114B’的總表面積與整個源極區域114的總表面積之比值介於1/2~11/12之間的條件。可理解的是，第4圖所示的源極區域114形狀僅為本發明的其中一可能範例，而本發明源極區域114的形狀，包含第一區域114A與第二區域114B的數量、排列等，可以依照實際需求而調整，也屬於本發明所涵蓋的範圍內。
此外，在上述實施例中，各環繞於汲極區域112外圍的元 件，包括源極區域114、基體區域116等皆呈現圓環狀，然而本發明不限於此，上述元件也可能具有其他形狀，例如方形、賽道形(racetrack-shaped)或其他適合的形狀，而從上視圖來看，較佳為對稱結構。
綜上所述，比起習知的高壓金氧半導體，本發明的高壓金 氧半導體之源極區域由兩種不同導電型態的部分所共同組成。更詳細說明，本發明的高壓金氧半導體之源極區域具有第一部分與第二部分，且第一部分與第二部分具有互補的導電型態，如此一來，由於從汲極區域流至源極區域的高壓訊號流量被分散，因此可以減少HV MOS高壓訊號的ESD電流流量直接經過源極，進而降低ESD損害發生的可能性，且增加HV MOS的穩定性。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100‧‧‧HV MOS電晶體元件
102‧‧‧基底
112‧‧‧汲極區域
114‧‧‧源極區域
114A‧‧‧第一部分
114B‧‧‧第二部分
116‧‧‧基體區域
120‧‧‧第一摻雜區
A-A’‧‧‧剖面線
B-B’‧‧‧剖面線
G‧‧‧間隔

Claims (14)

  1. 一種高壓金氧半導體電晶體元件，包含有：一基底，具有一第一導電型態；一閘極，設置於該基底上；一汲極區域，設置於該基底內，且該汲極區域具有一第二導電型態；以及一源極區域，設置於該基底內，其中該源極區域包含有至少一第一部分以及至少一第二部分，且該第一部分包含該第二導電型態，該第二部分包含有一第一導電型態，該第二導電型態與該第一導電型態互補。
  2. 如申請專利範圍第1項所述的高壓金氧半導體電晶體元件，其中該源極區域為一環狀結構，該第一部分與該第二部分皆為弧形結構。
  3. 如申請專利範圍第1項所述的高壓金氧半導體電晶體元件，其中該第二部分的總表面積大於該第一部分的總表面積。
  4. 如申請專利範圍第3項所述的高壓金氧半導體電晶體元件，其中該第二部分的總表面積與該源極區域的總表面積之比值介於1/2~11/12之間。
  5. 如申請專利範圍第1項所述的高壓金氧半導體電晶體元件，其中更包含一深井區，且該深井區包含該第二導電型態。
  6. 如申請專利範圍第5項所述的高壓金氧半導體電晶體元件，其 中該汲極區域與該第一摻雜區域皆設置於該深井區內。
  7. 如申請專利範圍第1項所述的高壓金氧半導體電晶體元件，其中更包含一高壓井區，且該高壓井區包含該第一導電型態。
  8. 如申請專利範圍第7項所述的高壓金氧半導體電晶體元件，其中該源極區域位於該高壓井區內。
  9. 如申請專利範圍第7項所述的高壓金氧半導體電晶體元件，其中更包含一基體區域，位於該高壓井區中。
  10. 如申請專利範圍第9項所述的高壓金氧半導體電晶體元件，其中該基體區域與該源極區域不互相重疊。
  11. 如申請專利範圍第9項所述的高壓金氧半導體電晶體元件，其中更包含至少一場氧化層，位於該基體區域與該源極區域之間。
  12. 如申請專利範圍第1項所述的高壓金氧半導體電晶體元件，其中該源極區域係為一不連續形摻雜區，且包含複數個間隔。
  13. 如申請專利範圍第1項所述的高壓金氧半導體電晶體元件，更包含一第一摻雜區，設置於該源極區域與該汲極區域之間，該第一摻雜區包含該第一導電型態。
  14. 如申請專利範圍第1項所述的高壓金氧半導體電晶體元件，其中該第一部分與該第二部分彼此不直接接觸。
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